From 8cbf2f47adb23613ac24087ddeea742d608df4b8 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 16 Aug 2023 05:11:25 -0400 Subject: [PATCH] RC? --- CPLD/LCMXO2-1200HC/.run_manager.ini | 9 - CPLD/LCMXO2-1200HC/.setting.ini | 4 - CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf | 17 - CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf | 68 - CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty | 205 - .../pn230815050136.tcr | 5 - .../pn230815052235.tcr | 5 - CPLD/LCMXO2-1200HC/impl1/.build_status | 62 - .../.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb | Bin 70832 -> 0 bytes CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 74348 -> 0 bytes .../LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb | Bin 67455 -> 0 bytes CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt | 1 - .../impl1/RAM2GS_LCMXO2_1200HC_impl1.alt | 75 - .../impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep | 21 - .../impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn | 86 - .../RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd | Bin 197895 -> 0 bytes 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diff --git a/CPLD/LCMXO2-1200HC/.setting.ini b/CPLD/LCMXO2-1200HC/.setting.ini deleted file mode 100644 index 39eb32a..0000000 --- a/CPLD/LCMXO2-1200HC/.setting.ini +++ /dev/null @@ -1,4 +0,0 @@ -[General] -PAR.auto_tasks=PARTrace, IOTiming -Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile -Export.auto_tasks=Jedecgen diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf deleted file mode 100644 index fddf68b..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf deleted file mode 100644 index 63de512..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf +++ /dev/null @@ -1,68 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "UFMSDO" SITE "27" ; -LOCATE COMP "nFWE" SITE "28" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "63" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty deleted file mode 100644 index 7292d5f..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr deleted file mode 100644 index 857aaf4..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr +++ /dev/null @@ -1,5 +0,0 @@ -#Start recording tcl command: 8/15/2023 05:01:06 -#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC -prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf" -prj_run Export -impl impl1 -forceAll -#Stop recording: 8/15/2023 05:01:36 diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr deleted file mode 100644 index 6049d67..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr +++ /dev/null @@ -1,5 +0,0 @@ -#Start recording tcl command: 8/15/2023 05:22:04 -#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC -prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf" -prj_run Export -impl impl1 -#Stop recording: 8/15/2023 05:22:35 diff --git a/CPLD/LCMXO2-1200HC/impl1/.build_status b/CPLD/LCMXO2-1200HC/impl1/.build_status deleted file mode 100644 index e131fe6..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/.build_status +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb deleted file mode 100644 index 20f45e5fc7c0eb948a503d13876a1f05c8109b05..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 70832 zcmeIbd3a>kbszWuR22&7t}38`W}{ndbS+@33Yf78G}|GiF0m-7Ws#P|#50p+vN0kZ zOOzaEcj7D-#kNT&CiUTKLIKcXw`u`c%Rf+qw!t>(*(cjfmRYmSWZ##WWG2f@X5##Q zcRlx3fu9XjC;21wN8NkQJ@1}-&pr2?bMJfazN=roGL=n|ZzuRQ{>G19nM(cqr~cwg z6BCbInN5A}#TQ;8K55J+gCukGR{QPELz4hI*OI?)^qas<%+xP0UYV;uI$!67KqMh% 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zUFhm^o~{%XFH^D7g}OAY)+Kj=F4{bd@!Biwb+nR6p)Ymc8{f~GP@(n*b!mH#E~WSC zGV^`9%y>wb*7xhu@~|$=kLc3$0bLsZR+omq)204@>r%H{m*NL?DLkr6{xMy0kL#iu c7bLa!CilgOVCAT4EEu*j{3{>zs`-Wg2N8|}mjD0& diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt deleted file mode 100644 index 0a575a4..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt +++ /dev/null @@ -1 +0,0 @@ -RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt deleted file mode 100644 index 96d3739..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt +++ /dev/null @@ -1,75 +0,0 @@ -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Tue Aug 15 05:22:21 2023 * -NOTE DESIGN NAME: RAM2GS * -NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * -NOTE PIN ASSIGNMENTS * -NOTE PINS RD[7] : 43 : inout * -NOTE PINS RD[6] : 42 : inout * -NOTE PINS RD[5] : 41 : inout * -NOTE PINS RD[4] : 40 : inout * -NOTE PINS RD[3] : 39 : inout * -NOTE PINS RD[2] : 38 : inout * -NOTE PINS RD[1] : 37 : inout * -NOTE PINS RD[0] : 36 : inout * -NOTE PINS Dout[7] : 82 : out * -NOTE PINS Dout[6] : 78 : out * -NOTE PINS Dout[5] : 84 : out * -NOTE PINS Dout[4] : 83 : out * -NOTE PINS Dout[3] : 85 : out * -NOTE PINS Dout[2] : 87 : out * -NOTE PINS Dout[1] : 86 : out * -NOTE PINS Dout[0] : 76 : out * -NOTE PINS LED : 34 : out * -NOTE PINS RBA[1] : 60 : out * -NOTE PINS RBA[0] : 58 : out * -NOTE PINS RA[11] : 59 : out * -NOTE PINS RA[10] : 64 : out * -NOTE PINS RA[9] : 63 : out * -NOTE PINS RA[8] : 65 : out * -NOTE PINS RA[7] : 75 : out * -NOTE PINS RA[6] : 68 : out * -NOTE PINS RA[5] : 70 : out * -NOTE PINS RA[4] : 74 : out * -NOTE PINS RA[3] : 71 : out * -NOTE PINS RA[2] : 69 : out * -NOTE PINS RA[1] : 67 : out * -NOTE PINS RA[0] : 66 : out * -NOTE PINS nRCS : 57 : out * -NOTE PINS RCKE : 53 : out * -NOTE PINS nRWE : 49 : out * -NOTE PINS nRRAS : 54 : out * -NOTE PINS nRCAS : 52 : out * -NOTE PINS RDQMH : 51 : out * -NOTE PINS RDQML : 48 : out * -NOTE PINS nUFMCS : 47 : out * -NOTE PINS UFMCLK : 29 : out * -NOTE PINS UFMSDI : 30 : out * -NOTE PINS PHI2 : 8 : in * -NOTE PINS MAin[9] : 32 : in * -NOTE PINS MAin[8] : 25 : in * -NOTE PINS MAin[7] : 18 : in * -NOTE PINS MAin[6] : 24 : in * -NOTE PINS MAin[5] : 19 : in * -NOTE PINS MAin[4] : 20 : in * -NOTE PINS MAin[3] : 21 : in * -NOTE PINS MAin[2] : 13 : in * -NOTE PINS MAin[1] : 12 : in * -NOTE PINS MAin[0] : 14 : in * -NOTE PINS CROW[1] : 16 : in * -NOTE PINS CROW[0] : 10 : in * -NOTE PINS Din[7] : 1 : in * -NOTE PINS Din[6] : 2 : in * -NOTE PINS Din[5] : 98 : in * -NOTE PINS Din[4] : 99 : in * -NOTE PINS Din[3] : 97 : in * -NOTE PINS Din[2] : 88 : in * -NOTE PINS Din[1] : 96 : in * -NOTE PINS Din[0] : 3 : in * -NOTE PINS nCCAS : 9 : in * -NOTE PINS nCRAS : 17 : in * -NOTE PINS nFWE : 28 : in * -NOTE PINS RCLK : 62 : in * -NOTE PINS UFMSDO : 27 : in * -NOTE CONFIGURATION MODE: NONE * -NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep deleted file mode 100644 index b2ad5bc..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep +++ /dev/null @@ -1,21 +0,0 @@ ----------------------------------------------------------------------- -Report for cell RAM2GS.TECH -Register bits: 102 of 1520 (6.711%) -I/O cells: 67 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 10 100.0 - FD1P3AX 29 100.0 - FD1P3AY 5 100.0 - FD1P3IX 3 100.0 - FD1S3AX 47 100.0 - FD1S3IX 14 100.0 - FD1S3JX 4 100.0 - GSR 1 100.0 - IB 26 100.0 - INV 3 100.0 - LUT4 122 100.0 - OB 33 100.0 - PFUMX 1 100.0 - TOTAL 306 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn deleted file mode 100644 index a0f2cfe..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn +++ /dev/null @@ -1,86 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:22:19 2023 - - -Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf - -Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream 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zO=Emp(MB_l&KGig#LA~=N>{4c4!eu$!0Orl3+KJ`hrAy_H_?nGkL+*#T}b1HLs}anGHk<+Mtg z`6R9S6b7ki$`l7FrsX(-_#4nK&2CJWP2N6i5|bNg$E~VV_S#Xnfwlm;w&P^GF*drR ziJf6L(YVmC?bCKkw0{B(^EGlKEz5{yZ@n_+Al!GP2}_rJ(P15p7Cd;Nu60h7uIW`0 zhe-p< zW;`6){a7@B82LiGp91cSMz>9mkQezQ=JbBgQQm~bK7BP$#s8}3=PVxsp<&9n-0Y13 z2diu6gL$UAn5W>aTb!HdIdGKlKG2q)14ju*slyuM&sb5D(mXXz+D!(mF3TJ>iKFs@ zYnvy<~6RJFK-k2;_W~PU|%HkOy1iJ5^bfncXsB@Uh%yE?kmWJ WER!}YsVapDi6(ad diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad deleted file mode 100644 index 9775856..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad +++ /dev/null @@ -1,309 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-1200HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.44 - -Tue Aug 15 05:22:12 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 2.5V | -| 1 | 2.5V | -| 2 | 2.5V | -| 3 | 2.5V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | | -| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | | -| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3C | | | | -| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | | -| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | | -| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | | -| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | -| 15/3 | unused, PULL:DOWN | | | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | | -| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | | -| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | | -| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | | -| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | | -| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | | -| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | | -| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | | -| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | | -| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | | -| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | | -| 45/2 | unused, PULL:DOWN | | | PB18C | | | | -| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | | -| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | | -| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | | -| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | | -| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | | -| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | | -| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | | -| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | | -| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | | -| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | -| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | | -| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | | -| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | | -| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | | -| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | | -| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | | -| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | | -| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | | -| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | | -| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | | -| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | | -| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | | -| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | | -| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | | -| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | | -| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | -| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | | -| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | | -| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | | -| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | | -| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | -| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | -| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | -| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | -| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | -| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | -| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | -| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | -| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | -| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | -| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | -| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | -| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | -| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | -| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | -| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | -| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | -| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | -| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | -| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | -| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | -| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | -| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | -| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | -| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | -| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "63"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "62"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "UFMCLK" SITE "29"; -LOCATE COMP "UFMSDI" SITE "30"; -LOCATE COMP "UFMSDO" SITE "27"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "28"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; -LOCATE COMP "nUFMCS" SITE "47"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:22:14 2023 - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par deleted file mode 100644 index 47ca8d6..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par +++ /dev/null @@ -1,301 +0,0 @@ - -Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -Tue Aug 15 05:22:08 2023 - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 67+4(JTAG)/108 66% used - 67+4(JTAG)/80 89% bonded - - SLICE 75/640 11% used - - - -Number of Signals: 285 -Number of Connections: 674 -WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. - -Pin Constraint Summary: - 66 out of 67 pins locked (98% locked). - -The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 40) - PHI2_c (driver: PHI2, clk load #: 13) - -WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. - -The following 1 signal is selected to use the secondary clock routing resources: - nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) - -WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -.......... -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 143529. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 143450 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 3 out of 108 (2%) - PLL : 0 out of 1 (0%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 - SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 - - PRIMARY : 2 out of 8 (25%) - SECONDARY: 1 out of 8 (12%) - -Edge Clocks: - No edge clock selected. - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. - 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. - Number of PIO comps: 67; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 2.5V | - | -| 1 | 20 / 21 ( 95%) | 2.5V | - | -| 2 | 17 / 20 ( 85%) | 2.5V | - | -| 3 | 17 / 20 ( 85%) | 2.5V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - -0 connections routed; 674 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 05:22:14 08/15/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 05:22:14 08/15/23 - -Start NBR section for initial routing at 05:22:14 08/15/23 -Level 1, iteration 1 -2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; -Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs -Level 2, iteration 1 -11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs -Level 3, iteration 1 -20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs -Level 4, iteration 1 -11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 05:22:15 08/15/23 -Level 1, iteration 1 -7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs -Level 4, iteration 1 -9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs -Level 4, iteration 2 -6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs -Level 4, iteration 3 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 4 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 5 -4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 6 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 7 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 8 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 9 -2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 10 -3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 11 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 12 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 13 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 14 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 15 -2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 16 -3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 17 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 18 -1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 19 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 20 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 21 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 22 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 23 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 24 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 25 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23 -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for re-routing at 05:22:15 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for post-routing at 05:22:15 08/15/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 254 (37.69%) - Estimated worst slack : -4.650ns - Timing score : 391939 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 391939 - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -4.650 -PAR_SUMMARY::Timing score> = 391.939 -PAR_SUMMARY::Worst slack> = 0.304 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd deleted file mode 100644 index 38b1fbf..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd +++ /dev/null @@ -1,38 +0,0 @@ -[ActiveSupport PAR] -; Global primary clocks -GLOBAL_PRIMARY_USED = 2; -; Global primary clock #0 -GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; -GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_0_LOADNUM = 40; -; Global primary clock #1 -GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; -GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_1_LOADNUM = 13; -; # of global secondary clocks -GLOBAL_SECONDARY_USED = 1; -; Global secondary clock #0 -GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; -GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; -GLOBAL_SECONDARY_0_LOADNUM = 9; -GLOBAL_SECONDARY_0_SIGTYPE = CLK; -; I/O Bank 0 Usage -BANK_0_USED = 13; -BANK_0_AVAIL = 19; -BANK_0_VCCIO = 2.5V; -BANK_0_VREF1 = NA; -; I/O Bank 1 Usage -BANK_1_USED = 20; -BANK_1_AVAIL = 21; -BANK_1_VCCIO = 2.5V; -BANK_1_VREF1 = NA; -; I/O Bank 2 Usage -BANK_2_USED = 17; -BANK_2_AVAIL = 20; -BANK_2_VCCIO = 2.5V; -BANK_2_VREF1 = NA; -; I/O Bank 3 Usage -BANK_3_USED = 17; -BANK_3_AVAIL = 20; -BANK_3_VCCIO = 2.5V; -BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par deleted file mode 100644 index 7d91ea8..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par +++ /dev/null @@ -1,28 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:22:08 2023 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t -RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir -RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset -D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml - - -Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -4.650 391939 0.304 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc deleted file mode 100644 index ec074a2..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc +++ /dev/null @@ -1 +0,0 @@ -DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed deleted file mode 100644 index 80ddd6d..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed +++ /dev/null @@ -1,2779 +0,0 @@ -* -NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* -NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Aug 15 05:22:19 2023* -NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd* -NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100* -NOTE JEDEC FILE STATUS: Final Version 1.95* -NOTE PIN ASSIGNMENTS* -NOTE PINS RD[7] : 43 : inout* -NOTE PINS RD[6] : 42 : inout* -NOTE PINS RD[5] : 41 : inout* -NOTE PINS RD[4] : 40 : inout* -NOTE PINS RD[3] : 39 : inout* -NOTE PINS RD[2] : 38 : inout* -NOTE PINS RD[1] : 37 : inout* -NOTE PINS RD[0] : 36 : inout* -NOTE PINS Dout[7] : 82 : out* -NOTE PINS Dout[6] : 78 : out* -NOTE PINS Dout[5] : 84 : out* -NOTE PINS Dout[4] : 83 : out* -NOTE PINS Dout[3] : 85 : out* -NOTE PINS Dout[2] : 87 : out* -NOTE PINS Dout[1] : 86 : out* -NOTE PINS Dout[0] : 76 : out* -NOTE PINS LED : 34 : out* -NOTE PINS RBA[1] : 60 : out* -NOTE PINS RBA[0] : 58 : out* -NOTE PINS RA[11] : 59 : out* -NOTE PINS RA[10] : 64 : out* -NOTE PINS RA[9] : 63 : out* -NOTE PINS RA[8] : 65 : out* -NOTE PINS RA[7] : 75 : out* -NOTE PINS RA[6] : 68 : out* -NOTE PINS RA[5] : 70 : out* -NOTE PINS RA[4] : 74 : out* -NOTE PINS RA[3] : 71 : out* -NOTE PINS RA[2] : 69 : out* -NOTE PINS RA[1] : 67 : out* -NOTE PINS RA[0] : 66 : out* -NOTE PINS nRCS : 57 : out* -NOTE PINS RCKE : 53 : out* -NOTE PINS nRWE : 49 : out* -NOTE PINS nRRAS : 54 : out* -NOTE PINS nRCAS : 52 : out* -NOTE PINS RDQMH : 51 : out* -NOTE PINS RDQML : 48 : out* -NOTE PINS nUFMCS : 47 : out* -NOTE PINS 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--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log +++ /dev/null @@ -1,4 +0,0 @@ ----- MParTrce Tool Log File ---- - -==== Par Standard Out ==== -==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf deleted file mode 100644 index 2743d95..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf +++ /dev/null @@ -1,4 +0,0 @@ -#BLOCK ASYNCPATHS; -#BLOCK RESETPATHS; - -#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata deleted file mode 100644 index 558a037..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata +++ /dev/null @@ -1,6331 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp deleted file mode 100644 index 934b075..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp +++ /dev/null @@ -1,402 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2GS' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial - RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr - RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O - neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200 - HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA - M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -Target Vendor: LATTICE -Target Device: LCMXO2-1200HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 08/15/23 05:22:05 - -Design Summary --------------- - - Number of registers: 102 out of 1520 (7%) - PFU registers: 102 out of 1280 (8%) - PIO registers: 0 out of 240 (0%) - Number of SLICEs: 75 out of 640 (12%) - SLICEs as Logic/ROM: 75 out of 640 (12%) - SLICEs as RAM: 0 out of 480 (0%) - SLICEs as Carry: 10 out of 640 (2%) - Number of LUT4s: 143 out of 1280 (11%) - Number used as logic LUTs: 123 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) - Number of block RAMs: 0 out of 7 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : No - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Number of PLLs: 0 out of 1 (0%) - Number of DQSDLLs: 0 out of 2 (0%) - Number of CLKDIVC: 0 out of 4 (0%) - Number of ECLKSYNCA: 0 out of 4 (0%) - Number of ECLKBRIDGECS: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 4 - Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) - - Page 1 - - - - -Design: RAM2GS Date: 08/15/23 05:22:05 - -Design Summary (cont) ---------------------- - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_6: 4 loads, 4 LSLICEs - Net RCLK_c_enable_5: 2 loads, 2 LSLICEs - Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_10: 3 loads, 3 LSLICEs - Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_16: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net RCLK_c_enable_15: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs - Net Ready_N_292: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs - Number of LSRs: 7 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_177: 1 loads, 1 LSLICEs - Net C1Submitted_N_237: 2 loads, 2 LSLICEs - Net n2366: 2 loads, 2 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net Ready: 18 loads - Net InitReady: 15 loads - Net RASr2: 15 loads - Net nRowColSel_N_35: 13 loads - Net nRowColSel: 12 loads - Net Din_c_4: 10 loads - Net MAin_c_1: 10 loads - Net Din_c_5: 9 loads - Net MAin_c_0: 9 loads - Net Din_c_0: 8 loads - - - - - Number of warnings: 0 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - - No errors or warnings present. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | - - Page 2 - - - - -Design: RAM2GS Date: 08/15/23 05:22:05 - -IO (PIO) Attributes (cont) --------------------------- -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 3 - - - - -Design: RAM2GS Date: 08/15/23 05:22:05 - -IO (PIO) Attributes (cont) --------------------------- -| RA[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RA[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RDQMH | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nUFMCS | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| UFMCLK | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| UFMSDI | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[2] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 4 - - - - -Design: RAM2GS Date: 08/15/23 05:22:05 - -IO (PIO) Attributes (cont) --------------------------- -| Din[6] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[3] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| UFMSDO | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block i2 undriven or does not drive anything - clipped. -Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_120 was merged into signal PHI2_c -Signal n1407 was merged into signal nRowColSel_N_34 -Signal n2380 was merged into signal Ready -Signal n1408 was merged into signal nRowColSel_N_35 -Signal nRWE_N_176 was merged into signal nRWE_N_177 -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. -Block i2046 was optimized away. -Block i1118_1_lut was optimized away. -Block i637_1_lut_rep_31 was optimized away. -Block i1119_1_lut was optimized away. -Block nRWE_I_50_1_lut was optimized away. -Block i1 was optimized away. - - - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 41 MB - - Page 5 - - - - -Design: RAM2GS Date: 08/15/23 05:22:05 - -Run Time and Memory Usage (cont) --------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 6 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. 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z&*RokV5P;oJA-wO&#`u3-I(H5d$6vzxzz!zON-p<2-dkVZgm3dyfn8ugLS^ctu7dm z<<>5kg&Co`u3%kba;qCyS2^4=QH#&5UBMDRhEUfXv*bCp8*;eZ>VfJ#ZtV`%MJaCe zM9b&a9$;mn+}abZG`IFbUY}dNz~WLub$f&LAUErJgLPkwzq=1u4>;V~7p*+E_5*9R zcsB;t{ZWqX57x>gxB7tPX1R3$Sht$o>WdsHZXF2LZ9cd9fpv3{TlHYwndVl1#G>39 zfDt~o2BH?1TL*!4hp;TL9upjKux|JGy9u!F71qIE-4x@P4b~%RZVdwK31)=q2IIRf zw+;d8mOQtHfOVI{twX`O+ve6`XbFy?V6Dn zg7u`wtx;gT%ZyOnXt16WS;m0%Y?fn5RONGPELg9b+&Tg*c2bKGMm_D{>SlrUN{m~x!Ft(aR*RFM=@pY(^P#CB$*fk} OLgAnyx3-5uBJ)3J((4ug diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t deleted file mode 100644 index 16daf53..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t +++ /dev/null @@ -1,9 +0,0 @@ --w --l 5 --i 6 --n 1 --t 1 --s 1 --c 0 --e 0 --exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t deleted file mode 100644 index 1635283..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "RAM2GS_LCMXO2_1200HC_impl1.log" --o "RAM2GS_LCMXO2_1200HC_impl1.csv" --pr "RAM2GS_LCMXO2_1200HC_impl1.prf" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad deleted file mode 100644 index 9775856..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad +++ /dev/null @@ -1,309 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-1200HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.44 - -Tue Aug 15 05:22:12 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 2.5V | -| 1 | 2.5V | -| 2 | 2.5V | -| 3 | 2.5V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | | -| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | | -| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3C | | | | -| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | | -| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | | -| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | | -| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | -| 15/3 | unused, PULL:DOWN | | | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | | -| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | | -| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | | -| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | | -| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | | -| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | | -| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | | -| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | | -| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | | -| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | | -| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | | -| 45/2 | unused, PULL:DOWN | | | PB18C | | | | -| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | | -| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | | -| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | | -| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | | -| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | | -| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | | -| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | | -| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | | -| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | | -| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | -| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | | -| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | | -| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | | -| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | | -| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | | -| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | | -| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | | -| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | | -| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | | -| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | | -| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | | -| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | | -| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | | -| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | | -| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | | -| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | -| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | | -| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | | -| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | | -| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | | -| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | -| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | -| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | -| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | -| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | -| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | -| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | -| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | -| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | -| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | -| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | -| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | -| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | -| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | -| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | -| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | -| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | -| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | -| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | -| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | -| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | -| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | -| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | -| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | -| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | -| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "63"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "62"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "UFMCLK" SITE "29"; -LOCATE COMP "UFMSDI" SITE "30"; -LOCATE COMP "UFMSDO" SITE "27"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "28"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; -LOCATE COMP "nUFMCS" SITE "47"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:22:14 2023 - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par deleted file mode 100644 index 7d1b7cf..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par +++ /dev/null @@ -1,329 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:22:08 2023 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t -RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir -RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset -D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml - - -Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -4.650 391939 0.304 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -Tue Aug 15 05:22:08 2023 - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 67+4(JTAG)/108 66% used - 67+4(JTAG)/80 89% bonded - - SLICE 75/640 11% used - - - -Number of Signals: 285 -Number of Connections: 674 -WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. - -Pin Constraint Summary: - 66 out of 67 pins locked (98% locked). - -The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 40) - PHI2_c (driver: PHI2, clk load #: 13) - -WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. - -The following 1 signal is selected to use the secondary clock routing resources: - nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) - -WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -.......... -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 143529. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 143450 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 3 out of 108 (2%) - PLL : 0 out of 1 (0%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 - SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 - - PRIMARY : 2 out of 8 (25%) - SECONDARY: 1 out of 8 (12%) - -Edge Clocks: - No edge clock selected. - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. - 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. - Number of PIO comps: 67; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 2.5V | - | -| 1 | 20 / 21 ( 95%) | 2.5V | - | -| 2 | 17 / 20 ( 85%) | 2.5V | - | -| 3 | 17 / 20 ( 85%) | 2.5V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - -0 connections routed; 674 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 05:22:14 08/15/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 05:22:14 08/15/23 - -Start NBR section for initial routing at 05:22:14 08/15/23 -Level 1, iteration 1 -2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; -Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs -Level 2, iteration 1 -11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs -Level 3, iteration 1 -20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs -Level 4, iteration 1 -11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 05:22:15 08/15/23 -Level 1, iteration 1 -7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs -Level 4, iteration 1 -9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs -Level 4, iteration 2 -6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs -Level 4, iteration 3 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 4 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 5 -4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 6 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 7 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 8 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 9 -2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 10 -3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 11 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 12 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 13 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 14 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 15 -2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 16 -3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 17 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 18 -1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 19 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 20 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 21 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 22 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 23 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 24 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 25 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23 -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for re-routing at 05:22:15 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for post-routing at 05:22:15 08/15/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 254 (37.69%) - Estimated worst slack : -4.650ns - Timing score : 391939 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 391939 - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -4.650 -PAR_SUMMARY::Timing score> = 391.939 -PAR_SUMMARY::Worst slack> = 0.304 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf deleted file mode 100644 index c80afd4..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf +++ /dev/null @@ -1,80 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:06 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[9]" SITE "63" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nFWE" SITE "28" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "UFMSDO" SITE "27" ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -COMMERCIAL ; - -// No timing preferences found. TRCE invokes auto-generation of timing preferences -// Section Autogen -FREQUENCY NET "RCLK_c" 299.401 MHz ; -FREQUENCY NET "PHI2_c" 99.079 MHz ; -// End Section Autogen diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt deleted file mode 100644 index e5e32de..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt +++ /dev/null @@ -1,10 +0,0 @@ --v -10 - - - - --gt --sethld --sp 4 --sphld m diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b deleted file mode 100644 index f5d2846..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b +++ /dev/null @@ -1,5 +0,0 @@ - - --g RamCfg:Reset - --path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 deleted file mode 100644 index e13b3ff..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 +++ /dev/null @@ -1,349 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:07 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 245 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 3.815ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i13 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) - - Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. - - Constraint Details: - - 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_57: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 -CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 -ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 -CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 -ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 -CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 -ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) - -------- - 6.873 (28.2% logic, 71.8% route), 4 logic levels. - -Warning: 139.762MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 104 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. - - Constraint Details: - - 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 -CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 -ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 -CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 -ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 -CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 -ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 -CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 -ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 -ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 9.577 (30.6% logic, 69.4% route), 6 logic levels. - -Warning: 50.592MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * - | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * - | | | ----------------------------------------------------------------------------- - - -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 78| 22.35% - | | | ----------------------------------------------------------------------------- - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 349 Score: 848079 -Cumulative negative slack: 584487 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:07 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.351ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. - - Constraint Details: - - 0.332ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) - -------- - 0.332 (40.1% logic, 59.9% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.447ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) - - Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. - - Constraint Details: - - 0.434ns physical path delay SLICE_15 to SLICE_15 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted -CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 -ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) - -------- - 0.434 (53.9% logic, 46.1% route), 2 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 - | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 349 (setup), 0 (hold) -Score: 848079 (setup), 0 (hold) -Cumulative negative slack: 584487 (584487+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr deleted file mode 100644 index 97270c5..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr +++ /dev/null @@ -1,2163 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:16 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 247 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 2.400ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) - - Delay: 5.574ns (43.6% logic, 56.4% route), 5 logic levels. - - Constraint Details: - - 5.574ns physical path delay SLICE_1 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 -CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 -ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 -CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 -ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 -CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 -ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 -CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 -ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) - -------- - 5.574 (43.6% logic, 56.4% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.383ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in InitReady_394 (to RCLK_c +) - - Delay: 5.441ns (35.6% logic, 64.4% route), 4 logic levels. - - Constraint Details: - - 5.441ns physical path delay SLICE_1 to SLICE_26 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_26: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 -CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 -ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 -CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 -ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 -CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 -ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) - -------- - 5.441 (35.6% logic, 64.4% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_26: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.217ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i16 (from RCLK_c +) - Destination: FF Data in nUFMCS_415 (to RCLK_c +) - - Delay: 5.391ns (45.1% logic, 54.9% route), 5 logic levels. - - Constraint Details: - - 5.391ns physical path delay SLICE_9 to SLICE_70 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) -ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 -CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 -ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 -CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 -ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 -CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 -ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 -CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 -ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) - -------- - 5.391 (45.1% logic, 54.9% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.180ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in nUFMCS_415 (to RCLK_c +) - - Delay: 5.354ns (45.4% logic, 54.6% route), 5 logic levels. - - Constraint Details: - - 5.354ns physical path delay SLICE_9 to SLICE_70 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 -CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 -ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 -CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 -ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 -CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 -ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 -CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 -ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) - -------- - 5.354 (45.4% logic, 54.6% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i16 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) - - Delay: 5.340ns (45.5% logic, 54.5% route), 5 logic levels. - - Constraint Details: - - 5.340ns physical path delay SLICE_9 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) -ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 -CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 -ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 -CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 -ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 -CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 -ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 -CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 -ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) - -------- - 5.340 (45.5% logic, 54.5% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i16 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) - - Delay: 5.332ns (45.6% logic, 54.4% route), 5 logic levels. - - Constraint Details: - - 5.332ns physical path delay SLICE_9 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) -ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 -CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 -ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 -CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 -ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 -CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 -ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 -CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 -ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) - -------- - 5.332 (45.6% logic, 54.4% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.149ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i16 (from RCLK_c +) - Destination: FF Data in InitReady_394 (to RCLK_c +) - - Delay: 5.207ns (37.2% logic, 62.8% route), 4 logic levels. - - Constraint Details: - - 5.207ns physical path delay SLICE_9 to SLICE_26 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_26: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) -ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 -CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 -ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 -CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 -ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 -CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 -ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) - -------- - 5.207 (37.2% logic, 62.8% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_26: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.131ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i7 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) - - Delay: 5.189ns (37.3% logic, 62.7% route), 4 logic levels. - - Constraint Details: - - 5.189ns physical path delay SLICE_2 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_57: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C15A.CLK to R7C15A.Q0 SLICE_2 (from RCLK_c) -ROUTE 3 1.086 R7C15A.Q0 to R8C14D.D0 FS_7 -CTOF_DEL --- 0.495 R8C14D.D0 to R8C14D.F0 SLICE_95 -ROUTE 1 0.747 R8C14D.F0 to R8C14A.C0 n15 -CTOF_DEL --- 0.495 R8C14A.C0 to R8C14A.F0 SLICE_86 -ROUTE 1 0.766 R8C14A.F0 to R8C16C.C0 n4_adj_7 -CTOF_DEL --- 0.495 R8C16C.C0 to R8C16C.F0 SLICE_84 -ROUTE 1 0.653 R8C16C.F0 to R8C16A.CE RCLK_c_enable_15 (to RCLK_c) - -------- - 5.189 (37.3% logic, 62.7% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C15A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.121ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) - - Delay: 5.295ns (45.9% logic, 54.1% route), 5 logic levels. - - Constraint Details: - - 5.295ns physical path delay SLICE_9 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_44: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 -CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 -ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 -CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 -ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 -CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 -ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 -CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 -ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) - -------- - 5.295 (45.9% logic, 54.1% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_44: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.087ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in UFMSDI_417 (to RCLK_c +) - - Delay: 5.261ns (46.2% logic, 53.8% route), 5 logic levels. - - Constraint Details: - - 5.261ns physical path delay SLICE_1 to SLICE_45 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_45: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 0.786 R7C15C.Q1 to R8C15C.C1 FS_12 -CTOF_DEL --- 0.495 R8C15C.C1 to R8C15C.F1 SLICE_80 -ROUTE 3 0.640 R8C15C.F1 to R8C14D.D1 n2375 -CTOF_DEL --- 0.495 R8C14D.D1 to R8C14D.F1 SLICE_95 -ROUTE 1 0.967 R8C14D.F1 to R8C14C.A1 n7 -CTOF_DEL --- 0.495 R8C14C.A1 to R8C14C.F1 SLICE_45 -ROUTE 1 0.436 R8C14C.F1 to R8C14C.C0 n2174 -CTOF_DEL --- 0.495 R8C14C.C0 to R8C14C.F0 SLICE_45 -ROUTE 1 0.000 R8C14C.F0 to R8C14C.DI0 UFMSDI_N_231 (to RCLK_c) - -------- - 5.261 (46.2% logic, 53.8% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_45: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 4.865 62.PADDI to R8C14C.CLK RCLK_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - -Warning: 174.216MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 88 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 7.065ns (41.4% logic, 58.6% route), 6 logic levels. - - Constraint Details: - - 7.065ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 -CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 -ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 -CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 -CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 7.065 (41.4% logic, 58.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_101: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 7.027ns (41.7% logic, 58.3% route), 6 logic levels. - - Constraint Details: - - 7.027ns physical path delay SLICE_93 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns - - Physical Path Details: - - Data path SLICE_93 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 -CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 -ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 -CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 -ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 -CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 7.027 (41.7% logic, 58.3% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 6.906ns (42.4% logic, 57.6% route), 6 logic levels. - - Constraint Details: - - 6.906ns physical path delay SLICE_102 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns - - Physical Path Details: - - Data path SLICE_102 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R8C15B.CLK to R8C15B.Q0 SLICE_102 (from PHI2_c) -ROUTE 1 0.623 R8C15B.Q0 to R9C15C.D1 Bank_4 -CTOF_DEL --- 0.495 R9C15C.D1 to R9C15C.F1 SLICE_99 -ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 -CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 -ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 -CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 6.906 (42.4% logic, 57.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_102: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R8C15B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 6.724ns (43.5% logic, 56.5% route), 6 logic levels. - - Constraint Details: - - 6.724ns physical path delay SLICE_103 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns - - Physical Path Details: - - Data path SLICE_103 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16D.CLK to R9C16D.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 0.645 R9C16D.Q1 to R9C14A.D0 Bank_3 -CTOF_DEL --- 0.495 R9C14A.D0 to R9C14A.F0 SLICE_68 -ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 -CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 -CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 6.724 (43.5% logic, 56.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_103: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16D.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 6.614ns (44.3% logic, 55.7% route), 6 logic levels. - - Constraint Details: - - 6.614ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 0.986 R9C16C.Q1 to R9C15A.A1 Bank_7 -CTOF_DEL --- 0.495 R9C15A.A1 to R9C15A.F1 SLICE_100 -ROUTE 1 0.315 R9C15A.F1 to R9C15B.D1 n2277 -CTOF_DEL --- 0.495 R9C15B.D1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 -CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 6.614 (44.3% logic, 55.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_101: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) - - Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. - - Constraint Details: - - 6.565ns physical path delay SLICE_101 to SLICE_10 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 -CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 -ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 -CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 -CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) - -------- - 6.565 (37.0% logic, 63.0% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_101: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) - - Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. - - Constraint Details: - - 6.565ns physical path delay SLICE_101 to SLICE_15 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 -CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 -ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 -CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 -CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) - -------- - 6.565 (37.0% logic, 63.0% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_101: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) - - Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. - - Constraint Details: - - 6.527ns physical path delay SLICE_93 to SLICE_10 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns - - Physical Path Details: - - Data path SLICE_93 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 -CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 -ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 -CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 -ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 -CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) - -------- - 6.527 (37.3% logic, 62.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) - - Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. - - Constraint Details: - - 6.527ns physical path delay SLICE_93 to SLICE_15 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns - - Physical Path Details: - - Data path SLICE_93 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 -CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 -ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 -CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 -ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 -CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 -ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 -CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 -ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) - -------- - 6.527 (37.3% logic, 62.7% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 6.490ns (37.5% logic, 62.5% route), 5 logic levels. - - Constraint Details: - - 6.490ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns - - Physical Path Details: - - Data path SLICE_101 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 -CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 -ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 -CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.688 R9C15B.F1 to R10C15C.D0 n26 -CTOF_DEL --- 0.495 R10C15C.D0 to R10C15C.F0 SLICE_104 -ROUTE 2 0.965 R10C15C.F0 to R9C14C.D1 n2363 -CTOF_DEL --- 0.495 R9C14C.D1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 6.490 (37.5% logic, 62.5% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_101: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c - -------- - 3.498 (0.0% logic, 100.0% route), 0 logic levels. - -Warning: 67.833MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 174.216 MHz| 5 * - | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 67.833 MHz| 6 * - | | | ----------------------------------------------------------------------------- - - -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 64| 19.10% - | | | -n1996 | 1| 49| 14.63% - | | | -n1997 | 1| 46| 13.73% - | | | -n1995 | 1| 45| 13.43% - | | | -n1998 | 1| 38| 11.34% - | | | -n1994 | 1| 37| 11.04% - | | | ----------------------------------------------------------------------------- - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 335 Score: 391939 -Cumulative negative slack: 304509 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:16 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C13B.CLK to R10C13B.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 0.152 R10C13B.Q0 to R10C13B.M1 n736 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr_382 (from RCLK_c +) - Destination: FF Data in CASr2_383 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_16 to SLICE_16 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_16 to SLICE_16: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q0 SLICE_16 (from RCLK_c) -ROUTE 1 0.152 R7C12B.Q0 to R7C12B.M1 CASr (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i8 (from RCLK_c +) - Destination: FF Data in IS_FSM__i9 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_75 to SLICE_75 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_75 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C13D.CLK to R10C13D.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.152 R10C13D.Q0 to R10C13D.M1 n732 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i12 (from RCLK_c +) - Destination: FF Data in IS_FSM__i13 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_78 to SLICE_78 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_78 to SLICE_78: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q0 SLICE_78 (from RCLK_c) -ROUTE 1 0.152 R8C12B.Q0 to R8C12B.M1 n728 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_78: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_78: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i14 (from RCLK_c +) - Destination: FF Data in IS_FSM__i15 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_81 to SLICE_81 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_81 to SLICE_81: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q0 SLICE_81 (from RCLK_c) -ROUTE 1 0.152 R9C12A.Q0 to R9C12A.M1 n726 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i2 (from RCLK_c +) - Destination: FF Data in IS_FSM__i3 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_84 to SLICE_84 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_84 to SLICE_84: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C16C.CLK to R8C16C.Q0 SLICE_84 (from RCLK_c) -ROUTE 1 0.152 R8C16C.Q0 to R8C16C.M1 n738 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_84: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_84: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i6 (from RCLK_c +) - Destination: FF Data in IS_FSM__i7 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_97 to SLICE_97 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_97: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C14A.CLK to R10C14A.Q0 SLICE_97 (from RCLK_c) -ROUTE 1 0.152 R10C14A.Q0 to R10C14A.M1 n734 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RASr_379 (from RCLK_c +) - Destination: FF Data in RASr2_380 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_30 to SLICE_30 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_30 to SLICE_30: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C13B.CLK to R8C13B.Q0 SLICE_30 (from RCLK_c) -ROUTE 2 0.154 R8C13B.Q0 to R8C13B.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i1 (from RCLK_c +) - Destination: FF Data in IS_FSM__i2 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_98 to SLICE_84 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_98 to SLICE_84: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q1 SLICE_98 (from RCLK_c) -ROUTE 4 0.154 R8C16D.Q1 to R8C16C.M0 nRCAS_N_165 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_84: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i0 (from RCLK_c +) - Destination: FF Data in IS_FSM__i1 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_98 to SLICE_98 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_98 to SLICE_98: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q0 SLICE_98 (from RCLK_c) -ROUTE 4 0.154 R8C16D.Q0 to R8C16D.M1 nRCS_N_139 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_15 to SLICE_15 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.132 R10C14C.Q0 to R10C14C.A0 C1Submitted -CTOF_DEL --- 0.101 R10C14C.A0 to R10C14C.F0 SLICE_15 -ROUTE 1 0.000 R10C14C.F0 to R10C14C.DI0 n1398 (to PHI2_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.629ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_407 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 0.601ns (38.9% logic, 61.1% route), 2 logic levels. - - Constraint Details: - - 0.601ns physical path delay SLICE_10 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.629ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C14B.CLK to R10C14B.Q0 SLICE_10 (from PHI2_c) -ROUTE 1 0.224 R10C14B.Q0 to R9C14C.B1 ADSubmitted -CTOF_DEL --- 0.101 R9C14C.B1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 0.601 (38.9% logic, 61.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.715ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in XOR8MEG_408 (to PHI2_c -) - - Delay: 0.687ns (34.1% logic, 65.9% route), 2 logic levels. - - Constraint Details: - - 0.687ns physical path delay SLICE_19 to SLICE_50 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.715ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.310 R9C14B.Q0 to R10C15B.B1 CmdEnable -CTOF_DEL --- 0.101 R10C15B.B1 to R10C15B.F1 SLICE_83 -ROUTE 1 0.143 R10C15B.F1 to R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c) - -------- - 0.687 (34.1% logic, 65.9% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.873ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) - FF CmdUFMCLK_413 - - Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. - - Constraint Details: - - 0.845ns physical path delay SLICE_19 to SLICE_100 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.873ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable -CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 -ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 -CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 -ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) - -------- - 0.845 (39.6% logic, 60.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.873ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) - - Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. - - Constraint Details: - - 0.845ns physical path delay SLICE_19 to SLICE_99 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.873ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable -CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 -ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 -CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 -ROUTE 2 0.148 R10C15A.F1 to R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c) - -------- - 0.845 (39.6% logic, 60.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C15C.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.252ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 1.224ns (35.6% logic, 64.4% route), 4 logic levels. - - Constraint Details: - - 1.224ns physical path delay SLICE_15 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.252ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.212 R10C14C.Q0 to R10C14D.A1 C1Submitted -CTOF_DEL --- 0.101 R10C14D.A1 to R10C14D.F1 SLICE_77 -ROUTE 1 0.222 R10C14D.F1 to R10C14A.B1 n2210 -CTOF_DEL --- 0.101 R10C14A.B1 to R10C14A.F1 SLICE_97 -ROUTE 1 0.211 R10C14A.F1 to R9C14C.A1 n7_adj_5 -CTOF_DEL --- 0.101 R9C14C.A1 to R9C14C.F1 SLICE_88 -ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 1.224 (35.6% logic, 64.4% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.277ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) - - Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. - - Constraint Details: - - 1.249ns physical path delay SLICE_19 to SLICE_20 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.277ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable -CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 -ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 -CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 -ROUTE 2 0.221 R9C15B.F0 to R9C17A.D1 n2220 -CTOF_DEL --- 0.101 R9C17A.D1 to R9C17A.F1 SLICE_89 -ROUTE 1 0.143 R9C17A.F1 to R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c) - -------- - 1.249 (34.9% logic, 65.1% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C17D.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.277ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) - - Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. - - Constraint Details: - - 1.249ns physical path delay SLICE_19 to SLICE_24 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.277ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable -CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 -ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 -CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 -ROUTE 2 0.221 R9C15B.F0 to R9C17A.D0 n2220 -CTOF_DEL --- 0.101 R9C17A.D0 to R9C17A.F0 SLICE_89 -ROUTE 1 0.143 R9C17A.F0 to R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c) - -------- - 1.249 (34.9% logic, 65.1% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C17C.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q XOR8MEG_408 (from PHI2_c -) - Destination: FF Data in RA11_385 (to PHI2_c +) - - Delay: 0.371ns (63.1% logic, 36.9% route), 2 logic levels. - - Constraint Details: - - 0.371ns physical path delay SLICE_50 to SLICE_33 meets - -0.013ns DIN_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.060ns) by 5.431ns - - Physical Path Details: - - Data path SLICE_50 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R10C15D.CLK to R10C15D.Q0 SLICE_50 (from PHI2_c) -ROUTE 1 0.137 R10C15D.Q0 to R10C16A.C0 XOR8MEG -CTOF_DEL --- 0.101 R10C16A.C0 to R10C16A.F0 SLICE_33 -ROUTE 1 0.000 R10C16A.F0 to R10C16A.DI0 RA11_N_184 (to PHI2_c) - -------- - 0.371 (63.1% logic, 36.9% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R10C16A.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) - FF CmdUFMCLK_413 - - Delay: 0.917ns (47.5% logic, 52.5% route), 4 logic levels. - - Constraint Details: - - 0.917ns physical path delay SLICE_93 to SLICE_100 meets - -0.028ns CE_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.075ns) by 5.992ns - - Physical Path Details: - - Data path SLICE_93 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R9C16A.CLK to R9C16A.Q0 SLICE_93 (from PHI2_c) -ROUTE 1 0.138 R9C16A.Q0 to R9C15A.C1 Bank_0 -CTOF_DEL --- 0.101 R9C15A.C1 to R9C15A.F1 SLICE_100 -ROUTE 1 0.053 R9C15A.F1 to R9C15B.D1 n2277 -CTOF_DEL --- 0.101 R9C15B.D1 to R9C15B.F1 SLICE_74 -ROUTE 8 0.142 R9C15B.F1 to R10C15A.D1 n26 -CTOF_DEL --- 0.101 R10C15A.D1 to R10C15A.F1 SLICE_73 -ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) - -------- - 0.917 (47.5% logic, 52.5% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C16A.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c - -------- - 1.203 (0.0% logic, 100.0% route), 0 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 - | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 335 (setup), 0 (hold) -Score: 391939 (setup), 0 (hold) -Cumulative negative slack: 304509 (304509+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html deleted file mode 100644 index 5f15130..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html +++ /dev/null @@ -1,152 +0,0 @@ - -Bitgen Report - - -

BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:42 2023
-
-
-Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                         2.08**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                      JTAG_PORT  |                       ENABLE**  |
-+---------------------------------+---------------------------------+
-|                       SDM_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                       I2C_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  CONFIGURATION  |                          CFG**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                        MY_ASSP  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|               ONE_TIME_PROGRAM  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                 ENABLE_TRANSFR  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  SHAREDEBRINIT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 1.95.
- 
-Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
- 
-===========
-UFM Summary.
-===========
-UFM Size:        511 Pages (128*511 Bits).
-UFM Utilization: General Purpose Flash Memory.
- 
-Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
-Initialized UFM Pages:                     0 Page.
- 
-Total CPU Time: 2 secs 
-Total REAL Time: 3 secs 
-Peak Memory Usage: 253 MB
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html deleted file mode 100644 index 7e2eb91..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html +++ /dev/null @@ -1,204 +0,0 @@ - -I/O Timing Report - - -
I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:22:17 2023
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     0.891      4       0.676     4
-CROW[1] nCRAS F     0.281      4       1.216     4
-Din[0]  PHI2  F     7.907      4       0.089     6
-Din[0]  nCCAS F     1.465      4       0.158     4
-Din[1]  PHI2  F     7.300      4       1.026     4
-Din[1]  nCCAS F     1.035      4       0.527     4
-Din[2]  PHI2  F     6.237      4       1.467     4
-Din[2]  nCCAS F     1.719      4      -0.108     M
-Din[3]  PHI2  F     6.623      4       0.176     6
-Din[3]  nCCAS F     0.339      4       0.916     4
-Din[4]  PHI2  F     6.902      4       1.033     4
-Din[4]  nCCAS F     0.687      4       0.951     4
-Din[5]  PHI2  F     6.837      4       1.369     4
-Din[5]  nCCAS F     2.810      4      -0.220     M
-Din[6]  PHI2  F     7.648      4      -0.050     M
-Din[6]  nCCAS F     1.281      4       0.266     4
-Din[7]  PHI2  F     7.823      4      -0.159     M
-Din[7]  nCCAS F     1.810      4      -0.096     M
-MAin[0] PHI2  F     6.751      4      -0.273     M
-MAin[0] nCRAS F     1.765      4      -0.033     4
-MAin[1] PHI2  F     5.718      4       0.117     M
-MAin[1] nCRAS F     1.814      4      -0.051     M
-MAin[2] PHI2  F     5.759      4      -0.021     M
-MAin[2] nCRAS F     1.323      4       0.309     4
-MAin[3] PHI2  F     6.165      4      -0.235     M
-MAin[3] nCRAS F     0.694      4       0.836     4
-MAin[4] PHI2  F     5.236      4      -0.147     M
-MAin[4] nCRAS F     0.730      4       0.835     4
-MAin[5] PHI2  F     6.024      4       0.135     M
-MAin[5] nCRAS F     0.734      4       0.868     4
-MAin[6] PHI2  F     5.689      4      -0.277     M
-MAin[6] nCRAS F     0.288      4       1.210     4
-MAin[7] PHI2  F     6.398      4      -0.307     M
-MAin[7] nCRAS F     1.215      4       0.401     4
-MAin[8] nCRAS F     0.817      4       0.727     4
-MAin[9] nCRAS F     0.941      4       0.601     4
-PHI2    RCLK  R     0.771      4       1.143     4
-UFMSDO  RCLK  R    -0.238      M       2.305     4
-nCCAS   RCLK  R     1.651      4       0.388     4
-nCCAS   nCRAS F     5.028      4      -0.828     M
-nCRAS   RCLK  R     0.593      4       1.309     4
-nFWE    PHI2  F     5.741      4       0.781     4
-nFWE    nCRAS F     0.578      4       0.996     4
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    14.758         4        4.129          M
-LED    nCRAS F    12.396         4        3.434          M
-RA[0]  RCLK  R    13.780         4        3.894          M
-RA[0]  nCRAS F    11.795         4        3.277          M
-RA[10] RCLK  R    12.425         4        3.587          M
-RA[11] PHI2  R    10.432         4        3.084          M
-RA[1]  RCLK  R    15.081         4        4.198          M
-RA[1]  nCRAS F    12.364         4        3.447          M
-RA[2]  RCLK  R    14.518         4        4.082          M
-RA[2]  nCRAS F    11.696         4        3.275          M
-RA[3]  RCLK  R    13.789         4        3.897          M
-RA[3]  nCRAS F    12.223         4        3.392          M
-RA[4]  RCLK  R    15.175         4        4.228          M
-RA[4]  nCRAS F    12.424         4        3.464          M
-RA[5]  RCLK  R    13.789         4        3.897          M
-RA[5]  nCRAS F    12.359         4        3.437          M
-RA[6]  RCLK  R    15.420         4        4.299          M
-RA[6]  nCRAS F    12.865         4        3.560          M
-RA[7]  RCLK  R    14.672         4        4.127          M
-RA[7]  nCRAS F    12.253         4        3.386          M
-RA[8]  RCLK  R    14.952         4        4.191          M
-RA[8]  nCRAS F    12.244         4        3.383          M
-RA[9]  RCLK  R    14.092         4        3.978          M
-RA[9]  nCRAS F    13.164         4        3.653          M
-RBA[0] nCRAS F    10.278         4        2.970          M
-RBA[1] nCRAS F    10.474         4        3.030          M
-RCKE   RCLK  R    12.407         4        3.610          M
-RDQMH  RCLK  R    13.754         4        3.857          M
-RDQML  RCLK  R    13.482         4        3.833          M
-RD[0]  nCCAS F    10.515         4        3.076          M
-RD[1]  nCCAS F    10.118         4        2.965          M
-RD[2]  nCCAS F     9.759         4        2.886          M
-RD[3]  nCCAS F     9.798         4        2.878          M
-RD[4]  nCCAS F    10.979         4        3.178          M
-RD[5]  nCCAS F    11.063         4        3.207          M
-RD[6]  nCCAS F    10.317         4        3.018          M
-RD[7]  nCCAS F    10.232         4        2.986          M
-UFMCLK RCLK  R    12.402         4        3.606          M
-UFMSDI RCLK  R    11.975         4        3.501          M
-nRCAS  RCLK  R    12.350         4        3.564          M
-nRCS   RCLK  R    11.923         4        3.459          M
-nRRAS  RCLK  R    11.995         4        3.494          M
-nRWE   RCLK  R    11.975         4        3.501          M
-nUFMCS RCLK  R    11.818         4        3.434          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with hold speed: 6
-WARNING: you must also run trce with setup speed: M
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj deleted file mode 100644 index 7edeb6a..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj +++ /dev/null @@ -1,41 +0,0 @@ --a "MachXO2" --d LCMXO2-1200HC --t TQFP100 --s 4 --frequency 200 --optimization_goal Balanced --bram_utilization 100 --ramstyle Auto --romstyle auto --dsp_utilization 100 --use_dsp 1 --use_carry_chain 1 --carry_chain_length 0 --force_gsr Auto --resource_sharing 1 --propagate_constants 1 --remove_duplicate_regs 1 --mux_style Auto --max_fanout 1000 --fsm_encoding_style Auto --twr_paths 3 --fix_gated_clocks 1 --loop_limit 1950 - - - --use_io_insertion 1 --resolve_mixed_drivers 0 --use_io_reg auto - - --lpf 1 --p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" --ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" --top RAM2GS - - --p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" - --ngd "RAM2GS_LCMXO2_1200HC_impl1.ngd" - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd deleted file mode 100644 index 4f5aca5..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd +++ /dev/null @@ -1,15 +0,0 @@ -[ActiveSupport MAP] -Device = LCMXO2-1200HC; -Package = TQFP100; -Performance = 4; -LUTS_avail = 1280; -LUTS_used = 143; -FF_avail = 1360; -FF_used = 102; -INPUT_LVCMOS25 = 26; -OUTPUT_LVCMOS25 = 33; -BIDI_LVCMOS25 = 8; -IO_avail = 80; -IO_used = 67; -EBR_avail = 7; -EBR_used = 0; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam deleted file mode 100644 index 764d169..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam +++ /dev/null @@ -1,88 +0,0 @@ -[ START MERGED ] -n2380 Ready -PHI2_N_120 PHI2_c -nRWE_N_176 nRWE_N_177 -n1407 nRowColSel_N_34 -n1408 nRowColSel_N_35 -[ END MERGED ] -[ START CLIPPED ] -GND_net -VCC_net -FS_610_add_4_19/S1 -FS_610_add_4_19/CO -FS_610_add_4_1/S0 -FS_610_add_4_1/CI -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:06 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[9]" SITE "63" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nFWE" SITE "28" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "UFMSDO" SITE "27" ; -SCHEMATIC END ; -[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr deleted file mode 100644 index a9cd083..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr +++ /dev/null @@ -1,10 +0,0 @@ ---------------------------------------------------- -Report for cell RAM2GS - Instance path: RAM2GS - Cell usage: - cell count Res Usage(%) - SLIC 75.00 100.0 - LUT4 123.00 100.0 - IOBUF 67 100.0 - PFUREG 102 100.0 - RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd deleted file mode 100644 index 2f8eda47865862a99814b4c51fef644bc9ba6125..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 140118 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F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hfaaa; - defparam inst1.INIT1 = 16'hfaaa; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; - - vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hF000; - defparam inst1.INIT1 = 16'h0555; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), - .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), - .CO1()); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hfaaa; - defparam inst1.INIT1 = 16'h0000; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut4 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - - lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40010 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - - lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40011 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - - lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; - - lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - endspecify - -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - - lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; - - lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output - F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40024 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - - lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - - lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); - wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; - - lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\i30/SLICE_71/i30/GATE_H0 )); - selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), - .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40065 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); - - xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), - .PADI(RD7)); - - specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); - endspecify - -endmodule - -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); - - IBPD INST1( .I(PADI), .O(Z)); - OBZPD INST2( .I(I), .T(T), .O(PAD)); -endmodule - -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); - - xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), - .PADI(RD6)); - - specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); - endspecify - -endmodule - -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); - - xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), - .PADI(RD5)); - - specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); - endspecify - -endmodule - -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); - - xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), - .PADI(RD4)); - - specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); - endspecify - -endmodule - -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); - - xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), - .PADI(RD3)); - - specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); - endspecify - -endmodule - -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); - - xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), - .PADI(RD2)); - - specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); - endspecify - -endmodule - -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); - - xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), - .PADI(RD1)); - - specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); - endspecify - -endmodule - -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); - - xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), - .PADI(RD0)); - - specify - (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); - endspecify - -endmodule - -module Dout_7_ ( input PADDO, output Dout7 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module xo2iobuf0068 ( input I, T, output PAD ); - - OBZPD INST5( .I(I), .T(T), .O(PAD)); -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_0_ ( input PADDO, output Dout0 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module LED ( input PADDO, output LED ); - wire GNDI; - - xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RBA_1_ ( input PADDO, output RBA1 ); - wire GNDI; - - xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RBA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RBA_0_ ( input PADDO, output RBA0 ); - wire GNDI; - - xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RBA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_11_ ( input PADDO, output RA11 ); - wire GNDI; - - xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_10_ ( input PADDO, output RA10 ); - wire GNDI; - - xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_9_ ( input PADDO, output RA9 ); - wire GNDI; - - xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_8_ ( input PADDO, output RA8 ); - wire GNDI; - - xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_7_ ( input PADDO, output RA7 ); - wire GNDI; - - xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_6_ ( input PADDO, output RA6 ); - wire GNDI; - - xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_5_ ( input PADDO, output RA5 ); - wire GNDI; - - xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_4_ ( input PADDO, output RA4 ); - wire GNDI; - - xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_3_ ( input PADDO, output RA3 ); - wire GNDI; - - xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_2_ ( input PADDO, output RA2 ); - wire GNDI; - - xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_1_ ( input PADDO, output RA1 ); - wire GNDI; - - xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_0_ ( input PADDO, output RA0 ); - wire GNDI; - - xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRCS ( input PADDO, output nRCS ); - wire GNDI; - - xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRCS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RCKE ( input PADDO, output RCKE ); - wire GNDI; - - xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RCKE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWE ( input PADDO, output nRWE ); - wire GNDI; - - xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRWE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRRAS ( input PADDO, output nRRAS ); - wire GNDI; - - xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRRAS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRCAS ( input PADDO, output nRCAS ); - wire GNDI; - - xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRCAS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RDQMH ( input PADDO, output RDQMH ); - wire GNDI; - - xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RDQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RDQML ( input PADDO, output RDQML ); - wire GNDI; - - xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RDQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nUFMCS ( input PADDO, output nUFMCS ); - wire GNDI; - - xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nUFMCS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module UFMCLK ( input PADDO, output UFMCLK ); - wire GNDI; - - xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => UFMCLK) = (0:0:0,0:0:0); - endspecify - -endmodule - -module UFMSDI ( input PADDO, output UFMSDI ); - wire GNDI; - - xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => UFMSDI) = (0:0:0,0:0:0); - endspecify - -endmodule - -module PHI2 ( output PADDI, input PHI2 ); - - xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); - - specify - (PHI2 => PADDI) = (0:0:0,0:0:0); - $width (posedge PHI2, 0:0:0); - $width (negedge PHI2, 0:0:0); - endspecify - -endmodule - -module xo2iobuf0069 ( output Z, input PAD ); - - IBPD INST1( .I(PAD), .O(Z)); -endmodule - -module MAin_9_ ( output PADDI, input MAin9 ); - - xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); - - specify - (MAin9 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin9, 0:0:0); - $width (negedge MAin9, 0:0:0); - endspecify - -endmodule - -module MAin_8_ ( output PADDI, input MAin8 ); - - xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); - - specify - (MAin8 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin8, 0:0:0); - $width (negedge MAin8, 0:0:0); - endspecify - -endmodule - -module MAin_7_ ( output PADDI, input MAin7 ); - - xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); - - specify - (MAin7 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin7, 0:0:0); - $width (negedge MAin7, 0:0:0); - endspecify - -endmodule - -module MAin_6_ ( output PADDI, input MAin6 ); - - xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); - - specify - (MAin6 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin6, 0:0:0); - $width (negedge MAin6, 0:0:0); - endspecify - -endmodule - -module MAin_5_ ( output PADDI, input MAin5 ); - - xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); - - specify - (MAin5 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin5, 0:0:0); - $width (negedge MAin5, 0:0:0); - endspecify - -endmodule - -module MAin_4_ ( output PADDI, input MAin4 ); - - xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); - - specify - (MAin4 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin4, 0:0:0); - $width (negedge MAin4, 0:0:0); - endspecify - -endmodule - -module MAin_3_ ( output PADDI, input MAin3 ); - - xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); - - specify - (MAin3 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin3, 0:0:0); - $width (negedge MAin3, 0:0:0); - endspecify - -endmodule - -module MAin_2_ ( output PADDI, input MAin2 ); - - xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); - - specify - (MAin2 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin2, 0:0:0); - $width (negedge MAin2, 0:0:0); - endspecify - -endmodule - -module MAin_1_ ( output PADDI, input MAin1 ); - - xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); - - specify - (MAin1 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin1, 0:0:0); - $width (negedge MAin1, 0:0:0); - endspecify - -endmodule - -module MAin_0_ ( output PADDI, input MAin0 ); - - xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); - - specify - (MAin0 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin0, 0:0:0); - $width (negedge MAin0, 0:0:0); - endspecify - -endmodule - -module CROW_1_ ( output PADDI, input CROW1 ); - - xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); - - specify - (CROW1 => PADDI) = (0:0:0,0:0:0); - $width (posedge CROW1, 0:0:0); - $width (negedge CROW1, 0:0:0); - endspecify - -endmodule - -module CROW_0_ ( output PADDI, input CROW0 ); - - xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); - - specify - (CROW0 => PADDI) = (0:0:0,0:0:0); - $width (posedge CROW0, 0:0:0); - $width (negedge CROW0, 0:0:0); - endspecify - -endmodule - -module Din_7_ ( output PADDI, input Din7 ); - - xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); - - specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); - endspecify - -endmodule - -module Din_6_ ( output PADDI, input Din6 ); - - xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); - - specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); - endspecify - -endmodule - -module Din_5_ ( output PADDI, input Din5 ); - - xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); - - specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); - endspecify - -endmodule - -module Din_4_ ( output PADDI, input Din4 ); - - xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); - - specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); - endspecify - -endmodule - -module Din_3_ ( output PADDI, input Din3 ); - - xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); - - specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); - endspecify - -endmodule - -module Din_2_ ( output PADDI, input Din2 ); - - xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); - - specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); - endspecify - -endmodule - -module Din_1_ ( output PADDI, input Din1 ); - - xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); - - specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); - endspecify - -endmodule - -module Din_0_ ( output PADDI, input Din0 ); - - xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); - - specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); - endspecify - -endmodule - -module nCCAS ( output PADDI, input nCCAS ); - - xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); - - specify - (nCCAS => PADDI) = (0:0:0,0:0:0); - $width (posedge nCCAS, 0:0:0); - $width (negedge nCCAS, 0:0:0); - endspecify - -endmodule - -module nCRAS ( output PADDI, input nCRAS ); - - xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); - - specify - (nCRAS => PADDI) = (0:0:0,0:0:0); - $width (posedge nCRAS, 0:0:0); - $width (negedge nCRAS, 0:0:0); - endspecify - -endmodule - -module nFWE ( output PADDI, input nFWE ); - - xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); - - specify - (nFWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nFWE, 0:0:0); - $width (negedge nFWE, 0:0:0); - endspecify - -endmodule - -module RCLK ( output PADDI, input RCLK ); - - xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); - - specify - (RCLK => PADDI) = (0:0:0,0:0:0); - $width (posedge RCLK, 0:0:0); - $width (negedge RCLK, 0:0:0); - endspecify - -endmodule - -module UFMSDO ( output PADDI, input UFMSDO ); - - xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); - - specify - (UFMSDO => PADDI) = (0:0:0,0:0:0); - $width (posedge UFMSDO, 0:0:0); - $width (negedge UFMSDO, 0:0:0); - endspecify - -endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html deleted file mode 100644 index acc608c..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html +++ /dev/null @@ -1,425 +0,0 @@ - -Project Summary - - -

-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-
-Design Information
-
-Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
-     RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
-     RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
-     neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
-     HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
-     M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO2-1200HCTQFP100
-Target Performance:   4
-Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:22:05
-
-
-Design Summary
-   Number of registers:    102 out of  1520 (7%)
-      PFU registers:          102 out of  1280 (8%)
-      PIO registers:            0 out of   240 (0%)
-   Number of SLICEs:        75 out of   640 (12%)
-      SLICEs as Logic/ROM:     75 out of   640 (12%)
-      SLICEs as RAM:            0 out of   480 (0%)
-      SLICEs as Carry:         10 out of   640 (2%)
-   Number of LUT4s:        143 out of  1280 (11%)
-      Number used as logic LUTs:        123
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       20
-      Number used as shift registers:     0
-   Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
-   Number of block RAMs:  0 out of 7 (0%)
-   Number of GSRs:        0 out of 1 (0%)
-   EFB used :        No
-   JTAG used :       No
-   Readback used :   No
-   Oscillator used : No
-   Startup used :    No
-   POR :             On
-   Bandgap :         On
-   Number of Power Controller:  0 out of 1 (0%)
-   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
-   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
-   Number of DCCA:  0 out of 8 (0%)
-   Number of DCMA:  0 out of 2 (0%)
-   Number of PLLs:  0 out of 1 (0%)
-   Number of DQSDLLs:  0 out of 2 (0%)
-   Number of CLKDIVC:  0 out of 4 (0%)
-   Number of ECLKSYNCA:  0 out of 4 (0%)
-   Number of ECLKBRIDGECS:  0 out of 2 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
-
-     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
-   Number of Clock Enables:  14
-     Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
-     Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
-     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
-     Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
-     Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
-     Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
-     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
-     Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
-     Net Ready_N_292: 1 loads, 1 LSLICEs
-     Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
-   Number of LSRs:  7
-     Net RASr2: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
-     Net Ready: 7 loads, 7 LSLICEs
-     Net nRWE_N_177: 1 loads, 1 LSLICEs
-     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
-     Net n2366: 2 loads, 2 LSLICEs
-     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net Ready: 18 loads
-     Net InitReady: 15 loads
-     Net RASr2: 15 loads
-     Net nRowColSel_N_35: 13 loads
-     Net nRowColSel: 12 loads
-     Net Din_c_4: 10 loads
-     Net MAin_c_1: 10 loads
-     Net Din_c_5: 9 loads
-     Net MAin_c_0: 9 loads
-     Net Din_c_0: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-   No errors or warnings present.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+
-| IO Name             | Direction | Levelmode | IO         |
-
-|                     |           |  IO_TYPE  | Register   |
-+---------------------+-----------+-----------+------------+
-| RD[7]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[6]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[5]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[4]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[3]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[2]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[1]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RD[0]               | BIDIR     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| LED                 | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RBA[1]              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RBA[0]              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| RA[3]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nRCS                | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RCKE                | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nRRAS               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nRCAS               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RDQMH               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RDQML               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nUFMCS              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| UFMCLK              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| UFMSDI              | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| PHI2                | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[9]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[8]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[7]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[6]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[5]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[4]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[3]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[2]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[1]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| MAin[0]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| CROW[1]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| CROW[0]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[7]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| Din[6]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[5]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[4]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[3]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[2]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[1]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| Din[0]              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nCCAS               | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nCRAS               | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| nFWE                | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| RCLK                | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| UFMSDO              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-
-
-Removed logic
-
-Block i2 undriven or does not drive anything - clipped.
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal PHI2_N_120 was merged into signal PHI2_c
-Signal n1407 was merged into signal nRowColSel_N_34
-Signal n2380 was merged into signal Ready
-Signal n1408 was merged into signal nRowColSel_N_35
-Signal nRWE_N_176 was merged into signal nRWE_N_177
-Signal GND_net undriven or does not drive anything - clipped.
-Signal VCC_net undriven or does not drive anything - clipped.
-Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
-Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
-Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
-Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
-Block i2046 was optimized away.
-Block i1118_1_lut was optimized away.
-Block i637_1_lut_rep_31 was optimized away.
-Block i1119_1_lut was optimized away.
-Block nRWE_I_50_1_lut was optimized away.
-Block i1 was optimized away.
-
-     
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 41 MB
-
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-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html deleted file mode 100644 index 232f92e..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html +++ /dev/null @@ -1,374 +0,0 @@ - -PAD Specification File - - -
PAD Specification File
-***************************
-
-PART TYPE:        LCMXO2-1200HC
-Performance Grade:      4
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.44
-
-Tue Aug 15 05:22:12 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                               |
-+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
-| CROW[0]   | 10/3     | LVCMOS25_IN   | PL4B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| CROW[1]   | 16/3     | LVCMOS25_IN   | PL8A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[0]    | 3/3      | LVCMOS25_IN   | PL3A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[1]    | 96/0     | LVCMOS25_IN   | PT10B |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[2]    | 88/0     | LVCMOS25_IN   | PT12A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[3]    | 97/0     | LVCMOS25_IN   | PT10A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[4]    | 99/0     | LVCMOS25_IN   | PT9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[5]    | 98/0     | LVCMOS25_IN   | PT9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[6]    | 2/3      | LVCMOS25_IN   | PL2D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Din[7]    | 1/3      | LVCMOS25_IN   | PL2C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| Dout[0]   | 76/0     | LVCMOS25_OUT  | PT17D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[1]   | 86/0     | LVCMOS25_OUT  | PT12C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[2]   | 87/0     | LVCMOS25_OUT  | PT12B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[3]   | 85/0     | LVCMOS25_OUT  | PT12D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[4]   | 83/0     | LVCMOS25_OUT  | PT15B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[5]   | 84/0     | LVCMOS25_OUT  | PT15A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[6]   | 78/0     | LVCMOS25_OUT  | PT16C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| Dout[7]   | 82/0     | LVCMOS25_OUT  | PT15C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| LED       | 34/2     | LVCMOS25_OUT  | PB9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| MAin[0]   | 14/3     | LVCMOS25_IN   | PL5C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[1]   | 12/3     | LVCMOS25_IN   | PL5A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[2]   | 13/3     | LVCMOS25_IN   | PL5B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[3]   | 21/3     | LVCMOS25_IN   | PL9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[4]   | 20/3     | LVCMOS25_IN   | PL9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[5]   | 19/3     | LVCMOS25_IN   | PL8D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[6]   | 24/3     | LVCMOS25_IN   | PL10C |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[7]   | 18/3     | LVCMOS25_IN   | PL8C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[8]   | 25/3     | LVCMOS25_IN   | PL10D |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| MAin[9]   | 32/2     | LVCMOS25_IN   | PB6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| PHI2      | 8/3      | LVCMOS25_IN   | PL3D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| RA[0]     | 66/1     | LVCMOS25_OUT  | PR4D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[10]    | 64/1     | LVCMOS25_OUT  | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[11]    | 59/1     | LVCMOS25_OUT  | PR8D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[1]     | 67/1     | LVCMOS25_OUT  | PR4C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[2]     | 69/1     | LVCMOS25_OUT  | PR4A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[3]     | 71/1     | LVCMOS25_OUT  | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[4]     | 74/1     | LVCMOS25_OUT  | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[5]     | 70/1     | LVCMOS25_OUT  | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[6]     | 68/1     | LVCMOS25_OUT  | PR4B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[7]     | 75/1     | LVCMOS25_OUT  | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[8]     | 65/1     | LVCMOS25_OUT  | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RA[9]     | 63/1     | LVCMOS25_OUT  | PR5C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RBA[0]    | 58/1     | LVCMOS25_OUT  | PR9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RBA[1]    | 60/1     | LVCMOS25_OUT  | PR8C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RCKE      | 53/1     | LVCMOS25_OUT  | PR9D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RCLK      | 62/1     | LVCMOS25_IN   | PR5D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| RDQMH     | 51/1     | LVCMOS25_OUT  | PR10D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RDQML     | 48/2     | LVCMOS25_OUT  | PB20C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| RD[0]     | 36/2     | LVCMOS25_BIDI | PB11C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[1]     | 37/2     | LVCMOS25_BIDI | PB11D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[2]     | 38/2     | LVCMOS25_BIDI | PB11A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[3]     | 39/2     | LVCMOS25_BIDI | PB11B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[4]     | 40/2     | LVCMOS25_BIDI | PB15A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[5]     | 41/2     | LVCMOS25_BIDI | PB15B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[6]     | 42/2     | LVCMOS25_BIDI | PB18A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[7]     | 43/2     | LVCMOS25_BIDI | PB18B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| UFMCLK    | 29/2     | LVCMOS25_OUT  | PB6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| UFMSDI    | 30/2     | LVCMOS25_OUT  | PB6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| UFMSDO    | 27/2     | LVCMOS25_IN   | PB4C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| nCCAS     | 9/3      | LVCMOS25_IN   | PL4A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| nCRAS     | 17/3     | LVCMOS25_IN   | PL8B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| nFWE      | 28/2     | LVCMOS25_IN   | PB4D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
-| nRCAS     | 52/1     | LVCMOS25_OUT  | PR10C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| nRCS      | 57/1     | LVCMOS25_OUT  | PR9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| nRRAS     | 54/1     | LVCMOS25_OUT  | PR9C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| nRWE      | 49/2     | LVCMOS25_OUT  | PB20D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-| nUFMCS    | 47/2     | LVCMOS25_OUT  | PB18D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
-+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 2.5V  |
-| 1    | 2.5V  |
-| 2    | 2.5V  |
-| 3    | 2.5V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| 1/3      | Din[7]                | LOCATED    | LVCMOS25_IN   | PL2C  | L_GPLLT_IN    |           |           |
-| 2/3      | Din[6]                | LOCATED    | LVCMOS25_IN   | PL2D  | L_GPLLC_IN    |           |           |
-| 3/3      | Din[0]                | LOCATED    | LVCMOS25_IN   | PL3A  | PCLKT3_2      |           |           |
-| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
-| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
-| 8/3      | PHI2                  | LOCATED    | LVCMOS25_IN   | PL3D  |               |           |           |
-| 9/3      | nCCAS                 | LOCATED    | LVCMOS25_IN   | PL4A  |               |           |           |
-| 10/3     | CROW[0]               | LOCATED    | LVCMOS25_IN   | PL4B  |               |           |           |
-| 12/3     | MAin[1]               | LOCATED    | LVCMOS25_IN   | PL5A  | PCLKT3_1      |           |           |
-| 13/3     | MAin[2]               | LOCATED    | LVCMOS25_IN   | PL5B  | PCLKC3_1      |           |           |
-| 14/3     | MAin[0]               | LOCATED    | LVCMOS25_IN   | PL5C  |               |           |           |
-| 15/3     |     unused, PULL:DOWN |            |               | PL5D  |               |           |           |
-| 16/3     | CROW[1]               | LOCATED    | LVCMOS25_IN   | PL8A  |               |           |           |
-| 17/3     | nCRAS                 | LOCATED    | LVCMOS25_IN   | PL8B  |               |           |           |
-| 18/3     | MAin[7]               | LOCATED    | LVCMOS25_IN   | PL8C  |               |           |           |
-| 19/3     | MAin[5]               | LOCATED    | LVCMOS25_IN   | PL8D  |               |           |           |
-| 20/3     | MAin[4]               | LOCATED    | LVCMOS25_IN   | PL9A  | PCLKT3_0      |           |           |
-| 21/3     | MAin[3]               | LOCATED    | LVCMOS25_IN   | PL9B  | PCLKC3_0      |           |           |
-| 24/3     | MAin[6]               | LOCATED    | LVCMOS25_IN   | PL10C |               |           |           |
-| 25/3     | MAin[8]               | LOCATED    | LVCMOS25_IN   | PL10D |               |           |           |
-| 27/2     | UFMSDO                | LOCATED    | LVCMOS25_IN   | PB4C  | CSSPIN        |           |           |
-| 28/2     | nFWE                  | LOCATED    | LVCMOS25_IN   | PB4D  |               |           |           |
-| 29/2     | UFMCLK                | LOCATED    | LVCMOS25_OUT  | PB6A  |               |           |           |
-| 30/2     | UFMSDI                | LOCATED    | LVCMOS25_OUT  | PB6B  |               |           |           |
-| 31/2     |     unused, PULL:DOWN |            |               | PB6C  | MCLK/CCLK     |           |           |
-| 32/2     | MAin[9]               | LOCATED    | LVCMOS25_IN   | PB6D  | SO/SPISO      |           |           |
-| 34/2     | LED                   | LOCATED    | LVCMOS25_OUT  | PB9A  | PCLKT2_0      |           |           |
-| 35/2     |     unused, PULL:DOWN |            |               | PB9B  | PCLKC2_0      |           |           |
-| 36/2     | RD[0]                 | LOCATED    | LVCMOS25_BIDI | PB11C |               |           |           |
-| 37/2     | RD[1]                 | LOCATED    | LVCMOS25_BIDI | PB11D |               |           |           |
-| 38/2     | RD[2]                 | LOCATED    | LVCMOS25_BIDI | PB11A | PCLKT2_1      |           |           |
-| 39/2     | RD[3]                 | LOCATED    | LVCMOS25_BIDI | PB11B | PCLKC2_1      |           |           |
-| 40/2     | RD[4]                 | LOCATED    | LVCMOS25_BIDI | PB15A |               |           |           |
-| 41/2     | RD[5]                 | LOCATED    | LVCMOS25_BIDI | PB15B |               |           |           |
-| 42/2     | RD[6]                 | LOCATED    | LVCMOS25_BIDI | PB18A |               |           |           |
-| 43/2     | RD[7]                 | LOCATED    | LVCMOS25_BIDI | PB18B |               |           |           |
-| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
-| 47/2     | nUFMCS                |            | LVCMOS25_OUT  | PB18D |               |           |           |
-| 48/2     | RDQML                 | LOCATED    | LVCMOS25_OUT  | PB20C | SN            |           |           |
-| 49/2     | nRWE                  | LOCATED    | LVCMOS25_OUT  | PB20D | SI/SISPI      |           |           |
-| 51/1     | RDQMH                 | LOCATED    | LVCMOS25_OUT  | PR10D | DQ1           |           |           |
-| 52/1     | nRCAS                 | LOCATED    | LVCMOS25_OUT  | PR10C | DQ1           |           |           |
-| 53/1     | RCKE                  | LOCATED    | LVCMOS25_OUT  | PR9D  | DQ1           |           |           |
-| 54/1     | nRRAS                 | LOCATED    | LVCMOS25_OUT  | PR9C  | DQ1           |           |           |
-| 57/1     | nRCS                  | LOCATED    | LVCMOS25_OUT  | PR9B  | DQ1           |           |           |
-| 58/1     | RBA[0]                | LOCATED    | LVCMOS25_OUT  | PR9A  | DQ1           |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVCMOS25_OUT  | PR8D  | DQ1           |           |           |
-| 60/1     | RBA[1]                | LOCATED    | LVCMOS25_OUT  | PR8C  | DQ1           |           |           |
-| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
-| 62/1     | RCLK                  | LOCATED    | LVCMOS25_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
-| 63/1     | RA[9]                 | LOCATED    | LVCMOS25_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVCMOS25_OUT  | PR5B  | DQS0N         |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVCMOS25_OUT  | PR5A  | DQS0          |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVCMOS25_OUT  | PR4D  | DQ0           |           |           |
-| 67/1     | RA[1]                 | LOCATED    | LVCMOS25_OUT  | PR4C  | DQ0           |           |           |
-| 68/1     | RA[6]                 | LOCATED    | LVCMOS25_OUT  | PR4B  | DQ0           |           |           |
-| 69/1     | RA[2]                 | LOCATED    | LVCMOS25_OUT  | PR4A  | DQ0           |           |           |
-| 70/1     | RA[5]                 | LOCATED    | LVCMOS25_OUT  | PR3B  | DQ0           |           |           |
-| 71/1     | RA[3]                 | LOCATED    | LVCMOS25_OUT  | PR3A  | DQ0           |           |           |
-| 74/1     | RA[4]                 | LOCATED    | LVCMOS25_OUT  | PR2B  | DQ0           |           |           |
-| 75/1     | RA[7]                 | LOCATED    | LVCMOS25_OUT  | PR2A  | DQ0           |           |           |
-| 76/0     | Dout[0]               | LOCATED    | LVCMOS25_OUT  | PT17D | DONE          |           |           |
-| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
-| 78/0     | Dout[6]               | LOCATED    | LVCMOS25_OUT  | PT16C |               |           |           |
-| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
-| 82/0     | Dout[7]               | LOCATED    | LVCMOS25_OUT  | PT15C | JTAGENB       |           |           |
-| 83/0     | Dout[4]               | LOCATED    | LVCMOS25_OUT  | PT15B |               |           |           |
-| 84/0     | Dout[5]               | LOCATED    | LVCMOS25_OUT  | PT15A |               |           |           |
-| 85/0     | Dout[3]               | LOCATED    | LVCMOS25_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
-| 86/0     | Dout[1]               | LOCATED    | LVCMOS25_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
-| 87/0     | Dout[2]               | LOCATED    | LVCMOS25_OUT  | PT12B | PCLKC0_1      |           |           |
-| 88/0     | Din[2]                | LOCATED    | LVCMOS25_IN   | PT12A | PCLKT0_1      |           |           |
-| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
-| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
-| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
-| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
-| 96/0     | Din[1]                | LOCATED    | LVCMOS25_IN   | PT10B |               |           |           |
-| 97/0     | Din[3]                | LOCATED    | LVCMOS25_IN   | PT10A |               |           |           |
-| 98/0     | Din[5]                | LOCATED    | LVCMOS25_IN   | PT9B  |               |           |           |
-| 99/0     | Din[4]                | LOCATED    | LVCMOS25_IN   | PT9A  |               |           |           |
-| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
-| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
-| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
-| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
-| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
-| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
-| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
-| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
-| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
-| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
-| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
-| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
-| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
-| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
-| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
-| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
-| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
-| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
-| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
-| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
-| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
-| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
-| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
-| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
-| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
-| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
-| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
-| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-
-sysCONFIG Pins:
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
-| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
-| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
-| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-
-Dedicated sysCONFIG Pins:
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "10";
-LOCATE  COMP  "CROW[1]"  SITE  "16";
-LOCATE  COMP  "Din[0]"  SITE  "3";
-LOCATE  COMP  "Din[1]"  SITE  "96";
-LOCATE  COMP  "Din[2]"  SITE  "88";
-LOCATE  COMP  "Din[3]"  SITE  "97";
-LOCATE  COMP  "Din[4]"  SITE  "99";
-LOCATE  COMP  "Din[5]"  SITE  "98";
-LOCATE  COMP  "Din[6]"  SITE  "2";
-LOCATE  COMP  "Din[7]"  SITE  "1";
-LOCATE  COMP  "Dout[0]"  SITE  "76";
-LOCATE  COMP  "Dout[1]"  SITE  "86";
-LOCATE  COMP  "Dout[2]"  SITE  "87";
-LOCATE  COMP  "Dout[3]"  SITE  "85";
-LOCATE  COMP  "Dout[4]"  SITE  "83";
-LOCATE  COMP  "Dout[5]"  SITE  "84";
-LOCATE  COMP  "Dout[6]"  SITE  "78";
-LOCATE  COMP  "Dout[7]"  SITE  "82";
-LOCATE  COMP  "LED"  SITE  "34";
-LOCATE  COMP  "MAin[0]"  SITE  "14";
-LOCATE  COMP  "MAin[1]"  SITE  "12";
-LOCATE  COMP  "MAin[2]"  SITE  "13";
-LOCATE  COMP  "MAin[3]"  SITE  "21";
-LOCATE  COMP  "MAin[4]"  SITE  "20";
-LOCATE  COMP  "MAin[5]"  SITE  "19";
-LOCATE  COMP  "MAin[6]"  SITE  "24";
-LOCATE  COMP  "MAin[7]"  SITE  "18";
-LOCATE  COMP  "MAin[8]"  SITE  "25";
-LOCATE  COMP  "MAin[9]"  SITE  "32";
-LOCATE  COMP  "PHI2"  SITE  "8";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "67";
-LOCATE  COMP  "RA[2]"  SITE  "69";
-LOCATE  COMP  "RA[3]"  SITE  "71";
-LOCATE  COMP  "RA[4]"  SITE  "74";
-LOCATE  COMP  "RA[5]"  SITE  "70";
-LOCATE  COMP  "RA[6]"  SITE  "68";
-LOCATE  COMP  "RA[7]"  SITE  "75";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "63";
-LOCATE  COMP  "RBA[0]"  SITE  "58";
-LOCATE  COMP  "RBA[1]"  SITE  "60";
-LOCATE  COMP  "RCKE"  SITE  "53";
-LOCATE  COMP  "RCLK"  SITE  "62";
-LOCATE  COMP  "RDQMH"  SITE  "51";
-LOCATE  COMP  "RDQML"  SITE  "48";
-LOCATE  COMP  "RD[0]"  SITE  "36";
-LOCATE  COMP  "RD[1]"  SITE  "37";
-LOCATE  COMP  "RD[2]"  SITE  "38";
-LOCATE  COMP  "RD[3]"  SITE  "39";
-LOCATE  COMP  "RD[4]"  SITE  "40";
-LOCATE  COMP  "RD[5]"  SITE  "41";
-LOCATE  COMP  "RD[6]"  SITE  "42";
-LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "UFMCLK"  SITE  "29";
-LOCATE  COMP  "UFMSDI"  SITE  "30";
-LOCATE  COMP  "UFMSDO"  SITE  "27";
-LOCATE  COMP  "nCCAS"  SITE  "9";
-LOCATE  COMP  "nCRAS"  SITE  "17";
-LOCATE  COMP  "nFWE"  SITE  "28";
-LOCATE  COMP  "nRCAS"  SITE  "52";
-LOCATE  COMP  "nRCS"  SITE  "57";
-LOCATE  COMP  "nRRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "49";
-LOCATE  COMP  "nUFMCS"  SITE  "47";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:22:14 2023
-
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html deleted file mode 100644 index 0c0c85e..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html +++ /dev/null @@ -1,397 +0,0 @@ - -Place & Route Report - - -
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:22:08 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
-RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
-RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
-
-
-Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -4.650       391939       0.304        0            07           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 7 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
-Tue Aug 15 05:22:08 2023
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)   67+4(JTAG)/108     66% used
-                  67+4(JTAG)/80      89% bonded
-
-   SLICE             75/640          11% used
-
-
-
-Number of Signals: 285
-Number of Connections: 674
-WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
-
-Pin Constraint Summary:
-   66 out of 67 pins locked (98% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 40)
-    PHI2_c (driver: PHI2, clk load #: 13)
-
-WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
-
-WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-No signal is selected as Global Set/Reset.
-.
-Starting Placer Phase 0.
-..........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-...................
-Placer score = 143529.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  143450
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 3 out of 108 (2%)
-  PLL        : 0 out of 1 (0%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 8 (25%)
-  SECONDARY: 1 out of 8 (12%)
-
-Edge Clocks:
-  No edge clock selected.
-
-
-
-
-I/O Usage Summary (final):
-   67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
-   67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 13 / 19 ( 68%) | 2.5V       | -         |
-| 1        | 20 / 21 ( 95%) | 2.5V       | -         |
-| 2        | 17 / 20 ( 85%) | 2.5V       | -         |
-| 3        | 17 / 20 ( 85%) | 2.5V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 674 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=6 clock_loads=4
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 05:22:14 08/15/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 05:22:14 08/15/23
-
-Start NBR section for initial routing at 05:22:14 08/15/23
-Level 1, iteration 1
-2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 6 secs 
-Level 2, iteration 1
-11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 7 secs 
-Level 3, iteration 1
-20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 7 secs 
-Level 4, iteration 1
-11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 7 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 05:22:15 08/15/23
-Level 1, iteration 1
-7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 7 secs 
-Level 4, iteration 1
-9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 7 secs 
-Level 4, iteration 2
-6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 7 secs 
-Level 4, iteration 3
-6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs 
-Level 4, iteration 4
-6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs 
-Level 4, iteration 5
-4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs 
-Level 4, iteration 6
-3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs 
-Level 4, iteration 7
-3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs 
-Level 4, iteration 8
-3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs 
-Level 4, iteration 9
-2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs 
-Level 4, iteration 10
-3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs 
-Level 4, iteration 11
-3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs 
-Level 4, iteration 12
-3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs 
-Level 4, iteration 13
-2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs 
-Level 4, iteration 14
-2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs 
-Level 4, iteration 15
-2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 16
-3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 17
-2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs 
-Level 4, iteration 18
-1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs 
-Level 4, iteration 19
-1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 20
-1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 21
-1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 22
-1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
-Level 4, iteration 23
-1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs 
-Level 4, iteration 24
-1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs 
-Level 4, iteration 25
-0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
-
-Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
-Level 4, iteration 1
-1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 7 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
-
-Start NBR section for re-routing at 05:22:15 08/15/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
-
-Start NBR section for post-routing at 05:22:15 08/15/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 254 (37.69%)
-  Estimated worst slack<setup> : -4.650ns
-  Timing score<setup> : 391939
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
-   Signal=nCCAS_c loads=6 clock_loads=4
-
-Total CPU time 6 secs 
-Total REAL time: 7 secs 
-Completely routed.
-End of route.  674 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 391939 
-
-Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = -4.650
-PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 6 secs 
-Total REAL time to completion: 7 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html deleted file mode 100644 index dfa4c74..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -

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RAM2GS_LCMXO2_1200HC project summary
Module Name:RAM2GS_LCMXO2_1200HCSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2GS_LCMXO2_1200HC.lpf
Physical Preference file:impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Product Version:3.12.1.454Patch Version:
Updated:2023/08/15 05:22:21
Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1
Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf

-

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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html deleted file mode 100644 index 04d87c3..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html +++ /dev/null @@ -1,430 +0,0 @@ - -Lattice Map TRACE Report - - -
Map TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:22:07 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • 
-                459 items scored, 245 timing errors detected.
-Warning: 139.762MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • 
-                113 items scored, 104 timing errors detected.
-Warning:  50.592MHz is the maximum frequency for this preference.
-
-Report Type:     based on TRACE automatically generated preferences
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-            459 items scored, 245 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 3.815ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
-
-   Delay:               6.873ns  (28.2% logic, 71.8% route), 4 logic levels.
-
- Constraint Details:
-
-      6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
-      3.340ns delay constraint less
-      0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_0.CLK to     SLICE_0.Q0 SLICE_0 (from RCLK_c)
-ROUTE         3   e 1.234     SLICE_0.Q0 to    SLICE_85.B0 FS_13
-CTOF_DEL    ---     0.495    SLICE_85.B0 to    SLICE_85.F0 SLICE_85
-ROUTE         5   e 1.234    SLICE_85.F0 to    SLICE_57.A1 n10
-CTOF_DEL    ---     0.495    SLICE_57.A1 to    SLICE_57.F1 SLICE_57
-ROUTE         2   e 1.234    SLICE_57.F1 to    SLICE_84.A0 n2367
-CTOF_DEL    ---     0.495    SLICE_84.A0 to    SLICE_84.F0 SLICE_84
-ROUTE         1   e 1.234    SLICE_84.F0 to    SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
-                  --------
-                    6.873   (28.2% logic, 71.8% route), 4 logic levels.
-
-Warning: 139.762MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-            113 items scored, 104 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
-
- Constraint Details:
-
-      9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452  SLICE_101.CLK to   SLICE_101.Q1 SLICE_101 (from PHI2_c)
-ROUTE         1   e 1.234   SLICE_101.Q1 to   SLICE_100.C1 Bank_7
-CTOF_DEL    ---     0.495   SLICE_100.C1 to   SLICE_100.F1 SLICE_100
-ROUTE         1   e 1.234   SLICE_100.F1 to    SLICE_74.B1 n2277
-CTOF_DEL    ---     0.495    SLICE_74.B1 to    SLICE_74.F1 SLICE_74
-ROUTE         8   e 1.234    SLICE_74.F1 to    SLICE_91.B1 n26
-CTOF_DEL    ---     0.495    SLICE_91.B1 to    SLICE_91.F1 SLICE_91
-ROUTE         1   e 1.234    SLICE_91.F1 to    SLICE_88.D0 n2362
-CTOF_DEL    ---     0.495    SLICE_88.D0 to    SLICE_88.F0 SLICE_88
-ROUTE         3   e 0.480    SLICE_88.F0 to    SLICE_88.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 1.234    SLICE_88.F1 to    SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
-
-Warning:  50.592MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  139.762 MHz|   4 *
-                                        |             |             |
-FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   50.592 MHz|   6 *
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-2 preferences(marked by "*" above) not met.
-
-----------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
-----------------------------------------------------------------------------
-n26                                     |       8|      78|     22.35%
-                                        |        |        |
-----------------------------------------------------------------------------
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
-   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 349  Score: 848079
-Cumulative negative slack: 584487
-
-Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:22:07 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-            459 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
-
-   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.332ns physical path delay SLICE_106 to SLICE_106 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
-
- Physical Path Details:
-
-      Data path SLICE_106 to SLICE_106:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133  SLICE_106.CLK to   SLICE_106.Q0 SLICE_106 (from RCLK_c)
-ROUTE         1   e 0.199   SLICE_106.Q0 to   SLICE_106.M1 n736 (to RCLK_c)
-                  --------
-                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.C0 C1Submitted
-CTOF_DEL    ---     0.101    SLICE_15.C0 to    SLICE_15.F0 SLICE_15
-ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n1398 (to PHI2_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.351 ns|   1  
-                                        |             |             |
-FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.447 ns|   2  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
-   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 349 (setup), 0 (hold)
-Score: 848079 (setup), 0 (hold)
-Cumulative negative slack: 584487 (584487+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
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    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html deleted file mode 100644 index 987f2af..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html +++ /dev/null @@ -1,2244 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:22:16 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (247 errors)
    • 
-                459 items scored, 247 timing errors detected.
-Warning: 174.216MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (88 errors)
    • 
-                113 items scored, 88 timing errors detected.
-Warning:  67.833MHz is the maximum frequency for this preference.
-
-Report Type:     based on TRACE automatically generated preferences
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-            459 items scored, 247 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 2.400ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
-
-   Delay:               5.574ns  (43.6% logic, 56.4% route), 5 logic levels.
-
- Constraint Details:
-
-      5.574ns physical path delay SLICE_1 to SLICE_44 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
-ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
-CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
-ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
-CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
-ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
-CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
-ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
-CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
-ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
-                  --------
-                    5.574   (43.6% logic, 56.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.383ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
-   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
-
-   Delay:               5.441ns  (35.6% logic, 64.4% route), 4 logic levels.
-
- Constraint Details:
-
-      5.441ns physical path delay SLICE_1 to SLICE_26 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
-ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
-CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
-ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
-CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
-ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
-CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
-ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
-                  --------
-                    5.441   (35.6% logic, 64.4% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.217ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
-   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
-
-   Delay:               5.391ns  (45.1% logic, 54.9% route), 5 logic levels.
-
- Constraint Details:
-
-      5.391ns physical path delay SLICE_9 to SLICE_70 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
-ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
-CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
-ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
-CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
-ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
-CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
-ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
-CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
-ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
-                  --------
-                    5.391   (45.1% logic, 54.9% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.180ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
-   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
-
-   Delay:               5.354ns  (45.4% logic, 54.6% route), 5 logic levels.
-
- Constraint Details:
-
-      5.354ns physical path delay SLICE_9 to SLICE_70 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
-ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
-CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
-ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
-CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
-ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
-CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
-ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
-CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
-ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
-                  --------
-                    5.354   (45.4% logic, 54.6% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
-
-   Delay:               5.340ns  (45.5% logic, 54.5% route), 5 logic levels.
-
- Constraint Details:
-
-      5.340ns physical path delay SLICE_9 to SLICE_44 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
-ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
-CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
-ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
-CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
-ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
-CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
-ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
-CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
-ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
-                  --------
-                    5.340   (45.5% logic, 54.5% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
-
-   Delay:               5.332ns  (45.6% logic, 54.4% route), 5 logic levels.
-
- Constraint Details:
-
-      5.332ns physical path delay SLICE_9 to SLICE_44 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
-ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
-CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
-ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
-CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
-ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
-CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
-ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
-CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
-ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
-                  --------
-                    5.332   (45.6% logic, 54.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.149ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
-   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
-
-   Delay:               5.207ns  (37.2% logic, 62.8% route), 4 logic levels.
-
- Constraint Details:
-
-      5.207ns physical path delay SLICE_9 to SLICE_26 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
-ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
-CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
-ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
-CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
-ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
-CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
-ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
-                  --------
-                    5.207   (37.2% logic, 62.8% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.131ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i7  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
-
-   Delay:               5.189ns  (37.3% logic, 62.7% route), 4 logic levels.
-
- Constraint Details:
-
-      5.189ns physical path delay SLICE_2 to SLICE_57 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C15A.CLK to      R7C15A.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     1.086      R7C15A.Q0 to      R8C14D.D0 FS_7
-CTOF_DEL    ---     0.495      R8C14D.D0 to      R8C14D.F0 SLICE_95
-ROUTE         1     0.747      R8C14D.F0 to      R8C14A.C0 n15
-CTOF_DEL    ---     0.495      R8C14A.C0 to      R8C14A.F0 SLICE_86
-ROUTE         1     0.766      R8C14A.F0 to      R8C16C.C0 n4_adj_7
-CTOF_DEL    ---     0.495      R8C16C.C0 to      R8C16C.F0 SLICE_84
-ROUTE         1     0.653      R8C16C.F0 to      R8C16A.CE RCLK_c_enable_15 (to RCLK_c)
-                  --------
-                    5.189   (37.3% logic, 62.7% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C15A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.121ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
-
-   Delay:               5.295ns  (45.9% logic, 54.1% route), 5 logic levels.
-
- Constraint Details:
-
-      5.295ns physical path delay SLICE_9 to SLICE_44 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
-ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
-CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
-ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
-CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
-ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
-CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
-ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
-CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
-ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
-                  --------
-                    5.295   (45.9% logic, 54.1% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_44:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.087ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
-   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
-
-   Delay:               5.261ns  (46.2% logic, 53.8% route), 5 logic levels.
-
- Constraint Details:
-
-      5.261ns physical path delay SLICE_1 to SLICE_45 exceeds
-      3.340ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
-ROUTE         5     0.786      R7C15C.Q1 to      R8C15C.C1 FS_12
-CTOF_DEL    ---     0.495      R8C15C.C1 to      R8C15C.F1 SLICE_80
-ROUTE         3     0.640      R8C15C.F1 to      R8C14D.D1 n2375
-CTOF_DEL    ---     0.495      R8C14D.D1 to      R8C14D.F1 SLICE_95
-ROUTE         1     0.967      R8C14D.F1 to      R8C14C.A1 n7
-CTOF_DEL    ---     0.495      R8C14C.A1 to      R8C14C.F1 SLICE_45
-ROUTE         1     0.436      R8C14C.F1 to      R8C14C.C0 n2174
-CTOF_DEL    ---     0.495      R8C14C.C0 to      R8C14C.F0 SLICE_45
-ROUTE         1     0.000      R8C14C.F0 to     R8C14C.DI0 UFMSDI_N_231 (to RCLK_c)
-                  --------
-                    5.261   (46.2% logic, 53.8% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     4.865       62.PADDI to     R8C14C.CLK RCLK_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-Warning: 174.216MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-            113 items scored, 88 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               7.065ns  (41.4% logic, 58.6% route), 6 logic levels.
-
- Constraint Details:
-
-      7.065ns physical path delay SLICE_101 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
-ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
-CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
-ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
-CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
-CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    7.065   (41.4% logic, 58.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i1  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               7.027ns  (41.7% logic, 58.3% route), 6 logic levels.
-
- Constraint Details:
-
-      7.027ns physical path delay SLICE_93 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
-ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
-CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
-ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
-CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
-ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
-CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    7.027   (41.7% logic, 58.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               6.906ns  (42.4% logic, 57.6% route), 6 logic levels.
-
- Constraint Details:
-
-      6.906ns physical path delay SLICE_102 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns
-
- Physical Path Details:
-
-      Data path SLICE_102 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R8C15B.CLK to      R8C15B.Q0 SLICE_102 (from PHI2_c)
-ROUTE         1     0.623      R8C15B.Q0 to      R9C15C.D1 Bank_4
-CTOF_DEL    ---     0.495      R9C15C.D1 to      R9C15C.F1 SLICE_99
-ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
-CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
-ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
-CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    6.906   (42.4% logic, 57.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_102:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R8C15B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               6.724ns  (43.5% logic, 56.5% route), 6 logic levels.
-
- Constraint Details:
-
-      6.724ns physical path delay SLICE_103 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns
-
- Physical Path Details:
-
-      Data path SLICE_103 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16D.CLK to      R9C16D.Q1 SLICE_103 (from PHI2_c)
-ROUTE         1     0.645      R9C16D.Q1 to      R9C14A.D0 Bank_3
-CTOF_DEL    ---     0.495      R9C14A.D0 to      R9C14A.F0 SLICE_68
-ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
-CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
-CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    6.724   (43.5% logic, 56.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_103:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16D.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               6.614ns  (44.3% logic, 55.7% route), 6 logic levels.
-
- Constraint Details:
-
-      6.614ns physical path delay SLICE_101 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q1 SLICE_101 (from PHI2_c)
-ROUTE         1     0.986      R9C16C.Q1 to      R9C15A.A1 Bank_7
-CTOF_DEL    ---     0.495      R9C15A.A1 to      R9C15A.F1 SLICE_100
-ROUTE         1     0.315      R9C15A.F1 to      R9C15B.D1 n2277
-CTOF_DEL    ---     0.495      R9C15B.D1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
-CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
-CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    6.614   (44.3% logic, 55.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
-
-   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
-
- Constraint Details:
-
-      6.565ns physical path delay SLICE_101 to SLICE_10 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
-ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
-CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
-ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
-CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
-CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
-                  --------
-                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
-
-   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
-
- Constraint Details:
-
-      6.565ns physical path delay SLICE_101 to SLICE_15 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
-ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
-CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
-ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
-CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
-CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
-                  --------
-                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i1  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
-
-   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
-
- Constraint Details:
-
-      6.527ns physical path delay SLICE_93 to SLICE_10 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
-ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
-CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
-ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
-CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
-ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
-CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
-                  --------
-                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i1  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
-
-   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
-
- Constraint Details:
-
-      6.527ns physical path delay SLICE_93 to SLICE_15 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
-ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
-CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
-ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
-CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
-ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
-CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
-ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
-CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
-ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
-                  --------
-                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               6.490ns  (37.5% logic, 62.5% route), 5 logic levels.
-
- Constraint Details:
-
-      6.490ns physical path delay SLICE_101 to SLICE_19 exceeds
-      5.047ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
-ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
-CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
-ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
-CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.688      R9C15B.F1 to     R10C15C.D0 n26
-CTOF_DEL    ---     0.495     R10C15C.D0 to     R10C15C.F0 SLICE_104
-ROUTE         2     0.965     R10C15C.F0 to      R9C14C.D1 n2363
-CTOF_DEL    ---     0.495      R9C14C.D1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    6.490   (37.5% logic, 62.5% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
-
-Warning:  67.833MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  174.216 MHz|   5 *
-                                        |             |             |
-FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   67.833 MHz|   6 *
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-2 preferences(marked by "*" above) not met.
-
-----------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
-----------------------------------------------------------------------------
-n26                                     |       8|      64|     19.10%
-                                        |        |        |
-n1996                                   |       1|      49|     14.63%
-                                        |        |        |
-n1997                                   |       1|      46|     13.73%
-                                        |        |        |
-n1995                                   |       1|      45|     13.43%
-                                        |        |        |
-n1998                                   |       1|      38|     11.34%
-                                        |        |        |
-n1994                                   |       1|      37|     11.04%
-                                        |        |        |
-----------------------------------------------------------------------------
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
-   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 335  Score: 391939
-Cumulative negative slack: 304509
-
-Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:22:16 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-            459 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_106 to SLICE_106 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_106 to SLICE_106:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C13B.CLK to     R10C13B.Q0 SLICE_106 (from RCLK_c)
-ROUTE         1     0.152     R10C13B.Q0 to     R10C13B.M1 n736 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_106:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_106:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr_382  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2_383  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R7C12B.CLK to      R7C12B.Q0 SLICE_16 (from RCLK_c)
-ROUTE         1     0.152      R7C12B.Q0 to      R7C12B.M1 CASr (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C13D.CLK to     R10C13D.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1     0.152     R10C13D.Q0 to     R10C13D.M1 n732 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_78 to SLICE_78 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_78 to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C12B.CLK to      R8C12B.Q0 SLICE_78 (from RCLK_c)
-ROUTE         1     0.152      R8C12B.Q0 to      R8C12B.M1 n728 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_81 to SLICE_81 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_81 to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C12A.CLK to      R9C12A.Q0 SLICE_81 (from RCLK_c)
-ROUTE         1     0.152      R9C12A.Q0 to      R9C12A.M1 n726 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_84 to SLICE_84 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_84 to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C16C.CLK to      R8C16C.Q0 SLICE_84 (from RCLK_c)
-ROUTE         1     0.152      R8C16C.Q0 to      R8C16C.M1 n738 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_97 to SLICE_97 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C14A.CLK to     R10C14A.Q0 SLICE_97 (from RCLK_c)
-ROUTE         1     0.152     R10C14A.Q0 to     R10C14A.M1 n734 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.306ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr_379  (from RCLK_c +)
-   Destination:    FF         Data in        RASr2_380  (to RCLK_c +)
-
-   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.287ns physical path delay SLICE_30 to SLICE_30 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
-
- Physical Path Details:
-
-      Data path SLICE_30 to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C13B.CLK to      R8C13B.Q0 SLICE_30 (from RCLK_c)
-ROUTE         2     0.154      R8C13B.Q0 to      R8C13B.M1 RASr (to RCLK_c)
-                  --------
-                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.306ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i1  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i2  (to RCLK_c +)
-
-   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.287ns physical path delay SLICE_98 to SLICE_84 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q1 SLICE_98 (from RCLK_c)
-ROUTE         4     0.154      R8C16D.Q1 to      R8C16C.M0 nRCAS_N_165 (to RCLK_c)
-                  --------
-                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.306ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
-
-   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.287ns physical path delay SLICE_98 to SLICE_98 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q0 SLICE_98 (from RCLK_c)
-ROUTE         4     0.154      R8C16D.Q0 to      R8C16D.M1 nRCS_N_139 (to RCLK_c)
-                  --------
-                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2     0.132     R10C14C.Q0 to     R10C14C.A0 C1Submitted
-CTOF_DEL    ---     0.101     R10C14C.A0 to     R10C14C.F0 SLICE_15
-ROUTE         1     0.000     R10C14C.F0 to    R10C14C.DI0 n1398 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.629ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               0.601ns  (38.9% logic, 61.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.601ns physical path delay SLICE_10 to SLICE_19 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.629ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C14B.CLK to     R10C14B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         1     0.224     R10C14B.Q0 to      R9C14C.B1 ADSubmitted
-CTOF_DEL    ---     0.101      R9C14C.B1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    0.601   (38.9% logic, 61.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.715ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
-
-   Delay:               0.687ns  (34.1% logic, 65.9% route), 2 logic levels.
-
- Constraint Details:
-
-      0.687ns physical path delay SLICE_19 to SLICE_50 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.715ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_50:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.310      R9C14B.Q0 to     R10C15B.B1 CmdEnable
-CTOF_DEL    ---     0.101     R10C15B.B1 to     R10C15B.F1 SLICE_83
-ROUTE         1     0.143     R10C15B.F1 to     R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c)
-                  --------
-                    0.687   (34.1% logic, 65.9% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_50:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.873ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
-                   FF                        CmdUFMCLK_413
-
-   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.845ns physical path delay SLICE_19 to SLICE_100 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_100:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
-CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
-ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
-CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
-ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
-                  --------
-                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_100:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.873ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
-
-   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.845ns physical path delay SLICE_19 to SLICE_99 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
-CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
-ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
-CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
-ROUTE         2     0.148     R10C15A.F1 to      R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c)
-                  --------
-                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C15C.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.252ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
-
-   Delay:               1.224ns  (35.6% logic, 64.4% route), 4 logic levels.
-
- Constraint Details:
-
-      1.224ns physical path delay SLICE_15 to SLICE_19 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.252ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2     0.212     R10C14C.Q0 to     R10C14D.A1 C1Submitted
-CTOF_DEL    ---     0.101     R10C14D.A1 to     R10C14D.F1 SLICE_77
-ROUTE         1     0.222     R10C14D.F1 to     R10C14A.B1 n2210
-CTOF_DEL    ---     0.101     R10C14A.B1 to     R10C14A.F1 SLICE_97
-ROUTE         1     0.211     R10C14A.F1 to      R9C14C.A1 n7_adj_5
-CTOF_DEL    ---     0.101      R9C14C.A1 to      R9C14C.F1 SLICE_88
-ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
-                  --------
-                    1.224   (35.6% logic, 64.4% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.277ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
-
-   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
-
- Constraint Details:
-
-      1.249ns physical path delay SLICE_19 to SLICE_20 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
-CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
-ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
-CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
-ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D1 n2220
-CTOF_DEL    ---     0.101      R9C17A.D1 to      R9C17A.F1 SLICE_89
-ROUTE         1     0.143      R9C17A.F1 to      R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c)
-                  --------
-                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C17D.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.277ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
-
-   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
-
- Constraint Details:
-
-      1.249ns physical path delay SLICE_19 to SLICE_24 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
-CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
-ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
-CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
-ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D0 n2220
-CTOF_DEL    ---     0.101      R9C17A.D0 to      R9C17A.F0 SLICE_89
-ROUTE         1     0.143      R9C17A.F0 to      R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c)
-                  --------
-                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C17C.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
-
-   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.
-
- Constraint Details:
-
-      0.371ns physical path delay SLICE_50 to SLICE_33 meets
-     -0.013ns DIN_HLD and
-     -5.047ns delay constraint less
-      0.000ns skew requirement (totaling -5.060ns) by 5.431ns
-
- Physical Path Details:
-
-      Data path SLICE_50 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R10C15D.CLK to     R10C15D.Q0 SLICE_50 (from PHI2_c)
-ROUTE         1     0.137     R10C15D.Q0 to     R10C16A.C0 XOR8MEG
-CTOF_DEL    ---     0.101     R10C16A.C0 to     R10C16A.F0 SLICE_33
-ROUTE         1     0.000     R10C16A.F0 to    R10C16A.DI0 RA11_N_184 (to PHI2_c)
-                  --------
-                    0.371   (63.1% logic, 36.9% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_50:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to    R10C16A.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
-                   FF                        CmdUFMCLK_413
-
-   Delay:               0.917ns  (47.5% logic, 52.5% route), 4 logic levels.
-
- Constraint Details:
-
-      0.917ns physical path delay SLICE_93 to SLICE_100 meets
-     -0.028ns CE_HLD and
-     -5.047ns delay constraint less
-      0.000ns skew requirement (totaling -5.075ns) by 5.992ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_100:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R9C16A.CLK to      R9C16A.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     0.138      R9C16A.Q0 to      R9C15A.C1 Bank_0
-CTOF_DEL    ---     0.101      R9C15A.C1 to      R9C15A.F1 SLICE_100
-ROUTE         1     0.053      R9C15A.F1 to      R9C15B.D1 n2277
-CTOF_DEL    ---     0.101      R9C15B.D1 to      R9C15B.F1 SLICE_74
-ROUTE         8     0.142      R9C15B.F1 to     R10C15A.D1 n26
-CTOF_DEL    ---     0.101     R10C15A.D1 to     R10C15A.F1 SLICE_73
-ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
-                  --------
-                    0.917   (47.5% logic, 52.5% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C16A.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_100:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
-                  --------
-                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.304 ns|   1  
-                                        |             |             |
-FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.379 ns|   2  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
-   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 335 (setup), 0 (hold)
-Score: 391939 (setup), 0 (hold)
-Cumulative negative slack: 304509 (304509+0)
---------------------------------------------------------------------------------
-
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    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log deleted file mode 100644 index d48a448..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log +++ /dev/null @@ -1,16 +0,0 @@ -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 309 blocks expanded -completed the first expansion -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr deleted file mode 100644 index ccd5368..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr +++ /dev/null @@ -1,297 +0,0 @@ --------------------------------------------------------------------------------- -Lattice Synthesis Timing Report, Version -Tue Aug 15 05:03:26 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Design: RAM2GS -Constraint file: -Report level: verbose report, limited to 3 items per constraint --------------------------------------------------------------------------------- - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] - 122 items scored, 119 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 7.418ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i1 (from PHI2_c +) - Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) - - Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. - - Constraint Details: - - 9.633ns data_path Bank_i1 to CmdEnable_405 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns - - Path Details: Bank_i1 to CmdEnable_405 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) -Route 1 e 0.941 Bank[1] -LUT4 --- 0.493 D to Z i8_4_lut -Route 2 e 1.141 n22 -LUT4 --- 0.493 B to Z i11_3_lut_rep_20 -Route 7 e 1.502 n2369 -LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut -Route 1 e 0.941 n2362 -LUT4 --- 0.493 D to Z i1_4_lut_adj_13 -Route 3 e 1.258 C1Submitted_N_237 -LUT4 --- 0.493 C to Z i34_4_lut -Route 1 e 0.941 PHI2_N_120_enable_1 - -------- - 9.633 (30.2% logic, 69.8% route), 6 logic levels. - - -Error: The following path violates requirements by 7.418ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i4 (from PHI2_c +) - Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) - - Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. - - Constraint Details: - - 9.633ns data_path Bank_i4 to CmdEnable_405 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns - - Path Details: Bank_i4 to CmdEnable_405 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) -Route 1 e 0.941 Bank[4] -LUT4 --- 0.493 C to Z i8_4_lut -Route 2 e 1.141 n22 -LUT4 --- 0.493 B to Z i11_3_lut_rep_20 -Route 7 e 1.502 n2369 -LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut -Route 1 e 0.941 n2362 -LUT4 --- 0.493 D to Z i1_4_lut_adj_13 -Route 3 e 1.258 C1Submitted_N_237 -LUT4 --- 0.493 C to Z i34_4_lut -Route 1 e 0.941 PHI2_N_120_enable_1 - -------- - 9.633 (30.2% logic, 69.8% route), 6 logic levels. - - -Error: The following path violates requirements by 7.256ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i3 (from PHI2_c +) - Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) - - Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels. - - Constraint Details: - - 9.471ns data_path Bank_i3 to CmdEnable_405 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns - - Path Details: Bank_i3 to CmdEnable_405 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) -Route 1 e 0.941 Bank[3] -LUT4 --- 0.493 B to Z i1989_2_lut -Route 1 e 0.941 n2287 -LUT4 --- 0.493 C to Z i12_4_lut -Route 8 e 1.540 n26 -LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut -Route 1 e 0.941 n2362 -LUT4 --- 0.493 D to Z i1_4_lut_adj_13 -Route 3 e 1.258 C1Submitted_N_237 -LUT4 --- 0.493 C to Z i34_4_lut -Route 1 e 0.941 PHI2_N_120_enable_1 - -------- - 9.471 (30.7% logic, 69.3% route), 6 logic levels. - -Warning: 9.918 ns is the maximum delay for this constraint. - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] - 498 items scored, 186 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 3.319ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) - Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) - - Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. - - Constraint Details: - - 8.159ns data_path FS_610__i13 to nUFMCS_415 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns - - Path Details: FS_610__i13 to nUFMCS_415 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c) -Route 3 e 1.315 FS[13] -LUT4 --- 0.493 B to Z i3_4_lut_adj_7 -Route 5 e 1.405 n10 -LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut -Route 2 e 1.141 n2368 -LUT4 --- 0.493 B to Z i1_2_lut_4_lut -Route 1 e 0.941 n64 -LUT4 --- 0.493 B to Z i1448_4_lut -Route 1 e 0.941 nUFMCS_N_199 - -------- - 8.159 (29.6% logic, 70.4% route), 5 logic levels. - - -Error: The following path violates requirements by 3.319ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) - Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) - - Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. - - Constraint Details: - - 8.159ns data_path FS_610__i15 to nUFMCS_415 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns - - Path Details: FS_610__i15 to nUFMCS_415 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c) -Route 3 e 1.315 FS[15] -LUT4 --- 0.493 C to Z i3_4_lut_adj_7 -Route 5 e 1.405 n10 -LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut -Route 2 e 1.141 n2368 -LUT4 --- 0.493 B to Z i1_2_lut_4_lut -Route 1 e 0.941 n64 -LUT4 --- 0.493 B to Z i1448_4_lut -Route 1 e 0.941 nUFMCS_N_199 - -------- - 8.159 (29.6% logic, 70.4% route), 5 logic levels. - - -Error: The following path violates requirements by 3.319ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_610__i16 (from RCLK_c +) - Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) - - Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. - - Constraint Details: - - 8.159ns data_path FS_610__i16 to nUFMCS_415 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns - - Path Details: FS_610__i16 to nUFMCS_415 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c) -Route 3 e 1.315 FS[16] -LUT4 --- 0.493 D to Z i3_4_lut_adj_7 -Route 5 e 1.405 n10 -LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut -Route 2 e 1.141 n2368 -LUT4 --- 0.493 B to Z i1_2_lut_4_lut -Route 1 e 0.941 n64 -LUT4 --- 0.493 B to Z i1448_4_lut -Route 1 e 0.941 nUFMCS_N_199 - -------- - 8.159 (29.6% logic, 70.4% route), 5 logic levels. - -Warning: 8.319 ns is the maximum delay for this constraint. - - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 * - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - --------------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total --------------------------------------------------------------------------------- -n26 | 8| 84| 27.54% - | | | -n1997 | 1| 36| 11.80% - | | | -n1996 | 1| 35| 11.48% - | | | -n1995 | 1| 33| 10.82% - | | | -n10 | 5| 32| 10.49% - | | | -n1998 | 1| 32| 10.49% - | | | --------------------------------------------------------------------------------- - - -Timing summary: ---------------- - -Timing errors: 305 Score: 1313492 - -Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage) - - -Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes -CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html deleted file mode 100644 index 8da9b01..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html +++ /dev/null @@ -1,362 +0,0 @@ - -Lattice Synthesis Timing Report - - -
    Lattice Synthesis Timing Report
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Tue Aug 15 05:03:26 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 119 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i1 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i1 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
-Route         1   e 0.941                                  Bank[1]
-LUT4        ---     0.493              D to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i4 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i4 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
-Route         1   e 0.941                                  Bank[4]
-LUT4        ---     0.493              C to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.256ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
-
- Constraint Details:
-
-      9.471ns data_path Bank_i3 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
-
- Path Details: Bank_i3 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
-Route         1   e 0.941                                  Bank[3]
-LUT4        ---     0.493              B to Z              i1989_2_lut
-Route         1   e 0.941                                  n2287
-LUT4        ---     0.493              C to Z              i12_4_lut
-Route         8   e 1.540                                  n26
-LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
-
-Warning: 9.918 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            498 items scored, 186 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i13 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
-Route         3   e 1.315                                  FS[13]
-LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i15 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
-Route         3   e 1.315                                  FS[15]
-LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i16 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
-Route         3   e 1.315                                  FS[16]
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-Warning: 8.319 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n26                                     |       8|      84|     27.54%
-                                        |        |        |
-n1997                                   |       1|      36|     11.80%
-                                        |        |        |
-n1996                                   |       1|      35|     11.48%
-                                        |        |        |
-n1995                                   |       1|      33|     10.82%
-                                        |        |        |
-n10                                     |       5|      32|     10.49%
-                                        |        |        |
-n1998                                   |       1|      32|     10.49%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 305  Score: 1313492
-
-Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
-
-
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    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v deleted file mode 100644 index 28a3dbb..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v +++ /dev/null @@ -1,802 +0,0 @@ -// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 -// Netlist written on Tue Aug 15 05:03:26 2023 -// -// Verilog Description of module RAM2GS -// - -module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, - LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, - nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) - input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) - input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) - input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) - input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) - input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) - output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) - output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) - output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) - input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) - output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) - output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) - output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) - output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) - output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) - output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) - output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) - output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) - output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) - input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) - - wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) - wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) - wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) - wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) - wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) - wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) - - wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, - RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, - Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, - Din_c_0; - wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) - - wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, - MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, - nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, - nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; - wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) - - wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, - RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; - wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) - - wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, - CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, - CmdUFMCS, InitReady, Ready, n10; - wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) - - wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, - n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, - nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, - n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, - nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, - n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, - nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, - nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, - CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, - n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, - RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, - UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, - n1999, n2287, n726, n727, n728, n729, n730, n732, n733, - n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, - PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, - PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, - Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, - n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, - RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, - n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, - RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, - n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, - Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, - Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, - n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64; - - VHI i2 (.Z(VCC_net)); - INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) - FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam PHI2r2_377.GSR = "ENABLED"; - LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), - .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7]) - defparam nRCAS_I_43_4_lut.init = 16'h3afa; - LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), - .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) - defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e; - LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), - .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) - defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; - FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam PHI2r3_378.GSR = "ENABLED"; - FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam RASr_379.GSR = "ENABLED"; - FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam RASr2_380.GSR = "ENABLED"; - FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam RASr3_381.GSR = "ENABLED"; - FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam CASr_382.GSR = "ENABLED"; - FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam CASr2_383.GSR = "ENABLED"; - FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam CASr3_384.GSR = "ENABLED"; - FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam RA11_385.GSR = "ENABLED"; - CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), - .COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_15.INIT0 = 16'hfaaa; - defparam FS_610_add_4_15.INIT1 = 16'hfaaa; - defparam FS_610_add_4_15.INJECT1_0 = "NO"; - defparam FS_610_add_4_15.INJECT1_1 = "NO"; - FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i0.GSR = "ENABLED"; - FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i0.GSR = "ENABLED"; - FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam FWEr_389.GSR = "ENABLED"; - FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam CBR_390.GSR = "ENABLED"; - FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) - defparam RCKE_395.GSR = "ENABLED"; - FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), - .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam nRCS_396.GSR = "ENABLED"; - LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1477_2_lut.init = 16'heeee; - FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), - .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam nRowColSel_402.GSR = "ENABLED"; - CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), - .COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_13.INIT0 = 16'hfaaa; - defparam FS_610_add_4_13.INIT1 = 16'hfaaa; - defparam FS_610_add_4_13.INJECT1_0 = "NO"; - defparam FS_610_add_4_13.INJECT1_1 = "NO"; - LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam i2_2_lut.init = 16'h8888; - FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), - .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam CmdEnable_405.GSR = "ENABLED"; - LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), - .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; - defparam i4_4_lut.init = 16'h4000; - FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), - .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam ADSubmitted_407.GSR = "ENABLED"; - LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; - defparam i26_4_lut.init = 16'hc0ca; - LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), - .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; - defparam i1_2_lut_3_lut_4_lut.init = 16'h0020; - FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), - .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam nRRAS_397.GSR = "ENABLED"; - LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) - defparam nRWE_I_50_1_lut.init = 16'h5555; - BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), - .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam nRCAS_398.GSR = "ENABLED"; - FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), - .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam nRWE_399.GSR = "ENABLED"; - FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam RA10_400.GSR = "ENABLED"; - FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), - .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam RCKEEN_401.GSR = "ENABLED"; - FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i0.GSR = "ENABLED"; - FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RBA__i1.GSR = "ENABLED"; - LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), - .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ; - defparam i1_4_lut.init = 16'hc444; - LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) - defparam i29_3_lut.init = 16'hcaca; - LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), - .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) - defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; - LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1956_2_lut.init = 16'heeee; - FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i0.GSR = "ENABLED"; - CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), - .COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_9.INIT0 = 16'hfaaa; - defparam FS_610_add_4_9.INIT1 = 16'hfaaa; - defparam FS_610_add_4_9.INJECT1_0 = "NO"; - defparam FS_610_add_4_9.INJECT1_1 = "NO"; - FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), - .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam C1Submitted_406.GSR = "ENABLED"; - FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), - .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) - defparam nUFMCS_415.GSR = "ENABLED"; - LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), - .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ; - defparam i2_4_lut.init = 16'h8088; - FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam S_FSM_i1.GSR = "ENABLED"; - CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), - .COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_7.INIT0 = 16'hfaaa; - defparam FS_610_add_4_7.INIT1 = 16'hfaaa; - defparam FS_610_add_4_7.INJECT1_0 = "NO"; - defparam FS_610_add_4_7.INJECT1_1 = "NO"; - LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ; - defparam i1_2_lut.init = 16'h2222; - LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), - .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; - defparam i1_2_lut_rep_15_4_lut.init = 16'h0008; - CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), - .COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_3.INIT0 = 16'hfaaa; - defparam FS_610_add_4_3.INIT1 = 16'hfaaa; - defparam FS_610_add_4_3.INJECT1_0 = "NO"; - defparam FS_610_add_4_3.INJECT1_1 = "NO"; - LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) - defparam RA11_I_54_3_lut.init = 16'hc6c6; - LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; - defparam i9_2_lut_3_lut.init = 16'h1f1f; - LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1491_2_lut_rep_30.init = 16'heeee; - LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), - .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; - defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10; - FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), - .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) - defparam UFMCLK_416.GSR = "ENABLED"; - LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), - .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; - LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), - .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; - defparam i3_4_lut.init = 16'h0800; - LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), - .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) - defparam i1_2_lut_rep_21_3_lut.init = 16'h2020; - LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), - .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), - .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), - .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), - .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; - CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), - .S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_1.INIT0 = 16'hF000; - defparam FS_610_add_4_1.INIT1 = 16'h0555; - defparam FS_610_add_4_1.INJECT1_0 = "NO"; - defparam FS_610_add_4_1.INJECT1_1 = "NO"; - LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), - .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; - FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam PHI2r_376.GSR = "ENABLED"; - LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), - .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; - defparam i1962_4_lut.init = 16'hfefa; - LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8]) - defparam i1423_2_lut.init = 16'hdddd; - LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), - .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; - FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam S_FSM_i3.GSR = "ENABLED"; - FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam S_FSM_i4.GSR = "ENABLED"; - LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), - .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) - defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200; - LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), - .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; - defparam MAin_c_0_bdd_4_lut.init = 16'h0200; - FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), - .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) - defparam UFMSDI_417.GSR = "ENABLED"; - LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), - .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), - .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; - LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), - .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6]) - defparam i1448_4_lut.init = 16'h3fbb; - LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), - .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; - defparam i2_3_lut_rep_18_4_lut.init = 16'h1000; - LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), - .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; - defparam i3_4_lut_adj_2.init = 16'hbfff; - LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), - .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) - defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; - LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) - defparam i1416_2_lut.init = 16'hbbbb; - LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; - defparam i2001_2_lut.init = 16'h7777; - LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), - .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; - defparam i2_3_lut_4_lut.init = 16'h4000; - LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), - .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; - defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001; - FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i0.GSR = "ENABLED"; - LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), - .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) - defparam i1427_4_lut.init = 16'hfcdd; - LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), - .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) - defparam i3_3_lut_4_lut.init = 16'h0002; - LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i1_2_lut_adj_3.init = 16'h8888; - LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam i1119_1_lut.init = 16'h5555; - LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), - .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; - defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd; - LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ; - defparam i11_3_lut_rep_20.init = 16'h8080; - LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), - .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; - defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f; - GSR GSR_INST (.GSR(VCC_net)); - LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) - defparam i1_4_lut_adj_4.init = 16'h2000; - LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i6_4_lut.init = 16'h8000; - LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), - .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i8_4_lut.init = 16'h8000; - LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), - .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; - defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff; - LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i5_4_lut.init = 16'h8000; - LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), - .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; - defparam i12_4_lut.init = 16'hbfff; - LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), - .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ; - defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf; - LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam i637_1_lut_rep_31.init = 16'h5555; - LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), - .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) - defparam i1573_4_lut.init = 16'hcac0; - LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), - .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i3_4_lut_adj_7.init = 16'hfffe; - LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) - defparam i786_2_lut.init = 16'heeee; - LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; - defparam i1_4_lut_adj_8.init = 16'h0002; - LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), - .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; - LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), - .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; - CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), - .COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_11.INIT0 = 16'hfaaa; - defparam FS_610_add_4_11.INIT1 = 16'hfaaa; - defparam FS_610_add_4_11.INJECT1_0 = "NO"; - defparam FS_610_add_4_11.INJECT1_1 = "NO"; - LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) - defparam i1603_3_lut.init = 16'hcaca; - LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), - .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i1979_4_lut.init = 16'h8000; - FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i15.GSR = "ENABLED"; - LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd; - LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), - .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i6_4_lut_adj_9.init = 16'hfffe; - LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), - .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) - defparam i1970_4_lut.init = 16'h3a0a; - LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam i1_2_lut_2_lut.init = 16'hdddd; - PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4)); - FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i14.GSR = "ENABLED"; - FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i13.GSR = "ENABLED"; - LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ; - defparam i1989_2_lut.init = 16'h8888; - LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) - defparam i2_3_lut_rep_32.init = 16'h8080; - LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) - defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f; - FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i12.GSR = "ENABLED"; - FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), - .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam XOR8MEG_408.GSR = "ENABLED"; - FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), - .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) - defparam n8MEGEN_418.GSR = "ENABLED"; - CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), - .S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_19.INIT0 = 16'hfaaa; - defparam FS_610_add_4_19.INIT1 = 16'h0000; - defparam FS_610_add_4_19.INJECT1_0 = "NO"; - defparam FS_610_add_4_19.INJECT1_1 = "NO"; - FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), - .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) - defparam LEDEN_419.GSR = "ENABLED"; - FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam Ready_404.GSR = "ENABLED"; - FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), - .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam CmdUFMCLK_413.GSR = "ENABLED"; - FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), - .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam CmdUFMSDI_414.GSR = "ENABLED"; - FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), - .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam Cmdn8MEGEN_410.GSR = "ENABLED"; - FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), - .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam CmdSubmitted_411.GSR = "ENABLED"; - FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), - .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) - defparam CmdUFMCS_412.GSR = "ENABLED"; - FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i11.GSR = "ENABLED"; - LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) - defparam i2008_2_lut_4_lut.init = 16'h0080; - LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17]) - defparam i1404_4_lut.init = 16'hcfc8; - LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam i1118_1_lut.init = 16'h5555; - FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i10.GSR = "ENABLED"; - LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) - defparam i1_2_lut_adj_10.init = 16'h2222; - LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam i1439_2_lut.init = 16'heeee; - FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i9.GSR = "ENABLED"; - LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) - defparam i1432_4_lut.init = 16'h3032; - LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ; - defparam i1_2_lut_rep_33.init = 16'h8888; - LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), - .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) - defparam i1_4_lut_4_lut.init = 16'h5540; - LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ; - defparam i4_2_lut.init = 16'heeee; - LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), - .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) - defparam i1589_4_lut.init = 16'hcac0; - LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ; - defparam i2_1_lut_rep_24.init = 16'h5555; - LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), - .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; - defparam i2_3_lut_4_lut_adj_11.init = 16'h0008; - FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i8.GSR = "ENABLED"; - FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i7.GSR = "ENABLED"; - FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i6.GSR = "ENABLED"; - FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i5.GSR = "ENABLED"; - FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i4.GSR = "ENABLED"; - FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i3.GSR = "ENABLED"; - FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i2.GSR = "ENABLED"; - FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) - defparam IS_FSM__i1.GSR = "ENABLED"; - FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RBA__i2.GSR = "ENABLED"; - FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i17.GSR = "ENABLED"; - FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i16.GSR = "ENABLED"; - FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i15.GSR = "ENABLED"; - FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i14.GSR = "ENABLED"; - FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i13.GSR = "ENABLED"; - FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i12.GSR = "ENABLED"; - FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i11.GSR = "ENABLED"; - FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i10.GSR = "ENABLED"; - FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i9.GSR = "ENABLED"; - FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i8.GSR = "ENABLED"; - FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i7.GSR = "ENABLED"; - FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i6.GSR = "ENABLED"; - FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i5.GSR = "ENABLED"; - FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i4.GSR = "ENABLED"; - FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i3.GSR = "ENABLED"; - FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i2.GSR = "ENABLED"; - FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610__i1.GSR = "ENABLED"; - FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i7.GSR = "ENABLED"; - FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i6.GSR = "ENABLED"; - FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i5.GSR = "ENABLED"; - FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i4.GSR = "ENABLED"; - FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i3.GSR = "ENABLED"; - FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i2.GSR = "ENABLED"; - FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) - defparam WRD_i1.GSR = "ENABLED"; - FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i9.GSR = "ENABLED"; - FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i8.GSR = "ENABLED"; - FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i7.GSR = "ENABLED"; - FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i6.GSR = "ENABLED"; - FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i5.GSR = "ENABLED"; - FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i4.GSR = "ENABLED"; - FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i3.GSR = "ENABLED"; - FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i2.GSR = "ENABLED"; - FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam RowA_i1.GSR = "ENABLED"; - FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i7.GSR = "ENABLED"; - LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; - defparam i2_3_lut_3_lut.init = 16'h4040; - LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) - defparam i1_2_lut_3_lut.init = 16'h1010; - LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) - defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555; - LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), - .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) - defparam i1_4_lut_4_lut_adj_12.init = 16'hff40; - LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), - .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; - defparam i1_4_lut_adj_13.init = 16'h0004; - FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i6.GSR = "ENABLED"; - FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i5.GSR = "ENABLED"; - FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i4.GSR = "ENABLED"; - FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i3.GSR = "ENABLED"; - FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i2.GSR = "ENABLED"; - FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) - defparam Bank_i1.GSR = "ENABLED"; - CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), - .COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_5.INIT0 = 16'hfaaa; - defparam FS_610_add_4_5.INIT1 = 16'hfaaa; - defparam FS_610_add_4_5.INJECT1_0 = "NO"; - defparam FS_610_add_4_5.INJECT1_1 = "NO"; - BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), - .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; - defparam i2_3_lut_4_lut_adj_14.init = 16'h2000; - BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), - .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) - defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe; - BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) - OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) - OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) - OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) - OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) - OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) - OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) - OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) - OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) - OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) - OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) - OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) - OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) - OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) - OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) - OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) - IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) - IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) - IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) - IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) - IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) - IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) - IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) - IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) - IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) - IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) - CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), - .COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam FS_610_add_4_17.INIT0 = 16'hfaaa; - defparam FS_610_add_4_17.INIT1 = 16'hfaaa; - defparam FS_610_add_4_17.INJECT1_0 = "NO"; - defparam FS_610_add_4_17.INJECT1_1 = "NO"; - LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ; - defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd; - LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ; - defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf; - LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23]) - defparam i2010_3_lut_3_lut.init = 16'hfbfb; - LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ; - defparam i5_3_lut.init = 16'hfefe; - LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), - .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i4_4_lut_adj_16.init = 16'hfffe; - LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i4_4_lut_adj_17.init = 16'h0002; - LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), - .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; - defparam i34_4_lut.init = 16'hc0c5; - LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ; - defparam i13_3_lut.init = 16'hc5c5; - LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), - .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i1_2_lut_4_lut.init = 16'hfffe; - LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), - .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) - defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa; - LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), - .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) - defparam i3_4_lut_adj_18.init = 16'h1000; - LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1930_2_lut.init = 16'heeee; - LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), - .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; - defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0; - LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i1_2_lut_adj_19.init = 16'h8888; - LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), - .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i2_4_lut_adj_20.init = 16'h1404; - LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1417_2_lut.init = 16'heeee; - LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), - .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; - defparam i2_4_lut_adj_21.init = 16'h0004; - LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), - .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; - defparam i3_4_lut_adj_22.init = 16'h0800; - LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ; - defparam i1_2_lut_adj_23.init = 16'hbbbb; - FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), - .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) - defparam InitReady_394.GSR = "ENABLED"; - LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), - .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) - defparam nRCS_I_0_448_3_lut.init = 16'hcaca; - LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), - .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef; - LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe; - LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), - .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam i2_3_lut_4_lut_adj_24.init = 16'h1000; - LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) - defparam i3_2_lut_rep_26.init = 16'heeee; - LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) - defparam i1_2_lut_rep_27.init = 16'heeee; - LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) - defparam i2_3_lut_rep_28.init = 16'h2020; - INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) - FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) - defparam S_FSM_i2.GSR = "ENABLED"; - INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) - VLO i1 (.Z(GND_net)); - TSALL TSALL_INST (.TSALL(GND_net)); - PUR PUR_INST (.PUR(VCC_net)); - defparam PUR_INST.RST_PULSE = 1; - LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), - .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) - defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff; - LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1_2_lut_rep_29.init = 16'heeee; - LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ; - defparam m1_lut.init = 16'hffff; - LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), - .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ; - defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04; - -endmodule -// -// Verilog Description of module TSALL -// module not written out since it is a black-box. -// - -// -// Verilog Description of module PUR -// module not written out since it is a black-box. -// - diff --git a/CPLD/LCMXO2-1200HC/impl1/automake.log b/CPLD/LCMXO2-1200HC/impl1/automake.log deleted file mode 100644 index f56d09d..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/automake.log +++ /dev/null @@ -1,859 +0,0 @@ - -map -a "MachXO2" -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_1200HC_impl1.ngd" -o "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_1200HC_impl1.prf" -mp "RAM2GS_LCMXO2_1200HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf" -c 0 -map: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - Process the file: RAM2GS_LCMXO2_1200HC_impl1.ngd - Picdevice="LCMXO2-1200HC" - - Pictype="TQFP100" - - Picspeed=4 - - Remove unused logic - - Do not produce over sized NCDs. - -Part used: LCMXO2-1200HCTQFP100, Performance used: 4. - -Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. - -Running general design DRC... - -Removing unused logic... - -Optimizing... - - - - -Design Summary: - Number of registers: 102 out of 1520 (7%) - PFU registers: 102 out of 1280 (8%) - PIO registers: 0 out of 240 (0%) - Number of SLICEs: 75 out of 640 (12%) - SLICEs as Logic/ROM: 75 out of 640 (12%) - SLICEs as RAM: 0 out of 480 (0%) - SLICEs as Carry: 10 out of 640 (2%) - Number of LUT4s: 143 out of 1280 (11%) - Number used as logic LUTs: 123 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) - Number of block RAMs: 0 out of 7 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : No - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Number of PLLs: 0 out of 1 (0%) - Number of DQSDLLs: 0 out of 2 (0%) - Number of CLKDIVC: 0 out of 4 (0%) - Number of ECLKSYNCA: 0 out of 4 (0%) - Number of ECLKBRIDGECS: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. - Number of clocks: 4 - Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_6: 4 loads, 4 LSLICEs - Net RCLK_c_enable_5: 2 loads, 2 LSLICEs - Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_10: 3 loads, 3 LSLICEs - Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_16: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net RCLK_c_enable_15: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs - Net Ready_N_292: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs - Number of LSRs: 7 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_177: 1 loads, 1 LSLICEs - Net C1Submitted_N_237: 2 loads, 2 LSLICEs - Net n2366: 2 loads, 2 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net Ready: 18 loads - Net InitReady: 15 loads - Net RASr2: 15 loads - Net nRowColSel_N_35: 13 loads - Net nRowColSel: 12 loads - Net Din_c_4: 10 loads - Net MAin_c_1: 10 loads - Net Din_c_5: 9 loads - Net MAin_c_0: 9 loads - Net Din_c_0: 8 loads - - - Number of warnings: 0 - Number of errors: 0 - - - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 41 MB - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. - -ncd2vdb "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb" - -Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. - -trce -f "RAM2GS_LCMXO2_1200HC_impl1.mt" -o "RAM2GS_LCMXO2_1200HC_impl1.tw1" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:07 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 349 Score: 848079 -Cumulative negative slack: 584487 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:07 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 349 (setup), 0 (hold) -Score: 848079 (setup), 0 (hold) -Cumulative negative slack: 584487 (584487+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 48 MB - - -ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo" -w -neg -ldbanno: version Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. - - -Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. -Writing Verilog netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 40 MB - -ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" -w -neg -ldbanno: version Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. - - -Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. -Writing VHDL netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho -Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 41 MB - -mpartrce -p "RAM2GS_LCMXO2_1200HC_impl1.p2t" -f "RAM2GS_LCMXO2_1200HC_impl1.p3t" -tf "RAM2GS_LCMXO2_1200HC_impl1.pt" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.ncd" - ----- MParTrce Tool ---- -Removing old design directory at request of -rem command line option to this program. -Running par. Please wait . . . - -Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -Tue Aug 15 05:22:08 2023 - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 67+4(JTAG)/108 66% used - 67+4(JTAG)/80 89% bonded - - SLICE 75/640 11% used - - - -Number of Signals: 285 -Number of Connections: 674 - - -Pin Constraint Summary: - 66 out of 67 pins locked (98% locked). - -The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 40) - PHI2_c (driver: PHI2, clk load #: 13) - - - - -The following 1 signal is selected to use the secondary clock routing resources: - nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) - - -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -.......... -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -................... -Placer score = 143529. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 143450 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 0 out of 8 (0%) - General PIO: 3 out of 108 (2%) - PLL : 0 out of 1 (0%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 - SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 - - PRIMARY : 2 out of 8 (25%) - SECONDARY: 1 out of 8 (12%) - -Edge Clocks: - No edge clock selected. - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. - 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. - Number of PIO comps: 67; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 2.5V | - | -| 1 | 20 / 21 ( 95%) | 2.5V | - | -| 2 | 17 / 20 ( 85%) | 2.5V | - | -| 3 | 17 / 20 ( 85%) | 2.5V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 3 secs - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - -0 connections routed; 674 unrouted. -Starting router resource preassignment - - - - - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 05:22:14 08/15/23 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 05:22:14 08/15/23 - -Start NBR section for initial routing at 05:22:14 08/15/23 -Level 1, iteration 1 -2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; -Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs -Level 2, iteration 1 -11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs -Level 3, iteration 1 -20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs -Level 4, iteration 1 -11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 05:22:15 08/15/23 -Level 1, iteration 1 -7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs -Level 4, iteration 1 -9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs -Level 4, iteration 2 -6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs -Level 4, iteration 3 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 4 -6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs -Level 4, iteration 5 -4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 6 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs -Level 4, iteration 7 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 8 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs -Level 4, iteration 9 -2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 10 -3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs -Level 4, iteration 11 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 12 -3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; -Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs -Level 4, iteration 13 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 14 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs -Level 4, iteration 15 -2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 16 -3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 17 -2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 18 -1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; -Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs -Level 4, iteration 19 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 20 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 21 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 22 -1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs -Level 4, iteration 23 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 24 -1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs -Level 4, iteration 25 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23 -Level 4, iteration 1 -1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs -Level 4, iteration 2 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for re-routing at 05:22:15 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; -Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs - -Start NBR section for post-routing at 05:22:15 08/15/23 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 254 (37.69%) - Estimated worst slack : -4.650ns - Timing score : 391939 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - - - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 391939 - -Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -4.650 -PAR_SUMMARY::Timing score> = 391.939 -PAR_SUMMARY::Worst slack> = 0.304 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Exiting par with exit code 0 -Exiting mpartrce with exit code 0 - -trce -f "RAM2GS_LCMXO2_1200HC_impl1.pt" -o "RAM2GS_LCMXO2_1200HC_impl1.twr" "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:16 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 335 Score: 391939 -Cumulative negative slack: 304509 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:22:16 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -Design file: ram2gs_lcmxo2_1200hc_impl1.ncd -Preference file: ram2gs_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 335 (setup), 0 (hold) -Score: 391939 (setup), 0 (hold) -Cumulative negative slack: 304509 (304509+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 46 MB - - -iotiming "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" -I/O Timing Report: -: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application iotiming from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 4 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 5 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 6 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: M -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... -Done. - -tmcheck -par "RAM2GS_LCMXO2_1200HC_impl1.par" - -bitgen -f "RAM2GS_LCMXO2_1200HC_impl1.t2b" -w "RAM2GS_LCMXO2_1200HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_1200HC_impl1.prf" - - -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - - -Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 511 Pages (128*511 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). -Initialized UFM Pages: 0 Page. - -Total CPU Time: 1 secs -Total REAL Time: 2 secs -Peak Memory Usage: 253 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html deleted file mode 100644 index 2f2bbe3..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html +++ /dev/null @@ -1,9 +0,0 @@ - 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
-Done: design load finished with (0) errors, and (0) warnings
-
-
    \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/impl1.xcf b/CPLD/LCMXO2-1200HC/impl1/impl1.xcf deleted file mode 100644 index 9cdf76b..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/impl1.xcf +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - JTAG - - - 1 - Lattice - MachXO2 - LCMXO2-1200HC - 0x012ba043 - All - LCMXO2-1200HC - - 8 - 11111111 - 1 - 0 - - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed - 08/15/23 05:01:25 - 0x680B - FLASH Erase,Program,Verify - - - - - SEQUENTIAL - ENTIRED CHAIN - No Override - TLR - TLR - - 1 - - - USB - EzUSB-0 - \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# - - TRST ABSENT; - ISPEN ABSENT; - - - diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior deleted file mode 100644 index 7695bfd..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior +++ /dev/null @@ -1,139 +0,0 @@ -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -// Design: RAM2GS -// Package: TQFP100 -// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd -// Version: Diamond (64-bit) 3.12.1.454 -// Written on Tue Aug 15 05:22:17 2023 -// M: Minimum Performance Grade -// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml - -I/O Timing Report (All units are in ns) - -Worst Case Results across Performance Grades (M, 6, 5, 4): - -// Input Setup and Hold Times - -Port Clock Edge Setup Performance_Grade Hold Performance_Grade ----------------------------------------------------------------------- -CROW[0] nCRAS F 0.891 4 0.676 4 -CROW[1] nCRAS F 0.281 4 1.216 4 -Din[0] PHI2 F 7.907 4 0.089 6 -Din[0] nCCAS F 1.465 4 0.158 4 -Din[1] PHI2 F 7.300 4 1.026 4 -Din[1] nCCAS F 1.035 4 0.527 4 -Din[2] PHI2 F 6.237 4 1.467 4 -Din[2] nCCAS F 1.719 4 -0.108 M -Din[3] PHI2 F 6.623 4 0.176 6 -Din[3] nCCAS F 0.339 4 0.916 4 -Din[4] PHI2 F 6.902 4 1.033 4 -Din[4] nCCAS F 0.687 4 0.951 4 -Din[5] PHI2 F 6.837 4 1.369 4 -Din[5] nCCAS F 2.810 4 -0.220 M -Din[6] PHI2 F 7.648 4 -0.050 M -Din[6] nCCAS F 1.281 4 0.266 4 -Din[7] PHI2 F 7.823 4 -0.159 M -Din[7] nCCAS F 1.810 4 -0.096 M -MAin[0] PHI2 F 6.751 4 -0.273 M -MAin[0] nCRAS F 1.765 4 -0.033 4 -MAin[1] PHI2 F 5.718 4 0.117 M -MAin[1] nCRAS F 1.814 4 -0.051 M -MAin[2] PHI2 F 5.759 4 -0.021 M -MAin[2] nCRAS F 1.323 4 0.309 4 -MAin[3] PHI2 F 6.165 4 -0.235 M -MAin[3] nCRAS F 0.694 4 0.836 4 -MAin[4] PHI2 F 5.236 4 -0.147 M -MAin[4] nCRAS F 0.730 4 0.835 4 -MAin[5] PHI2 F 6.024 4 0.135 M -MAin[5] nCRAS F 0.734 4 0.868 4 -MAin[6] PHI2 F 5.689 4 -0.277 M -MAin[6] nCRAS F 0.288 4 1.210 4 -MAin[7] PHI2 F 6.398 4 -0.307 M -MAin[7] nCRAS F 1.215 4 0.401 4 -MAin[8] nCRAS F 0.817 4 0.727 4 -MAin[9] nCRAS F 0.941 4 0.601 4 -PHI2 RCLK R 0.771 4 1.143 4 -UFMSDO RCLK R -0.238 M 2.305 4 -nCCAS RCLK R 1.651 4 0.388 4 -nCCAS nCRAS F 5.028 4 -0.828 M -nCRAS RCLK R 0.593 4 1.309 4 -nFWE PHI2 F 5.741 4 0.781 4 -nFWE nCRAS F 0.578 4 0.996 4 - - -// Clock to Output Delay - -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------- -LED RCLK R 14.758 4 4.129 M -LED nCRAS F 12.396 4 3.434 M -RA[0] RCLK R 13.780 4 3.894 M -RA[0] nCRAS F 11.795 4 3.277 M -RA[10] RCLK R 12.425 4 3.587 M -RA[11] PHI2 R 10.432 4 3.084 M -RA[1] RCLK R 15.081 4 4.198 M -RA[1] nCRAS F 12.364 4 3.447 M -RA[2] RCLK R 14.518 4 4.082 M -RA[2] nCRAS F 11.696 4 3.275 M -RA[3] RCLK R 13.789 4 3.897 M -RA[3] nCRAS F 12.223 4 3.392 M -RA[4] RCLK R 15.175 4 4.228 M -RA[4] nCRAS F 12.424 4 3.464 M -RA[5] RCLK R 13.789 4 3.897 M -RA[5] nCRAS F 12.359 4 3.437 M -RA[6] RCLK R 15.420 4 4.299 M -RA[6] nCRAS F 12.865 4 3.560 M -RA[7] RCLK R 14.672 4 4.127 M -RA[7] nCRAS F 12.253 4 3.386 M -RA[8] RCLK R 14.952 4 4.191 M -RA[8] nCRAS F 12.244 4 3.383 M -RA[9] RCLK R 14.092 4 3.978 M -RA[9] nCRAS F 13.164 4 3.653 M -RBA[0] nCRAS F 10.278 4 2.970 M -RBA[1] nCRAS F 10.474 4 3.030 M -RCKE RCLK R 12.407 4 3.610 M -RDQMH RCLK R 13.754 4 3.857 M -RDQML RCLK R 13.482 4 3.833 M -RD[0] nCCAS F 10.515 4 3.076 M -RD[1] nCCAS F 10.118 4 2.965 M -RD[2] nCCAS F 9.759 4 2.886 M -RD[3] nCCAS F 9.798 4 2.878 M -RD[4] nCCAS F 10.979 4 3.178 M -RD[5] nCCAS F 11.063 4 3.207 M -RD[6] nCCAS F 10.317 4 3.018 M -RD[7] nCCAS F 10.232 4 2.986 M -UFMCLK RCLK R 12.402 4 3.606 M -UFMSDI RCLK R 11.975 4 3.501 M -nRCAS RCLK R 12.350 4 3.564 M -nRCS RCLK R 11.923 4 3.459 M -nRRAS RCLK R 11.995 4 3.494 M -nRWE RCLK R 11.975 4 3.501 M -nUFMCS RCLK R 11.818 4 3.434 M -WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with hold speed: 6 -WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd deleted file mode 100644 index 0894708..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd +++ /dev/null @@ -1,13 +0,0 @@ -[ActiveSupport TRCE] -; Setup Analysis -Fmax_0 = 174.216 MHz (299.401 MHz); -Fmax_1 = 67.833 MHz (99.079 MHz); -Failed = 2 (Total 2); -Clock_ports = 4; -Clock_nets = 4; -; Hold Analysis -Fmax_0 = 0.304 ns (0.000 ns); -Fmax_1 = 0.379 ns (0.000 ns); -Failed = 0 (Total 2); -Clock_ports = 4; -Clock_nets = 4; diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis.log b/CPLD/LCMXO2-1200HC/impl1/synthesis.log deleted file mode 100644 index fee4113..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/synthesis.log +++ /dev/null @@ -1,239 +0,0 @@ -synthesis: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:25 2023 - - -Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml - -Synthesis options: -The -a option is MachXO2. -The -s option is 4. -The -t option is TQFP100. -The -d option is LCMXO2-1200HC. -Using package TQFP100. -Using performance grade 4. - - -########################################################## - -### Lattice Family : MachXO2 - -### Device : LCMXO2-1200HC - -### Package : TQFP100 - -### Speed : 4 - -########################################################## - - - -INFO - synthesis: User-Selected Strategy Settings -Optimization goal = Balanced -Top-level module name = RAM2GS. -Target frequency = 200.000000 MHz. -Maximum fanout = 1000. -Timing path count = 3 -BRAM utilization = 100.000000 % -DSP usage = true -DSP utilization = 100.000000 % -fsm_encoding_style = auto -resolve_mixed_drivers = 0 -fix_gated_clocks = 1 - -Mux style = Auto -Use Carry Chain = true -carry_chain_length = 0 -Loop Limit = 1950. -Use IO Insertion = TRUE -Use IO Reg = AUTO - -Resource Sharing = TRUE -Propagate Constants = TRUE -Remove Duplicate Registers = TRUE -force_gsr = auto -ROM style = auto -RAM style = auto -The -comp option is FALSE. -The -syn option is FALSE. --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) --p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added) --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) -Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v -NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd --sdc option: SDC file input not used. --lpf option: Output file option is ON. -Hardtimer checking is enabled (default). The -dt option is not used. -The -r option is OFF. [ Remove LOC Properties is OFF. ] -Technology check ok... - -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Compile design. -Compile Design Begin -Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Top module name (Verilog): RAM2GS -INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 -WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 -WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 -WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Top-level module name = RAM2GS. -INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding -original encoding -> new encoding (one-hot encoding) - - 0000 -> 0000000000000001 - - 0001 -> 0000000000000010 - - 0010 -> 0000000000000100 - - 0011 -> 0000000000001000 - - 0100 -> 0000000000010000 - - 0101 -> 0000000000100000 - - 0110 -> 0000000001000000 - - 0111 -> 0000000010000000 - - 1000 -> 0000000100000000 - - 1001 -> 0000001000000000 - - 1010 -> 0000010000000000 - - 1011 -> 0000100000000000 - - 1100 -> 0001000000000000 - - 1101 -> 0010000000000000 - - 1110 -> 0100000000000000 - - 1111 -> 1000000000000000 - -INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding -original encoding -> new encoding (one-hot encoding) - - 00 -> 0001 - - 01 -> 0010 - - 10 -> 0100 - - 11 -> 1000 - - - - -GSR will not be inferred because no asynchronous signal was found in the netlist. -WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. -Applying 200.000000 MHz constraint to all clocks - -WARNING - synthesis: No user .sdc file. -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. - -################### Begin Area Report (RAM2GS)###################### -Number of register bits => 102 of 1520 (6 % ) -BB => 8 -CCU2D => 10 -FD1P3AX => 29 -FD1P3AY => 5 -FD1P3IX => 3 -FD1S3AX => 47 -FD1S3IX => 14 -FD1S3JX => 4 -GSR => 1 -IB => 26 -INV => 3 -LUT4 => 122 -OB => 33 -PFUMX => 1 -################### End Area Report ################## - -################### Begin BlackBox Report ###################### -TSALL => 1 -################### End BlackBox Report ################## - -################### Begin Clock Report ###################### -Clock Nets -Number of Clocks: 4 - Net : RCLK_c, loads : 62 - Net : PHI2_c, loads : 11 - Net : nCCAS_c, loads : 2 - Net : nCRAS_c, loads : 2 -Clock Enable Nets -Number of Clock Enables: 14 -Top 10 highest fanout Clock Enables: - Net : RCLK_c_enable_27, loads : 16 - Net : RCLK_c_enable_6, loads : 4 - Net : PHI2_N_120_enable_8, loads : 3 - Net : RCLK_c_enable_10, loads : 3 - Net : RCLK_c_enable_5, loads : 2 - Net : PHI2_N_120_enable_3, loads : 1 - Net : Ready_N_292, loads : 1 - Net : PHI2_N_120_enable_2, loads : 1 - Net : RCLK_c_enable_15, loads : 1 - Net : PHI2_N_120_enable_6, loads : 1 -Highest fanout non-clock nets -Top 10 highest fanout non-clock nets: - Net : RCLK_c_enable_27, loads : 16 - Net : InitReady, loads : 15 - Net : nCRAS_c__inv, loads : 15 - Net : RASr2, loads : 14 - Net : nRowColSel_N_35, loads : 13 - Net : n2380, loads : 13 - Net : nRowColSel, loads : 12 - Net : Ready, loads : 12 - Net : Din_c_4, loads : 10 - Net : MAin_c_1, loads : 10 -################### End Clock Report ################## - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - - -Peak Memory Usage: 55.238 MB - --------------------------------------------------------------- -Elapsed CPU time for LSE flow : 0.891 secs --------------------------------------------------------------- diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html deleted file mode 100644 index 1a480d5..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html +++ /dev/null @@ -1,304 +0,0 @@ - -Synthesis and Ngdbuild Report - - -
    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:25 2023
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
-
-Synthesis options:
-The -a option is MachXO2.
-The -s option is 4.
-The -t option is TQFP100.
-The -d option is LCMXO2-1200HC.
-Using package TQFP100.
-Using performance grade 4.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO2
-
-### Device  : LCMXO2-1200HC
-
-### Package : TQFP100
-
-### Speed   : 4
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
-Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
-NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 1520 (6 % )
-BB => 8
-CCU2D => 10
-FD1P3AX => 29
-FD1P3AY => 5
-FD1P3IX => 3
-FD1S3AX => 47
-FD1S3IX => 14
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-LUT4 => 122
-OB => 33
-PFUMX => 1
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 14
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : RCLK_c_enable_6, loads : 4
-  Net : PHI2_N_120_enable_8, loads : 3
-  Net : RCLK_c_enable_10, loads : 3
-  Net : RCLK_c_enable_5, loads : 2
-  Net : PHI2_N_120_enable_3, loads : 1
-  Net : Ready_N_292, loads : 1
-  Net : PHI2_N_120_enable_2, loads : 1
-  Net : RCLK_c_enable_15, loads : 1
-  Net : PHI2_N_120_enable_6, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : InitReady, loads : 15
-  Net : nCRAS_c__inv, loads : 15
-  Net : RASr2, loads : 14
-  Net : nRowColSel_N_35, loads : 13
-  Net : n2380, loads : 13
-  Net : nRowColSel, loads : 12
-  Net : Ready, loads : 12
-  Net : Din_c_4, loads : 10
-  Net : MAin_c_1, loads : 10
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 55.238  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.891  secs
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    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list deleted file mode 100644 index 1c1a02c..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list +++ /dev/null @@ -1,250 +0,0 @@ -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v -3 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-LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" -LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" -LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" -LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" -LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" -LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" -LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" -LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" -LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" -LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" -LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" -LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" -LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" -LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" -LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" -LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" -LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" -LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" -LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" -LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" -LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" -LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" -LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" -LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" -LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" -LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" -LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" -LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" -LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" -LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" -LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" -LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" -LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" -LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" -LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]" -LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" -LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" -LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" -LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" -LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" -LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" -LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" -LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" -LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" -LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" -LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini index 713c9cf..4c7a004 100644 --- a/CPLD/LCMXO2-640HC/.setting.ini +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -1,4 +1,4 @@ [General] Export.auto_tasks=Jedecgen -PAR.auto_tasks=PARTrace, IOTiming -Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile +PAR.auto_tasks=@@empty() +Map.auto_tasks=@@empty() diff --git a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini index f26306f..0d0cdb7 100644 --- a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini +++ b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini @@ -6,14 +6,14 @@ sig_sort_ascending=true active_Sheet=Port Assignments [Port%20Assignments] -Name="164,0" +Name="154,0" Group%20By="84,1" Pin="50,2" BANK="62,3" BANK_VCC="90,4" VREF="60,5" IO_TYPE="147,6" -PULLMODE="97,7" +PULLMODE="119,7" DRIVE="67,8" SLEWRATE="92,9" CLAMP="71,10" @@ -63,7 +63,7 @@ Name="100,ELLIPSIS" Prioritize="100,ELLIPSIS" [Timing%20Preferences] -Preference%20Name="129,ELLIPSIS" +Preference%20Name="158,ELLIPSIS" Preference%20Value="105,ELLIPSIS" Preference%20Unit="98,ELLIPSIS" diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf index 49c9e13..5b8e620 100644 --- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf @@ -1,7 +1,7 @@ - + @@ -12,6 +12,9 @@ + + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf index 63de512..dbcda5a 100644 --- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf @@ -25,7 +25,7 @@ LOCATE COMP "MAin[7]" SITE "18" ; LOCATE COMP "MAin[8]" SITE "25" ; LOCATE COMP "MAin[9]" SITE "32" ; LOCATE COMP "UFMSDO" SITE "27" ; -LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "nFWE" SITE "15" ; LOCATE COMP "Dout[0]" SITE "76" ; LOCATE COMP "Dout[1]" SITE "86" ; LOCATE COMP "Dout[2]" SITE "87" ; @@ -52,8 +52,8 @@ LOCATE COMP "RBA[1]" SITE "60" ; LOCATE COMP "RCKE" SITE "53" ; LOCATE COMP "RDQMH" SITE "51" ; LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "UFMCLK" SITE "28" ; +LOCATE COMP "UFMSDI" SITE "29" ; LOCATE COMP "nRCAS" SITE "52" ; LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "nRRAS" SITE "54" ; @@ -66,3 +66,71 @@ LOCATE COMP "RD[4]" SITE "40" ; LOCATE COMP "RD[5]" SITE "41" ; LOCATE COMP "RD[6]" SITE "42" ; LOCATE COMP "RD[7]" SITE "43" ; +IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS33 DRIVE=NA PULLMODE=KEEPER ; +IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS33 SLEWRATE=NA DRIVE=NA PULLMODE=KEEPER ; +IOBUF PORT "PHI2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "nCCAS" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "nCRAS" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ; +IOBUF PORT "nFWE" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "LED" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=24 SLEWRATE=SLOW ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RCKE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RDQMH" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RDQML" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "nRCAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "nRCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "nRRAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ; +LOCATE COMP "nUFMCS" SITE "30" ; diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty index feec63c..39b91c8 100644 --- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty @@ -88,7 +88,7 @@ - + @@ -172,15 +172,15 @@ - - + + - + - + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr new file mode 100644 index 0000000..391d367 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr @@ -0,0 +1,79 @@ +#Start recording tcl command: 8/15/2023 22:16:47 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" +prj_run Export -impl impl1 +prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc" +prj_run Export -impl impl1 +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 -forceAll +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +prj_run Export -impl impl1 -forceAll +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +prj_run Export -impl impl1 +launch_synplify_prj impl1 +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_strgy set_value -strategy Strategy1 syn_pipelining_retiming=None syn_frequency=70 +prj_strgy set_value -strategy Strategy1 map_io_reg=Both +prj_run Export -impl impl1 +prj_run Export -impl impl1 +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_project close +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_project close +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_project close +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_project close +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +prj_run Export -impl impl1 +pgr_program run +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +prj_run Export -impl impl1 -forceAll +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_program run +prj_run Export -impl impl1 +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +pgr_program run +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_program run +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 -forceAll +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +prj_run Export -impl impl1 +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +pgr_program run +pgr_program run +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_run Export -impl impl1 +pgr_program run +pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf" +prj_project save +prj_project close +#Stop recording: 8/16/2023 01:57:20 diff --git a/CPLD/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2-640HC/impl1/.build_status index 96c9059..c1e52c6 100644 --- a/CPLD/LCMXO2-640HC/impl1/.build_status +++ b/CPLD/LCMXO2-640HC/impl1/.build_status @@ -6,43 +6,46 @@ - + - - - - - + + + + + - - - - + + + + - - - + + - - + + + + + - - - + + + + - - - - - - - - - + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt index 4bf1035..84dc5f9 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt @@ -1,9 +1,24 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Tue Aug 15 05:03:41 2023 * +NOTE DATE CREATED: Tue Aug 15 23:30:13 2023 * NOTE DESIGN NAME: RAM2GS * NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * NOTE PIN ASSIGNMENTS * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS UFMSDO : 27 : in * +NOTE PINS UFMSDI : 29 : out * +NOTE PINS UFMCLK : 28 : out * +NOTE PINS nUFMCS : 30 : out * +NOTE PINS RDQML : 48 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS RCLK : 62 : in * +NOTE PINS nRCS : 57 : out * NOTE PINS RD[7] : 43 : inout * NOTE PINS RD[6] : 42 : inout * NOTE PINS RD[5] : 41 : inout * @@ -11,18 +26,6 @@ NOTE PINS RD[4] : 40 : inout * NOTE PINS RD[3] : 39 : inout * NOTE PINS RD[2] : 38 : inout * NOTE PINS RD[1] : 37 : inout * -NOTE PINS RD[0] : 36 : inout * -NOTE PINS Dout[7] : 82 : out * -NOTE PINS Dout[6] : 78 : out * -NOTE PINS Dout[5] : 84 : out * -NOTE PINS Dout[4] : 83 : out * -NOTE PINS Dout[3] : 85 : out * -NOTE PINS Dout[2] : 87 : out * -NOTE PINS Dout[1] : 86 : out * -NOTE PINS Dout[0] : 76 : out * -NOTE PINS LED : 34 : out * -NOTE PINS RBA[1] : 60 : out * -NOTE PINS RBA[0] : 58 : out * NOTE PINS RA[11] : 59 : out * NOTE PINS RA[10] : 64 : out * NOTE PINS RA[9] : 63 : out * @@ -35,17 +38,29 @@ NOTE PINS RA[3] : 71 : out * NOTE PINS RA[2] : 69 : out * NOTE PINS RA[1] : 67 : out * NOTE PINS RA[0] : 66 : out * -NOTE PINS nRCS : 57 : out * -NOTE PINS RCKE : 53 : out * -NOTE PINS nRWE : 49 : out * -NOTE PINS nRRAS : 54 : out * -NOTE PINS nRCAS : 52 : out * -NOTE PINS RDQMH : 51 : out * -NOTE PINS RDQML : 48 : out * -NOTE PINS nUFMCS : 77 : out * -NOTE PINS UFMCLK : 29 : out * -NOTE PINS UFMSDI : 30 : out * -NOTE PINS PHI2 : 8 : in * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS LED : 34 : out * +NOTE PINS nFWE : 15 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * NOTE PINS MAin[9] : 32 : in * NOTE PINS MAin[8] : 25 : in * NOTE PINS MAin[7] : 18 : in * @@ -56,20 +71,5 @@ NOTE PINS MAin[3] : 21 : in * NOTE PINS MAin[2] : 13 : in * NOTE PINS MAin[1] : 12 : in * NOTE PINS MAin[0] : 14 : in * -NOTE PINS CROW[1] : 16 : in * -NOTE PINS CROW[0] : 10 : in * -NOTE PINS Din[7] : 1 : in * -NOTE PINS Din[6] : 2 : in * -NOTE PINS Din[5] : 98 : in * -NOTE PINS Din[4] : 99 : in * -NOTE PINS Din[3] : 97 : in * -NOTE PINS Din[2] : 88 : in * -NOTE PINS Din[1] : 96 : in * -NOTE PINS Din[0] : 3 : in * -NOTE PINS nCCAS : 9 : in * -NOTE PINS nCRAS : 17 : in * -NOTE PINS nFWE : 28 : in * -NOTE PINS RCLK : 62 : in * -NOTE PINS UFMSDO : 27 : in * NOTE CONFIGURATION MODE: NONE * NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr new file mode 100644 index 0000000..41b5352 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr @@ -0,0 +1,29 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.verilog + +Register bits: 90 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 11 100.0 + FD1S3AX 49 100.0 + FD1S3AY 1 100.0 + FD1S3IX 3 100.0 + GSR 1 100.0 + IB 26 100.0 + IFS1P3DX 9 100.0 + INV 7 100.0 + OB 33 100.0 + OFS1P3BX 4 100.0 + OFS1P3DX 12 100.0 + OFS1P3JX 1 100.0 + ORCALUT4 135 100.0 + PFUMX 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 314 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn index e34c8b7..e41242e 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:39 2023 +Tue Aug 15 23:30:11 2023 Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf @@ -83,4 +83,4 @@ Initialized UFM Pages: 0 Page. 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real time: 7 secs +0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs Level 2, iteration 1 -7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; -Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs Level 3, iteration 1 -12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; -Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:03:35 08/15/23 +Start NBR section for normal routing at 23:30:11 08/15/23 Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Level 4, iteration 2 -3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs -Level 4, iteration 3 -2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 5 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23 + +Start NBR section for re-routing at 23:30:11 08/15/23 Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for re-routing at 05:03:35 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs - -Start NBR section for post-routing at 05:03:35 08/15/23 +Start NBR section for post-routing at 23:30:11 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 260 (38.58%) - Estimated worst slack : -5.122ns - Timing score : 452301 + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 5.827ns + Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Total CPU time 7 secs -Total REAL time: 7 secs +Total CPU time 5 secs +Total REAL time: 6 secs Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. +End of route. 703 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 -Timing score: 452301 +Timing score: 0 Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. @@ -211,14 +194,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -5.122 -PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 5.827 +PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 7 secs -Total REAL time to completion: 7 secs +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd index cf7ea22..293586e 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd @@ -4,35 +4,40 @@ GLOBAL_PRIMARY_USED = 2; ; Global primary clock #0 GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_0_LOADNUM = 40; +GLOBAL_PRIMARY_0_LOADNUM = 39; ; Global primary clock #1 GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_1_LOADNUM = 13; +GLOBAL_PRIMARY_1_LOADNUM = 18; ; # of global secondary clocks -GLOBAL_SECONDARY_USED = 1; +GLOBAL_SECONDARY_USED = 2; ; Global secondary clock #0 GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; -GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_LOADNUM = 11; GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; Global secondary clock #1 +GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c; +GLOBAL_SECONDARY_1_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_1_LOADNUM = 10; +GLOBAL_SECONDARY_1_SIGTYPE = CLK; ; I/O Bank 0 Usage -BANK_0_USED = 14; +BANK_0_USED = 13; BANK_0_AVAIL = 19; -BANK_0_VCCIO = 2.5V; +BANK_0_VCCIO = 3.3V; BANK_0_VREF1 = NA; ; I/O Bank 1 Usage BANK_1_USED = 20; BANK_1_AVAIL = 20; -BANK_1_VCCIO = 2.5V; +BANK_1_VCCIO = 3.3V; BANK_1_VREF1 = NA; ; I/O Bank 2 Usage BANK_2_USED = 16; BANK_2_AVAIL = 20; -BANK_2_VCCIO = 2.5V; +BANK_2_VCCIO = 3.3V; BANK_2_VREF1 = NA; ; I/O Bank 3 Usage -BANK_3_USED = 17; +BANK_3_USED = 18; BANK_3_AVAIL = 20; -BANK_3_VCCIO = 2.5V; +BANK_3_VCCIO = 3.3V; BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par index 6a48b30..a998d0c 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:28 2023 +Tue Aug 15 23:30:05 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir @@ -17,11 +17,11 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -5.122 452301 0.304 0 07 Completed +5_1 * 0 5.827 0 0.304 0 06 Completed * : Design saved. -Total (real) run time for 1-seed: 7 secs +Total (real) run time for 1-seed: 6 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi new file mode 100644 index 0000000..84a0084 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi @@ -0,0 +1,2989 @@ +(edif RAM2GS + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2023 8 15 23 12 46) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell CCU2D (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A0 (direction INPUT)) + (port B0 (direction INPUT)) + (port C0 (direction INPUT)) + (port D0 (direction INPUT)) + (port A1 (direction INPUT)) + (port B1 (direction INPUT)) + (port C1 (direction INPUT)) + (port D1 (direction INPUT)) + (port CIN (direction INPUT)) + (port COUT (direction OUTPUT)) + (port S0 (direction OUTPUT)) + (port S1 (direction OUTPUT)) + ) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0000")) + (property INIT0 (string "0000")) + ) + ) + (cell BB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port B (direction INOUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell OB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell FD1S3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AY (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3JX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3BX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell ORCALUT4 (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell PFUMX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port ALUT (direction INPUT)) + (port BLUT (direction INPUT)) + (port C0 (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell RAM2GS (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port PHI2 (direction INPUT)) + (port (array (rename main "MAin[9:0]") 10) (direction INPUT)) + (port (array (rename crow "CROW[1:0]") 2) (direction INPUT)) + (port (array (rename din "Din[7:0]") 8) (direction INPUT)) + (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) + (port nCCAS (direction INPUT)) + (port nCRAS (direction INPUT)) + (port nFWE (direction INPUT)) + (port LED (direction OUTPUT)) + (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT)) + (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) + (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) + (port nRCS (direction OUTPUT)) + (port RCLK (direction INPUT)) + (port RCKE (direction OUTPUT)) + (port nRWE (direction OUTPUT)) + (port nRRAS (direction OUTPUT)) + (port nRCAS (direction OUTPUT)) + (port RDQMH (direction OUTPUT)) + (port RDQML (direction OUTPUT)) + (port nUFMCS (direction OUTPUT)) + (port UFMCLK (direction OUTPUT)) + (port UFMSDI (direction OUTPUT)) + (port UFMSDO (direction INPUT)) + ) + (contents + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) + ) + (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) + ) + (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (B+A)+C A))")) + ) + (instance UFMSDI_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!B !A))")) + ) + (instance UFMSDI_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance UFMCLK_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA11_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT))) + ) + (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C B))")) + ) + (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+A)+D (!C (!B+A)))")) + ) + (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance UFMCLK_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B+A)))")) + ) + (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance CmdEnable17_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)+C (B !A))+D (!C+!A))")) + ) + (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C !A)")) + ) + (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !A+C (B !A))")) + ) + (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(B+A)))")) + ) + (instance un1_FS_13_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_FS_14_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance un1_CmdEnable20_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) + ) + (instance UFMCLK_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A))")) + ) + (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) + ) + (instance nRWE_s_i_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))")) + ) + (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (!B A)+C !B))")) + ) + (instance C1WR_7_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance un1_CmdEnable20_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !A)+D (!C (!B !A)+C !A))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) + ) + (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance nUFMCS_s_0_m4_yy (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) + ) + (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) + ) + (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D A)")) + ) + (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + ) + (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + ) + (instance nRCAS_r_i_a3_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (C (!B A)))")) + ) + (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) + ) + (instance un1_CmdEnable20_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance C1WR_7_0_o3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(C+(B+!A)))")) + ) + (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B !A))")) + ) + (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (!B A))")) + ) + (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B A)))")) + ) + (instance CmdEnable16_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+A))")) + ) + (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) + ) + (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance XOR8MEG_3_u_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance C1Submitted_s_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance UFMCLK_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance CmdEnable16_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A)))")) + ) + (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance C1WR_7_0_o3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+!A)))")) + ) + (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_CmdEnable20_0_o3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+!A))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A)))")) + ) + (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance CmdEnable17_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_0 "un9_RA_i_m3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_1 "un9_RA_i_m3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_2 "un9_RA_i_m3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_3 "un9_RA_i_m3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_4 "un9_RA_i_m3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_5 "un9_RA_i_m3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_6 "un9_RA_i_m3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_7 "un9_RA_i_m3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_9 "un9_RA_i_m3[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance un1_PHI2r3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance C1WR_7_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance CmdEnable17_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) + ) + (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) + ) + (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C !B+C (!B !A)))")) + ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C (!B !A))")) + ) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D A)")) + ) + (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (!C A+C !B))")) + ) + (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))")) + ) + (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A))+D (!B A))")) + ) + (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance nRRAS_5_u_i_0_RNILD5I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) + ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x5002")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_15 "FS_cry_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (net CBR (joined + (portRef Q (instanceRef CBR)) + (portRef A (instanceRef nRCS_0io_RNO_0)) + (portRef A (instanceRef nRWE_0io_RNO_1)) + (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u)) + (portRef B (instanceRef nRowColSel_0_0_a3_0)) + (portRef A (instanceRef LED_pad_RNO)) + (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + )) + (net C1Submitted (joined + (portRef Q (instanceRef C1Submitted)) + (portRef A (instanceRef C1Submitted_s_0)) + (portRef A (instanceRef un1_CmdEnable20_0_a2_1)) + )) + (net (rename Bank_2 "Bank[2]") (joined + (portRef Q (instanceRef Bank_0io_2)) + (portRef B (instanceRef C1WR_7_0_o3_6)) + )) + (net Ready (joined + (portRef Q (instanceRef Ready)) + (portRef B (instanceRef IS_RNO_0)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef D (instanceRef nRCS_0io_RNO)) + (portRef C (instanceRef nRWE_0io_RNO_1)) + (portRef D (instanceRef RCKEEN_8_u)) + (portRef D (instanceRef nRowColSel_0_0_a3_0)) + (portRef D (instanceRef nRRAS_5_u_i_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef C (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef A (instanceRef Ready_RNO)) + (portRef A (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef S_RNICVV51_0)) + )) + (net n8MEGEN (joined + (portRef Q (instanceRef n8MEGEN)) + (portRef D (instanceRef RA11d)) + (portRef C (instanceRef Cmdn8MEGEN_RNO)) + )) + (net CO0 (joined + (portRef Q (instanceRef S_0)) + (portRef D (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef nRWE_0io_RNO_0)) + (portRef B (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef S_0_i_o2_1)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef A (instanceRef S_RNO_0)) + (portRef C (instanceRef nRCAS_r_i_a3_1_1_tz)) + (portRef A (instanceRef nRowColSel_0_0)) + (portRef C (instanceRef S_RNICVV51_0)) + )) + (net (rename S_1 "S[1]") (joined + (portRef Q (instanceRef S_1)) + (portRef C (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef nRCS_0io_RNO_0)) + (portRef D (instanceRef nRWE_0io_RNO_1)) + (portRef C (instanceRef nRCAS_0io_RNO_0)) + (portRef D (instanceRef nRCAS_0io_RNO)) + (portRef D (instanceRef RCKEEN_8_u_1_0)) + (portRef B (instanceRef S_0_i_o2_1)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef B (instanceRef S_RNO_0)) + (portRef D (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef B (instanceRef S_RNICVV51_0)) + )) + (net RASr2 (joined + (portRef Q (instanceRef RASr2)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef B (instanceRef RCKE_2_0)) + (portRef B (instanceRef nRRAS_5_u_i_0)) + (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + (portRef A (instanceRef nRWE_s_i_tz_0)) + (portRef D (instanceRef RASr3)) + (portRef B (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef RASr2_RNIAFR1)) + )) + (net InitReady (joined + (portRef Q (instanceRef InitReady)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef B (instanceRef n8MEGEN_5_i_m2)) + (portRef B (instanceRef LEDEN_RNO)) + (portRef B (instanceRef UFMCLK_r_i_a2_2_2)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef B (instanceRef PHI2r3_RNITCN41)) + (portRef B (instanceRef nUFMCS_s_0_m4_yy)) + (portRef C (instanceRef nUFMCS15_0_a2)) + (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef A (instanceRef UFMSDI_ens2_i_a0)) + (portRef A (instanceRef UFMCLK_0io_RNO_1)) + (portRef B (instanceRef un1_FS_13_i_0)) + (portRef B (instanceRef un1_FS_14_i_0)) + (portRef B (instanceRef UFMCLK_0io_RNO)) + (portRef B (instanceRef InitReady_RNO)) + (portRef D (instanceRef Ready_RNO)) + (portRef C (instanceRef RCKEEN_8_u_0_0)) + )) + (net FWEr (joined + (portRef Q (instanceRef FWEr)) + (portRef B (instanceRef nRWE_0io_RNO_1)) + (portRef C (instanceRef RCKEEN_8_u_1_0)) + (portRef C (instanceRef nRowColSel_0_0_a3_0)) + (portRef D (instanceRef nRCAS_r_i_a3_1_1_tz)) + )) + (net CASr3 (joined + (portRef Q (instanceRef CASr3)) + (portRef B (instanceRef nRWE_0io_RNO_0)) + (portRef A (instanceRef nRowColSel_0_0_a3_0)) + (portRef B (instanceRef nRCAS_r_i_a3_1_1_tz)) + )) + (net (rename IS_0 "IS[0]") (joined + (portRef Q (instanceRef IS_0)) + (portRef A (instanceRef IS_RNO_0)) + (portRef D (instanceRef nRRAS_5_u_i_0_RNILD5I)) + (portRef A (instanceRef IS_n1_0_x2)) + (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef IS_RNO_2)) + (portRef A (instanceRef nRRAS_5_u_i)) + (portRef A (instanceRef nRWE_s_i_a3_1_0)) + (portRef D (instanceRef IS_RNO_3)) + (portRef A (instanceRef RA10_0io_RNO)) + )) + (net (rename IS_3 "IS[3]") (joined + (portRef Q (instanceRef IS_3)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef RA10_0io_RNO_0)) + (portRef A (instanceRef IS_RNO_3)) + )) + (net (rename IS_2 "IS[2]") (joined + (portRef Q (instanceRef IS_2)) + (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef IS_RNO_2)) + (portRef C (instanceRef nRWE_s_i_a3_1_0)) + (portRef B (instanceRef RA10_0io_RNO_0)) + (portRef B (instanceRef IS_RNO_3)) + )) + (net (rename IS_1 "IS[1]") (joined + (portRef Q (instanceRef IS_1)) + (portRef B (instanceRef IS_n1_0_x2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef B (instanceRef IS_RNO_2)) + (portRef B (instanceRef nRWE_s_i_a3_1_0)) + (portRef A (instanceRef RA10_0io_RNO_0)) + (portRef C (instanceRef IS_RNO_3)) + )) + (net (rename FS_5 "FS[5]") (joined + (portRef Q (instanceRef FS_5)) + (portRef A0 (instanceRef FS_cry_0_5)) + (portRef D (instanceRef un1_FS_14_i_a2_0_1)) + (portRef D (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef UFMSDI_ens2_i_o2)) + )) + (net (rename FS_6 "FS[6]") (joined + (portRef Q (instanceRef FS_6)) + (portRef A1 (instanceRef FS_cry_0_5)) + (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef B (instanceRef un1_FS_13_i_a2_6)) + )) + (net (rename FS_7 "FS[7]") (joined + (portRef Q (instanceRef FS_7)) + (portRef A0 (instanceRef FS_cry_0_7)) + (portRef C (instanceRef un1_FS_13_i_a2_6)) + (portRef B (instanceRef UFMSDI_ens2_i_o2)) + )) + (net (rename FS_8 "FS[8]") (joined + (portRef Q (instanceRef FS_8)) + (portRef A1 (instanceRef FS_cry_0_7)) + (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0)) + )) + (net (rename FS_9 "FS[9]") (joined + (portRef Q (instanceRef FS_9)) + (portRef A0 (instanceRef FS_cry_0_9)) + (portRef C (instanceRef UFMSDI_ens2_i_o2)) + (portRef B (instanceRef un1_FS_13_i_a2_8)) + )) + (net (rename FS_0 "FS[0]") (joined + (portRef Q (instanceRef FS_0)) + (portRef A1 (instanceRef FS_cry_0_0)) + (portRef A (instanceRef un1_FS_14_i_a2_0_1)) + (portRef A (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_1 "FS[1]") (joined + (portRef Q (instanceRef FS_1)) + (portRef A0 (instanceRef FS_cry_0_1)) + (portRef A (instanceRef un1_FS_13_i_a2_6)) + (portRef A (instanceRef UFMCLK_r_i_m2)) + )) + (net (rename FS_2 "FS[2]") (joined + (portRef Q (instanceRef FS_2)) + (portRef A1 (instanceRef FS_cry_0_1)) + (portRef B (instanceRef un1_FS_14_i_a2_0_1)) + (portRef B (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_3 "FS[3]") (joined + (portRef Q (instanceRef FS_3)) + (portRef A0 (instanceRef FS_cry_0_3)) + (portRef C (instanceRef un1_FS_14_i_a2_0_1)) + (portRef C (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_10 "FS[10]") (joined + (portRef Q (instanceRef FS_10)) + (portRef A1 (instanceRef FS_cry_0_9)) + (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef D (instanceRef un1_FS_13_i_a2_6)) + (portRef A (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef nUFMCS15_0_a2)) + )) + (net (rename FS_11 "FS[11]") (joined + (portRef Q (instanceRef FS_11)) + (portRef A0 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef InitReady3_0_a2_3)) + (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef C (instanceRef UFMCLK_r_i_m2)) + (portRef B (instanceRef nUFMCS15_0_a2)) + (portRef C (instanceRef un1_FS_13_i_a2_8)) + )) + (net (rename FS_12 "FS[12]") (joined + (portRef Q (instanceRef FS_12)) + (portRef A1 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef A (instanceRef InitReady3_0_a2_5)) + )) + (net (rename FS_13 "FS[13]") (joined + (portRef Q (instanceRef FS_13)) + (portRef A0 (instanceRef FS_cry_0_13)) + (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef B (instanceRef InitReady3_0_a2_5)) + )) + (net (rename FS_14 "FS[14]") (joined + (portRef Q (instanceRef FS_14)) + (portRef A1 (instanceRef FS_cry_0_13)) + (portRef B (instanceRef InitReady3_0_a2_3)) + (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3)) + )) + (net (rename FS_15 "FS[15]") (joined + (portRef Q (instanceRef FS_15)) + (portRef A0 (instanceRef FS_cry_0_15)) + (portRef C (instanceRef InitReady3_0_a2_5)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) + )) + (net (rename FS_16 "FS[16]") (joined + (portRef Q (instanceRef FS_16)) + (portRef A1 (instanceRef FS_cry_0_15)) + (portRef B (instanceRef InitReady3_0_a2)) + (portRef B (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net (rename FS_17 "FS[17]") (joined + (portRef Q (instanceRef FS_17)) + (portRef A0 (instanceRef FS_s_0_17)) + (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef D (instanceRef InitReady3_0_a2_5)) + )) + (net PHI2r2 (joined + (portRef Q (instanceRef PHI2r2)) + (portRef A (instanceRef un1_PHI2r3_0)) + (portRef C (instanceRef PHI2r3_RNITCN41)) + (portRef D (instanceRef PHI2r3)) + )) + (net CmdUFMCS (joined + (portRef Q (instanceRef CmdUFMCS)) + (portRef A (instanceRef nUFMCS_s_0_m4_yy)) + )) + (net CASr2 (joined + (portRef Q (instanceRef CASr2)) + (portRef A (instanceRef nRWE_0io_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef nRCAS_r_i_a3_1_1_tz)) + (portRef D (instanceRef CASr3)) + )) + (net CASr (joined + (portRef Q (instanceRef CASr)) + (portRef D (instanceRef CASr2)) + )) + (net PHI2r (joined + (portRef Q (instanceRef PHI2r_0io)) + (portRef D (instanceRef PHI2r2)) + )) + (net RASr (joined + (portRef Q (instanceRef RASr)) + (portRef A (instanceRef RCKE_2_0)) + (portRef D (instanceRef RASr2)) + )) + (net (rename Bank_0 "Bank[0]") (joined + (portRef Q (instanceRef Bank_0io_0)) + (portRef A (instanceRef C1WR_7_0_o3_6)) + )) + (net (rename Bank_1 "Bank[1]") (joined + (portRef Q (instanceRef Bank_0io_1)) + (portRef A (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_3 "Bank[3]") (joined + (portRef Q (instanceRef Bank_0io_3)) + (portRef B (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_4 "Bank[4]") (joined + (portRef Q (instanceRef Bank_0io_4)) + (portRef C (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_5 "Bank[5]") (joined + (portRef Q (instanceRef Bank_0io_5)) + (portRef D (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_6 "Bank[6]") (joined + (portRef Q (instanceRef Bank_0io_6)) + (portRef A (instanceRef C1WR_7_0_o3)) + )) + (net (rename Bank_7 "Bank[7]") (joined + (portRef Q (instanceRef Bank_0io_7)) + (portRef B (instanceRef C1WR_7_0_o3)) + )) + (net (rename RowA_0 "RowA[0]") (joined + (portRef Q (instanceRef RowA_0)) + (portRef B (instanceRef un9_RA_i_m3_0)) + )) + (net (rename RowA_1 "RowA[1]") (joined + (portRef Q (instanceRef RowA_1)) + (portRef B (instanceRef un9_RA_i_m3_1)) + )) + (net (rename RowA_2 "RowA[2]") (joined + (portRef Q (instanceRef RowA_2)) + (portRef B (instanceRef un9_RA_i_m3_2)) + )) + (net (rename RowA_3 "RowA[3]") (joined + (portRef Q (instanceRef RowA_3)) + (portRef B (instanceRef un9_RA_i_m3_3)) + )) + (net (rename RowA_4 "RowA[4]") (joined + (portRef Q (instanceRef RowA_4)) + (portRef B (instanceRef un9_RA_i_m3_4)) + )) + (net (rename RowA_5 "RowA[5]") (joined + (portRef Q (instanceRef RowA_5)) + (portRef B (instanceRef un9_RA_i_m3_5)) + )) + (net (rename RowA_6 "RowA[6]") (joined + (portRef Q (instanceRef RowA_6)) + (portRef B (instanceRef un9_RA_i_m3_6)) + )) + (net (rename RowA_7 "RowA[7]") (joined + (portRef Q (instanceRef RowA_7)) + (portRef B (instanceRef un9_RA_i_m3_7)) + )) + (net (rename RowA_8 "RowA[8]") (joined + (portRef Q (instanceRef RowA_8)) + (portRef B (instanceRef un9_RA_8)) + )) + (net (rename RowA_9 "RowA[9]") (joined + (portRef Q (instanceRef RowA_9)) + (portRef B (instanceRef un9_RA_i_m3_9)) + )) + (net (rename WRD_0 "WRD[0]") (joined + (portRef Q (instanceRef WRD_0io_0)) + (portRef I (instanceRef RD_pad_0)) + )) + (net (rename WRD_1 "WRD[1]") (joined + (portRef Q (instanceRef WRD_0io_1)) + (portRef I (instanceRef RD_pad_1)) + )) + (net (rename WRD_2 "WRD[2]") (joined + (portRef Q (instanceRef WRD_0io_2)) + (portRef I (instanceRef RD_pad_2)) + )) + (net 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(portRef A (instanceRef ADSubmitted_r_0)) + (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2)) + )) + (net CmdEnable_0_sqmuxa (joined + (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2)) + (portRef D (instanceRef CmdEnable_s)) + )) + (net C1Submitted_s_0 (joined + (portRef Z (instanceRef C1Submitted_s_0)) + (portRef D (instanceRef C1Submitted)) + )) + (net ADSubmitted_r_0 (joined + (portRef Z (instanceRef ADSubmitted_r_0)) + (portRef D (instanceRef ADSubmitted)) + )) + (net UFMSDI_RNO (joined + (portRef Z (instanceRef UFMSDI_RNO)) + (portRef D (instanceRef UFMSDI)) + )) + (net CmdEnable_s (joined + (portRef Z (instanceRef CmdEnable_s)) + (portRef D (instanceRef CmdEnable)) + )) + (net nRowColSel_0_0 (joined + (portRef Z (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef nRowColSel)) + )) + (net XOR8MEG_3 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_0)) + (portRef D (instanceRef XOR8MEG)) + )) + (net RCKEEN_8 (joined + (portRef Z (instanceRef RCKEEN_8_u)) + (portRef D (instanceRef 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(portRef D (instanceRef UFMCLK_0io)) + )) + (net UFMSDI_ens2_i_a0 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_a0)) + (portRef A (instanceRef UFMSDI_RNO_0)) + )) + (net nUFMCS_s_0_m4_yy (joined + (portRef Z (instanceRef nUFMCS_s_0_m4_yy)) + (portRef C (instanceRef nUFMCS_s_0_N_5_i)) + )) + (net N_27_i_1 (joined + (portRef Z (instanceRef nRCAS_r_i_a3_1_1_tz)) + (portRef B (instanceRef nRCS_0io_RNO)) + (portRef A (instanceRef nRCAS_0io_RNO)) + )) + (net CmdLEDEN_4_u_i_a2_0_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0)) + (portRef B (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0)) + )) + (net CmdEnable16_0_a2_0 (joined + (portRef Z (instanceRef CmdEnable16_0_a2_0_2)) + (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2)) + )) + (net nCRAS_c_i (joined + (portRef Z (instanceRef nCRAS_pad_RNIBPVB)) + (portRef CK (instanceRef CBR)) + (portRef CK (instanceRef FWEr)) + (portRef CK (instanceRef RowA_9)) + (portRef CK (instanceRef RowA_8)) + (portRef CK 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(portRef UFMSDI) + )) + (net UFMSDO_c (joined + (portRef O (instanceRef UFMSDO_pad)) + (portRef C (instanceRef n8MEGEN_5_i_m2)) + )) + (net UFMSDO (joined + (portRef UFMSDO) + (portRef I (instanceRef UFMSDO_pad)) + )) + (net N_415_0 (joined + (portRef Z (instanceRef CmdSubmitted_RNO)) + (portRef D (instanceRef CmdSubmitted)) + )) + (net N_416_0 (joined + (portRef Z (instanceRef InitReady_RNO)) + (portRef D (instanceRef InitReady)) + )) + (net N_417_0 (joined + (portRef Z (instanceRef Ready_RNO)) + (portRef D (instanceRef Ready)) + )) + (net N_418_0 (joined + (portRef Z (instanceRef Ready_fast_RNO)) + (portRef D (instanceRef Ready_fast)) + )) + (net nFWE_c_i (joined + (portRef Z (instanceRef FWEr_RNO)) + (portRef D (instanceRef FWEr)) + )) + (net nCRAS_c_i_0 (joined + (portRef Z (instanceRef RASr_RNO)) + (portRef D (instanceRef RASr)) + )) + (net nCCAS_c_i (joined + (portRef Z (instanceRef nCCAS_pad_RNISUR8)) + (portRef D (instanceRef CASr)) + (portRef D (instanceRef CBR)) + (portRef SCLK (instanceRef WRD_0io_7)) + (portRef SCLK (instanceRef WRD_0io_6)) + (portRef SCLK (instanceRef WRD_0io_5)) + (portRef SCLK (instanceRef WRD_0io_4)) + (portRef SCLK (instanceRef WRD_0io_3)) + (portRef SCLK (instanceRef WRD_0io_2)) + (portRef SCLK (instanceRef WRD_0io_1)) + (portRef SCLK (instanceRef WRD_0io_0)) + )) + (net (rename IS_i_0 "IS_i[0]") (joined + (portRef Z (instanceRef RA10_0io_RNO)) + (portRef D (instanceRef RA10_0io)) + )) + (net RASr2_i (joined + (portRef Z (instanceRef RASr2_RNIAFR1)) + (portRef CD (instanceRef S_1)) + (portRef CD (instanceRef S_0)) + )) + (net UFMSDI_RNO_1 (joined + (portRef Z (instanceRef UFMSDI_RNO_1)) + (portRef BLUT (instanceRef UFMSDI_RNO)) + )) + (net UFMSDI_RNO_0 (joined + (portRef Z (instanceRef UFMSDI_RNO_0)) + (portRef ALUT (instanceRef UFMSDI_RNO)) + )) + (net N_1 (joined + (portRef CIN (instanceRef FS_cry_0_0)) + )) + ) + (property orig_inst_of (string "RAM2GS")) + ) + ) + ) + (design RAM2GS (cellRef RAM2GS (libraryRef work)) + (property PART (string "lcmxo2_640hc-4") )) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.fse b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.fse new file mode 100644 index 0000000..e69de29 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm new file mode 100644 index 0000000..c490adf --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm @@ -0,0 +1,9 @@ + + + syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed index 94c4dd3..bf90645 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed @@ -2,11 +2,26 @@ NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Aug 15 05:03:40 2023* +NOTE DATE CREATED: Tue Aug 15 23:30:12 2023* NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd* NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* NOTE JEDEC FILE STATUS: Final Version 1.95* NOTE PIN ASSIGNMENTS* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS UFMSDO : 27 : in* +NOTE PINS UFMSDI : 29 : out* +NOTE PINS UFMCLK : 28 : out* +NOTE PINS nUFMCS : 30 : out* +NOTE PINS RDQML : 48 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS RCLK : 62 : in* +NOTE PINS nRCS : 57 : out* NOTE PINS RD[7] : 43 : inout* NOTE PINS RD[6] : 42 : inout* NOTE PINS RD[5] : 41 : inout* @@ -14,18 +29,6 @@ NOTE PINS RD[4] : 40 : inout* NOTE PINS RD[3] : 39 : inout* NOTE PINS RD[2] : 38 : inout* NOTE PINS RD[1] : 37 : inout* -NOTE PINS RD[0] : 36 : inout* -NOTE PINS Dout[7] : 82 : out* -NOTE PINS Dout[6] : 78 : out* -NOTE PINS Dout[5] : 84 : out* -NOTE PINS Dout[4] : 83 : out* -NOTE PINS Dout[3] : 85 : out* -NOTE PINS Dout[2] : 87 : out* -NOTE PINS Dout[1] : 86 : out* -NOTE PINS Dout[0] : 76 : out* -NOTE PINS LED : 34 : out* -NOTE PINS RBA[1] : 60 : out* -NOTE PINS RBA[0] : 58 : out* NOTE PINS RA[11] : 59 : out* NOTE PINS RA[10] : 64 : out* NOTE PINS RA[9] : 63 : out* @@ -38,17 +41,29 @@ NOTE PINS RA[3] : 71 : out* NOTE PINS RA[2] : 69 : out* NOTE PINS RA[1] : 67 : out* NOTE PINS RA[0] : 66 : out* -NOTE PINS nRCS : 57 : out* -NOTE PINS RCKE : 53 : out* -NOTE PINS nRWE : 49 : out* -NOTE PINS nRRAS : 54 : out* -NOTE PINS nRCAS : 52 : out* -NOTE PINS RDQMH : 51 : out* -NOTE PINS RDQML : 48 : out* -NOTE PINS nUFMCS : 77 : out* -NOTE PINS UFMCLK : 29 : out* -NOTE PINS UFMSDI : 30 : out* -NOTE PINS PHI2 : 8 : in* +NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[0] : 58 : out* +NOTE PINS LED : 34 : out* +NOTE PINS nFWE : 15 : in* +NOTE PINS nCRAS : 17 : in* +NOTE PINS nCCAS : 9 : in* +NOTE PINS Dout[7] : 82 : out* +NOTE PINS Dout[6] : 78 : out* +NOTE PINS Dout[5] : 84 : out* +NOTE PINS Dout[4] : 83 : out* +NOTE PINS Dout[3] : 85 : out* +NOTE PINS Dout[2] : 87 : out* +NOTE PINS Dout[1] : 86 : out* +NOTE PINS Din[7] : 1 : in* +NOTE PINS Din[6] : 2 : in* +NOTE PINS Din[5] : 98 : in* +NOTE PINS Din[4] : 99 : in* +NOTE PINS Din[3] : 97 : in* +NOTE PINS Din[2] : 88 : in* +NOTE PINS Din[1] : 96 : in* +NOTE PINS Din[0] : 3 : in* +NOTE PINS CROW[1] : 16 : in* +NOTE PINS CROW[0] : 10 : in* NOTE PINS MAin[9] : 32 : in* NOTE PINS MAin[8] : 25 : in* NOTE PINS MAin[7] : 18 : in* @@ -59,352 +74,337 @@ NOTE PINS MAin[3] : 21 : in* NOTE PINS MAin[2] : 13 : in* NOTE PINS MAin[1] : 12 : in* NOTE PINS MAin[0] : 14 : in* -NOTE PINS CROW[1] : 16 : in* -NOTE PINS CROW[0] : 10 : in* -NOTE PINS Din[7] : 1 : in* -NOTE PINS Din[6] : 2 : in* -NOTE PINS Din[5] : 98 : in* -NOTE PINS Din[4] : 99 : in* -NOTE PINS Din[3] : 97 : in* -NOTE PINS Din[2] : 88 : in* -NOTE PINS Din[1] : 96 : in* -NOTE PINS Din[0] : 3 : in* -NOTE PINS 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+11111111111111111111111111111111111111111111111111111111111111111100001010000000000000000000000000000000000000000000000000000000 +00101010101001110010001000000000000000000000000001000000000000000000000000000000111111111111111101011110000000000000000000000000 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * NOTE END CONFIG DATA* -L41088 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +L41344 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -1426,10 +1426,10 @@ L41088 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -C5769* +C812F* NOTE FEATURE_ROW* E0000000000000000000000000000000000000000000000000000000000000000 0000010001100000* NOTE User Electronic Signature Data* UH00000000* -0994 +0A8E diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp index 36bafd6..d92d1b7 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp @@ -6,30 +6,30 @@ Design Information ------------------ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr - RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One - Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i - mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_ - LCMXO2_640HC.lpf -c 0 -gui -msgset + -ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd + -pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D: + /OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640 + HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2- + 640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-640HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 08/15/23 05:03:24 +Mapped on: 08/15/23 23:30:05 Design Summary -------------- - Number of registers: 102 out of 877 (12%) - PFU registers: 102 out of 640 (16%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 75 out of 320 (23%) - SLICEs as Logic/ROM: 75 out of 320 (23%) + Number of registers: 93 out of 877 (11%) + PFU registers: 64 out of 640 (10%) + PIO registers: 29 out of 237 (12%) + Number of SLICEs: 81 out of 320 (25%) + SLICEs as Logic/ROM: 81 out of 320 (25%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 143 out of 640 (22%) - Number used as logic LUTs: 123 + Number of LUT4s: 159 out of 640 (25%) + Number used as logic LUTs: 139 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -53,67 +53,66 @@ Design Summary 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 - Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_6: 4 loads, 4 LSLICEs - Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 ) + Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 6 + Net XOR8MEG18: 3 loads, 3 LSLICEs + Net i2_i: 1 loads, 0 LSLICEs Page 1 -Design: RAM2GS Date: 08/15/23 05:03:24 +Design: RAM2GS Date: 08/15/23 23:30:05 Design Summary (cont) --------------------- - Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_10: 3 loads, 3 LSLICEs - Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_16: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net RCLK_c_enable_15: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs - Net Ready_N_292: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs - Number of LSRs: 7 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_177: 1 loads, 1 LSLICEs - Net C1Submitted_N_237: 2 loads, 2 LSLICEs - Net n2366: 2 loads, 2 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_28: 1 loads, 1 LSLICEs + Net N_188_i: 2 loads, 2 LSLICEs + Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs + Number of LSRs: 3 + Net RA10s_i: 1 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net Ready: 18 loads - Net InitReady: 15 loads - Net RASr2: 15 loads - Net nRowColSel_N_35: 13 loads + Net InitReady: 17 loads + Net Ready: 15 loads + Net Ready_fast: 14 loads + Net Din_c[5]: 12 loads Net nRowColSel: 12 loads - Net Din_c_4: 10 loads - Net MAin_c_1: 10 loads - Net Din_c_5: 9 loads - Net MAin_c_0: 9 loads - Net Din_c_0: 8 loads + Net S[1]: 12 loads + Net RASr2: 10 loads + Net CO0: 9 loads + Net Din_c[3]: 9 loads + Net Din_c[4]: 9 loads - Number of warnings: 0 + Number of warnings: 6 Number of errors: 0 Design Errors/Warnings ---------------------- - No errors or warnings present. +WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad. +WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad. +WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad. +WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. +WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. +WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. IO (PIO) Attributes ------------------- @@ -122,193 +121,187 @@ IO (PIO) Attributes | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS25 | | +| RD[0] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS25 | | +| Dout[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS33 | IN | Page 2 -Design: RAM2GS Date: 08/15/23 05:03:24 +Design: RAM2GS Date: 08/15/23 23:30:05 IO (PIO) Attributes (cont) -------------------------- -| RD[5] | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS25 | | +| UFMSDO | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS25 | | +| UFMSDI | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS25 | | +| UFMCLK | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS25 | | +| nUFMCS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS25 | | +| RDQML | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS25 | | +| RDQMH | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS25 | | +| nRCAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS25 | | +| nRRAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS25 | | +| nRWE | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS25 | | +| RCKE | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS25 | | +| RCLK | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS25 | | +| nRCS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS25 | | +| RD[7] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVCMOS25 | | +| RD[6] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVCMOS25 | | +| RD[5] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVCMOS25 | | +| RD[4] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVCMOS25 | | +| RD[3] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVCMOS25 | | +| RD[2] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVCMOS25 | | +| RD[1] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVCMOS25 | | +| RA[11] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVCMOS25 | | +| RA[10] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVCMOS25 | | +| RA[9] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVCMOS25 | | +| RA[8] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVCMOS25 | | +| RA[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[3] | OUTPUT | LVCMOS25 | | +| RA[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVCMOS25 | | +| RA[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVCMOS25 | | +| RA[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | Page 3 -Design: RAM2GS Date: 08/15/23 05:03:24 +Design: RAM2GS Date: 08/15/23 23:30:05 IO (PIO) Attributes (cont) -------------------------- -| RA[0] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVCMOS25 | | +| RA[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVCMOS25 | | +| RA[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVCMOS25 | | +| RA[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVCMOS25 | | +| RBA[1] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVCMOS25 | | +| RBA[0] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RDQMH | OUTPUT | LVCMOS25 | | +| LED | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVCMOS25 | | +| nFWE | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nUFMCS | OUTPUT | LVCMOS25 | | +| nCRAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMCLK | OUTPUT | LVCMOS25 | | +| nCCAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMSDI | OUTPUT | LVCMOS25 | | +| Dout[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVCMOS25 | | +| Dout[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVCMOS25 | | +| Dout[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVCMOS25 | | +| Dout[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVCMOS25 | | +| Dout[3] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVCMOS25 | | +| Dout[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVCMOS25 | | +| Dout[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVCMOS25 | | +| Din[7] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVCMOS25 | | +| Din[6] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[2] | INPUT | LVCMOS25 | | +| Din[5] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVCMOS25 | | +| Din[4] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVCMOS25 | | +| Din[3] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVCMOS25 | | +| Din[2] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVCMOS25 | | +| Din[1] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS25 | | +| Din[0] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVCMOS25 | | +| CROW[1] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS25 | | +| CROW[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS25 | | +| MAin[9] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | Page 4 -Design: RAM2GS Date: 08/15/23 05:03:24 +Design: RAM2GS Date: 08/15/23 23:30:05 IO (PIO) Attributes (cont) -------------------------- -| Din[3] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS25 | | +| MAin[7] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVCMOS25 | | +| MAin[6] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS25 | | +| MAin[5] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVCMOS25 | | +| MAin[4] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVCMOS25 | | +| MAin[3] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVCMOS25 | | +| MAin[2] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVCMOS25 | | +| MAin[1] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMSDO | INPUT | LVCMOS25 | | +| MAin[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ Removed logic ------------- -Block i2 undriven or does not drive anything - clipped. Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_120 was merged into signal PHI2_c -Signal n1407 was merged into signal nRowColSel_N_34 -Signal n2380 was merged into signal Ready -Signal n1408 was merged into signal nRowColSel_N_35 -Signal nRWE_N_176 was merged into signal nRWE_N_177 -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. -Block i2046 was optimized away. -Block i1118_1_lut was optimized away. -Block i637_1_lut_rep_31 was optimized away. -Block i1119_1_lut was optimized away. -Block nRWE_I_50_1_lut was optimized away. -Block i1 was optimized away. +Signal nCRAS_c_i was merged into signal nCRAS_c +Signal RASr2_i was merged into signal RASr2 +Signal XOR8MEG.CN was merged into signal PHI2_c +Signal GND undriven or does not drive anything - clipped. +Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. +Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. +Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. +Signal N_1 undriven or does not drive anything - clipped. +Block nCRAS_pad_RNIBPVB was optimized away. +Block RASr2_RNIAFR1 was optimized away. +Block XOR8MEG.CN was optimized away. +Block GND was optimized away. @@ -317,7 +310,7 @@ Run Time and Memory Usage Total CPU Time: 0 secs Total REAL Time: 0 secs - Peak Memory Usage: 35 MB + Peak Memory Usage: 36 MB @@ -325,6 +318,13 @@ Run Time and Memory Usage + + + + + + + Page 5 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd index 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zD+TM%Sx_BW@4MiBpT+tsvd9-ltTz?4BI{2kN?Vh)tpsXA*1JVeTe3c|LG8%;C=1#} zvgn{)rEMJ4o~*wp>Oj^j24Wq_`c%a_k@bd(btdbR1WMy%y{CifC9?+VLe|GFxQ{u)xwn`9}1x=X($P!Fh}QAl0s~>kOLYc`AVR%WIb<##*wvJ2aP9d zooYLQtb(dHk*pV0=_Ki`hXlGBi*jT0pxKn`>wpfW+yGVYFv=xV>~PAB zu~C|&+`uI02q6`lL%IFjP^@k)cmq++L1ZbAXE(: -4.914ns/-481.988ns; real time: 7 secs +0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs Level 2, iteration 1 -7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; -Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs Level 3, iteration 1 -12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; -Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:03:35 08/15/23 +Start NBR section for normal routing at 23:30:11 08/15/23 Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Level 4, iteration 2 -3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs -Level 4, iteration 3 -2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 5 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23 + +Start NBR section for re-routing at 23:30:11 08/15/23 Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for re-routing at 05:03:35 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs - -Start NBR section for post-routing at 05:03:35 08/15/23 +Start NBR section for post-routing at 23:30:11 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 260 (38.58%) - Estimated worst slack : -5.122ns - Timing score : 452301 + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 5.827ns + Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Total CPU time 7 secs -Total REAL time: 7 secs +Total CPU time 5 secs +Total REAL time: 6 secs Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. +End of route. 703 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 -Timing score: 452301 +Timing score: 0 Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. @@ -239,14 +222,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -5.122 -PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 5.827 +PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 7 secs -Total REAL time to completion: 7 secs +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf index ccdc34a..0109563 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf @@ -1,7 +1,22 @@ SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 23:30:05 2023 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "UFMSDI" SITE "29" ; +LOCATE COMP "UFMCLK" SITE "28" ; +LOCATE COMP "nUFMCS" SITE "30" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "RD[7]" SITE "43" ; LOCATE COMP "RD[6]" SITE "42" ; LOCATE COMP "RD[5]" SITE "41" ; @@ -9,18 +24,6 @@ LOCATE COMP "RD[4]" SITE "40" ; LOCATE COMP "RD[3]" SITE "39" ; LOCATE COMP "RD[2]" SITE "38" ; LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RA[10]" SITE "64" ; LOCATE COMP "RA[9]" SITE "63" ; @@ -33,16 +36,29 @@ LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; -LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "nFWE" SITE "15" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; LOCATE COMP "MAin[9]" SITE "32" ; LOCATE COMP "MAin[8]" SITE "25" ; LOCATE COMP "MAin[7]" SITE "18" ; @@ -53,28 +69,11 @@ LOCATE COMP "MAin[3]" SITE "21" ; LOCATE COMP "MAin[2]" SITE "13" ; LOCATE COMP "MAin[1]" SITE "12" ; LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nFWE" SITE "28" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "UFMSDO" SITE "27" ; +FREQUENCY PORT "PHI2" 2.900000 MHz ; +FREQUENCY PORT "nCCAS" 2.900000 MHz ; +FREQUENCY PORT "nCRAS" 2.900000 MHz ; +FREQUENCY PORT "RCLK" 62.500000 MHz ; SCHEMATIC END ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; COMMERCIAL ; - -// No timing preferences found. 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zWB;xvd}UETe+FGewCeSf)#;DZA(ZQogpTc&^_#VguJi%Aa=9<)4w~qW)JBl&I;E1{ jrcYFFm;OHh00960;&M>n0ssI2|NjF3H#L1vq>ups^2NNb literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf new file mode 100644 index 0000000..f622489 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf @@ -0,0 +1,964 @@ +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEPC + +# Tue Aug 15 23:12:41 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) +Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + +Selecting top level module RAM2GS +@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) +Running optimization stage 2 on RAM2GS ....... +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB) + +For a summary of runtime and memory usage per design unit, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv + + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:42 2023 + +###########################################################] +# Tue Aug 15 23:12:42 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) + +Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt +See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + +@N: FX493 |Applying initial value "0" on instance InitReady. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance RCKE. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCS. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRRAS. +@N: FX493 |Applying initial value "0" on instance CmdUFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdUFMCS. +@N: FX493 |Applying initial value "0" on instance CmdUFMSDI. +@N: FX493 |Applying initial value "0" on instance C1Submitted. +@N: FX493 |Applying initial value "0" on instance CmdSubmitted. +@N: FX493 |Applying initial value "0" on instance ADSubmitted. +@N: FX493 |Applying initial value "0" on instance XOR8MEG. +@N: FX493 |Applying initial value "1" on instance nUFMCS. +@N: FX493 |Applying initial value "0" on instance UFMSDI. +@N: FX493 |Applying initial value "0" on instance UFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdEnable. +@N: FX493 |Applying initial value "1" on instance nRWE. + +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +--------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 +======================================================================================= + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +RCLK 48 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) +======================================================================================== + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 RCLK port 48 nRWE +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Aug 15 23:12:44 2023 + +###########################################################] +# Tue Aug 15 23:12:44 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: FX493 |Applying initial value "0" on instance IS[0]. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance IS[1]. +@N: FX493 |Applying initial value "0" on instance IS[2]. +@N: FX493 |Applying initial value "0" on instance IS[3]. + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s -2.34ns 128 / 89 + 2 0h:00m:01s -2.34ns 140 / 89 + 3 0h:00m:01s -2.34ns 140 / 89 +@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. +Timing driven replication report +Added 1 Registers via timing driven replication +Added 0 LUTs via timing driven replication + + 4 0h:00m:01s -2.04ns 140 / 90 + + + 5 0h:00m:01s -2.04ns 141 / 90 + 6 0h:00m:01s -2.04ns 141 / 90 + 7 0h:00m:01s -2.04ns 141 / 90 + 8 0h:00m:01s -2.04ns 141 / 90 + 9 0h:00m:01s -2.04ns 141 / 90 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB) + +Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB) + +@N: MT615 |Found clock RCLK with period 16.00ns +@N: MT615 |Found clock PHI2 with period 350.00ns +@N: MT615 |Found clock nCRAS with period 350.00ns +@N: MT615 |Found clock nCCAS with period 350.00ns + + +##### START OF TIMING REPORT #####[ +# Timing report written on Tue Aug 15 23:12:47 2023 +# + + +Top view: RAM2GS +Requested Frequency: 2.9 MHz +Wire load mode: top +Paths requested: 3 +Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: -2.389 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------- +PHI2 2.9 MHz 0.8 MHz 350.000 1186.150 -2.389 declared default_clkgroup +RCLK 62.5 MHz 18.4 MHz 16.000 54.224 -0.784 declared default_clkgroup +nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +nCRAS 2.9 MHz 1.0 MHz 350.000 987.210 -1.821 declared default_clkgroup +=================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------------- +RCLK RCLK | 16.000 8.400 | No paths - | No paths - | No paths - +RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths - +RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - +PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -2.389 +PHI2 PHI2 | No paths - | 350.000 345.378 | 175.000 167.920 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.821 +============================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -2.389 +CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 0.972 -1.517 +CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 0.972 -0.740 +CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 +Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 +CmdUFMCLK PHI2 FD1P3AX Q CmdUFMCLK 0.972 -0.500 +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.920 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.920 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.920 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.920 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------- +UFMCLK_0io PHI2 OFS1P3DX SP i2_i 0.528 -2.389 +nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i 1.089 -1.829 +UFMSDI PHI2 FD1S3AX D UFMSDI_RNO 1.462 -1.751 +LEDEN PHI2 FD1P3AX SP N_28 0.528 -1.236 +n8MEGEN PHI2 FD1P3AX SP N_26 0.528 -1.236 +LEDEN PHI2 FD1P3AX D N_74_i 1.089 -0.572 +n8MEGEN PHI2 FD1P3AX D N_131 1.089 -0.572 +UFMCLK_0io PHI2 OFS1P3DX D i1_i 1.089 -0.500 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r_0 175.089 167.920 +C1Submitted PHI2 FD1S3AX D C1Submitted_s_0 175.089 167.920 +============================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -2.389 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMCLK_0io / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMCLK_0io_RNO_0 ORCALUT4 A In 0.000 2.301 r - +UFMCLK_0io_RNO_0 ORCALUT4 Z Out 0.617 2.917 r - +i2_i Net - - - - 1 +UFMCLK_0io OFS1P3DX SP In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.829 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: nUFMCS / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.301 r - +nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.617 2.917 r - +nUFMCS_s_0_N_5_i Net - - - - 1 +nUFMCS FD1S3AY D In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.462 + + - Propagation time: 3.214 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.751 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMSDI / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMSDI_RNO PFUMX C0 In 0.000 2.301 r - +UFMSDI_RNO PFUMX Z Out 0.913 3.214 r - +UFMSDI_RNO Net - - - - 1 +UFMSDI FD1S3AX D In 0.000 3.214 r - +================================================================================== + + + + +==================================== +Detailed Report for Clock: RCLK +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 +LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 +FS[12] RCLK FD1S3AX Q FS[12] 1.108 8.400 +FS[13] RCLK FD1S3AX Q FS[13] 1.108 8.400 +FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.400 +FS[17] RCLK FD1S3AX Q FS[17] 1.108 8.400 +FS[16] RCLK FD1S3AX Q FS[16] 1.148 9.377 +FS[15] RCLK FD1S3AX Q FS[15] 1.108 9.417 +InitReady RCLK FD1S3AX Q InitReady 1.268 9.849 +================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------ +RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 +RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 +RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 +RowA[1] RCLK FD1S3AX D RowAd_0[1] 1.089 -0.784 +RowA[2] RCLK FD1S3AX D RowAd_0[2] 1.089 -0.784 +RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0.784 +RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 +RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 +RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 +RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784 +==================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[0] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[0] ORCALUT4 B In 0.000 1.256 r - +RBAd[0] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[0] Net - - - - 1 +RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[9] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[9] ORCALUT4 B In 0.000 1.256 r - +RowAd[9] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[9] Net - - - - 1 +RowA[9] FD1S3AX D In 0.000 1.873 f - +================================================================================= + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[8] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[8] ORCALUT4 B In 0.000 1.256 r - +RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[8] Net - - - - 1 +RowA[8] FD1S3AX D In 0.000 1.873 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: nCRAS +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------- +CBR nCRAS FD1S3AX Q CBR 1.204 -1.821 +FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.765 +========================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_179_i 1.089 -1.821 +nRWE_0io nCRAS OFS1P3BX D N_180_i 1.089 -1.821 +nRCS_0io nCRAS OFS1P3BX D N_27_i 1.089 -1.765 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.749 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693 +======================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.293 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.909 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.909 f - +======================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 A In 0.000 2.293 r - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.909 r - +N_180_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.909 r - +======================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.765 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.148 1.148 r - +FWEr Net - - - - 4 +nRCAS_r_i_a3_1_1_tz ORCALUT4 D In 0.000 1.148 r - +nRCAS_r_i_a3_1_1_tz ORCALUT4 Z Out 1.089 2.237 r - +N_27_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.237 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.853 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.853 f - +====================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 90 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + + +Details: +BB: 8 +CCU2D: 10 +FD1P3AX: 11 +FD1S3AX: 49 +FD1S3AY: 1 +FD1S3IX: 3 +GSR: 1 +IB: 26 +IFS1P3DX: 9 +INV: 7 +OB: 33 +OFS1P3BX: 4 +OFS1P3DX: 12 +OFS1P3JX: 1 +ORCALUT4: 135 +PFUMX: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Tue Aug 15 23:12:47 2023 + +###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srm new file mode 100644 index 0000000000000000000000000000000000000000..33a15e2b3c8940c428801e37843c0d766a5e4b2a GIT binary patch literal 30417 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/dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr @@ -0,0 +1,964 @@ +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEPC + +# Tue Aug 15 23:12:41 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) +Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + +Selecting top level module RAM2GS +@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) +Running optimization stage 2 on RAM2GS ....... +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB) + +For a summary of runtime and memory usage per design unit, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv + + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:41 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 23:12:42 2023 + +###########################################################] +# Tue Aug 15 23:12:42 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) + +Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt +See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + +@N: FX493 |Applying initial value "0" on instance InitReady. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance RCKE. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCS. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRRAS. +@N: FX493 |Applying initial value "0" on instance CmdUFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdUFMCS. +@N: FX493 |Applying initial value "0" on instance CmdUFMSDI. +@N: FX493 |Applying initial value "0" on instance C1Submitted. +@N: FX493 |Applying initial value "0" on instance CmdSubmitted. +@N: FX493 |Applying initial value "0" on instance ADSubmitted. +@N: FX493 |Applying initial value "0" on instance XOR8MEG. +@N: FX493 |Applying initial value "1" on instance nUFMCS. +@N: FX493 |Applying initial value "0" on instance UFMSDI. +@N: FX493 |Applying initial value "0" on instance UFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdEnable. +@N: FX493 |Applying initial value "1" on instance nRWE. + +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +--------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 +======================================================================================= + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +RCLK 48 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) +======================================================================================== + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 RCLK port 48 nRWE +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Aug 15 23:12:44 2023 + +###########################################################] +# Tue Aug 15 23:12:44 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: FX493 |Applying initial value "0" on instance IS[0]. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance IS[1]. +@N: FX493 |Applying initial value "0" on instance IS[2]. +@N: FX493 |Applying initial value "0" on instance IS[3]. + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s -2.34ns 128 / 89 + 2 0h:00m:01s -2.34ns 140 / 89 + 3 0h:00m:01s -2.34ns 140 / 89 +@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. +Timing driven replication report +Added 1 Registers via timing driven replication +Added 0 LUTs via timing driven replication + + 4 0h:00m:01s -2.04ns 140 / 90 + + + 5 0h:00m:01s -2.04ns 141 / 90 + 6 0h:00m:01s -2.04ns 141 / 90 + 7 0h:00m:01s -2.04ns 141 / 90 + 8 0h:00m:01s -2.04ns 141 / 90 + 9 0h:00m:01s -2.04ns 141 / 90 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB) + +Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB) + +@N: MT615 |Found clock RCLK with period 16.00ns +@N: MT615 |Found clock PHI2 with period 350.00ns +@N: MT615 |Found clock nCRAS with period 350.00ns +@N: MT615 |Found clock nCCAS with period 350.00ns + + +##### START OF TIMING REPORT #####[ +# Timing report written on Tue Aug 15 23:12:47 2023 +# + + +Top view: RAM2GS +Requested Frequency: 2.9 MHz +Wire load mode: top +Paths requested: 3 +Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: -2.389 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------- +PHI2 2.9 MHz 0.8 MHz 350.000 1186.150 -2.389 declared default_clkgroup +RCLK 62.5 MHz 18.4 MHz 16.000 54.224 -0.784 declared default_clkgroup +nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +nCRAS 2.9 MHz 1.0 MHz 350.000 987.210 -1.821 declared default_clkgroup +=================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------------- +RCLK RCLK | 16.000 8.400 | No paths - | No paths - | No paths - +RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths - +RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - +PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -2.389 +PHI2 PHI2 | No paths - | 350.000 345.378 | 175.000 167.920 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.821 +============================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -2.389 +CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 0.972 -1.517 +CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 0.972 -0.740 +CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 +Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 +CmdUFMCLK PHI2 FD1P3AX Q CmdUFMCLK 0.972 -0.500 +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.920 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.920 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.920 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.920 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------- +UFMCLK_0io PHI2 OFS1P3DX SP i2_i 0.528 -2.389 +nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i 1.089 -1.829 +UFMSDI PHI2 FD1S3AX D UFMSDI_RNO 1.462 -1.751 +LEDEN PHI2 FD1P3AX SP N_28 0.528 -1.236 +n8MEGEN PHI2 FD1P3AX SP N_26 0.528 -1.236 +LEDEN PHI2 FD1P3AX D N_74_i 1.089 -0.572 +n8MEGEN PHI2 FD1P3AX D N_131 1.089 -0.572 +UFMCLK_0io PHI2 OFS1P3DX D i1_i 1.089 -0.500 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r_0 175.089 167.920 +C1Submitted PHI2 FD1S3AX D C1Submitted_s_0 175.089 167.920 +============================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -2.389 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMCLK_0io / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMCLK_0io_RNO_0 ORCALUT4 A In 0.000 2.301 r - +UFMCLK_0io_RNO_0 ORCALUT4 Z Out 0.617 2.917 r - +i2_i Net - - - - 1 +UFMCLK_0io OFS1P3DX SP In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.829 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: nUFMCS / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.301 r - +nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.617 2.917 r - +nUFMCS_s_0_N_5_i Net - - - - 1 +nUFMCS FD1S3AY D In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.462 + + - Propagation time: 3.214 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.751 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMSDI / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMSDI_RNO PFUMX C0 In 0.000 2.301 r - +UFMSDI_RNO PFUMX Z Out 0.913 3.214 r - +UFMSDI_RNO Net - - - - 1 +UFMSDI FD1S3AX D In 0.000 3.214 r - +================================================================================== + + + + +==================================== +Detailed Report for Clock: RCLK +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 +LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 +FS[12] RCLK FD1S3AX Q FS[12] 1.108 8.400 +FS[13] RCLK FD1S3AX Q FS[13] 1.108 8.400 +FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.400 +FS[17] RCLK FD1S3AX Q FS[17] 1.108 8.400 +FS[16] RCLK FD1S3AX Q FS[16] 1.148 9.377 +FS[15] RCLK FD1S3AX Q FS[15] 1.108 9.417 +InitReady RCLK FD1S3AX Q InitReady 1.268 9.849 +================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------ +RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 +RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 +RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 +RowA[1] RCLK FD1S3AX D RowAd_0[1] 1.089 -0.784 +RowA[2] RCLK FD1S3AX D RowAd_0[2] 1.089 -0.784 +RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0.784 +RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 +RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 +RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 +RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784 +==================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[0] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[0] ORCALUT4 B In 0.000 1.256 r - +RBAd[0] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[0] Net - - - - 1 +RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[9] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[9] ORCALUT4 B In 0.000 1.256 r - +RowAd[9] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[9] Net - - - - 1 +RowA[9] FD1S3AX D In 0.000 1.873 f - +================================================================================= + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[8] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[8] ORCALUT4 B In 0.000 1.256 r - +RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[8] Net - - - - 1 +RowA[8] FD1S3AX D In 0.000 1.873 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: nCRAS +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------- +CBR nCRAS FD1S3AX Q CBR 1.204 -1.821 +FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.765 +========================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_179_i 1.089 -1.821 +nRWE_0io nCRAS OFS1P3BX D N_180_i 1.089 -1.821 +nRCS_0io nCRAS OFS1P3BX D N_27_i 1.089 -1.765 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.749 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693 +======================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.293 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.909 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.909 f - +======================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 A In 0.000 2.293 r - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.909 r - +N_180_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.909 r - +======================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.765 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.148 1.148 r - +FWEr Net - - - - 4 +nRCAS_r_i_a3_1_1_tz ORCALUT4 D In 0.000 1.148 r - +nRCAS_r_i_a3_1_1_tz ORCALUT4 Z Out 1.089 2.237 r - +N_27_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.237 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.853 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.853 f - +====================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 90 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + + +Details: +BB: 8 +CCU2D: 10 +FD1P3AX: 11 +FD1S3AX: 49 +FD1S3AY: 1 +FD1S3IX: 3 +GSR: 1 +IB: 26 +IFS1P3DX: 9 +INV: 7 +OB: 33 +OFS1P3BX: 4 +OFS1P3DX: 12 +OFS1P3JX: 1 +ORCALUT4: 135 +PFUMX: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB) + +Process took 0h:00m:02s realtime, 0h:00m:02s cputime +# Tue Aug 15 23:12:47 2023 + +###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr.db b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr.db new file mode 100644 index 0000000000000000000000000000000000000000..5deabf552e6b31ce08ea3399a2ca3f27b1febfc0 GIT binary patch literal 16384 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zax4F}U){Qo1nXx%l3zxc-8eYV4Tm`MV>WqPPR`QV_!Tkq+I-)!j|;GmEnSb<+if`- zv$pxz+DixTJ2>#zv-hjEJb~R`>BKtq{!00p3G-~(n@=dN=H?(wtj(MqjeVhRfp0Hs ze*?#nfp*M_B2!rboT24#RY$%X*ZxkG!AINJ#7AMk56+YS$okrM31&?Psv|nEId7;V z%pOiNZ>X1F3t^twd2@2`v=8>O^mS}ranG@4h+mrcuF;p5kN1}MoBG<}SLC4F#OB;{ zk=Mr3b?=HT(sTuxN!KH*Yhw98X|3KG(`L5^L?`PAg!z`A_Wu9?0RR8ua!}v`00030{{sMKyEE_nd;kCgEL;`< literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 index 4d39d68..8c774fb 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 +Tue Aug 15 22:56:32 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -30,7 +30,6 @@ Device,speed: LCMXO2-640HC,4 Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- -Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- @@ -38,87 +37,131 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 245 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 3.815ns +Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i13 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + Delay: 10.424ns (36.2% logic, 63.8% route), 7 logic levels. Constraint Details: - 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + 10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns Physical Path Details: - Data path SLICE_0 to SLICE_57: + Data path Din[3]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 -CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 -ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 -CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 -ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 -CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 -ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[3]_MGIOL.IN to SLICE_43.C1 Bank[3] +CTOF_DEL --- 0.495 SLICE_43.C1 to SLICE_43.F1 SLICE_43 +ROUTE 1 e 1.234 SLICE_43.F1 to SLICE_69.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 SLICE_69.D0 to SLICE_69.F0 SLICE_69 +ROUTE 5 e 1.234 SLICE_69.F0 to SLICE_60.D0 un1_Bank_1 +CTOF_DEL --- 0.495 SLICE_60.D0 to SLICE_60.F0 SLICE_60 +ROUTE 2 e 1.234 SLICE_60.F0 to SLICE_46.A1 ADWR +CTOF_DEL --- 0.495 SLICE_46.A1 to SLICE_46.F1 SLICE_46 +ROUTE 3 e 0.480 SLICE_46.F1 to SLICE_46.D0 un1_ADWR +CTOF_DEL --- 0.495 SLICE_46.D0 to SLICE_46.F0 SLICE_46 +ROUTE 1 e 1.234 SLICE_46.F0 to SLICE_18.C0 un1_CMDWR +CTOOFX_DEL --- 0.721 SLICE_18.C0 to SLICE_18.OFX0 SLICE_18 +ROUTE 1 e 0.001 SLICE_18.OFX0 to SLICE_18.DI0 CmdEnable_s (to PHI2_c) -------- - 6.873 (28.2% logic, 71.8% route), 4 logic levels. + 10.424 (36.2% logic, 63.8% route), 7 logic levels. -Warning: 139.762MHz is the maximum frequency for this preference. +Report: 47.214MHz is the maximum frequency for this preference. ================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 104 timing errors detected. +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.412ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels. Constraint Details: - 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + 11.306ns physical path delay SLICE_1 to SLICE_27 meets + 16.000ns delay constraint less + 0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_1 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 -CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 -ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 -CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 -ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 -CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 -ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 -CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 -ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 -ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_1.Q0 to SLICE_72.D1 FS[17] +CTOF_DEL --- 0.495 SLICE_72.D1 to SLICE_72.F1 SLICE_72 +ROUTE 1 e 1.234 SLICE_72.F1 to SLICE_64.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_59.C1 N_129 +CTOF_DEL --- 0.495 SLICE_59.C1 to SLICE_59.F1 SLICE_59 +ROUTE 2 e 0.480 SLICE_59.F1 to SLICE_59.D0 N_145 +CTOF_DEL --- 0.495 SLICE_59.D0 to SLICE_59.F0 SLICE_59 +ROUTE 2 e 1.234 SLICE_59.F0 to SLICE_56.B0 N_139_8 +CTOF_DEL --- 0.495 SLICE_56.B0 to SLICE_56.F0 SLICE_56 +ROUTE 1 e 1.234 SLICE_56.F0 to SLICE_54.C0 N_140 +CTOF_DEL --- 0.495 SLICE_54.C0 to SLICE_54.F0 SLICE_54 +ROUTE 1 e 1.234 SLICE_54.F0 to SLICE_27.CE N_28 (to RCLK_c) -------- - 9.577 (30.6% logic, 69.4% route), 6 logic levels. + 11.306 (30.3% logic, 69.7% route), 7 logic levels. -Warning: 50.592MHz is the maximum frequency for this preference. +Report: 86.296MHz is the maximum frequency for this preference. Report Summary -------------- @@ -126,21 +169,18 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.214 MHz| 7 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 86.296 MHz| 7 | | | ---------------------------------------------------------------------------- -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 78| 22.35% - | | | ----------------------------------------------------------------------------- +All preferences were met. Clock Domains Analysis @@ -148,14 +188,20 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -168,8 +214,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -181,14 +227,14 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing summary (Setup): --------------- -Timing errors: 349 Score: 848079 -Cumulative negative slack: 584487 +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 +Tue Aug 15 22:56:32 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -212,40 +258,8 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.351ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. - - Constraint Details: - - 0.332ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) - -------- - 0.332 (40.1% logic, 59.9% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -253,38 +267,86 @@ Passed: The following path meets requirements by 0.447ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. Constraint Details: - 0.434ns physical path delay SLICE_15 to SLICE_15 meets + 0.434ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns Physical Path Details: - Data path SLICE_15 to SLICE_15: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted -CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 -ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted +CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10 +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c) -------- 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_14.Q0 to SLICE_14.M1 CASr (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- @@ -297,14 +359,20 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -317,8 +385,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -333,16 +401,16 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage) Timing summary (Setup and Hold): --------------- -Timing errors: 349 (setup), 0 (hold) -Score: 848079 (setup), 0 (hold) -Cumulative negative slack: 584487 (584487+0) +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr index 813d789..b451cd5 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr @@ -13,7 +13,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 +Tue Aug 15 22:56:39 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -30,7 +30,6 @@ Device,speed: LCMXO2-640HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- -Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- @@ -38,1045 +37,1125 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 264 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 2.902ns +Passed: The following path meets requirements by 163.401ns (weighted slack = 326.802ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in UFMSDI_417 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 6.076ns (40.0% logic, 60.0% route), 5 logic levels. + Delay: 8.950ns (28.6% logic, 71.4% route), 5 logic levels. Constraint Details: - 6.076ns physical path delay SLICE_1 to SLICE_45 exceeds - 3.340ns delay constraint less + 8.950ns physical path delay Din[3]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.401ns Physical Path Details: - Data path SLICE_1 to SLICE_45: + Data path Din[3]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 -CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 -CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 -ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 -CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 -ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 -CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 6.076 (40.0% logic, 60.0% route), 5 logic levels. + 8.950 (28.6% logic, 71.4% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_45: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.710ns +Passed: The following path meets requirements by 163.452ns (weighted slack = 326.904ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i14 (from RCLK_c +) - Destination: FF Data in UFMSDI_417 (to RCLK_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.884ns (41.3% logic, 58.7% route), 5 logic levels. + Delay: 8.899ns (28.7% logic, 71.3% route), 5 logic levels. Constraint Details: - 5.884ns physical path delay SLICE_0 to SLICE_45 exceeds - 3.340ns delay constraint less + 8.899ns physical path delay Din[7]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.452ns Physical Path Details: - Data path SLICE_0 to SLICE_45: + Data path Din[7]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q1 SLICE_0 (from RCLK_c) -ROUTE 5 0.792 R6C8D.Q1 to R4C8D.C1 FS_14 -CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 -CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 -ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 -CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 -ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 -CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7] +CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.884 (41.3% logic, 58.7% route), 5 logic levels. + 8.899 (28.7% logic, 71.3% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_0: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_45: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.665ns +Passed: The following path meets requirements by 163.522ns (weighted slack = 327.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CASr2_383 (from RCLK_c +) - Destination: FF Data in nRCS_396 (to RCLK_c +) + Source: FF Q Bank_0io[4] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.839ns (41.7% logic, 58.3% route), 5 logic levels. + Delay: 8.829ns (29.0% logic, 71.0% route), 5 logic levels. Constraint Details: - 5.839ns physical path delay SLICE_16 to SLICE_61 exceeds - 3.340ns delay constraint less + 8.829ns physical path delay Din[4]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.522ns Physical Path Details: - Data path SLICE_16 to SLICE_61: + Data path Din[4]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C9B.CLK to R4C9B.Q1 SLICE_16 (from RCLK_c) -ROUTE 3 1.000 R4C9B.Q1 to R6C9D.A0 CASr2 -CTOF_DEL --- 0.495 R6C9D.A0 to R6C9D.F0 SLICE_96 -ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 -CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 -ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 -CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 -ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 -CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 -ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4] +CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.839 (41.7% logic, 58.3% route), 5 logic levels. + 8.829 (29.0% logic, 71.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_16: + Source Clock Path PHI2 to Din[4]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C9B.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_61: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.621ns +Passed: The following path meets requirements by 163.573ns (weighted slack = 327.146ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.679ns (34.1% logic, 65.9% route), 4 logic levels. + Delay: 8.502ns (44.4% logic, 55.6% route), 7 logic levels. Constraint Details: - 5.679ns physical path delay SLICE_9 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns + 8.502ns physical path delay Din[3]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.573ns Physical Path Details: - Data path SLICE_9 to SLICE_57: + Data path Din[3]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.793 R4C8A.F0 to R4C8B.C1 n10 -CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 SLICE_57 -ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 -CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.679 (34.1% logic, 65.9% route), 4 logic levels. + 8.502 (44.4% logic, 55.6% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.513ns +Passed: The following path meets requirements by 163.624ns (weighted slack = 327.248ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.571ns (34.8% logic, 65.2% route), 4 logic levels. + Delay: 8.451ns (44.6% logic, 55.4% route), 7 logic levels. Constraint Details: - 5.571ns physical path delay SLICE_1 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns + 8.451ns physical path delay Din[7]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.624ns Physical Path Details: - Data path SLICE_1 to SLICE_57: + Data path Din[7]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 -CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.021 R4C8D.F1 to R4C8B.B1 n2375 -CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_57 -ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 -CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7] +CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.571 (34.8% logic, 65.2% route), 4 logic levels. + 8.451 (44.6% logic, 55.4% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.487ns +Passed: The following path meets requirements by 163.694ns (weighted slack = 327.388ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i3 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.545ns (34.9% logic, 65.1% route), 4 logic levels. + Delay: 8.381ns (45.0% logic, 55.0% route), 7 logic levels. Constraint Details: - 5.545ns physical path delay SLICE_8 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns + 8.381ns physical path delay Din[4]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.694ns Physical Path Details: - Data path SLICE_8 to SLICE_57: + Data path Din[4]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7C.CLK to R6C7C.Q0 SLICE_8 (from RCLK_c) -ROUTE 2 1.306 R6C7C.Q0 to R4C7D.A1 FS_3 -CTOF_DEL --- 0.495 R4C7D.A1 to R4C7D.F1 SLICE_86 -ROUTE 1 1.004 R4C7D.F1 to R4C7D.B0 n14 -CTOF_DEL --- 0.495 R4C7D.B0 to R4C7D.F0 SLICE_86 -ROUTE 1 0.645 R4C7D.F0 to R4C8C.D0 n4_adj_7 -CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4] +CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.545 (34.9% logic, 65.1% route), 4 logic levels. + 8.381 (45.0% logic, 55.0% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_8: + Source Clock Path PHI2 to Din[4]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C7C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.479ns +Passed: The following path meets requirements by 163.812ns (weighted slack = 327.624ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in nUFMCS_415 (to RCLK_c +) + Source: FF Q Bank_0io[0] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.653ns (43.0% logic, 57.0% route), 5 logic levels. + Delay: 8.712ns (27.9% logic, 72.1% route), 5 logic levels. Constraint Details: - 5.653ns physical path delay SLICE_9 to SLICE_70 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns + 8.712ns physical path delay SLICE_63 to Din[0]_MGIOL meets + 172.414ns delay constraint less + -0.173ns skew and + 0.063ns CE_SET requirement (totaling 172.524ns) by 163.812ns Physical Path Details: - Data path SLICE_9 to SLICE_70: + Data path SLICE_63 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.640 R4C8A.F0 to R4C9D.D1 n10 -CTOF_DEL --- 0.495 R4C9D.D1 to R4C9D.F1 SLICE_76 -ROUTE 2 0.635 R4C9D.F1 to R4C9A.D1 n2368 -CTOF_DEL --- 0.495 R4C9A.D1 to R4C9A.F1 SLICE_70 -ROUTE 1 0.626 R4C9A.F1 to R4C9A.D0 n64 -CTOF_DEL --- 0.495 R4C9A.D0 to R4C9A.F0 SLICE_70 -ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 nUFMCS_N_199 (to RCLK_c) +REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c) +ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0] +CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.653 (43.0% logic, 57.0% route), 5 logic levels. + 8.712 (27.9% logic, 72.1% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to SLICE_63: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_70: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C9A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.452ns +Passed: The following path meets requirements by 163.984ns (weighted slack = 327.968ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) + Source: FF Q Bank_0io[0] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.626ns (43.2% logic, 56.8% route), 5 logic levels. + Delay: 8.264ns (44.1% logic, 55.9% route), 7 logic levels. Constraint Details: - 5.626ns physical path delay SLICE_9 to SLICE_44 exceeds - 3.340ns delay constraint less + 8.264ns physical path delay SLICE_63 to SLICE_18 meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns + 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.984ns Physical Path Details: - Data path SLICE_9 to SLICE_44: + Data path SLICE_63 to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.672 R4C8A.F0 to R4C8A.D1 n10 -CTOF_DEL --- 0.495 R4C8A.D1 to R4C8A.F1 SLICE_85 -ROUTE 1 0.766 R4C8A.F1 to R4C6B.C1 n2267 -CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_44 -ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 -CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) +REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c) +ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0] +CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.626 (43.2% logic, 56.8% route), 5 logic levels. + 8.264 (44.1% logic, 55.9% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to SLICE_63: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_44: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.438ns +Passed: The following path meets requirements by 164.041ns (weighted slack = 328.082ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CASr3_384 (from RCLK_c +) - Destination: FF Data in nRCS_396 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) - Delay: 5.612ns (43.3% logic, 56.7% route), 5 logic levels. + Delay: 8.034ns (38.0% logic, 62.0% route), 6 logic levels. Constraint Details: - 5.612ns physical path delay SLICE_5 to SLICE_61 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns + 8.034ns physical path delay Din[3]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.041ns Physical Path Details: - Data path SLICE_5 to SLICE_61: + Data path Din[3]_MGIOL to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) -ROUTE 2 0.773 R6C7A.Q0 to R6C9D.C0 CASr3 -CTOF_DEL --- 0.495 R6C9D.C0 to R6C9D.F0 SLICE_96 -ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 -CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 -ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 -CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 -ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 -CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 -ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8B.C1 ADWR +CTOF_DEL --- 0.495 R3C8B.C1 to R3C8B.F1 SLICE_10 +ROUTE 2 1.013 R3C8B.F1 to R3C8B.B0 CmdEnable17 +CTOF_DEL --- 0.495 R3C8B.B0 to R3C8B.F0 SLICE_10 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c) -------- - 5.612 (43.3% logic, 56.7% route), 5 logic levels. + 8.034 (38.0% logic, 62.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_5: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_61: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8B.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.423ns +Passed: The following path meets requirements by 164.046ns (weighted slack = 328.092ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i13 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) + Source: FF Q Bank_0io[2] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.597ns (43.5% logic, 56.5% route), 5 logic levels. + Delay: 8.478ns (28.7% logic, 71.3% route), 5 logic levels. Constraint Details: - 5.597ns physical path delay SLICE_0 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns + 8.478ns physical path delay SLICE_68 to Din[0]_MGIOL meets + 172.414ns delay constraint less + -0.173ns skew and + 0.063ns CE_SET requirement (totaling 172.524ns) by 164.046ns Physical Path Details: - Data path SLICE_0 to SLICE_44: + Data path SLICE_68 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 1.433 R6C8D.Q0 to R6C6C.B0 FS_13 -CTOF_DEL --- 0.495 R6C6C.B0 to R6C6C.F0 SLICE_105 -ROUTE 1 0.315 R6C6C.F0 to R6C6A.D1 n12 -CTOF_DEL --- 0.495 R6C6A.D1 to R6C6A.F1 SLICE_82 -ROUTE 3 0.981 R6C6A.F1 to R4C6B.D1 n13_adj_6 -CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 SLICE_44 -ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 -CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) +REG_DEL --- 0.452 R3C9C.CLK to R3C9C.Q0 SLICE_68 (from PHI2_c) +ROUTE 1 1.079 R3C9C.Q0 to R3C6A.C1 Bank[2] +CTOF_DEL --- 0.495 R3C6A.C1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.597 (43.5% logic, 56.5% route), 5 logic levels. + 8.478 (28.7% logic, 71.3% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_0: + Source Clock Path PHI2 to SLICE_68: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C9C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_44: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Warning: 160.205MHz is the maximum frequency for this preference. +Report: 55.475MHz is the maximum frequency for this preference. ================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 85 timing errors detected. +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns) +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 6.127ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.301ns (40.1% logic, 59.9% route), 6 logic levels. + Delay: 9.591ns (35.7% logic, 64.3% route), 7 logic levels. Constraint Details: - 7.301ns physical path delay SLICE_103 to SLICE_19 exceeds - 5.047ns delay constraint less + 9.591ns physical path delay SLICE_4 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.127ns Physical Path Details: - Data path SLICE_103 to SLICE_19: + Data path SLICE_4 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12] +CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 7.301 (40.1% logic, 59.9% route), 6 logic levels. + 9.591 (35.7% logic, 64.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) +Passed: The following path meets requirements by 6.287ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + Delay: 9.431ns (36.3% logic, 63.7% route), 7 logic levels. Constraint Details: - 6.946ns physical path delay SLICE_103 to SLICE_10 exceeds - 5.047ns delay constraint less + 9.431ns physical path delay SLICE_1 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.287ns Physical Path Details: - Data path SLICE_103 to SLICE_10: + Data path SLICE_1 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17] +CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.946 (35.0% logic, 65.0% route), 5 logic levels. + 9.431 (36.3% logic, 63.7% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) +Passed: The following path meets requirements by 6.319ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + Delay: 9.399ns (36.4% logic, 63.6% route), 7 logic levels. Constraint Details: - 6.946ns physical path delay SLICE_103 to SLICE_15 exceeds - 5.047ns delay constraint less + 9.399ns physical path delay SLICE_3 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.319ns Physical Path Details: - Data path SLICE_103 to SLICE_15: + Data path SLICE_3 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13] +CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.946 (35.0% logic, 65.0% route), 5 logic levels. + 9.399 (36.4% logic, 63.6% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns) +Passed: The following path meets requirements by 6.646ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.901ns (42.4% logic, 57.6% route), 6 logic levels. + Delay: 9.072ns (37.7% logic, 62.3% route), 7 logic levels. Constraint Details: - 6.901ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less + 9.072ns physical path delay SLICE_3 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.646ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_3 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 0.658 R6C4D.Q1 to R6C5D.D1 FS[14] +CTOF_DEL --- 0.495 R6C5D.D1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.901 (42.4% logic, 57.6% route), 6 logic levels. + 9.072 (37.7% logic, 62.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns) +Passed: The following path meets requirements by 6.977ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.832ns (42.8% logic, 57.2% route), 6 logic levels. + Delay: 8.741ns (39.1% logic, 60.9% route), 7 logic levels. Constraint Details: - 6.832ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.741ns physical path delay SLICE_4 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.977ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_4 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 0.744 R4C7C.Q1 to R5C7B.C1 Bank_7 -CTOF_DEL --- 0.495 R5C7B.C1 to R5C7B.F1 SLICE_100 -ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 -CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12] +CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.832 (42.8% logic, 57.2% route), 6 logic levels. + 8.741 (39.1% logic, 60.9% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns) +Passed: The following path meets requirements by 7.097ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[16] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.821ns (42.9% logic, 57.1% route), 6 logic levels. + Delay: 8.621ns (34.0% logic, 66.0% route), 6 logic levels. Constraint Details: - 6.821ns physical path delay SLICE_102 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.621ns physical path delay SLICE_2 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.097ns Physical Path Details: - Data path SLICE_102 to SLICE_19: + Data path SLICE_2 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C6A.CLK to R5C6A.Q0 SLICE_102 (from PHI2_c) -ROUTE 1 0.766 R5C6A.Q0 to R5C8D.C1 Bank_4 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 -CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 -ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 -CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c) +ROUTE 4 1.017 R6C5A.Q1 to R6C5C.B1 FS[16] +CTOF_DEL --- 0.495 R6C5C.B1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.821 (42.9% logic, 57.1% route), 6 logic levels. + 8.621 (34.0% logic, 66.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_102: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns) +Passed: The following path meets requirements by 7.137ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.711ns (43.6% logic, 56.4% route), 6 logic levels. + Delay: 8.581ns (39.9% logic, 60.1% route), 7 logic levels. Constraint Details: - 6.711ns physical path delay SLICE_93 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.581ns physical path delay SLICE_1 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.137ns Physical Path Details: - Data path SLICE_93 to SLICE_19: + Data path SLICE_1 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q0 SLICE_93 (from PHI2_c) -ROUTE 1 0.623 R5C8C.Q0 to R5C7B.D1 Bank_0 -CTOF_DEL --- 0.495 R5C7B.D1 to R5C7B.F1 SLICE_100 -ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 -CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17] +CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.711 (43.6% logic, 56.4% route), 6 logic levels. + 8.581 (39.9% logic, 60.1% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns) +Passed: The following path meets requirements by 7.169ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.681ns (43.8% logic, 56.2% route), 6 logic levels. + Delay: 8.549ns (40.0% logic, 60.0% route), 7 logic levels. Constraint Details: - 6.681ns physical path delay SLICE_93 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.549ns physical path delay SLICE_3 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.169ns Physical Path Details: - Data path SLICE_93 to SLICE_19: + Data path SLICE_3 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.626 R5C8C.Q1 to R5C8D.D1 Bank_1 -CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 -CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 -ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 -CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13] +CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.681 (43.8% logic, 56.2% route), 6 logic levels. + 8.549 (40.0% logic, 60.0% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) +Passed: The following path meets requirements by 7.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMCLK_0io (to RCLK_c +) - Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + Delay: 8.739ns (27.8% logic, 72.2% route), 5 logic levels. Constraint Details: - 6.546ns physical path delay SLICE_101 to SLICE_10 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + 8.739ns physical path delay SLICE_4 to UFMCLK_MGIOL meets + 16.000ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.281ns Physical Path Details: - Data path SLICE_101 to SLICE_10: + Data path SLICE_4 to UFMCLK_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.434 R6C4C.Q1 to R6C5D.B0 FS[12] +CTOF_DEL --- 0.495 R6C5D.B0 to R6C5D.F0 SLICE_72 +ROUTE 2 1.902 R6C5D.F0 to R5C5C.A1 N_137_5 +CTOF_DEL --- 0.495 R5C5C.A1 to R5C5C.F1 SLICE_48 +ROUTE 2 0.982 R5C5C.F1 to R5C5C.A0 UFMCLK_r_i_a2_2_2 +CTOF_DEL --- 0.495 R5C5C.A0 to R5C5C.F0 SLICE_48 +ROUTE 1 0.693 R5C5C.F0 to R5C5D.B0 d_m3_0_a2_0 +CTOF_DEL --- 0.495 R5C5D.B0 to R5C5D.F0 SLICE_47 +ROUTE 1 1.296 R5C5D.F0 to IOL_B4C.OPOS i1_i (to RCLK_c) -------- - 6.546 (37.2% logic, 62.8% route), 5 logic levels. + 8.739 (27.8% logic, 72.2% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path RCLK to UFMCLK_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 39 3.243 62.PADDI to IOL_B4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.243 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) +Passed: The following path meets requirements by 7.354ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + Delay: 8.364ns (35.0% logic, 65.0% route), 6 logic levels. Constraint Details: - 6.546ns physical path delay SLICE_101 to SLICE_15 exceeds - 5.047ns delay constraint less + 8.364ns physical path delay SLICE_2 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.354ns Physical Path Details: - Data path SLICE_101 to SLICE_15: + Data path SLICE_2 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.760 R6C5A.Q0 to R6C5C.C1 FS[15] +CTOF_DEL --- 0.495 R6C5C.C1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.546 (37.2% logic, 62.8% route), 5 logic levels. + 8.364 (35.0% logic, 65.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Warning: 65.729MHz is the maximum frequency for this preference. +Report: 101.286MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1084,31 +1163,18 @@ Report Summary Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 160.205 MHz| 5 * +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 55.475 MHz| 5 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 65.729 MHz| 6 * +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 101.286 MHz| 7 | | | ---------------------------------------------------------------------------- -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 63| 18.05% - | | | -n1996 | 1| 49| 14.04% - | | | -n1997 | 1| 46| 13.18% - | | | -n1995 | 1| 45| 12.89% - | | | -n1998 | 1| 38| 10.89% - | | | -n1994 | 1| 37| 10.60% - | | | ----------------------------------------------------------------------------- +All preferences were met. Clock Domains Analysis @@ -1116,14 +1182,20 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -1136,8 +1208,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -1149,14 +1221,14 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing summary (Setup): --------------- -Timing errors: 349 Score: 452301 -Cumulative negative slack: 370485 +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 +Tue Aug 15 22:56:39 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1180,444 +1252,8 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8D.CLK to R3C8D.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 0.152 R3C8D.Q0 to R3C8D.M1 n736 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr_382 (from RCLK_c +) - Destination: FF Data in CASr2_383 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_16 to SLICE_16 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_16 to SLICE_16: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_16 (from RCLK_c) -ROUTE 1 0.152 R4C9B.Q0 to R4C9B.M1 CASr (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i8 (from RCLK_c +) - Destination: FF Data in IS_FSM__i9 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_75 to SLICE_75 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_75 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.152 R3C9D.Q0 to R3C9D.M1 n732 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i10 (from RCLK_c +) - Destination: FF Data in IS_FSM__i11 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_79 to SLICE_79 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_79 to SLICE_79: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_79 (from RCLK_c) -ROUTE 1 0.152 R5C8B.Q0 to R5C8B.M1 n730 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_79: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_79: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i14 (from RCLK_c +) - Destination: FF Data in IS_FSM__i15 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_81 to SLICE_81 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_81 to SLICE_81: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C9C.CLK to R6C9C.Q0 SLICE_81 (from RCLK_c) -ROUTE 1 0.152 R6C9C.Q0 to R6C9C.M1 n726 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i7 (from RCLK_c +) - Destination: FF Data in IS_FSM__i8 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_97 to SLICE_75 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q1 SLICE_97 (from RCLK_c) -ROUTE 1 0.152 R3C9A.Q1 to R3C9D.M0 n733 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i6 (from RCLK_c +) - Destination: FF Data in IS_FSM__i7 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_97 to SLICE_97 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_97: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_97 (from RCLK_c) -ROUTE 1 0.152 R3C9A.Q0 to R3C9A.M1 n734 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RASr_379 (from RCLK_c +) - Destination: FF Data in RASr2_380 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_30 to SLICE_30 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_30 to SLICE_30: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_30 (from RCLK_c) -ROUTE 2 0.154 R5C10B.Q0 to R5C10B.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2_377 (from RCLK_c +) - Destination: FF Data in PHI2r3_378 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_36 to SLICE_69 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_36 to SLICE_69: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10A.CLK to R4C10A.Q1 SLICE_36 (from RCLK_c) -ROUTE 3 0.154 R4C10A.Q1 to R4C10C.M1 PHI2r2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_36: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C10A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_69: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C10C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.307ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i0 (from RCLK_c +) - Destination: FF Data in IS_FSM__i1 (to RCLK_c +) - - Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. - - Constraint Details: - - 0.288ns physical path delay SLICE_98 to SLICE_98 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.307ns - - Physical Path Details: - - Data path SLICE_98 to SLICE_98: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C11A.CLK to R6C11A.Q0 SLICE_98 (from RCLK_c) -ROUTE 4 0.155 R6C11A.Q0 to R6C11A.M1 nRCS_N_139 (to RCLK_c) - -------- - 0.288 (46.2% logic, 53.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1625,471 +1261,914 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_15 to SLICE_15 meets + 0.366ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_15 to SLICE_15: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 C1Submitted -CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_15 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 ADSubmitted +CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_10 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.851ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in XOR8MEG_408 (to PHI2_c -) - - Delay: 0.823ns (28.4% logic, 71.6% route), 2 logic levels. - - Constraint Details: - - 0.823ns physical path delay SLICE_19 to SLICE_50 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.851ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.332 R5C9D.Q0 to R5C6B.D1 CmdEnable -CTOF_DEL --- 0.101 R5C6B.D1 to R5C6B.F1 SLICE_83 -ROUTE 1 0.257 R5C6B.F1 to R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c) - -------- - 0.823 (28.4% logic, 71.6% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.906ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_407 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 0.878ns (26.7% logic, 73.3% route), 2 logic levels. - - Constraint Details: - - 0.878ns physical path delay SLICE_10 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.906ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_10 (from PHI2_c) -ROUTE 1 0.501 R3C8A.Q0 to R5C9A.B1 ADSubmitted -CTOF_DEL --- 0.101 R5C9A.B1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 0.878 (26.7% logic, 73.3% route), 2 logic levels. - Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.937ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.909ns (48.0% logic, 52.0% route), 4 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.909ns physical path delay SLICE_15 to SLICE_19 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_13 to SLICE_13 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.937ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_15 to SLICE_19: + Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.136 R3C8B.Q0 to R3C9B.D1 C1Submitted -CTOF_DEL --- 0.101 R3C9B.D1 to R3C9B.F1 SLICE_77 -ROUTE 1 0.056 R3C9B.F1 to R3C9A.C1 n2210 -CTOF_DEL --- 0.101 R3C9A.C1 to R3C9A.F1 SLICE_97 -ROUTE 1 0.138 R3C9A.F1 to R5C9A.C1 n7_adj_5 -CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c) +ROUTE 2 0.132 R3C8A.Q0 to R3C8A.A0 C1Submitted +CTOF_DEL --- 0.101 R3C8A.A0 to R3C8A.F0 SLICE_13 +ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 C1Submitted_s (to PHI2_c) -------- - 0.909 (48.0% logic, 52.0% route), 4 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_15: + Source Clock Path PHI2 to SLICE_13: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path PHI2 to SLICE_13: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 1.059ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) - FF CmdUFMCLK_413 + Source: FF Q CmdSubmitted (from PHI2_c -) + Destination: FF Data in CmdSubmitted (to PHI2_c -) - Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 1.031ns physical path delay SLICE_19 to SLICE_100 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_20 to SLICE_20 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_19 to SLICE_100: + Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 -CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 -ROUTE 2 0.260 R5C6D.F1 to R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c) +REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_20 (from PHI2_c) +ROUTE 4 0.132 R4C8B.Q0 to R4C8B.A0 CmdSubmitted +CTOF_DEL --- 0.101 R4C8B.A0 to R4C8B.F0 SLICE_20 +ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 N_412_0 (to PHI2_c) -------- - 1.031 (32.5% logic, 67.5% route), 3 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_19: + Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C7B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.059ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) - - Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. - - Constraint Details: - - 1.031ns physical path delay SLICE_19 to SLICE_99 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.059ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 -CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 -ROUTE 2 0.260 R5C6D.F1 to R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c) - -------- - 1.031 (32.5% logic, 67.5% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.106ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) - - Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. - - Constraint Details: - - 1.078ns physical path delay SLICE_19 to SLICE_20 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.106ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 -CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 -ROUTE 2 0.138 R5C7D.F0 to R3C7C.D1 n2220 -CTOF_DEL --- 0.101 R3C7C.D1 to R3C7C.F1 SLICE_89 -ROUTE 1 0.143 R3C7C.F1 to R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c) - -------- - 1.078 (40.4% logic, 59.6% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C7D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 1.106ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) - Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 1.078ns physical path delay SLICE_19 to SLICE_24 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_42 to SLICE_42 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_19 to SLICE_24: + Data path SLICE_42 to SLICE_42: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 -CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 -ROUTE 2 0.138 R5C7D.F0 to R3C7C.D0 n2220 -CTOF_DEL --- 0.101 R3C7C.D0 to R3C7C.F0 SLICE_89 -ROUTE 1 0.143 R3C7C.F0 to R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c) +REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_42 (from PHI2_c) +ROUTE 2 0.132 R5C9B.Q0 to R5C9B.A0 XOR8MEG +CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_42 +ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 XOR8MEG_3 (to PHI2_c) -------- - 1.078 (40.4% logic, 59.6% route), 4 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.435ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.422ns (68.5% logic, 31.5% route), 2 logic levels. + + Constraint Details: + + 0.422ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.435ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 3 0.133 R3C8C.Q0 to R3C8C.A0 CmdEnable +CTOOFX_DEL --- 0.156 R3C8C.A0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.422 (68.5% logic, 31.5% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.440ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.427ns (67.7% logic, 32.3% route), 2 logic levels. + + Constraint Details: + + 0.427ns physical path delay SLICE_10 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.440ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.138 R3C8B.Q0 to R3C8C.C1 ADSubmitted +CTOOFX_DEL --- 0.156 R3C8C.C1 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.427 (67.7% logic, 32.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.526ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.513ns (56.3% logic, 43.7% route), 2 logic levels. + + Constraint Details: + + 0.513ns physical path delay SLICE_13 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.526ns + + Physical Path Details: + + Data path SLICE_13 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c) +ROUTE 2 0.224 R3C8A.Q0 to R3C8C.B0 C1Submitted +CTOOFX_DEL --- 0.156 R3C8C.B0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.513 (56.3% logic, 43.7% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_13: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.527ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.514ns (56.2% logic, 43.8% route), 2 logic levels. + + Constraint Details: + + 0.514ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.527ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 3 0.225 R3C8C.Q0 to R3C8C.B1 CmdEnable +CTOOFX_DEL --- 0.156 R3C8C.B1 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.514 (56.2% logic, 43.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_19 to SLICE_19 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.212 R5C8B.Q0 to R5C8A.A1 CmdLEDEN +CTOF_DEL --- 0.101 R5C8A.A1 to R5C8A.F1 SLICE_70 +ROUTE 1 0.056 R5C8A.F1 to R5C8B.C0 N_59 +CTOF_DEL --- 0.101 R5C8B.C0 to R5C8B.F0 SLICE_19 +ROUTE 1 0.000 R5C8B.F0 to R5C8B.DI0 N_14_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_24: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C7B.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns) +Passed: The following path meets requirements by 0.702ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q XOR8MEG_408 (from PHI2_c -) - Destination: FF Data in RA11_385 (to PHI2_c +) + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels. + Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels. Constraint Details: - 0.444ns physical path delay SLICE_50 to SLICE_33 meets + 0.689ns physical path delay SLICE_21 to SLICE_21 meets -0.013ns DIN_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.060ns) by 5.504ns + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.702ns Physical Path Details: - Data path SLICE_50 to SLICE_33: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C6A.CLK to R4C6A.Q0 SLICE_50 (from PHI2_c) -ROUTE 1 0.210 R4C6A.Q0 to R4C6C.A0 XOR8MEG -CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_33 -ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 RA11_N_184 (to PHI2_c) +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R5C8D.Q0 to R5C8C.B1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R5C8C.B1 to R5C8C.F1 SLICE_50 +ROUTE 1 0.130 R5C8C.F1 to R5C8D.A0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_21 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 N_12_i (to PHI2_c) -------- - 0.444 (52.7% logic, 47.3% route), 2 logic levels. + 0.689 (48.6% logic, 51.4% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_50: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_33: + Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6C.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns) +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) - Delay: 0.839ns (52.0% logic, 48.0% route), 4 logic levels. + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: - 0.839ns physical path delay SLICE_93 to SLICE_15 meets - -0.013ns DIN_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.060ns) by 5.899ns + 0.285ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: - Data path SLICE_93 to SLICE_15: + Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.133 R5C8C.Q1 to R5C8D.D1 Bank_1 -CTOF_DEL --- 0.101 R5C8D.D1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.214 R5C8D.F1 to R3C8B.A1 n22 -CTOF_DEL --- 0.101 R3C8B.A1 to R3C8B.F1 SLICE_15 -ROUTE 1 0.056 R3C8B.F1 to R3C8B.C0 n2365 -CTOF_DEL --- 0.101 R3C8B.C0 to R3C8B.F0 SLICE_15 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_14 (from RCLK_c) +ROUTE 1 0.152 R5C9A.Q0 to R5C9A.M1 CASr (to RCLK_c) -------- - 0.839 (52.0% logic, 48.0% route), 4 logic levels. + 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. + 1.059 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.309ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) + + Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels. + + Constraint Details: + + 0.290ns physical path delay SLICE_29 to SLICE_29 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.309ns + + Physical Path Details: + + Data path SLICE_29 to SLICE_29: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q0 SLICE_29 (from RCLK_c) +ROUTE 2 0.157 R6C12B.Q0 to R6C12B.M1 RASr (to RCLK_c) + -------- + 0.290 (45.9% logic, 54.1% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in RASr3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_29 to SLICE_32 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_29 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q1 SLICE_29 (from RCLK_c) +ROUTE 10 0.159 R6C12B.Q1 to R6C12A.M1 RASr2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_65 to SLICE_65 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_65 to SLICE_65: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C4B.CLK to R4C4B.Q0 SLICE_65 (from RCLK_c) +ROUTE 3 0.159 R4C4B.Q0 to R4C4B.M1 PHI2r2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_65: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_65: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[0] (from RCLK_c +) + Destination: FF Data in FS[0] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_0 to SLICE_0 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C3A.CLK to R6C3A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R6C3A.Q1 to R6C3A.A1 FS[0] +CTOF_DEL --- 0.101 R6C3A.A1 to R6C3A.F1 SLICE_0 +ROUTE 1 0.000 R6C3A.F1 to R6C3A.DI1 FS_s[0] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in FS[13] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_3 to SLICE_3 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_3: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.132 R6C4D.Q0 to R6C4D.A0 FS[13] +CTOF_DEL --- 0.101 R6C4D.A0 to R6C4D.F0 SLICE_3 +ROUTE 1 0.000 R6C4D.F0 to R6C4D.DI0 FS_s[13] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Ready_fast (from RCLK_c +) + Destination: FF Data in Ready_fast (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_34 to SLICE_34 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_34 to SLICE_34: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C13C.CLK to R4C13C.Q0 SLICE_34 (from RCLK_c) +ROUTE 14 0.132 R4C13C.Q0 to R4C13C.A0 Ready_fast +CTOF_DEL --- 0.101 R4C13C.A0 to R4C13C.F0 SLICE_34 +ROUTE 1 0.000 R4C13C.F0 to R4C13C.DI0 N_415_0 (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in FS[12] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_4 to SLICE_4 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_4: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 0.132 R6C4C.Q1 to R6C4C.A1 FS[12] +CTOF_DEL --- 0.101 R6C4C.A1 to R6C4C.F1 SLICE_4 +ROUTE 1 0.000 R6C4C.F1 to R6C4C.DI1 FS_s[12] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nUFMCS (from RCLK_c +) + Destination: FF Data in nUFMCS (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_45 to SLICE_45 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_45 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5A.CLK to R5C5A.Q0 SLICE_45 (from RCLK_c) +ROUTE 1 0.130 R5C5A.Q0 to R5C5A.A0 nUFMCS_c +CTOF_DEL --- 0.101 R5C5A.A0 to R5C5A.F0 SLICE_45 +ROUTE 2 0.002 R5C5A.F0 to R5C5A.DI0 nUFMCS_s_0_N_5_i (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS[9] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_5 to SLICE_5 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_5: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4B.CLK to R6C4B.Q0 SLICE_5 (from RCLK_c) +ROUTE 3 0.132 R6C4B.Q0 to R6C4B.A0 FS[9] +CTOF_DEL --- 0.101 R6C4B.A0 to R6C4B.F0 SLICE_5 +ROUTE 1 0.000 R6C4B.F0 to R6C4B.DI0 FS_s[9] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- @@ -2097,9 +2176,13 @@ Report Summary Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- @@ -2112,14 +2195,20 @@ Clock Domains Analysis Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -2132,8 +2221,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -2148,16 +2237,16 @@ Timing summary (Hold): Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage) Timing summary (Setup and Hold): --------------- -Timing errors: 349 (setup), 0 (hold) -Score: 452301 (setup), 0 (hold) -Cumulative negative slack: 370485 (370485+0) +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html index 7144090..52bf9a9 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:00:22 2023 +Tue Aug 15 23:30:11 2023 Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf @@ -93,7 +93,7 @@ Initialized UFM Pages: 0 Page. Total CPU Time: 1 secs Total REAL Time: 2 secs -Peak Memory Usage: 245 MB +Peak Memory Usage: 246 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt new file mode 100644 index 0000000..a668f03 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt @@ -0,0 +1,155 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 + +# Written on Tue Aug 15 23:12:44 2023 + +##### DESIGN INFO ####################################################### + +Top View: "RAM2GS" +Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" + + + + +##### SUMMARY ############################################################ + +Found 0 issues in 0 out of 4 constraints + + +##### DETAILS ############################################################ + + + +Clock Relationships +******************* + +Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise +----------------------------------------------------------------------------------------------------------------------------------- +RCLK RCLK | 16.000 | No paths | No paths | No paths +RCLK PHI2 | 2.000 | No paths | 1.000 | No paths +RCLK nCRAS | No paths | No paths | 1.000 | No paths +PHI2 RCLK | No paths | No paths | No paths | 1.000 +PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000 +nCRAS RCLK | No paths | No paths | No paths | 1.000 +=================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + +@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + +Unconstrained Start/End Points +****************************** + +p:CROW[0] +p:CROW[1] +p:Din[0] +p:Din[1] +p:Din[2] +p:Din[3] +p:Din[4] +p:Din[5] +p:Din[6] +p:Din[7] +p:Dout[0] +p:Dout[1] +p:Dout[2] +p:Dout[3] +p:Dout[4] +p:Dout[5] +p:Dout[6] +p:Dout[7] +p:MAin[0] +p:MAin[1] +p:MAin[2] +p:MAin[3] +p:MAin[4] +p:MAin[5] +p:MAin[6] +p:MAin[7] +p:MAin[8] +p:MAin[9] +p:RA[0] +p:RA[1] +p:RA[2] +p:RA[3] +p:RA[4] +p:RA[5] +p:RA[6] +p:RA[7] +p:RA[8] +p:RA[9] +p:RA[10] +p:RA[11] +p:RBA[0] +p:RBA[1] +p:RCKE +p:RDQMH +p:RDQML +p:RD[0] (bidir end point) +p:RD[0] (bidir start point) +p:RD[1] (bidir end point) +p:RD[1] (bidir start point) +p:RD[2] (bidir end point) +p:RD[2] (bidir start point) +p:RD[3] (bidir end point) +p:RD[3] (bidir start point) +p:RD[4] (bidir end point) +p:RD[4] (bidir start point) +p:RD[5] (bidir end point) +p:RD[5] (bidir start point) +p:RD[6] (bidir end point) +p:RD[6] (bidir start point) +p:RD[7] (bidir end point) +p:RD[7] (bidir start point) +p:UFMCLK +p:UFMSDI +p:UFMSDO +p:nFWE +p:nRCAS +p:nRCS +p:nRRAS +p:nRWE +p:nUFMCS + + +Inapplicable constraints +************************ + +(none) + + +Applicable constraints with issues +********************************** + +(none) + + +Constraints with matching wildcard expressions +********************************************** + +(none) + + +Library Report +************** + + +# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt.db b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..97ba9ca96a4a412eb68b2f1d5c67ff1ea98261ab GIT binary patch literal 8192 zcmeH~zfQw25XPNA1p@^J1OuvcVxkBoZP@|?ZB+?G2PnLNn>el2#0J|btXX*-o`@&l z6>zGCA~945!NQ$#v3Y?R2OxyF^R&Y(9D84#&x@g0 zFAJA=JFivS%F(0?G}`r@)x$ojU1))Eb!m7f`LVvVr*)rb%53nxl%zAa*@5$@j_@hh9j V`I&~6HNxgsBW7F2{_*eo@D3o_eV+gT literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html index 85916f1..acbafe8 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html @@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2gs_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Tue Aug 15 05:03:37 2023 +// Written on Tue Aug 15 22:56:41 2023 // M: Minimum Performance Grade // iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml @@ -50,101 +50,100 @@ Worst Case Results across Performance Grades (M, 6, 5, 4): Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- -CROW[0] nCRAS F 0.993 4 0.541 4 -CROW[1] nCRAS F 0.293 4 1.148 4 -Din[0] PHI2 F 4.804 4 1.483 4 -Din[0] nCCAS F 1.539 4 -0.150 M -Din[1] PHI2 F 4.733 4 0.702 4 -Din[1] nCCAS F 1.638 4 -0.177 M -Din[2] PHI2 F 4.046 4 1.702 4 -Din[2] nCCAS F 1.651 4 -0.121 M -Din[3] PHI2 F 4.770 4 1.575 4 -Din[3] nCCAS F 1.973 4 -0.207 M -Din[4] PHI2 F 5.656 4 0.720 4 -Din[4] nCCAS F 1.606 4 -0.156 M -Din[5] PHI2 F 4.165 4 1.131 4 -Din[5] nCCAS F 0.618 4 0.435 4 -Din[6] PHI2 F 5.309 4 1.478 4 -Din[6] nCCAS F 1.331 4 -0.053 M -Din[7] PHI2 F 5.874 4 1.774 4 -Din[7] nCCAS F 2.023 4 -0.205 M -MAin[0] PHI2 F 5.149 4 0.137 M -MAin[0] nCRAS F -0.022 M 1.415 4 -MAin[1] PHI2 F 4.216 4 1.539 4 -MAin[1] nCRAS F 1.716 4 -0.018 M -MAin[2] PHI2 F 3.754 4 0.553 4 -MAin[2] nCRAS F -0.164 M 1.715 4 -MAin[3] PHI2 F 5.957 4 -0.100 M -MAin[3] nCRAS F 0.033 4 1.356 4 -MAin[4] PHI2 F 5.652 4 -0.180 M -MAin[4] nCRAS F -0.173 M 1.726 4 -MAin[5] PHI2 F 4.938 4 0.693 6 -MAin[5] nCRAS F 0.005 4 1.395 4 -MAin[6] PHI2 F 5.535 4 -0.147 M -MAin[6] nCRAS F 0.012 4 1.387 4 -MAin[7] PHI2 F 5.951 4 -0.083 M -MAin[7] nCRAS F 0.858 4 0.664 4 -MAin[8] nCRAS F 0.526 4 0.915 4 -MAin[9] nCRAS F 0.038 4 1.342 4 -PHI2 RCLK R 2.772 4 -0.342 M -UFMSDO RCLK R 0.780 4 0.632 4 -nCCAS RCLK R 0.557 4 0.872 4 -nCCAS nCRAS F 2.108 4 -0.053 M -nCRAS RCLK R 2.536 4 -0.169 M -nFWE PHI2 F 5.830 4 0.629 4 -nFWE nCRAS F 1.386 4 0.176 4 +CROW[0] nCRAS F 3.268 4 -0.395 M +CROW[1] nCRAS F 1.999 4 -0.040 M +Din[0] PHI2 F 4.389 4 3.636 4 +Din[0] nCCAS F 0.646 4 0.538 4 +Din[1] PHI2 F 4.456 4 3.516 4 +Din[1] nCCAS F 1.108 4 0.143 4 +Din[2] PHI2 F 4.106 4 3.516 4 +Din[2] nCCAS F 1.315 4 0.036 M +Din[3] PHI2 F 4.427 4 3.516 4 +Din[3] nCCAS F 1.893 4 -0.089 M +Din[4] PHI2 F 4.612 4 3.516 4 +Din[4] nCCAS F 0.714 4 0.460 4 +Din[5] PHI2 F 4.805 4 3.516 4 +Din[5] nCCAS F 1.636 4 -0.054 M +Din[6] PHI2 F 4.266 4 3.636 4 +Din[6] nCCAS F 1.078 4 0.185 4 +Din[7] PHI2 F 5.607 4 3.636 4 +Din[7] nCCAS F 2.050 4 -0.188 M +MAin[0] PHI2 F 6.493 4 -0.289 M +MAin[0] nCRAS F 0.832 4 0.632 4 +MAin[1] PHI2 F 5.109 4 0.055 M +MAin[1] nCRAS F 1.627 4 0.047 M +MAin[2] PHI2 F 5.349 4 0.695 4 +MAin[2] nCRAS F 1.684 4 0.048 M +MAin[3] PHI2 F 7.301 4 -0.533 M +MAin[3] nCRAS F 1.660 4 0.035 M +MAin[4] PHI2 F 6.167 4 -0.223 M +MAin[4] nCRAS F 1.339 4 0.181 4 +MAin[5] PHI2 F 6.923 4 -0.449 M +MAin[5] nCRAS F 1.082 4 0.412 4 +MAin[6] PHI2 F 6.784 4 -0.408 M +MAin[6] nCRAS F 0.961 4 0.423 4 +MAin[7] PHI2 F 6.547 4 -0.171 M +MAin[7] nCRAS F 1.331 4 0.186 4 +MAin[8] nCRAS F 0.454 4 0.874 4 +MAin[9] nCRAS F 0.782 4 0.684 4 +PHI2 RCLK R -0.312 M 3.167 4 +UFMSDO RCLK R 0.397 4 0.958 4 +nCCAS RCLK R 2.272 4 -0.095 M +nCCAS nCRAS F 3.094 4 -0.308 M +nCRAS RCLK R 1.843 4 0.009 M +nFWE PHI2 F 5.987 4 -0.179 M +nFWE nCRAS F 0.594 4 0.839 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ -LED RCLK R 11.611 4 3.288 M -LED nCRAS F 12.009 4 3.367 M -RA[0] RCLK R 12.268 4 3.492 M -RA[0] nCRAS F 11.741 4 3.284 M -RA[10] RCLK R 10.004 4 2.964 M -RA[11] PHI2 R 10.669 4 3.160 M -RA[1] RCLK R 12.975 4 3.665 M -RA[1] nCRAS F 11.918 4 3.321 M -RA[2] RCLK R 12.531 4 3.533 M -RA[2] nCRAS F 11.755 4 3.277 M -RA[3] RCLK R 11.851 4 3.375 M -RA[3] nCRAS F 12.624 4 3.513 M -RA[4] RCLK R 13.380 4 3.775 M -RA[4] nCRAS F 12.857 4 3.569 M -RA[5] RCLK R 12.767 4 3.632 M -RA[5] nCRAS F 12.469 4 3.456 M -RA[6] RCLK R 12.163 4 3.468 M -RA[6] nCRAS F 12.141 4 3.394 M -RA[7] RCLK R 11.990 4 3.375 M -RA[7] nCRAS F 12.172 4 3.381 M -RA[8] RCLK R 11.712 4 3.314 M -RA[8] nCRAS F 12.431 4 3.457 M -RA[9] RCLK R 11.412 4 3.233 M -RA[9] nCRAS F 12.128 4 3.377 M -RBA[0] nCRAS F 10.844 4 3.124 M -RBA[1] nCRAS F 10.216 4 2.967 M -RCKE RCLK R 10.964 4 3.209 M -RDQMH RCLK R 12.109 4 3.426 M -RDQML RCLK R 10.974 4 3.140 M -RD[0] nCCAS F 8.747 4 2.603 M -RD[1] nCCAS F 8.747 4 2.603 M -RD[2] nCCAS F 8.737 4 2.605 M -RD[3] nCCAS F 9.239 4 2.740 M -RD[4] nCCAS F 9.283 4 2.726 M -RD[5] nCCAS F 9.355 4 2.761 M -RD[6] nCCAS F 9.106 4 2.681 M -RD[7] nCCAS F 9.181 4 2.711 M -UFMCLK RCLK R 10.078 4 3.002 M -UFMSDI RCLK R 10.108 4 2.996 M -nRCAS RCLK R 10.525 4 3.100 M -nRCS RCLK R 10.119 4 2.984 M -nRRAS RCLK R 10.200 4 3.024 M -nRWE RCLK R 9.984 4 2.972 M -nUFMCS RCLK R 10.165 4 3.020 M +LED RCLK R 11.623 4 3.337 M +LED nCRAS F 10.867 4 3.086 M +RA[0] RCLK R 10.387 4 3.085 M +RA[0] nCRAS F 10.473 4 3.018 M +RA[10] RCLK R 8.141 4 2.620 M +RA[11] PHI2 R 8.610 4 2.756 M +RA[1] RCLK R 11.208 4 3.281 M +RA[1] nCRAS F 10.655 4 3.096 M +RA[2] RCLK R 11.477 4 3.355 M +RA[2] nCRAS F 10.655 4 3.096 M +RA[3] RCLK R 10.954 4 3.201 M +RA[3] nCRAS F 10.693 4 3.092 M +RA[4] RCLK R 12.338 4 3.584 M +RA[4] nCRAS F 10.776 4 3.099 M +RA[5] RCLK R 11.516 4 3.347 M +RA[5] nCRAS F 11.072 4 3.177 M +RA[6] RCLK R 11.068 4 3.255 M +RA[6] nCRAS F 10.655 4 3.096 M +RA[7] RCLK R 10.823 4 3.207 M +RA[7] nCRAS F 11.129 4 3.214 M +RA[8] RCLK R 11.034 4 3.275 M +RA[8] nCRAS F 10.664 4 3.099 M +RA[9] RCLK R 10.925 4 3.239 M +RA[9] nCRAS F 10.710 4 3.093 M +RBA[0] nCRAS F 8.157 4 2.563 M +RBA[1] nCRAS F 8.157 4 2.563 M +RCKE RCLK R 8.141 4 2.620 M +RDQMH RCLK R 11.337 4 3.355 M +RDQML RCLK R 10.800 4 3.223 M +RD[0] nCCAS F 7.888 4 2.510 M +RD[1] nCCAS F 7.888 4 2.510 M +RD[2] nCCAS F 7.888 4 2.510 M +RD[3] nCCAS F 7.888 4 2.510 M +RD[4] nCCAS F 7.888 4 2.510 M +RD[5] nCCAS F 7.888 4 2.510 M +RD[6] nCCAS F 7.888 4 2.510 M +RD[7] nCCAS F 7.888 4 2.510 M +UFMCLK RCLK R 8.121 4 2.627 M +UFMSDI RCLK R 8.121 4 2.627 M +nRCAS RCLK R 8.141 4 2.620 M +nRCS RCLK R 8.141 4 2.620 M +nRRAS RCLK R 8.141 4 2.620 M +nRWE RCLK R 8.121 4 2.627 M +nUFMCS RCLK R 8.121 4 2.627 M WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with hold speed: 6 WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd index bcf1f47..0053977 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd @@ -3,12 +3,12 @@ Device = LCMXO2-640HC; Package = TQFP100; Performance = 4; LUTS_avail = 640; -LUTS_used = 143; +LUTS_used = 159; FF_avail = 719; -FF_used = 102; -INPUT_LVCMOS25 = 26; -OUTPUT_LVCMOS25 = 33; -BIDI_LVCMOS25 = 8; +FF_used = 93; +INPUT_LVCMOS33 = 26; +OUTPUT_LVCMOS33 = 33; +BIDI_LVCMOS33 = 8; IO_avail = 79; IO_used = 67; EBR_avail = 2; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam index 5798330..65fe70d 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam @@ -1,23 +1,35 @@ [ START MERGED ] -n2380 Ready -PHI2_N_120 PHI2_c -nRWE_N_176 nRWE_N_177 -n1407 nRowColSel_N_34 -n1408 nRowColSel_N_35 +RASr2_i RASr2 +XOR8MEG.CN PHI2_c +nCRAS_c_i nCRAS_c [ END MERGED ] [ START CLIPPED ] -GND_net -VCC_net -FS_610_add_4_19/S1 -FS_610_add_4_19/CO -FS_610_add_4_1/S0 -FS_610_add_4_1/CI +GND +FS_s_0_S1[17] +FS_s_0_COUT[17] +FS_cry_0_S0[0] +N_1 [ END CLIPPED ] [ START DESIGN PREFS ] SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 23:30:05 2023 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "UFMSDI" SITE "29" ; +LOCATE COMP "UFMCLK" SITE "28" ; +LOCATE COMP "nUFMCS" SITE "30" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "RD[7]" SITE "43" ; LOCATE COMP "RD[6]" SITE "42" ; LOCATE COMP "RD[5]" SITE "41" ; @@ -25,18 +37,6 @@ LOCATE COMP "RD[4]" SITE "40" ; LOCATE COMP "RD[3]" SITE "39" ; LOCATE COMP "RD[2]" SITE "38" ; LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RA[10]" SITE "64" ; LOCATE COMP "RA[9]" SITE "63" ; @@ -49,16 +49,29 @@ LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "UFMCLK" SITE "29" ; -LOCATE COMP "UFMSDI" SITE "30" ; -LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "nFWE" SITE "15" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; LOCATE COMP "MAin[9]" SITE "32" ; LOCATE COMP "MAin[8]" SITE "25" ; LOCATE COMP "MAin[7]" SITE "18" ; @@ -69,20 +82,9 @@ LOCATE COMP "MAin[3]" SITE "21" ; LOCATE COMP "MAin[2]" SITE "13" ; LOCATE COMP "MAin[1]" SITE "12" ; LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nFWE" SITE "28" ; -LOCATE COMP "RCLK" SITE "62" ; -LOCATE COMP "UFMSDO" SITE "27" ; +FREQUENCY PORT "PHI2" 2.900000 MHz ; +FREQUENCY PORT "nCCAS" 2.900000 MHz ; +FREQUENCY PORT "nCRAS" 2.900000 MHz ; +FREQUENCY PORT "RCLK" 62.500000 MHz ; SCHEMATIC END ; [ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr index a9cd083..bc09ec9 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr @@ -3,8 +3,10 @@ Report for cell RAM2GS Instance path: RAM2GS Cell usage: cell count Res Usage(%) - SLIC 75.00 100.0 - LUT4 123.00 100.0 + SLIC 81.00 100.0 + IOLGC 29.00 100.0 + LUT4 139.00 100.0 + IOREG 29 100.0 IOBUF 67 100.0 - PFUREG 102 100.0 + PFUREG 64 100.0 RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd index 3b0a349a8f4a8a9d395c9d3450b234324d65587a..0fa9172913ee8b1a42242d439d4267f74dc0b7a2 100644 GIT binary patch literal 149601 zcmeHw2bf&Nk^dWMgI19wL^Mm5kbs@pBrOQoo!ONZZIEVHf#g9Tfdyy<3MSbY=bRG` z*f{5$b51y?bHee?>3lxh=kxh|zWeXLx~jXXyI#+(K&$a;_4fNpnpdy8y1Kf4U7g;0 zOP2ickGaAFA5Uf{v&-Fsg*79|wg-AXmP>NC?J8W`(vl1m2e%9t&h2PxSzAm-H}tK~ z1G6oGzhlim`~CMjC?QGa_7C@L9O*A@>B{HevI&{2UH{5#7?J(Rr&FwT?FcSRh>ATW!XKC&#!zF#C!l>>Xm9!A8Z~-fb;suyY}sk z+J*YD3GSm=C%BJxo!~wic7pq8*$M7b2UA^tw5`hTS&!7OYCY-~=ahT8qfSR1WcAzR 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    lLP0^F10SPn|X%jYv9{n!xrh$(@M{{M#hMd!AHp-!(o6_@Cf$TdJuS#H9cnY5wPhlP7 zt**fF`P6jU87ElOA0VmYzpi0^Xff^RIH zM!gtMF&pD)3u8QKqU`Grnl^4ncRpca;{6K~Ct!78?5`KefZ_^d*M%2Y1BP(gaHHd@ ztm=trUkM31_JIWLbuR?bl0Z@X&JJYP(-6q660tsHDo~ X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO", + generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); @@ -108,36 +108,21 @@ InstancePath : string := "SLICE_0"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic; FCO: out Std_logic); + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; @@ -147,16 +132,10 @@ ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; @@ -181,46 +160,34 @@ S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i14: vmuxregsre + FS_0: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i13: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_15: ccu2B0 - port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, - C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + FS_cry_0_0: ccu2B0 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out) VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; @@ -230,8 +197,6 @@ VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; @@ -256,24 +221,6 @@ TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", @@ -289,39 +236,14 @@ END IF; - F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); @@ -336,12 +258,6 @@ OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); @@ -350,6 +266,31 @@ end Structure; +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + -- entity SLICE_1 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -364,26 +305,14 @@ MsgOn : boolean := TRUE; InstancePath : string := "SLICE_1"; - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; @@ -391,10 +320,8 @@ tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic; FCO: out Std_logic); + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; @@ -403,10 +330,7 @@ architecture Structure of SLICE_1 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; @@ -414,9 +338,6 @@ signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; @@ -431,34 +352,29 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20001 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i12: vmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); + FS_17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i11: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_13: ccu2B0 - port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, - C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); + FS_s_0_17: ccu20001 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); @@ -467,26 +383,16 @@ -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; @@ -495,24 +401,6 @@ BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", @@ -548,9 +436,6 @@ F0_zd := F0_out; Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -569,44 +454,36 @@ PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + -- entity SLICE_2 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -688,24 +565,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i8: vmuxregsre + FS_16: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i7: vmuxregsre + FS_15: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_9: ccu2B0 + FS_cry_0_15: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -945,24 +822,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i6: vmuxregsre + FS_14: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i5: vmuxregsre + FS_13: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_7: ccu2B0 + FS_cry_0_13: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -1202,24 +1079,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i2: vmuxregsre + FS_12: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i1: vmuxregsre + FS_11: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_3: ccu2B0 + FS_cry_0_11: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -1378,31 +1255,6 @@ end Structure; --- entity ccu20001 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity ccu20001 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; - - end ccu20001; - - architecture Structure of ccu20001 is - begin - inst1: CCU2D - generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - -- entity SLICE_5 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -1418,26 +1270,35 @@ InstancePath : string := "SLICE_5"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; @@ -1448,12 +1309,15 @@ ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; @@ -1472,47 +1336,51 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu20001 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i0: vmuxregsre + FS_10: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - CASr3_384: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + FS_9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_1: ccu20001 - port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, - C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + FS_cry_0_9: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out, - Q1_out, FCO_out) + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; @@ -1524,8 +1392,8 @@ VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; @@ -1551,22 +1419,22 @@ Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, @@ -1583,11 +1451,22 @@ END IF; + F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, @@ -1599,6 +1478,12 @@ OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); @@ -1613,6 +1498,12 @@ OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); @@ -1702,24 +1593,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i10: vmuxregsre + FS_8: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i9: vmuxregsre + FS_7: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_11: ccu2B0 + FS_cry_0_7: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -1878,31 +1769,6 @@ end Structure; --- entity ccu20002 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity ccu20002 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; - - end ccu20002; - - architecture Structure of ccu20002 is - begin - inst1: CCU2D - generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - -- entity SLICE_7 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -1917,14 +1783,26 @@ MsgOn : boolean := TRUE; InstancePath : string := "SLICE_7"; + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; @@ -1932,8 +1810,10 @@ tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; @@ -1942,7 +1822,10 @@ architecture Structure of SLICE_7 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; @@ -1950,6 +1833,9 @@ signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; @@ -1971,22 +1857,27 @@ S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i17: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); + FS_6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_add_4_19: ccu20002 - port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, - C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); + FS_5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_cry_0_5: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); @@ -1995,16 +1886,26 @@ -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; @@ -2013,6 +1914,24 @@ BEGIN IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", @@ -2048,6 +1967,9 @@ F0_zd := F0_out; Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -2066,6 +1988,39 @@ PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -2152,24 +2107,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i4: vmuxregsre + FS_4: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i3: vmuxregsre + FS_3: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_5: ccu2B0 + FS_cry_0_3: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -2409,24 +2364,24 @@ component gnd port (PWR0: out Std_logic); end component; - component ccu2B0 + component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin - FS_610_i16: vmuxregsre + FS_2: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); - FS_610_i15: vmuxregsre + FS_1: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); - FS_610_add_4_17: ccu2B0 + FS_cry_0_1: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); @@ -2602,7 +2557,7 @@ architecture Structure of lut4 is begin INST10: ROM16X1A - generic map (initval => X"0002") + generic map (initval => X"8080") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; @@ -2623,32 +2578,10 @@ architecture Structure of lut40003 is begin INST10: ROM16X1A - generic map (initval => X"2000") + generic map (initval => X"00F2") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity vmuxregsre0004 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity vmuxregsre0004 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE; - - end vmuxregsre0004; - - architecture Structure of vmuxregsre0004 is - begin - INST01: FL1P3IY - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); - end Structure; - -- entity inverter library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -2682,7 +2615,6 @@ MsgOn : boolean := TRUE; InstancePath : string := "SLICE_10"; - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -2691,10 +2623,7 @@ tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); @@ -2703,27 +2632,17 @@ tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; @@ -2733,7 +2652,6 @@ architecture Structure of SLICE_10 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; @@ -2743,21 +2661,26 @@ signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; + signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; component vcc port (PWR1: out Std_logic); end component; + component gnd + port (PWR0: out Std_logic); + end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); @@ -2766,22 +2689,19 @@ port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; begin - i3_3_lut_4_lut: lut4 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_4_lut_adj_4: lut40003 + CmdEnable17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADSubmitted_r: lut40003 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - ADSubmitted_407: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); + ADSubmitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter @@ -2790,7 +2710,6 @@ -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); @@ -2799,8 +2718,6 @@ VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; @@ -2808,14 +2725,11 @@ SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out) + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; @@ -2825,12 +2739,6 @@ VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; @@ -2855,54 +2763,6 @@ TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", @@ -2947,16 +2807,13 @@ Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, + 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, + 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, @@ -2966,6 +2823,27 @@ end Structure; +-- entity lut40004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + -- entity lut40005 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -2983,10 +2861,232 @@ architecture Structure of lut40005 is begin INST10: ROM16X1A - generic map (initval => X"FF7F") + generic map (initval => X"F2F2") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; +-- entity SLICE_13 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_13 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_13"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_13 : ENTITY IS TRUE; + + end SLICE_13; + + architecture Structure of SLICE_13 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdEnable16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + C1Submitted_s: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + C1Submitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40006 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -3004,6895 +3104,44 @@ architecture Structure of lut40006 is begin INST10: ROM16X1A - generic map (initval => X"E0F0") + generic map (initval => X"EEEE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity vmuxregsre0007 +-- entity lut40007 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity vmuxregsre0007 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE; - - end vmuxregsre0007; - - architecture Structure of vmuxregsre0007 is - begin - INST01: FL1P3JY - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); - end Structure; - --- entity SLICE_15 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_15 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_15"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE; - - end SLICE_15; - - architecture Structure of SLICE_15 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40005 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40006 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component vmuxregsre0007 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - i13_2_lut_rep_16_4_lut: lut40005 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1110_2_lut_3_lut_4_lut: lut40006 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - C1Submitted_406: vmuxregsre0007 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40008 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40008 is + entity lut40007 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); - ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; - end lut40008; + end lut40007; - architecture Structure of lut40008 is + architecture Structure of lut40007 is begin INST10: ROM16X1A generic map (initval => X"5555") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_16 +-- entity SLICE_14 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_16 is + entity SLICE_14 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_16"; - - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; - - end SLICE_16; - - architecture Structure of SLICE_16 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40008 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2045: lut40008 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CASr2_383: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CASr_382: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40009 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40009 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; - - end lut40009; - - architecture Structure of lut40009 is - begin - INST10: ROM16X1A - generic map (initval => X"C0CA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40010 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40010 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; - - end lut40010; - - architecture Structure of lut40010 is - begin - INST10: ROM16X1A - generic map (initval => X"4000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_19 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_19 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_19"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; - - end SLICE_19; - - architecture Structure of SLICE_19 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal GNDI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40009 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40010 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i26_4_lut: lut40009 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i2_3_lut_4_lut: lut40010 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - CmdEnable_405: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40011 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40011 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; - - end lut40011; - - architecture Structure of lut40011 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_20 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_20 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_20"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; - - end SLICE_20; - - architecture Structure of SLICE_20 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40011 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - n2447_001_BUF1_BUF1: lut40011 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CmdSubmitted_411: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0 <= F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40012 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40012 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; - - end lut40012; - - architecture Structure of lut40012 is - begin - INST10: ROM16X1A - generic map (initval => X"FEFE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40013 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40013 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; - - end lut40013; - - architecture Structure of lut40013 is - begin - INST10: ROM16X1A - generic map (initval => X"CC5C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_24 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_24 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_24"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; - - end SLICE_24; - - architecture Structure of SLICE_24 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40012 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40013 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_3_lut_adj_15: lut40012 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - Cmdn8MEGEN_I_93_4_lut: lut40013 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - Cmdn8MEGEN_410: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40014 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40014 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; - - end lut40014; - - architecture Structure of lut40014 is - begin - INST10: ROM16X1A - generic map (initval => X"4040") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_25 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_25 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_25"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; - - end SLICE_25; - - architecture Structure of SLICE_25 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40008 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40014 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2_3_lut_3_lut: lut40014 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i2_1_lut_rep_24: lut40008 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - CBR_390: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - FWEr_389: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, - CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_26 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_26 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_26"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; - - end SLICE_26; - - architecture Structure of SLICE_26 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40011 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - n2447_000_BUF1_BUF1: lut40011 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - InitReady_394: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0 <= F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_27 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_27 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_27"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; - - end SLICE_27; - - architecture Structure of SLICE_27 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40011 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - m1_lut: lut40011 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - LEDEN_419: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0 <= F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40015 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40015 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; - - end lut40015; - - architecture Structure of lut40015 is - begin - INST10: ROM16X1A - generic map (initval => X"FBFB") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_30 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_30 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_30"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; - - end SLICE_30; - - architecture Structure of SLICE_30 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40008 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40015 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2010_3_lut_3_lut: lut40015 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i2044: lut40008 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - RASr2_380: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - RASr_379: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, - CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40016 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40016 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; - - end lut40016; - - architecture Structure of lut40016 is - begin - INST10: ROM16X1A - generic map (initval => X"8080") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40017 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40017 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; - - end lut40017; - - architecture Structure of lut40017 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFB") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_32 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_32 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_32"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; - - end SLICE_32; - - architecture Structure of SLICE_32 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component vmuxregsre0007 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40016 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40017 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2_3_lut_rep_32: lut40016 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i2_2_lut_3_lut_4_lut: lut40017 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - RA10_400: vmuxregsre0007 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_NOTIN, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40018 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40018 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; - - end lut40018; - - architecture Structure of lut40018 is - begin - INST10: ROM16X1A - generic map (initval => X"1010") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40019 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40019 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; - - end lut40019; - - architecture Structure of lut40019 is - begin - INST10: ROM16X1A - generic map (initval => X"C6C6") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_33 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_33 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_33"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; - - end SLICE_33; - - architecture Structure of SLICE_33 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40018 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40019 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_3_lut: lut40018 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - RA11_I_54_3_lut: lut40019 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - RA11_385: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_NOTIN, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40020 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40020 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; - - end lut40020; - - architecture Structure of lut40020 is - begin - INST10: ROM16X1A - generic map (initval => X"20FF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40021 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40021 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; - - end lut40021; - - architecture Structure of lut40021 is - begin - INST10: ROM16X1A - generic map (initval => X"CACA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_35 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_35 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_35"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; - - end SLICE_35; - - architecture Structure of SLICE_35 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40020 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_4_lut_adj_25: lut40020 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i29_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - RCKEEN_401: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40022 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40022 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; - - end lut40022; - - architecture Structure of lut40022 is - begin - INST10: ROM16X1A - generic map (initval => X"CFC8") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_36 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_36 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_36"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; - - end SLICE_36; - - architecture Structure of SLICE_36 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40022 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1404_4_lut: lut40022 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - PHI2r2_377: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - RCKE_395: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, - CLK_dly, F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_37 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_37 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_37"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; - - end SLICE_37; - - architecture Structure of SLICE_37 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40011 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - n2447_002_BUF1_BUF1: lut40011 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - Ready_404: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0 <= F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40023 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40023 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; - - end lut40023; - - architecture Structure of lut40023 is - begin - INST10: ROM16X1A - generic map (initval => X"3A0A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_44 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_44 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_44"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; - - end SLICE_44; - - architecture Structure of SLICE_44 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40023 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1970_4_lut: lut40023 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1603_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - UFMCLK_416: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40024 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40024 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; - - end lut40024; - - architecture Structure of lut40024 is - begin - INST10: ROM16X1A - generic map (initval => X"CAC0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_45 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_45 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_45"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; - - end SLICE_45; - - architecture Structure of SLICE_45 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component lut4 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40024 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i4_4_lut_adj_17: lut4 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1589_4_lut: lut40024 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - UFMSDI_417: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40025 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40025 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; - - end lut40025; - - architecture Structure of lut40025 is - begin - INST10: ROM16X1A - generic map (initval => X"FEFA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40026 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40026 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; - - end lut40026; - - architecture Structure of lut40026 is - begin - INST10: ROM16X1A - generic map (initval => X"0008") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_50 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_50 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_50"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; - - end SLICE_50; - - architecture Structure of SLICE_50 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal GNDI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40025 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40026 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1962_4_lut: lut40025 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i2_3_lut_4_lut_adj_11: lut40026 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - XOR8MEG_408: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40027 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40027 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; - - end lut40027; - - architecture Structure of lut40027 is - begin - INST10: ROM16X1A - generic map (initval => X"1000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40028 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40028 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; - - end lut40028; - - architecture Structure of lut40028 is - begin - INST10: ROM16X1A - generic map (initval => X"BF04") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_57 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_57 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_57"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; - - end SLICE_57; - - architecture Structure of SLICE_57 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40027 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2_3_lut_rep_18_4_lut: lut40027 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - n8MEGEN_I_14_3_lut_4_lut: lut40028 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - n8MEGEN_418: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40029 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40029 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; - - end lut40029; - - architecture Structure of lut40029 is - begin - INST10: ROM16X1A - generic map (initval => X"3AFA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40030 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40030 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; - - end lut40030; - - architecture Structure of lut40030 is - begin - INST10: ROM16X1A - generic map (initval => X"FE0E") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity vmuxregsre0031 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity vmuxregsre0031 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE; - - end vmuxregsre0031; - - architecture Structure of vmuxregsre0031 is - begin - INST01: FL1P3BX - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); - end Structure; - --- entity SLICE_59 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_59 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_59"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; - - end SLICE_59; - - architecture Structure of SLICE_59 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40029 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40030 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component vmuxregsre0031 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - nRCAS_I_43_4_lut: lut40029 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - nRCAS_I_0_452_3_lut_4_lut: lut40030 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - nRCAS_398: vmuxregsre0031 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40032 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40032 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; - - end lut40032; - - architecture Structure of lut40032 is - begin - INST10: ROM16X1A - generic map (initval => X"1F10") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_61 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_61 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_61"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; - - end SLICE_61; - - architecture Structure of SLICE_61 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component vmuxregsre0031 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40032 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - nRCS_I_31_3_lut_4_lut: lut40032 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - nRCS_I_0_448_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - nRCS_396: vmuxregsre0031 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40033 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40033 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; - - end lut40033; - - architecture Structure of lut40033 is - begin - INST10: ROM16X1A - generic map (initval => X"BFFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_62 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_62 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_62"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; - - end SLICE_62; - - architecture Structure of SLICE_62 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40029 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component vmuxregsre0031 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40033 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i3_4_lut_adj_2: lut40033 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - nRCS_N_137_I_0_4_lut: lut40029 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - nRRAS_397: vmuxregsre0031 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40034 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40034 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; - - end lut40034; - - architecture Structure of lut40034 is - begin - INST10: ROM16X1A - generic map (initval => X"EEEE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40035 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40035 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; - - end lut40035; - - architecture Structure of lut40035 is - begin - INST10: ROM16X1A - generic map (initval => X"CFC5") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_64 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_64 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_64"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; - - end SLICE_64; - - architecture Structure of SLICE_64 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0031 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40035 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1477_2_lut: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - nRWE_I_0_455_4_lut: lut40035 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - nRWE_399: vmuxregsre0031 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40036 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40036 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; - - end lut40036; - - architecture Structure of lut40036 is - begin - INST10: ROM16X1A - generic map (initval => X"3032") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_65 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_65 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_65"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; - - end SLICE_65; - - architecture Structure of SLICE_65 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40036 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i786_2_lut: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1432_4_lut: lut40036 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - nRowColSel_402: vmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40037 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40037 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; - - end lut40037; - - architecture Structure of lut40037 is - begin - INST10: ROM16X1A - generic map (initval => X"BBBB") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_66 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_66 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_66"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; - - end SLICE_66; - - architecture Structure of SLICE_66 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40037 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_adj_23: lut40037 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1439_2_lut: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - S_FSM_i4: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_NOTIN, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40038 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40038 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; - - end lut40038; - - architecture Structure of lut40038 is - begin - INST10: ROM16X1A - generic map (initval => X"2222") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_67 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_67 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_67"; - - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; - - end SLICE_67; - - architecture Structure of SLICE_67 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40038 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_adj_10: lut40038 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - S_FSM_i3: vmuxregsre0004 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_NOTIN, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40039 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40039 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; - - end lut40039; - - architecture Structure of lut40039 is - begin - INST10: ROM16X1A - generic map (initval => X"8888") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_68 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_68 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_68"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; - - end SLICE_68; - - architecture Structure of SLICE_68 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40039 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i4_2_lut: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1989_2_lut: lut40039 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - S_FSM_i2: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_NOTIN, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_69 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_69 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_69"; + InstancePath : string := "SLICE_14"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -9921,11 +3170,11 @@ F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; - end SLICE_69; + end SLICE_14; - architecture Structure of SLICE_69 is + architecture Structure of SLICE_14 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; @@ -9955,27 +3204,27 @@ component gnd port (PWR0: out Std_logic); end component; - component lut40008 + component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40034 + component lut40007 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1491_2_lut_rep_30: lut40034 + nCCAS_pad_RNI01SJ: lut40006 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - RASr2_I_0_1_lut_rep_25: lut40008 + nCCAS_pad_RNISUR8: lut40007 port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - PHI2r3_378: vmuxregsre + CASr2: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); - S_FSM_i1: vmuxregsre + CASr: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); @@ -10111,61 +3360,5979 @@ end Structure; --- entity lut40040 +-- entity lut40008 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity lut40040 is + entity lut40008 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); - ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; - end lut40040; + end lut40008; - architecture Structure of lut40040 is + architecture Structure of lut40008 is begin INST10: ROM16X1A - generic map (initval => X"FFFE") + generic map (initval => X"0800") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity lut40041 +-- entity lut40009 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity lut40041 is + entity lut40009 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); - ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; - end lut40041; + end lut40009; - architecture Structure of lut40041 is + architecture Structure of lut40009 is begin INST10: ROM16X1A - generic map (initval => X"3FBB") + generic map (initval => X"DDDD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_70 +-- entity vmuxregsre0010 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_70 is + entity vmuxregsre0010 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0010 : ENTITY IS TRUE; + + end vmuxregsre0010; + + architecture Structure of vmuxregsre0010 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_17 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_17 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_70"; + InstancePath : string := "SLICE_17"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE; + + end SLICE_17; + + architecture Structure of SLICE_17 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0010 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3_2: lut40008 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_RNO_0: lut40009 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_0: vmuxregsre0010 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"AC8C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_18_SLICE_18_K1_H1: Std_logic; + signal SLICE_18_CmdEnable_s_GATE_H0: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_18_K1: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, + Z=>SLICE_18_SLICE_18_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdEnable_s_GATE: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_18_CmdEnable_s_GATE_H0); + CmdEnable: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + SLICE_18_K0K1MUX: selmux2 + port map (D0=>SLICE_18_CmdEnable_s_GATE_H0, D1=>SLICE_18_SLICE_18_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"0203") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdLEDEN_4_u_i_a2_0: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdLEDEN_RNO: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdLEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdUFMCLK_1_sqmuxa_0_a2: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdSubmitted_RNO: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdSubmitted: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"5151") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_21 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_21 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_21"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE; + + end SLICE_21; + + architecture Structure of SLICE_21 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Cmdn8MEGEN_4_u_i_a2_2: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_RNO: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Cmdn8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_22 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_22 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_22"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE; + + end SLICE_22; + + architecture Structure of SLICE_22 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CMDWR_2: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + FWEr_RNO: lut40007 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FWEr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"FFF7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"A9A9") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_0io_RNO: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_RNO_0: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"7878") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"6666") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_RNO_2: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_n1_0_x2: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"6AAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_RNO_3: lut40023 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + InitReady3_0_a2: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + InitReady_RNO: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_27 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_27 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_27"; + + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; + + end SLICE_27; + + architecture Structure of SLICE_27 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LEDEN_RNO: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, + Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_29 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_29 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_29"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE; + + end SLICE_29; + + architecture Structure of SLICE_29 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + LED_pad_RNO: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr_RNO: lut40007 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"5072") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"DCCC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_8_u_RNO: lut40026 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKEEN_8_u: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RCKEEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"FE30") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RBAd_1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_2_0: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RCKE: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"7F7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + begin + INST10: ROM16X1A + generic map (initval => X"AEAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_33 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_33 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_33"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; + + end SLICE_33; + + architecture Structure of SLICE_33 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_o2: lut40030 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_RNO: lut40031 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Ready: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_0_sqmuxa_0_a3: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + Ready_fast_RNO: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_fast: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_0: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_1: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_0: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_3: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_2: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_3: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_2: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_5: lut40024 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_4: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_5: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_4: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_38 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_38 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_38"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE; + + end SLICE_38; + + architecture Structure of SLICE_38 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_7: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_6: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_7: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_6: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_39 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_39 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_39"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE; + + end SLICE_39; + + architecture Structure of SLICE_39 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RowAd_9: lut40024 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowAd_8: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + RowA_9: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + RowA_8: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_negedge, + SetupLow => tsetup_DI1_CLK_noedge_negedge, + HoldHigh => thold_DI1_CLK_noedge_negedge, + HoldLow => thold_DI1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_40 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_40 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_40"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE; + + end SLICE_40; + + architecture Structure of SLICE_40 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0010 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCAS_0_sqmuxa_1_0_a3: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_0_i_o2_1: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_1: vmuxregsre0010 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"1110") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_41 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_41 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_41"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE; + + end SLICE_41; + + architecture Structure of SLICE_41 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal SLICE_41_SLICE_41_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_41_UFMSDI_RNO_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_41_K1: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>SLICE_41_SLICE_41_K1_H1); + UFMSDI_RNO_GATE: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, + Z=>SLICE_41_UFMSDI_RNO_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMSDI: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_41_K0K1MUX: selmux2 + port map (D0=>SLICE_41_UFMSDI_RNO_GATE_H0, D1=>SLICE_41_SLICE_41_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"A0CC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_42 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_42 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_42"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); @@ -10187,16 +9354,16 @@ tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; @@ -10204,11 +9371,11 @@ CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE; - end SLICE_70; + end SLICE_42; - architecture Structure of SLICE_70 is + architecture Structure of SLICE_42 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; @@ -10230,36 +9397,42 @@ signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; - component vmuxregsre0031 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); + component inverter + port (I: in Std_logic; Z: out Std_logic); end component; - component lut40040 + component lut40035 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40041 + component lut40036 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1_2_lut_4_lut: lut40040 + un1_Din_3: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1448_4_lut: lut40041 + XOR8MEG_3_u: lut40036 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - nUFMCS_415: vmuxregsre0031 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + XOR8MEG: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); @@ -10305,6 +9478,275 @@ BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"8B8B") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_Bank_1_4: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_5_i_m2: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, @@ -10361,6 +9803,308 @@ Q0_zd := Q0_out; F1_zd := F1_out; + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"DCEC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0010 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRowColSel_0_0_a3_0: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRowColSel_0_0: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel: vmuxregsre0010 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, @@ -10405,82 +10149,85 @@ end Structure; --- entity lut40042 +-- entity lut40040 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity lut40042 is + entity lut40040 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); - ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; - end lut40042; + end lut40040; - architecture Structure of lut40042 is + architecture Structure of lut40040 is begin INST10: ROM16X1A - generic map (initval => X"1F1F") + generic map (initval => X"000B") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity lut40043 +-- entity lut40041 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity lut40043 is + entity lut40041 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); - ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; - end lut40043; + end lut40041; - architecture Structure of lut40043 is + architecture Structure of lut40041 is begin INST10: ROM16X1A - generic map (initval => X"5540") + generic map (initval => X"5F4E") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity selmux2 +-- entity vmuxregsre0042 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity selmux2 is + entity vmuxregsre0042 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); - ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF vmuxregsre0042 : ENTITY IS TRUE; - end selmux2; + end vmuxregsre0042; - architecture Structure of selmux2 is + architecture Structure of vmuxregsre0042 is begin - INST1: MUX21 - port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); end Structure; --- entity i30_SLICE_71 +-- entity SLICE_45 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity i30_SLICE_71 is + entity SLICE_45 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "i30_SLICE_71"; + InstancePath : string := "SLICE_45"; + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -10488,27 +10235,39 @@ tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; - end i30_SLICE_71; + end SLICE_45; - architecture Structure of i30_SLICE_71 is + architecture Structure of SLICE_45 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; @@ -10516,185 +10275,45 @@ signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic; - signal i30_SLICE_71_i30_GATE_H0: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40042 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40043 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - begin - i30_SLICE_71_K1: lut40042 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, - Z=>i30_SLICE_71_i30_SLICE_71_K1_H1); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i30_GATE: lut40043 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>i30_SLICE_71_i30_GATE_H0); - i30_SLICE_71_K0K1MUX: selmux2 - port map (D0=>i30_SLICE_71_i30_GATE_H0, - D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40044 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40044 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; - - end lut40044; - - architecture Structure of lut40044 is - begin - INST10: ROM16X1A - generic map (initval => X"FF40") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_72 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_72 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_72"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; - - end SLICE_72; - - architecture Structure of SLICE_72 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; + signal VCCI: Std_logic; signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; component gnd port (PWR0: out Std_logic); end component; - component lut40039 + component lut40040 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40044 + component lut40041 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; + component vmuxregsre0042 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; begin - i1_4_lut_4_lut_adj_12: lut40044 + nUFMCS_s_0_m4_yy: lut40040 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i2_2_lut: lut40039 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + nUFMCS_s_0_N_5_i: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nUFMCS: vmuxregsre0042 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); @@ -10705,37 +10324,98 @@ VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); END IF; F0_zd := F0_out; + Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, + 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, @@ -10757,19 +10437,61 @@ end Structure; --- entity SLICE_73 +-- entity lut40043 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_73 is + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"EAAA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"FF80") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_46 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_46 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_73"; + InstancePath : string := "SLICE_46"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); @@ -10793,11 +10515,11 @@ B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE; - end SLICE_73; + end SLICE_46; - architecture Structure of SLICE_73 is + architecture Structure of SLICE_46 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; @@ -10811,18 +10533,18 @@ signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - component lut40003 + component lut40043 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40010 + component lut40044 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i2_3_lut_4_lut_adj_14: lut40003 + un1_ADWR: lut40043 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i4_4_lut: lut40010 + un1_CMDWR: lut40044 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs @@ -10909,967 +10631,23 @@ architecture Structure of lut40045 is begin INST10: ROM16X1A - generic map (initval => X"0020") + generic map (initval => X"0B00") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_74 +-- entity SLICE_47 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_74 is + entity SLICE_47 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_74"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; - - end SLICE_74; - - architecture Structure of SLICE_74 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40033 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i12_4_lut: lut40033 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut_3_lut_4_lut: lut40045 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - RowA_i1: vmuxregsre0004 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RowA_i0: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_75 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_75 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_75"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; - - end SLICE_75; - - architecture Structure of SLICE_75 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40027 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40038 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i3_4_lut_adj_18: lut40027 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut: lut40038 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - IS_FSM_i9: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i8: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_76 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_76 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_76"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; - - end SLICE_76; - - architecture Structure of SLICE_76 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component vmuxregsre0007 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40012 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40026 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_rep_19_3_lut: lut40012 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1_2_lut_rep_15_4_lut: lut40026 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - RowA_i9: vmuxregsre0007 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RowA_i8: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40046 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40046 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; - - end lut40046; - - architecture Structure of lut40046 is - begin - INST10: ROM16X1A - generic map (initval => X"0800") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_77 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_77 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_77"; + InstancePath : string := "SLICE_47"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); @@ -11893,11 +10671,11 @@ B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE; - end SLICE_77; + end SLICE_47; - architecture Structure of SLICE_77 is + architecture Structure of SLICE_47 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; @@ -11911,14 +10689,18 @@ signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - component lut40046 + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i3_4_lut_adj_22: lut40046 + nUFMCS15_0_a2: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i3_4_lut: lut40046 + UFMCLK_0io_RNO: lut40045 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs @@ -11988,6 +10770,160 @@ end Structure; +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"0E0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_48 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_48 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_48"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE; + + end SLICE_48; + + architecture Structure of SLICE_48 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + UFMCLK_r_i_a2_2_2: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + UFMCLK_0io_RNO_1: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40047 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -12005,10 +10941,145 @@ architecture Structure of lut40047 is begin INST10: ROM16X1A - generic map (initval => X"F0DD") + generic map (initval => X"0BFB") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; +-- entity SLICE_49 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + IS_0_sqmuxa_0_o2_0: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_nRCAS_6_sqmuxa_i_0: lut40047 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40048 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -12026,291 +11097,10 @@ architecture Structure of lut40048 is begin INST10: ROM16X1A - generic map (initval => X"DDDD") + generic map (initval => X"2722") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_78 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_78 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_78"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; - - end SLICE_78; - - architecture Structure of SLICE_78 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40047 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40048 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - nRCS_N_146_bdd_4_lut: lut40047 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1423_2_lut: lut40048 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - IS_FSM_i13: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i12: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40049 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -12328,105 +11118,65 @@ architecture Structure of lut40049 is begin INST10: ROM16X1A - generic map (initval => X"0200") + generic map (initval => X"F4F4") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_79 +-- entity SLICE_50 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_79 is + entity SLICE_50 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_79"; + InstancePath : string := "SLICE_50"; + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; - end SLICE_79; + end SLICE_50; - architecture Structure of SLICE_79 is + architecture Structure of SLICE_50 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; component gnd port (PWR0: out Std_logic); end component; - component lut40016 + component lut40048 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -12435,186 +11185,71 @@ Z: out Std_logic); end component; begin - i11_3_lut_rep_20: lut40016 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + Cmdn8MEGEN_4_u_i_0: lut40048 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + Cmdn8MEGEN_4_u_i_o2: lut40049 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); - MAin_c_0_bdd_4_lut: lut40049 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - IS_FSM_i11: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i10: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, + 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, + 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, + 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, + 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -12637,136 +11272,10 @@ architecture Structure of lut40050 is begin INST10: ROM16X1A - generic map (initval => X"0001") + generic map (initval => X"1313") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_80 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_80 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_80"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; - - end SLICE_80; - - architecture Structure of SLICE_80 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40050 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i3_2_lut_rep_26: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i2005_3_lut_rep_17_4_lut: lut40050 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40051 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -12784,102 +11293,65 @@ architecture Structure of lut40051 is begin INST10: ROM16X1A - generic map (initval => X"FCDD") + generic map (initval => X"1303") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_81 +-- entity SLICE_51 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_81 is + entity SLICE_51 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_81"; + InstancePath : string := "SLICE_51"; + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE; - end SLICE_81; + end SLICE_51; - architecture Structure of SLICE_81 is + architecture Structure of SLICE_51 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; component gnd port (PWR0: out Std_logic); end component; - component lut40034 + component lut40050 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -12888,141 +11360,41 @@ Z: out Std_logic); end component; begin - i1_2_lut_rep_29: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + nRCAS_0io_RNO_0: lut40050 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - i1427_4_lut: lut40051 + nRCAS_0io_RNO: lut40051 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - IS_FSM_i15: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i14: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -13040,30 +11412,19 @@ PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, + 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -13086,322 +11447,10 @@ architecture Structure of lut40052 is begin INST10: ROM16X1A - generic map (initval => X"8000") + generic map (initval => X"FEFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_82 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_82 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_82"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; - - end SLICE_82; - - architecture Structure of SLICE_82 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component vmuxregsre0007 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40039 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40052 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i6_4_lut: lut40052 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut_adj_3: lut40039 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - RowA_i5: vmuxregsre0007 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RowA_i4: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40053 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -13419,10 +11468,143 @@ architecture Structure of lut40053 is begin INST10: ROM16X1A - generic map (initval => X"0004") + generic map (initval => X"5051") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; +-- entity SLICE_52 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_52 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_52"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE; + + end SLICE_52; + + architecture Structure of SLICE_52 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_nRCAS_6_sqmuxa_i_o2: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRRAS_5_u_i_0_RNILD5I: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40054 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -13440,145 +11622,10 @@ architecture Structure of lut40054 is begin INST10: ROM16X1A - generic map (initval => X"FFDF") + generic map (initval => X"FF40") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_83 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_83 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_83"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; - - end SLICE_83; - - architecture Structure of SLICE_83 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40053 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40054 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2_4_lut_adj_21: lut40053 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i2_3_lut_4_lut_adj_6: lut40054 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40055 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -13596,105 +11643,65 @@ architecture Structure of lut40055 is begin INST10: ROM16X1A - generic map (initval => X"2020") + generic map (initval => X"0202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_84 +-- entity SLICE_53 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_84 is + entity SLICE_53 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_84"; + InstancePath : string := "SLICE_53"; + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE; - end SLICE_84; + end SLICE_53; - architecture Structure of SLICE_84 is + architecture Structure of SLICE_53 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; component gnd port (PWR0: out Std_logic); end component; - component lut40024 + component lut40054 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -13703,186 +11710,71 @@ Z: out Std_logic); end component; begin - i2_3_lut_rep_28: lut40055 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + nRWE_s_i_tz_0: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + S_RNICVV51_0: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); - i1573_4_lut: lut40024 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - IS_FSM_i3: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i2: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, + 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, + 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, + 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, + 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -13905,712 +11797,10 @@ architecture Structure of lut40056 is begin INST10: ROM16X1A - generic map (initval => X"FFEF") + generic map (initval => X"4444") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_85 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_85 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_85"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; - - end SLICE_85; - - architecture Structure of SLICE_85 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40040 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40056 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1969_2_lut_3_lut_4_lut: lut40056 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i3_4_lut_adj_7: lut40040 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_86 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_86 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_86"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; - - end SLICE_86; - - architecture Structure of SLICE_86 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut4 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40012 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i5_3_lut: lut40012 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1_4_lut_adj_8: lut4 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - RASr3_381: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - PHI2r_376: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_87 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_87 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_87"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; - - end SLICE_87; - - architecture Structure of SLICE_87 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40040 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40048 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i4_4_lut_adj_16: lut40040 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut_2_lut: lut40048 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - RBA_i2: vmuxregsre0004 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RBA_i1: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40057 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -14628,106 +11818,62 @@ architecture Structure of lut40057 is begin INST10: ROM16X1A - generic map (initval => X"C0C5") + generic map (initval => X"F8F0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_88 +-- entity SLICE_54 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_88 is + entity SLICE_54 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_88"; + InstancePath : string := "SLICE_54"; - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE; - end SLICE_88; + end SLICE_54; - architecture Structure of SLICE_88 is + architecture Structure of SLICE_54 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal VCCI: Std_logic; signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; component gnd port (PWR0: out Std_logic); end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40053 + component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -14736,123 +11882,40 @@ Z: out Std_logic); end component; begin - i34_4_lut: lut40057 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_4_lut_adj_13: lut40053 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - WRD_i7: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); + un1_PHI2r3_0: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - WRD_i6: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); + un1_FS_13_i_0: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -14870,35 +11933,148 @@ PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, + 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_55 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_55 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_55"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE; + + end SLICE_55; + + architecture Structure of SLICE_55 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_14_i_a2_0: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_FS_14_i_0: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, PathCondition => TRUE)), - GlitchData => Q1_GlitchData, + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -14922,10 +12098,143 @@ architecture Structure of lut40058 is begin INST10: ROM16X1A - generic map (initval => X"8088") + generic map (initval => X"0100") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; +-- entity SLICE_56 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_13_i_a2_1: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + un1_FS_13_i_a2: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40059 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -14943,23 +12252,23 @@ architecture Structure of lut40059 is begin INST10: ROM16X1A - generic map (initval => X"C444") + generic map (initval => X"2202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_89 +-- entity SLICE_57 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_89 is + entity SLICE_57 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_89"; + InstancePath : string := "SLICE_57"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); @@ -14969,9 +12278,6 @@ tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); @@ -14979,31 +12285,18 @@ tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; - end SLICE_89; + end SLICE_57; - architecture Structure of SLICE_89 is + architecture Structure of SLICE_57 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; @@ -15014,35 +12307,10 @@ signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40058 + component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -15051,22 +12319,10 @@ Z: out Std_logic); end component; begin - i2_4_lut: lut40058 + CmdSubmitted_1_sqmuxa_0_a2: lut40059 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_4_lut: lut40059 + XOR8MEG18: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - WRD_i5: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - WRD_i4: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -15079,95 +12335,24 @@ VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -15185,13 +12370,6 @@ PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, @@ -15208,279 +12386,6 @@ PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_90 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_90 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_90"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; - - end SLICE_90; - - architecture Structure of SLICE_90 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40049 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40055 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_3_lut_4_lut_adj_1: lut40049 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut_rep_21_3_lut: lut40055 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - WRD_i1: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - WRD_i0: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -15503,10 +12408,404 @@ architecture Structure of lut40060 is begin INST10: ROM16X1A - generic map (initval => X"DFDF") + generic map (initval => X"5155") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; +-- entity SLICE_58 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + UFMSDI_ens2_i_a2_4_2: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + UFMSDI_ens2_i_a0: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + UFMSDI_en_ss0_0_a2_0: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un1_FS_13_i_a2_8: lut40015 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + ADWR_3: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + ADWR: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity lut40061 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -15524,324 +12823,10 @@ architecture Structure of lut40061 is begin INST10: ROM16X1A - generic map (initval => X"DFFF") + generic map (initval => X"1010") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_91 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_91 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_91"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; - - end SLICE_91; - - architecture Structure of SLICE_91 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40060 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1_2_lut_rep_13_3_lut: lut40060 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1_2_lut_3_lut_4_lut_adj_5: lut40061 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - RowA_i3: vmuxregsre0004 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RowA_i2: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40062 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -15859,25 +12844,24 @@ architecture Structure of lut40062 is begin INST10: ROM16X1A - generic map (initval => X"0080") + generic map (initval => X"FF32") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_92 +-- entity SLICE_61 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_92 is + entity SLICE_61 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_92"; + InstancePath : string := "SLICE_61"; - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -15885,44 +12869,25 @@ tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; - end SLICE_92; + end SLICE_61; - architecture Structure of SLICE_92 is + architecture Structure of SLICE_61 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; @@ -15930,35 +12895,14 @@ signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal VCCI: Std_logic; signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; component gnd port (PWR0: out Std_logic); end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40005 + component lut40061 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; @@ -15967,27 +12911,16 @@ Z: out Std_logic); end component; begin - i2008_2_lut_4_lut: lut40062 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i1_2_lut_rep_22_4_lut: lut40005 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - WRD_i3: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); + nRCS_0io_RNO_0: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - WRD_i2: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); + nRRAS_5_u_i: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); @@ -15995,95 +12928,24 @@ VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; F0_zd := F0_out; - Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, @@ -16101,36 +12963,19 @@ PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, + 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, + 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -16153,26 +12998,174 @@ architecture Structure of lut40063 is begin INST10: ROM16X1A - generic map (initval => X"7777") + generic map (initval => X"0002") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_93 +-- entity SLICE_62 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_93 is + entity SLICE_62 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_93"; + InstancePath : string := "SLICE_62"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RA10_2_sqmuxa_0_o2: lut40006 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_s_i_a3_1_0: lut40063 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); @@ -16181,6 +13174,7 @@ tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); @@ -16197,20 +13191,22 @@ tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; - end SLICE_93; + end SLICE_63; - architecture Structure of SLICE_93 is + architecture Structure of SLICE_63 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; @@ -16238,27 +13234,27 @@ component gnd port (PWR0: out Std_logic); end component; - component lut40021 + component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40063 + component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i2001_2_lut: lut40063 + C1WR_1: lut40064 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - MAin_9_I_0_427_i10_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - Bank_i1: vmuxregsre + C1WR_3: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_0io_1: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); - Bank_i0: vmuxregsre + Bank_0io_0: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); @@ -16267,6 +13263,7 @@ BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); @@ -16283,8 +13280,8 @@ VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, - M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; @@ -16362,13 +13359,16 @@ VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, + 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, + 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, @@ -16402,153 +13402,6 @@ end Structure; --- entity lut40064 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity lut40064 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; - - end lut40064; - - architecture Structure of lut40064 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFD") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_94 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_94 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_94"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; - - end SLICE_94; - - architecture Structure of SLICE_94 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40048 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i771_2_lut_rep_23_2_lut: lut40048 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i2_3_lut_4_lut_4_lut: lut40064 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40065 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -16566,25 +13419,24 @@ architecture Structure of lut40065 is begin INST10: ROM16X1A - generic map (initval => X"1404") + generic map (initval => X"AAC0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_95 +-- entity SLICE_64 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_95 is + entity SLICE_64 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_95"; + InstancePath : string := "SLICE_64"; - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -16592,7 +13444,6 @@ tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); @@ -16601,19 +13452,17 @@ tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; - end SLICE_95; + end SLICE_64; - architecture Structure of SLICE_95 is + architecture Structure of SLICE_64 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; @@ -16624,157 +13473,30 @@ signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - component lut40040 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i2_4_lut_adj_20: lut40065 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - i6_4_lut_adj_9: lut40040 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_96 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_96 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_96"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; - - end SLICE_96; - - architecture Structure of SLICE_96 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; - component lut40027 + component lut40052 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40034 + component lut40065 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1_2_lut_rep_27: lut40034 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + UFMSDI_ens2_i_o2_0: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - i2_3_lut_4_lut_adj_24: lut40027 + UFMCLK_r_i_m2: lut40065 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); @@ -16783,8 +13505,8 @@ VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; @@ -16818,10 +13540,13 @@ Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, + 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, @@ -16848,309 +13573,36 @@ architecture Structure of lut40066 is begin INST10: ROM16X1A - generic map (initval => X"C5C5") + generic map (initval => X"3B33") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_97 +-- entity SLICE_65 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_97 is + entity SLICE_65 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_97"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; - - end SLICE_97; - - architecture Structure of SLICE_97 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i13_3_lut: lut40066 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1956_2_lut: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - IS_FSM_i7: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - IS_FSM_i6: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, - M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_98 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_98 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_98"; + InstancePath : string := "SLICE_65"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); @@ -17163,28 +13615,26 @@ tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; - end SLICE_98; + end SLICE_65; - architecture Structure of SLICE_98 is + architecture Structure of SLICE_65 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; @@ -17192,8 +13642,6 @@ signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; @@ -17214,28 +13662,28 @@ component gnd port (PWR0: out Std_logic); end component; - component lut40021 + component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40037 + component lut40066 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1416_2_lut: lut40037 + UFMCLK_0io_RNO_0: lut40006 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - MAin_9_I_0_427_i9_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - IS_FSM_i1: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + PHI2r3_RNITCN41: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); - IS_FSM_i0: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + PHI2r2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs @@ -17243,12 +13691,12 @@ BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; @@ -17257,12 +13705,11 @@ BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, - M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; @@ -17276,8 +13723,6 @@ VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; @@ -17320,24 +13765,6 @@ TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", @@ -17360,13 +13787,16 @@ VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, + 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, + 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, @@ -17400,1298 +13830,6 @@ end Structure; --- entity SLICE_99 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_99 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_99"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; - - end SLICE_99; - - architecture Structure of SLICE_99 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40052 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i8_4_lut: lut40052 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - MAin_9_I_0_427_i8_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CmdUFMSDI_414: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_100 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_100 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_100"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; - - end SLICE_100; - - architecture Structure of SLICE_100 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40052 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - i1979_4_lut: lut40052 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - MAin_9_I_0_427_i7_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CmdUFMCS_412: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - CmdUFMCLK_413: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_negedge, - SetupLow => tsetup_CE_CLK_noedge_negedge, - HoldHigh => thold_CE_CLK_noedge_negedge, - HoldLow => thold_CE_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_101 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_101 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_101"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; - - end SLICE_101; - - architecture Structure of SLICE_101 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - MAin_9_I_0_427_i1_3_lut: lut40021 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - MAin_9_I_0_427_i6_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - Bank_i7: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - Bank_i6: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_102 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_102 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_102"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; - - end SLICE_102; - - architecture Structure of SLICE_102 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - MAin_9_I_0_427_i2_3_lut: lut40021 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - MAin_9_I_0_427_i5_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - Bank_i5: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - Bank_i4: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_103 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity SLICE_103 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_103"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; - - end SLICE_103; - - architecture Structure of SLICE_103 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component vmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40021 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - MAin_9_I_0_427_i3_3_lut: lut40021 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - MAin_9_I_0_427_i4_3_lut: lut40021 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - Bank_i3: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - Bank_i2: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - -- entity lut40067 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -18709,200 +13847,433 @@ architecture Structure of lut40067 is begin INST10: ROM16X1A - generic map (initval => X"FDFD") + generic map (initval => X"3AFA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; --- entity SLICE_104 +-- entity lut40068 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_104 is + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + begin + INST10: ROM16X1A + generic map (initval => X"200F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_104"; + InstancePath : string := "SLICE_66"; + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_0io_RNO: lut40067 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_r_i_a3_1_1_tz: lut40068 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; - end SLICE_104; + end SLICE_67; - architecture Structure of SLICE_104 is + architecture Structure of SLICE_67 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + ADWR_6: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + ADWR_2: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - signal LSR_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; - component vmuxregsre0004 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40034 + component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40067 + component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1417_2_lut: lut40034 + CmdEnable16_3: lut40064 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - i1_2_lut_rep_14_3_lut: lut40067 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - RowA_i7: vmuxregsre0004 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q1_out); + CmdEnable16_5: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_0io_2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - LSR_INVERTERIN: inverter - port map (I=>LSR_dly, Z=>LSR_NOTIN); - RowA_i6: vmuxregsre0004 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, - M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", @@ -18910,47 +14281,17 @@ RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, - RefTransition => '\', + RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", @@ -18969,17 +14310,19 @@ F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; - Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, + 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, + 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, @@ -19001,31 +14344,24 @@ PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; --- entity SLICE_105 +-- entity SLICE_69 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_105 is + entity SLICE_69 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_105"; + InstancePath : string := "SLICE_69"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); @@ -19044,11 +14380,11 @@ C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; - end SLICE_105; + end SLICE_69; - architecture Structure of SLICE_105 is + architecture Structure of SLICE_69 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; @@ -19064,20 +14400,20 @@ component gnd port (PWR0: out Std_logic); end component; - component lut40039 + component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40052 + component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1_2_lut_adj_19: lut40039 + un1_Bank_1_3: lut40056 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); - i5_4_lut: lut40052 + un1_Bank_1: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs @@ -19139,79 +14475,584 @@ end Structure; --- entity SLICE_106 +-- entity lut40069 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity SLICE_106 is + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + begin + INST10: ROM16X1A + generic map (initval => X"4454") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_106"; + InstancePath : string := "SLICE_70"; + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + CmdLEDEN_4_u_i_a2: lut40069 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + Cmdn8MEGEN_4_u_i_o2_0: lut40070 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + begin + INST10: ROM16X1A + generic map (initval => X"AABF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE; + + end SLICE_71; + + architecture Structure of SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_0: lut40071 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_0io_RNO: lut40072 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + UFMSDI_ens2_i_o2_0_3: lut40073 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + InitReady3_0_a2_5: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); - ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; - end SLICE_106; + end SLICE_73; - architecture Structure of SLICE_106 is + architecture Structure of SLICE_73 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal GNDI: Std_logic; signal VCCI: Std_logic; + signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; @@ -19223,93 +15064,66 @@ component gnd port (PWR0: out Std_logic); end component; - component lut40034 + component lut40038 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; - component lut40039 + component lut40058 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin - i1_2_lut_rep_33: lut40039 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - i1930_2_lut: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - IS_FSM_i5: vmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); + CmdEnable16_4: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdEnable17_5: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); - IS_FSM_i4: vmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", @@ -19328,6 +15142,2956 @@ TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + begin + INST10: ROM16X1A + generic map (initval => X"040C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + XOR8MEG_3_u_1: lut40074 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + CmdEnable17_4: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CBR: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40076 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40076 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE; + + end lut40076; + + architecture Structure of lut40076 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40077 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40077 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE; + + end lut40077; + + architecture Structure of lut40077 is + begin + INST10: ROM16X1A + generic map (initval => X"ACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40076 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQML: lut40076 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_9: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40078 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40078 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE; + + end lut40078; + + architecture Structure of lut40078 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40079 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40079 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE; + + end lut40079; + + architecture Structure of lut40079 is + begin + INST10: ROM16X1A + generic map (initval => X"70CF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40078 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40079 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRWE_0io_RNO_1: lut40078 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + RCKEEN_8_u_1_0: lut40079 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40080 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40080 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE; + + end lut40080; + + architecture Structure of lut40080 is + begin + INST10: ROM16X1A + generic map (initval => X"5400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40081 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40081 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE; + + end lut40081; + + architecture Structure of lut40081 is + begin + INST10: ROM16X1A + generic map (initval => X"1111") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40080 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40081 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRRAS_5_u_i_0: lut40080 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40082 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40082 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE; + + end lut40082; + + architecture Structure of lut40082 is + begin + INST10: ROM16X1A + generic map (initval => X"2C2C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40082 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_14_i_a2_0_1: lut40035 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + UFMSDI_ens2_i_o2: lut40082 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RDQMH: lut40024 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_8: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_7: lut40077 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_0: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_6: lut40077 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_1: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_5: lut40077 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_2: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40077 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un9_RA_4: lut40077 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + un9_RA_3: lut40077 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40083 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40083 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE; + + end lut40083; + + architecture Structure of lut40083 is + begin + INST10: ROM16X1A + generic map (initval => X"C048") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40083 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RBAd_0: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11d: lut40083 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + un1_FS_13_i_a2_6: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + InitReady3_0_a2_3: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: OBW + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'X'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RD_pad_0: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD0_out) + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RD0_zd := RD0_out; + + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE; + + end mfflsre; + + architecture Structure of mfflsre is + begin + INST01: FD1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity RD_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE; + + end RD_0_MGIOL; + + architecture Structure of RD_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0084 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0084 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0084 : ENTITY IS TRUE; + + end xo2iobuf0084; + + architecture Structure of xo2iobuf0084 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0085 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0085 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0085 : ENTITY IS TRUE; + + end xo2iobuf0085; + + architecture Structure of xo2iobuf0085 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0085 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0085 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity smuxlregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity smuxlregsre is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE; + + end smuxlregsre; + + architecture Structure of smuxlregsre is + begin + INST01: IFS1P3DX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q); + end Structure; + +-- entity PHI2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE; + + end PHI2_MGIOL; + + architecture Structure of PHI2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + PHI2r_0io: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0086 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0086 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0086 : ENTITY IS TRUE; + + end xo2iobuf0086; + + architecture Structure of xo2iobuf0086 is + begin + INST1: IB + port map (I=>PAD, O=>Z); + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>UFMSDIS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01 ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDI_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDI_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDI_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDI_MGIOL : ENTITY IS TRUE; + + end UFMSDI_MGIOL; + + architecture Structure of UFMSDI_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + UFMSDI_r0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>UFMCLKS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01 ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLK_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLK_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLK_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; + CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLK_MGIOL : ENTITY IS TRUE; + + end UFMCLK_MGIOL; + + architecture Structure of UFMCLK_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + UFMCLK_0io: mfflsre + port map (D0=>OPOS_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CE_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", @@ -19361,70 +18125,1457 @@ END IF; - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, + GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; --- entity xo2iobuf +-- entity nUFMCSB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity xo2iobuf is - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; - ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); - end xo2iobuf; + port (IOLDO: in Std_logic; nUFMCSS: out Std_logic); - architecture Structure of xo2iobuf is + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; begin - INST1: IBPD - port map (I=>PADI, O=>Z); - INST2: OBZPD - port map (I=>I, T=>T, O=>PAD); + nUFMCS_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>nUFMCSS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01 ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mfflsre0087 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0087 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0087 : ENTITY IS TRUE; + + end mfflsre0087; + + architecture Structure of mfflsre0087 is + begin + INST01: FD1P3BX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity nUFMCS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nUFMCS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCS_MGIOL : ENTITY IS TRUE; + + end nUFMCS_MGIOL; + + architecture Structure of nUFMCS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0087 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nUFMCS_r1: mfflsre0087 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RDQMLS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RDQMHS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>nRCASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE; + + end nRCAS_MGIOL; + + architecture Structure of nRCAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0087 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCAS_0io: mfflsre0087 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>nRRASS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRAS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRAS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRAS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE; + + end nRRAS_MGIOL; + + architecture Structure of nRRAS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0087 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRRAS_0io: mfflsre0087 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>nRWES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWE_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWE_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWE_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE; + + end nRWE_MGIOL; + + architecture Structure of nRWE_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0087 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRWE_0io: mfflsre0087 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>RCKES_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKE_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKE_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKE_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKE_MGIOL : ENTITY IS TRUE; + + end RCKE_MGIOL; + + architecture Structure of RCKE_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RCKE_r2: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>nRCSS_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCS_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCS_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCS_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE; + + end nRCS_MGIOL; + + architecture Structure of nRCS_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre0087 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + nRCS_0io: mfflsre0087 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + end Structure; -- entity RD_7_B @@ -19441,19 +19592,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_7_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD7 : VitalDelayType := 0 ns; - tpw_RD7_posedge : VitalDelayType := 0 ns; - tpw_RD7_negedge : VitalDelayType := 0 ns; - tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD7: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; @@ -19462,49 +19606,170 @@ architecture Structure of RD_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD7_ipd : std_logic := 'X'; - signal RD7_out : std_logic := 'Z'; + signal RD7_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_7_713: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, - PADI=>RD7_ipd); + RD_pad_7: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD7_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD7_ipd, RD7, tipd_RD7); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD7_out) VARIABLE RD7_zd : std_logic := 'X'; VARIABLE RD7_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD7_RD7 : x01 := '0'; - VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD7_zd := RD7_out; + + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_7_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE; + + end RD_7_MGIOL; + + architecture Structure of RD_7_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_7: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD7_ipd, - TestSignalName => "RD7", - Period => tperiod_RD7, - PulseWidthHigh => tpw_RD7_posedge, - PulseWidthLow => tpw_RD7_negedge, - PeriodData => periodcheckinfo_RD7, - Violation => tviol_RD7_RD7, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -19512,26 +19777,15 @@ END IF; - PADDI_zd := PADDI_out; - RD7_zd := RD7_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD7_ipd'last_event, - PathDelay => tpd_RD7_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD7, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD7, - PathCondition => TRUE)), - GlitchData => RD7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -19551,19 +19805,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_6_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD6 : VitalDelayType := 0 ns; - tpw_RD6_posedge : VitalDelayType := 0 ns; - tpw_RD6_negedge : VitalDelayType := 0 ns; - tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD6: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; @@ -19572,49 +19819,170 @@ architecture Structure of RD_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD6_ipd : std_logic := 'X'; - signal RD6_out : std_logic := 'Z'; + signal RD6_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_6_714: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, - PADI=>RD6_ipd); + RD_pad_6: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD6_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD6_ipd, RD6, tipd_RD6); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD6_out) VARIABLE RD6_zd : std_logic := 'X'; VARIABLE RD6_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD6_RD6 : x01 := '0'; - VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD6_zd := RD6_out; + + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE; + + end RD_6_MGIOL; + + architecture Structure of RD_6_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_6: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD6_ipd, - TestSignalName => "RD6", - Period => tperiod_RD6, - PulseWidthHigh => tpw_RD6_posedge, - PulseWidthLow => tpw_RD6_negedge, - PeriodData => periodcheckinfo_RD6, - Violation => tviol_RD6_RD6, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -19622,26 +19990,15 @@ END IF; - PADDI_zd := PADDI_out; - RD6_zd := RD6_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD6_ipd'last_event, - PathDelay => tpd_RD6_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD6, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD6, - PathCondition => TRUE)), - GlitchData => RD6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -19661,19 +20018,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_5_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD5 : VitalDelayType := 0 ns; - tpw_RD5_posedge : VitalDelayType := 0 ns; - tpw_RD5_negedge : VitalDelayType := 0 ns; - tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD5: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; @@ -19682,49 +20032,170 @@ architecture Structure of RD_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD5_ipd : std_logic := 'X'; - signal RD5_out : std_logic := 'Z'; + signal RD5_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_5_715: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, - PADI=>RD5_ipd); + RD_pad_5: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD5_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD5_ipd, RD5, tipd_RD5); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD5_out) VARIABLE RD5_zd : std_logic := 'X'; VARIABLE RD5_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD5_RD5 : x01 := '0'; - VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD5_zd := RD5_out; + + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE; + + end RD_5_MGIOL; + + architecture Structure of RD_5_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_5: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD5_ipd, - TestSignalName => "RD5", - Period => tperiod_RD5, - PulseWidthHigh => tpw_RD5_posedge, - PulseWidthLow => tpw_RD5_negedge, - PeriodData => periodcheckinfo_RD5, - Violation => tviol_RD5_RD5, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -19732,26 +20203,15 @@ END IF; - PADDI_zd := PADDI_out; - RD5_zd := RD5_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD5_ipd'last_event, - PathDelay => tpd_RD5_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD5, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD5, - PathCondition => TRUE)), - GlitchData => RD5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -19771,19 +20231,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_4_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD4 : VitalDelayType := 0 ns; - tpw_RD4_posedge : VitalDelayType := 0 ns; - tpw_RD4_negedge : VitalDelayType := 0 ns; - tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD4: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; @@ -19792,49 +20245,170 @@ architecture Structure of RD_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD4_ipd : std_logic := 'X'; - signal RD4_out : std_logic := 'Z'; + signal RD4_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_4_716: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, - PADI=>RD4_ipd); + RD_pad_4: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD4_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD4_ipd, RD4, tipd_RD4); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD4_out) VARIABLE RD4_zd : std_logic := 'X'; VARIABLE RD4_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD4_RD4 : x01 := '0'; - VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD4_zd := RD4_out; + + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE; + + end RD_4_MGIOL; + + architecture Structure of RD_4_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_4: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD4_ipd, - TestSignalName => "RD4", - Period => tperiod_RD4, - PulseWidthHigh => tpw_RD4_posedge, - PulseWidthLow => tpw_RD4_negedge, - PeriodData => periodcheckinfo_RD4, - Violation => tviol_RD4_RD4, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -19842,26 +20416,15 @@ END IF; - PADDI_zd := PADDI_out; - RD4_zd := RD4_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD4_ipd'last_event, - PathDelay => tpd_RD4_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD4, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD4, - PathCondition => TRUE)), - GlitchData => RD4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -19881,19 +20444,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_3_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD3 : VitalDelayType := 0 ns; - tpw_RD3_posedge : VitalDelayType := 0 ns; - tpw_RD3_negedge : VitalDelayType := 0 ns; - tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD3: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; @@ -19902,49 +20458,170 @@ architecture Structure of RD_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD3_ipd : std_logic := 'X'; - signal RD3_out : std_logic := 'Z'; + signal RD3_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_3_717: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, - PADI=>RD3_ipd); + RD_pad_3: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD3_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD3_ipd, RD3, tipd_RD3); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD3_out) VARIABLE RD3_zd : std_logic := 'X'; VARIABLE RD3_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD3_RD3 : x01 := '0'; - VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD3_zd := RD3_out; + + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE; + + end RD_3_MGIOL; + + architecture Structure of RD_3_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_3: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD3_ipd, - TestSignalName => "RD3", - Period => tperiod_RD3, - PulseWidthHigh => tpw_RD3_posedge, - PulseWidthLow => tpw_RD3_negedge, - PeriodData => periodcheckinfo_RD3, - Violation => tviol_RD3_RD3, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -19952,26 +20629,15 @@ END IF; - PADDI_zd := PADDI_out; - RD3_zd := RD3_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD3_ipd'last_event, - PathDelay => tpd_RD3_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD3, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD3, - PathCondition => TRUE)), - GlitchData => RD3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -19991,19 +20657,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_2_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD2 : VitalDelayType := 0 ns; - tpw_RD2_posedge : VitalDelayType := 0 ns; - tpw_RD2_negedge : VitalDelayType := 0 ns; - tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD2: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; @@ -20012,49 +20671,170 @@ architecture Structure of RD_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD2_ipd : std_logic := 'X'; - signal RD2_out : std_logic := 'Z'; + signal RD2_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_2_718: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, - PADI=>RD2_ipd); + RD_pad_2: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD2_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD2_ipd, RD2, tipd_RD2); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD2_out) VARIABLE RD2_zd : std_logic := 'X'; VARIABLE RD2_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD2_RD2 : x01 := '0'; - VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + + END IF; + + RD2_zd := RD2_out; + + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE; + + end RD_2_MGIOL; + + architecture Structure of RD_2_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + WRD_0io_2: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD2_ipd, - TestSignalName => "RD2", - Period => tperiod_RD2, - PulseWidthHigh => tpw_RD2_posedge, - PulseWidthLow => tpw_RD2_negedge, - PeriodData => periodcheckinfo_RD2, - Violation => tviol_RD2_RD2, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -20062,26 +20842,15 @@ END IF; - PADDI_zd := PADDI_out; - RD2_zd := RD2_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD2_ipd'last_event, - PathDelay => tpd_RD2_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD2, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD2, - PathCondition => TRUE)), - GlitchData => RD2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -20101,19 +20870,12 @@ MsgOn : boolean := TRUE; InstancePath : string := "RD_1_B"; + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD1 : VitalDelayType := 0 ns; - tpw_RD1_posedge : VitalDelayType := 0 ns; - tpw_RD1_negedge : VitalDelayType := 0 ns; - tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tpd_IOLDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD1: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; @@ -20122,73 +20884,44 @@ architecture Structure of RD_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD1_ipd : std_logic := 'X'; - signal RD1_out : std_logic := 'Z'; + signal RD1_out : std_logic := 'X'; component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin - Dout_pad_1_719: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, - PADI=>RD1_ipd); + RD_pad_1: xo2iobuf + port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD1_ipd, RD1, tipd_RD1); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD1_out) VARIABLE RD1_zd : std_logic := 'X'; VARIABLE RD1_GlitchData : VitalGlitchDataType; - VARIABLE tviol_RD1_RD1 : x01 := '0'; - VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => RD1_ipd, - TestSignalName => "RD1", - Period => tperiod_RD1, - PulseWidthHigh => tpw_RD1_posedge, - PulseWidthLow => tpw_RD1_negedge, - PeriodData => periodcheckinfo_RD1, - Violation => tviol_RD1_RD1, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); END IF; - PADDI_zd := PADDI_out; RD1_zd := RD1_out; - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD1_ipd'last_event, - PathDelay => tpd_RD1_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD1, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RD1, PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD1, + 1 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, PathCondition => TRUE)), GlitchData => RD1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -20197,84 +20930,124 @@ end Structure; --- entity RD_0_B +-- entity RD_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity RD_0_B is + entity RD_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "RD_0_B"; + InstancePath : string := "RD_1_MGIOL"; - tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); - tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RD0 : VitalDelayType := 0 ns; - tpw_RD0_posedge : VitalDelayType := 0 ns; - tpw_RD0_negedge : VitalDelayType := 0 ns; - tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD0: inout Std_logic); + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); - ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE; - end RD_0_B; + end RD_1_MGIOL; - architecture Structure of RD_0_B is + architecture Structure of RD_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal PADDT_ipd : std_logic := 'X'; - signal PADDO_ipd : std_logic := 'X'; - signal RD0_ipd : std_logic := 'X'; - signal RD0_out : std_logic := 'Z'; + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; - component xo2iobuf - port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; - PAD: out Std_logic; PADI: in Std_logic); + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - Dout_pad_0_720: xo2iobuf - port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, - PADI=>RD0_ipd); + WRD_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE RD0_zd : std_logic := 'X'; - VARIABLE RD0_GlitchData : VitalGlitchDataType; + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; - VARIABLE tviol_RD0_RD0 : x01 := '0'; - VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); VitalPeriodPulseCheck ( - TestSignal => RD0_ipd, - TestSignalName => "RD0", - Period => tperiod_RD0, - PulseWidthHigh => tpw_RD0_posedge, - PulseWidthLow => tpw_RD0_negedge, - PeriodData => periodcheckinfo_RD0, - Violation => tviol_RD0_RD0, + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -20282,848 +21055,15 @@ END IF; - PADDI_zd := PADDI_out; - RD0_zd := RD0_out; + IOLDO_zd := IOLDO_out; VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RD0_ipd'last_event, - PathDelay => tpd_RD0_PADDI, + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01Z ( - OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, - Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, - PathDelay => tpd_PADDT_RD0, - PathCondition => TRUE), - 1 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RD0, - PathCondition => TRUE)), - GlitchData => RD0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity xo2iobuf0068 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity xo2iobuf0068 is - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - - ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE; - - end xo2iobuf0068; - - architecture Structure of xo2iobuf0068 is - begin - INST5: OBZPD - port map (I=>I, T=>T, O=>PAD); - end Structure; - --- entity Dout_7_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; - - end Dout_7_B; - - architecture Structure of Dout_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout7_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_7: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) - VARIABLE Dout7_zd : std_logic := 'X'; - VARIABLE Dout7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout7_zd := Dout7_out; - - VitalPathDelay01 ( - OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout7, - PathCondition => TRUE)), - GlitchData => Dout7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_6_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; - - end Dout_6_B; - - architecture Structure of Dout_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout6_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_6: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) - VARIABLE Dout6_zd : std_logic := 'X'; - VARIABLE Dout6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout6_zd := Dout6_out; - - VitalPathDelay01 ( - OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout6, - PathCondition => TRUE)), - GlitchData => Dout6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_5_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; - - end Dout_5_B; - - architecture Structure of Dout_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout5_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_5: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) - VARIABLE Dout5_zd : std_logic := 'X'; - VARIABLE Dout5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout5_zd := Dout5_out; - - VitalPathDelay01 ( - OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout5, - PathCondition => TRUE)), - GlitchData => Dout5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_4_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; - - end Dout_4_B; - - architecture Structure of Dout_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout4_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_4: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) - VARIABLE Dout4_zd : std_logic := 'X'; - VARIABLE Dout4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout4_zd := Dout4_out; - - VitalPathDelay01 ( - OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout4, - PathCondition => TRUE)), - GlitchData => Dout4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_3_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; - - end Dout_3_B; - - architecture Structure of Dout_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout3_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_3: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) - VARIABLE Dout3_zd : std_logic := 'X'; - VARIABLE Dout3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout3_zd := Dout3_out; - - VitalPathDelay01 ( - OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout3, - PathCondition => TRUE)), - GlitchData => Dout3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_2_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; - - end Dout_2_B; - - architecture Structure of Dout_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout2_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_2: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) - VARIABLE Dout2_zd : std_logic := 'X'; - VARIABLE Dout2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout2_zd := Dout2_out; - - VitalPathDelay01 ( - OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout2, - PathCondition => TRUE)), - GlitchData => Dout2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_1_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; - - end Dout_1_B; - - architecture Structure of Dout_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_1: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) - VARIABLE Dout1_zd : std_logic := 'X'; - VARIABLE Dout1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout1_zd := Dout1_out; - - VitalPathDelay01 ( - OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout1, - PathCondition => TRUE)), - GlitchData => Dout1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity Dout_0_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity Dout_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "Dout_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; Dout0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; - - end Dout_0_B; - - architecture Structure of Dout_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal Dout0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - Dout_pad_0: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) - VARIABLE Dout0_zd : std_logic := 'X'; - VARIABLE Dout0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - Dout0_zd := Dout0_out; - - VitalPathDelay01 ( - OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_Dout0, - PathCondition => TRUE)), - GlitchData => Dout0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LEDB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity LEDB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LEDB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; LEDS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; - - end LEDB; - - architecture Structure of LEDB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal LEDS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - LED_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) - VARIABLE LEDS_zd : std_logic := 'X'; - VARIABLE LEDS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - LEDS_zd := LEDS_out; - - VitalPathDelay01 ( - OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_LEDS, - PathCondition => TRUE)), - GlitchData => LEDS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity RBA_1_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity RBA_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "RBA_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; RBA1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; - - end RBA_1_B; - - architecture Structure of RBA_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal RBA1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - RBA_pad_1: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) - VARIABLE RBA1_zd : std_logic := 'X'; - VARIABLE RBA1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - RBA1_zd := RBA1_out; - - VitalPathDelay01 ( - OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RBA1, - PathCondition => TRUE)), - GlitchData => RBA1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity RBA_0_B - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity RBA_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "RBA_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; RBA0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; - - end RBA_0_B; - - architecture Structure of RBA_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal RBA0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - RBA_pad_0: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) - VARIABLE RBA0_zd : std_logic := 'X'; - VARIABLE RBA0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - RBA0_zd := RBA0_out; - - VitalPathDelay01 ( - OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RBA0, - PathCondition => TRUE)), - GlitchData => RBA0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; @@ -21143,10 +21083,10 @@ MsgOn : boolean := TRUE; InstancePath : string := "RA_11_B"; - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); - port (PADDO: in Std_logic; RA11: out Std_logic); + port (IOLDO: in Std_logic; RA11: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; @@ -21155,29 +21095,23 @@ architecture Structure of RA_11_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDO_ipd : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal RA11_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_11: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_11: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>RA11_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; - VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VitalBehavior : PROCESS (IOLDO_ipd, RA11_out) VARIABLE RA11_zd : std_logic := 'X'; VARIABLE RA11_GlitchData : VitalGlitchDataType; @@ -21192,8 +21126,8 @@ VitalPathDelay01 ( OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RA11, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA11, PathCondition => TRUE)), GlitchData => RA11_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -21202,6 +21136,139 @@ end Structure; +-- entity RA_11_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE; + + end RA_11_MGIOL; + + architecture Structure of RA_11_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA11_0io: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity RA_10_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -21216,10 +21283,10 @@ MsgOn : boolean := TRUE; InstancePath : string := "RA_10_B"; - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); - port (PADDO: in Std_logic; RA10: out Std_logic); + port (IOLDO: in Std_logic; RA10: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; @@ -21228,29 +21295,23 @@ architecture Structure of RA_10_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDO_ipd : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; signal RA10_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_10: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_10: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>RA10_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; - VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VitalBehavior : PROCESS (IOLDO_ipd, RA10_out) VARIABLE RA10_zd : std_logic := 'X'; VARIABLE RA10_GlitchData : VitalGlitchDataType; @@ -21265,8 +21326,8 @@ VitalPathDelay01 ( OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RA10, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RA10, PathCondition => TRUE)), GlitchData => RA10_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -21275,6 +21336,184 @@ end Structure; +-- entity mfflsre0088 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity mfflsre0088 is + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mfflsre0088 : ENTITY IS TRUE; + + end mfflsre0088; + + architecture Structure of mfflsre0088 is + begin + INST01: FD1P3JX + generic map (GSR => "DISABLED") + port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); + end Structure; + +-- entity RA_10_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_MGIOL"; + + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE; + + end RA_10_MGIOL; + + architecture Structure of RA_10_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component mfflsre0088 + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + RA10_0io: mfflsre0088 + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, + Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_posedge, + SetupLow => tsetup_OPOS_CLK_noedge_posedge, + HoldHigh => thold_OPOS_CLK_noedge_posedge, + HoldLow => thold_OPOS_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity RA_9_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -21304,18 +21543,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA9_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_9: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_9: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA9_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21377,18 +21610,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA8_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_8: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_8: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA8_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21450,18 +21677,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA7_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_7: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_7: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA7_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21523,18 +21744,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA6_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_6: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_6: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA6_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21596,18 +21811,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA5_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_5: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_5: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA5_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21669,18 +21878,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA4_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_4: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_4: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA4_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21742,18 +21945,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA3_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_3: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_3: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA3_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21815,18 +22012,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA2_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_2: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_2: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA2_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21888,18 +22079,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA1_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_1: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_1: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA1_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -21961,18 +22146,12 @@ signal PADDO_ipd : std_logic := 'X'; signal RA0_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - RA_pad_0: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RA_pad_0: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>RA0_out); -- INPUT PATH DELAYs WireDelay : BLOCK @@ -22005,57 +22184,51 @@ end Structure; --- entity nRCSB +-- entity RBA_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity nRCSB is + entity RBA_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "nRCSB"; + InstancePath : string := "RBA_1_B"; - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); - port (PADDO: in Std_logic; nRCSS: out Std_logic); + port (IOLDO: in Std_logic; RBA1: out Std_logic); - ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; - end nRCSB; + end RBA_1_B; - architecture Structure of nRCSB is + architecture Structure of RBA_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDO_ipd : std_logic := 'X'; - signal nRCSS_out : std_logic := 'X'; + signal IOLDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - nRCS_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); + RBA_pad_1: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>RBA1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; - VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) - VARIABLE nRCSS_zd : std_logic := 'X'; - VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; BEGIN @@ -22064,71 +22237,204 @@ END IF; - nRCSS_zd := nRCSS_out; + RBA1_zd := RBA1_out; VitalPathDelay01 ( - OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_nRCSS, + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA1, PathCondition => TRUE)), - GlitchData => nRCSS_GlitchData, + GlitchData => RBA1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; --- entity RCKEB +-- entity RBA_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity RCKEB is + entity RBA_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "RCKEB"; + InstancePath : string := "RBA_1_MGIOL"; - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (PADDO: in Std_logic; RCKES: out Std_logic); + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); - ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE; - end RCKEB; + end RBA_1_MGIOL; - architecture Structure of RCKEB is + architecture Structure of RBA_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDO_ipd : std_logic := 'X'; - signal RCKES_out : std_logic := 'X'; + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; component gnd port (PWR0: out Std_logic); end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - RCKE_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + RBA_0io_1: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) - VARIABLE RCKES_zd : std_logic := 'X'; - VARIABLE RCKES_GlitchData : VitalGlitchDataType; + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_IOLDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (IOLDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal IOLDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0084 + port map (I=>IOLDO_ipd, PAD=>RBA0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; BEGIN @@ -22137,71 +22443,223 @@ END IF; - RCKES_zd := RCKES_out; + RBA0_zd := RBA0_out; VitalPathDelay01 ( - OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RCKES, + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, + PathDelay => tpd_IOLDO_RBA0, PathCondition => TRUE)), - GlitchData => RCKES_GlitchData, + GlitchData => RBA0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; --- entity nRWEB +-- entity RBA_0_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity nRWEB is + entity RBA_0_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "nRWEB"; + InstancePath : string := "RBA_0_MGIOL"; - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_OPOS_CLK : VitalDelayType := 0 ns; + tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (PADDO: in Std_logic; nRWES: out Std_logic); + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); - ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE; - end nRWEB; + end RBA_0_MGIOL; - architecture Structure of nRWEB is + architecture Structure of RBA_0_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDO_ipd : std_logic := 'X'; - signal nRWES_out : std_logic := 'X'; + signal IOLDO_out : std_logic := 'X'; + signal OPOS_ipd : std_logic := 'X'; + signal OPOS_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; component gnd port (PWR0: out Std_logic); end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component mfflsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - nRWE_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + RBA_0io_0: mfflsre + port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) + VARIABLE IOLDO_zd : std_logic := 'X'; + VARIABLE IOLDO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_OPOS_CLK : x01 := '0'; + VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => OPOS_dly, + TestSignalName => "OPOS", + TestDelay => tisd_OPOS_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_OPOS_CLK_noedge_negedge, + SetupLow => tsetup_OPOS_CLK_noedge_negedge, + HoldHigh => thold_OPOS_CLK_noedge_negedge, + HoldLow => thold_OPOS_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => OPOS_CLK_TimingDatash, + Violation => tviol_OPOS_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + IOLDO_zd := IOLDO_out; + + VitalPathDelay01 ( + OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_IOLDO, + PathCondition => TRUE)), + GlitchData => IOLDO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0089 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0089 is + port (I: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0089 : ENTITY IS TRUE; + + end xo2iobuf0089; + + architecture Structure of xo2iobuf0089 is + begin + INST5: OB + port map (I=>I, O=>PAD); + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + component xo2iobuf0089 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0089 + port map (I=>PADDO_ipd, PAD=>LEDS_out); + -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; - VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) - VARIABLE nRWES_zd : std_logic := 'X'; - VARIABLE nRWES_GlitchData : VitalGlitchDataType; + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; BEGIN @@ -22210,613 +22668,102 @@ END IF; - nRWES_zd := nRWES_out; + LEDS_zd := LEDS_out; VitalPathDelay01 ( - OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_nRWES, + PathDelay => tpd_PADDO_LEDS, PathCondition => TRUE)), - GlitchData => nRWES_GlitchData, + GlitchData => LEDS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; --- entity nRRASB +-- entity xo2iobuf0090 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity nRRASB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "nRRASB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; nRRASS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; - - end nRRASB; - - architecture Structure of nRRASB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal nRRASS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - nRRAS_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) - VARIABLE nRRASS_zd : std_logic := 'X'; - VARIABLE nRRASS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - nRRASS_zd := nRRASS_out; - - VitalPathDelay01 ( - OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_nRRASS, - PathCondition => TRUE)), - GlitchData => nRRASS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity nRCASB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity nRCASB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "nRCASB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; nRCASS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; - - end nRCASB; - - architecture Structure of nRCASB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal nRCASS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - nRCAS_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) - VARIABLE nRCASS_zd : std_logic := 'X'; - VARIABLE nRCASS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - nRCASS_zd := nRCASS_out; - - VitalPathDelay01 ( - OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_nRCASS, - PathCondition => TRUE)), - GlitchData => nRCASS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity RDQMHB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity RDQMHB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "RDQMHB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; RDQMHS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; - - end RDQMHB; - - architecture Structure of RDQMHB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal RDQMHS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - RDQMH_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) - VARIABLE RDQMHS_zd : std_logic := 'X'; - VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - RDQMHS_zd := RDQMHS_out; - - VitalPathDelay01 ( - OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RDQMHS, - PathCondition => TRUE)), - GlitchData => RDQMHS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity RDQMLB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity RDQMLB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "RDQMLB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; RDQMLS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; - - end RDQMLB; - - architecture Structure of RDQMLB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal RDQMLS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - RDQML_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) - VARIABLE RDQMLS_zd : std_logic := 'X'; - VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - RDQMLS_zd := RDQMLS_out; - - VitalPathDelay01 ( - OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_RDQMLS, - PathCondition => TRUE)), - GlitchData => RDQMLS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity nUFMCSB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity nUFMCSB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "nUFMCSB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; nUFMCSS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; - - end nUFMCSB; - - architecture Structure of nUFMCSB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal nUFMCSS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - nUFMCS_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) - VARIABLE nUFMCSS_zd : std_logic := 'X'; - VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - nUFMCSS_zd := nUFMCSS_out; - - VitalPathDelay01 ( - OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_nUFMCSS, - PathCondition => TRUE)), - GlitchData => nUFMCSS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity UFMCLKB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity UFMCLKB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "UFMCLKB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; UFMCLKS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; - - end UFMCLKB; - - architecture Structure of UFMCLKB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal UFMCLKS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - UFMCLK_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) - VARIABLE UFMCLKS_zd : std_logic := 'X'; - VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - UFMCLKS_zd := UFMCLKS_out; - - VitalPathDelay01 ( - OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_UFMCLKS, - PathCondition => TRUE)), - GlitchData => UFMCLKS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity UFMSDIB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity UFMSDIB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "UFMSDIB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; UFMSDIS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; - - end UFMSDIB; - - architecture Structure of UFMSDIB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal UFMSDIS_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component xo2iobuf0068 - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - UFMSDI_pad: xo2iobuf0068 - port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) - VARIABLE UFMSDIS_zd : std_logic := 'X'; - VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - UFMSDIS_zd := UFMSDIS_out; - - VitalPathDelay01 ( - OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_UFMSDIS, - PathCondition => TRUE)), - GlitchData => UFMSDIS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity xo2iobuf0069 - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity xo2iobuf0069 is + entity xo2iobuf0090 is port (Z: out Std_logic; PAD: in Std_logic); - ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF xo2iobuf0090 : ENTITY IS TRUE; - end xo2iobuf0069; + end xo2iobuf0090; - architecture Structure of xo2iobuf0069 is + architecture Structure of xo2iobuf0090 is begin - INST1: IBPD + INST1: IBPU port map (I=>PAD, O=>Z); end Structure; --- entity PHI2B +-- entity nFWEB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity PHI2B is + entity nFWEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "PHI2B"; + InstancePath : string := "nFWEB"; - tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); - tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_PHI2S : VitalDelayType := 0 ns; - tpw_PHI2S_posedge : VitalDelayType := 0 ns; - tpw_PHI2S_negedge : VitalDelayType := 0 ns); + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; PHI2S: in Std_logic); + port (PADDI: out Std_logic; nFWES: in Std_logic); - ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; - end PHI2B; + end nFWEB; - architecture Structure of PHI2B is + architecture Structure of nFWEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal PHI2S_ipd : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - PHI2_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + nFWE_pad: xo2iobuf0090 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; - VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => PHI2S_ipd, - TestSignalName => "PHI2S", - Period => tperiod_PHI2S, - PulseWidthHigh => tpw_PHI2S_posedge, - PulseWidthLow => tpw_PHI2S_negedge, - PeriodData => periodcheckinfo_PHI2S, - Violation => tviol_PHI2S_PHI2S, + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -22828,8 +22775,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, - PathDelay => tpd_PHI2S_PADDI, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -22838,69 +22785,69 @@ end Structure; --- entity MAin_9_B +-- entity nCRASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_9_B is + entity nCRASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_9_B"; + InstancePath : string := "nCRASB"; - tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin9 : VitalDelayType := 0 ns; - tpw_MAin9_posedge : VitalDelayType := 0 ns; - tpw_MAin9_negedge : VitalDelayType := 0 ns); + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin9: in Std_logic); + port (PADDI: out Std_logic; nCRASS: in Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; - end MAin_9_B; + end nCRASB; - architecture Structure of MAin_9_B is + architecture Structure of nCRASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal MAin9_ipd : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - MAin_pad_9: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin9_ipd); + nCRAS_pad: xo2iobuf0090 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin9_MAin9 : x01 := '0'; - VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin9_ipd, - TestSignalName => "MAin9", - Period => tperiod_MAin9, - PulseWidthHigh => tpw_MAin9_posedge, - PulseWidthLow => tpw_MAin9_negedge, - PeriodData => periodcheckinfo_MAin9, - Violation => tviol_MAin9_MAin9, + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -22912,8 +22859,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, - PathDelay => tpd_MAin9_PADDI, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -22922,69 +22869,69 @@ end Structure; --- entity MAin_8_B +-- entity nCCASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_8_B is + entity nCCASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_8_B"; + InstancePath : string := "nCCASB"; - tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin8 : VitalDelayType := 0 ns; - tpw_MAin8_posedge : VitalDelayType := 0 ns; - tpw_MAin8_negedge : VitalDelayType := 0 ns); + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin8: in Std_logic); + port (PADDI: out Std_logic; nCCASS: in Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; - end MAin_8_B; + end nCCASB; - architecture Structure of MAin_8_B is + architecture Structure of nCCASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal MAin8_ipd : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - MAin_pad_8: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin8_ipd); + nCCAS_pad: xo2iobuf0090 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin8_MAin8 : x01 := '0'; - VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin8_ipd, - TestSignalName => "MAin8", - Period => tperiod_MAin8, - PulseWidthHigh => tpw_MAin8_posedge, - PulseWidthLow => tpw_MAin8_negedge, - PeriodData => periodcheckinfo_MAin8, - Violation => tviol_MAin8_MAin8, + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -22996,8 +22943,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, - PathDelay => tpd_MAin8_PADDI, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23006,69 +22953,538 @@ end Structure; --- entity MAin_7_B +-- entity Dout_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_7_B is + entity Dout_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_7_B"; + InstancePath : string := "Dout_7_B"; - tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin7 : VitalDelayType := 0 ns; - tpw_MAin7_posedge : VitalDelayType := 0 ns; - tpw_MAin7_negedge : VitalDelayType := 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); - port (PADDI: out Std_logic; MAin7: in Std_logic); + port (PADDO: in Std_logic; Dout7: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; - end MAin_7_B; + end Dout_7_B; - architecture Structure of MAin_7_B is + architecture Structure of Dout_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin7_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); end component; begin - MAin_pad_7: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin7_ipd); + Dout_pad_7: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout7_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout6_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout5_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout4_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout3_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout2_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + component xo2iobuf0084 + port (I: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0084 + port map (I=>PADDO_ipd, PAD=>Dout1_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin7_MAin7 : x01 := '0'; - VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin7_ipd, - TestSignalName => "MAin7", - Period => tperiod_MAin7, - PulseWidthHigh => tpw_MAin7_posedge, - PulseWidthLow => tpw_MAin7_negedge, - PeriodData => periodcheckinfo_MAin7, - Violation => tviol_MAin7_MAin7, + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23080,8 +23496,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, - PathDelay => tpd_MAin7_PADDI, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23090,69 +23506,202 @@ end Structure; --- entity MAin_6_B +-- entity Din_7_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_6_B is + entity Din_7_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_6_B"; + InstancePath : string := "Din_7_MGIOL"; - tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin6 : VitalDelayType := 0 ns; - tpw_MAin6_posedge : VitalDelayType := 0 ns; - tpw_MAin6_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin6: in Std_logic); + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE; - end MAin_6_B; + end Din_7_MGIOL; - architecture Structure of MAin_6_B is + architecture Structure of Din_7_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin6_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_6: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin6_ipd); + Bank_0io_7: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin6_MAin6 : x01 := '0'; - VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin6_ipd, - TestSignalName => "MAin6", - Period => tperiod_MAin6, - PulseWidthHigh => tpw_MAin6_posedge, - PulseWidthLow => tpw_MAin6_negedge, - PeriodData => periodcheckinfo_MAin6, - Violation => tviol_MAin6_MAin6, + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23164,8 +23713,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, - PathDelay => tpd_MAin6_PADDI, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23174,69 +23723,202 @@ end Structure; --- entity MAin_5_B +-- entity Din_6_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_5_B is + entity Din_6_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_5_B"; + InstancePath : string := "Din_6_MGIOL"; - tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin5 : VitalDelayType := 0 ns; - tpw_MAin5_posedge : VitalDelayType := 0 ns; - tpw_MAin5_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin5: in Std_logic); + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE; - end MAin_5_B; + end Din_6_MGIOL; - architecture Structure of MAin_5_B is + architecture Structure of Din_6_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin5_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_5: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin5_ipd); + Bank_0io_6: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin5_MAin5 : x01 := '0'; - VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin5_ipd, - TestSignalName => "MAin5", - Period => tperiod_MAin5, - PulseWidthHigh => tpw_MAin5_posedge, - PulseWidthLow => tpw_MAin5_negedge, - PeriodData => periodcheckinfo_MAin5, - Violation => tviol_MAin5_MAin5, + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23248,8 +23930,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, - PathDelay => tpd_MAin5_PADDI, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23258,69 +23940,202 @@ end Structure; --- entity MAin_4_B +-- entity Din_5_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_4_B is + entity Din_5_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_4_B"; + InstancePath : string := "Din_5_MGIOL"; - tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin4 : VitalDelayType := 0 ns; - tpw_MAin4_posedge : VitalDelayType := 0 ns; - tpw_MAin4_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin4: in Std_logic); + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE; - end MAin_4_B; + end Din_5_MGIOL; - architecture Structure of MAin_4_B is + architecture Structure of Din_5_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin4_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_4: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin4_ipd); + Bank_0io_5: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin4_MAin4 : x01 := '0'; - VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin4_ipd, - TestSignalName => "MAin4", - Period => tperiod_MAin4, - PulseWidthHigh => tpw_MAin4_posedge, - PulseWidthLow => tpw_MAin4_negedge, - PeriodData => periodcheckinfo_MAin4, - Violation => tviol_MAin4_MAin4, + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23332,8 +24147,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, - PathDelay => tpd_MAin4_PADDI, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23342,69 +24157,202 @@ end Structure; --- entity MAin_3_B +-- entity Din_4_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_3_B is + entity Din_4_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_3_B"; + InstancePath : string := "Din_4_MGIOL"; - tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin3 : VitalDelayType := 0 ns; - tpw_MAin3_posedge : VitalDelayType := 0 ns; - tpw_MAin3_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin3: in Std_logic); + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE; - end MAin_3_B; + end Din_4_MGIOL; - architecture Structure of MAin_3_B is + architecture Structure of Din_4_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin3_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_3: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin3_ipd); + Bank_0io_4: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin3_MAin3 : x01 := '0'; - VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin3_ipd, - TestSignalName => "MAin3", - Period => tperiod_MAin3, - PulseWidthHigh => tpw_MAin3_posedge, - PulseWidthLow => tpw_MAin3_negedge, - PeriodData => periodcheckinfo_MAin3, - Violation => tviol_MAin3_MAin3, + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23416,8 +24364,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, - PathDelay => tpd_MAin3_PADDI, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23426,69 +24374,202 @@ end Structure; --- entity MAin_2_B +-- entity Din_3_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_2_B is + entity Din_3_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_2_B"; + InstancePath : string := "Din_3_MGIOL"; - tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin2 : VitalDelayType := 0 ns; - tpw_MAin2_posedge : VitalDelayType := 0 ns; - tpw_MAin2_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin2: in Std_logic); + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE; - end MAin_2_B; + end Din_3_MGIOL; - architecture Structure of MAin_2_B is + architecture Structure of Din_3_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin2_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_2: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin2_ipd); + Bank_0io_3: smuxlregsre + port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_posedge, + SetupLow => tsetup_DI_CLK_noedge_posedge, + HoldHigh => thold_DI_CLK_noedge_posedge, + HoldLow => thold_DI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin2_MAin2 : x01 := '0'; - VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin2_ipd, - TestSignalName => "MAin2", - Period => tperiod_MAin2, - PulseWidthHigh => tpw_MAin2_posedge, - PulseWidthLow => tpw_MAin2_negedge, - PeriodData => periodcheckinfo_MAin2, - Violation => tviol_MAin2_MAin2, + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23500,8 +24581,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, - PathDelay => tpd_MAin2_PADDI, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23510,69 +24591,231 @@ end Structure; --- entity MAin_1_B +-- entity Din_2_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_1_B is + entity Din_2_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_1_B"; + InstancePath : string := "Din_2_MGIOL"; - tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin1 : VitalDelayType := 0 ns; - tpw_MAin1_posedge : VitalDelayType := 0 ns; - tpw_MAin1_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin1: in Std_logic); + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE; - end MAin_1_B; + end Din_2_MGIOL; - architecture Structure of MAin_1_B is + architecture Structure of Din_2_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin1_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_1: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin1_ipd); + CmdUFMCS: smuxlregsre + port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_negedge, + SetupLow => tsetup_DI_CLK_noedge_negedge, + HoldHigh => thold_DI_CLK_noedge_negedge, + HoldLow => thold_DI_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin1_MAin1 : x01 := '0'; - VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin1_ipd, - TestSignalName => "MAin1", - Period => tperiod_MAin1, - PulseWidthHigh => tpw_MAin1_posedge, - PulseWidthLow => tpw_MAin1_negedge, - PeriodData => periodcheckinfo_MAin1, - Violation => tviol_MAin1_MAin1, + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23584,8 +24827,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, - PathDelay => tpd_MAin1_PADDI, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23594,69 +24837,231 @@ end Structure; --- entity MAin_0_B +-- entity Din_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity MAin_0_B is + entity Din_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "MAin_0_B"; + InstancePath : string := "Din_1_MGIOL"; - tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_MAin0 : VitalDelayType := 0 ns; - tpw_MAin0_posedge : VitalDelayType := 0 ns; - tpw_MAin0_negedge : VitalDelayType := 0 ns); + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; MAin0: in Std_logic); + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); - ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE; - end MAin_0_B; + end Din_1_MGIOL; - architecture Structure of MAin_0_B is + architecture Structure of Din_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - signal PADDI_out : std_logic := 'X'; - signal MAin0_ipd : std_logic := 'X'; + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); end component; begin - MAin_pad_0: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>MAin0_ipd); + CmdUFMCLK: smuxlregsre + port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_negedge, + SetupLow => tsetup_DI_CLK_noedge_negedge, + HoldHigh => thold_DI_CLK_noedge_negedge, + HoldLow => thold_DI_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0086 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_MAin0_MAin0 : x01 := '0'; - VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => MAin0_ipd, - TestSignalName => "MAin0", - Period => tperiod_MAin0, - PulseWidthHigh => tpw_MAin0_posedge, - PulseWidthLow => tpw_MAin0_negedge, - PeriodData => periodcheckinfo_MAin0, - Violation => tviol_MAin0_MAin0, + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23668,8 +25073,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, - PathDelay => tpd_MAin0_PADDI, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23678,6 +25083,168 @@ end Structure; +-- entity Din_0_MGIOL + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_MGIOL is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_MGIOL"; + + tipd_DI : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI_CLK : VitalDelayType := 0 ns; + tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE; + + end Din_0_MGIOL; + + architecture Structure of Din_0_MGIOL is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI_ipd : std_logic := 'X'; + signal DI_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal INP_out : std_logic := 'X'; + + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component smuxlregsre + port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; + LSR: in Std_logic; Q: out Std_logic); + end component; + begin + CmdUFMSDI: smuxlregsre + port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI_ipd, DI, tipd_DI); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) + VARIABLE INP_zd : std_logic := 'X'; + VARIABLE INP_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI_CLK : x01 := '0'; + VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI_dly, + TestSignalName => "DI", + TestDelay => tisd_DI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI_CLK_noedge_negedge, + SetupLow => tsetup_DI_CLK_noedge_negedge, + HoldHigh => thold_DI_CLK_noedge_negedge, + HoldLow => thold_DI_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI_CLK_TimingDatash, + Violation => tviol_DI_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + INP_zd := INP_out; + + VitalPathDelay01 ( + OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_INP, + PathCondition => TRUE)), + GlitchData => INP_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + -- entity CROW_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; @@ -23710,11 +25277,11 @@ signal PADDI_out : std_logic := 'X'; signal CROW1_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - CROW_pad_1: xo2iobuf0069 + CROW_pad_1: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>CROW1_ipd); -- INPUT PATH DELAYs @@ -23794,11 +25361,11 @@ signal PADDI_out : std_logic := 'X'; signal CROW0_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - CROW_pad_0: xo2iobuf0069 + CROW_pad_0: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>CROW0_ipd); -- INPUT PATH DELAYs @@ -23846,69 +25413,69 @@ end Structure; --- entity Din_7_B +-- entity MAin_9_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_7_B is + entity MAin_9_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_7_B"; + InstancePath : string := "MAin_9_B"; - tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din7 : VitalDelayType := 0 ns; - tpw_Din7_posedge : VitalDelayType := 0 ns; - tpw_Din7_negedge : VitalDelayType := 0 ns); + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din7: in Std_logic); + port (PADDI: out Std_logic; MAin9: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; - end Din_7_B; + end MAin_9_B; - architecture Structure of Din_7_B is + architecture Structure of MAin_9_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din7_ipd : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_7: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din7_ipd); + MAin_pad_9: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din7_Din7 : x01 := '0'; - VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din7_ipd, - TestSignalName => "Din7", - Period => tperiod_Din7, - PulseWidthHigh => tpw_Din7_posedge, - PulseWidthLow => tpw_Din7_negedge, - PeriodData => periodcheckinfo_Din7, - Violation => tviol_Din7_Din7, + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -23920,8 +25487,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din7_ipd'last_event, - PathDelay => tpd_Din7_PADDI, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -23930,69 +25497,69 @@ end Structure; --- entity Din_6_B +-- entity MAin_8_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_6_B is + entity MAin_8_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_6_B"; + InstancePath : string := "MAin_8_B"; - tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din6 : VitalDelayType := 0 ns; - tpw_Din6_posedge : VitalDelayType := 0 ns; - tpw_Din6_negedge : VitalDelayType := 0 ns); + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din6: in Std_logic); + port (PADDI: out Std_logic; MAin8: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; - end Din_6_B; + end MAin_8_B; - architecture Structure of Din_6_B is + architecture Structure of MAin_8_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din6_ipd : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_6: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din6_ipd); + MAin_pad_8: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din6_Din6 : x01 := '0'; - VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din6_ipd, - TestSignalName => "Din6", - Period => tperiod_Din6, - PulseWidthHigh => tpw_Din6_posedge, - PulseWidthLow => tpw_Din6_negedge, - PeriodData => periodcheckinfo_Din6, - Violation => tviol_Din6_Din6, + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24004,8 +25571,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din6_ipd'last_event, - PathDelay => tpd_Din6_PADDI, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24014,69 +25581,69 @@ end Structure; --- entity Din_5_B +-- entity MAin_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_5_B is + entity MAin_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_5_B"; + InstancePath : string := "MAin_7_B"; - tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din5 : VitalDelayType := 0 ns; - tpw_Din5_posedge : VitalDelayType := 0 ns; - tpw_Din5_negedge : VitalDelayType := 0 ns); + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din5: in Std_logic); + port (PADDI: out Std_logic; MAin7: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; - end Din_5_B; + end MAin_7_B; - architecture Structure of Din_5_B is + architecture Structure of MAin_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din5_ipd : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_5: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din5_ipd); + MAin_pad_7: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din5_Din5 : x01 := '0'; - VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din5_ipd, - TestSignalName => "Din5", - Period => tperiod_Din5, - PulseWidthHigh => tpw_Din5_posedge, - PulseWidthLow => tpw_Din5_negedge, - PeriodData => periodcheckinfo_Din5, - Violation => tviol_Din5_Din5, + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24088,8 +25655,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din5_ipd'last_event, - PathDelay => tpd_Din5_PADDI, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24098,69 +25665,69 @@ end Structure; --- entity Din_4_B +-- entity MAin_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_4_B is + entity MAin_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_4_B"; + InstancePath : string := "MAin_6_B"; - tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din4 : VitalDelayType := 0 ns; - tpw_Din4_posedge : VitalDelayType := 0 ns; - tpw_Din4_negedge : VitalDelayType := 0 ns); + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din4: in Std_logic); + port (PADDI: out Std_logic; MAin6: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; - end Din_4_B; + end MAin_6_B; - architecture Structure of Din_4_B is + architecture Structure of MAin_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din4_ipd : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_4: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din4_ipd); + MAin_pad_6: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din4_Din4 : x01 := '0'; - VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din4_ipd, - TestSignalName => "Din4", - Period => tperiod_Din4, - PulseWidthHigh => tpw_Din4_posedge, - PulseWidthLow => tpw_Din4_negedge, - PeriodData => periodcheckinfo_Din4, - Violation => tviol_Din4_Din4, + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24172,8 +25739,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din4_ipd'last_event, - PathDelay => tpd_Din4_PADDI, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24182,69 +25749,69 @@ end Structure; --- entity Din_3_B +-- entity MAin_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_3_B is + entity MAin_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_3_B"; + InstancePath : string := "MAin_5_B"; - tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din3 : VitalDelayType := 0 ns; - tpw_Din3_posedge : VitalDelayType := 0 ns; - tpw_Din3_negedge : VitalDelayType := 0 ns); + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din3: in Std_logic); + port (PADDI: out Std_logic; MAin5: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; - end Din_3_B; + end MAin_5_B; - architecture Structure of Din_3_B is + architecture Structure of MAin_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din3_ipd : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_3: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din3_ipd); + MAin_pad_5: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din3_Din3 : x01 := '0'; - VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din3_ipd, - TestSignalName => "Din3", - Period => tperiod_Din3, - PulseWidthHigh => tpw_Din3_posedge, - PulseWidthLow => tpw_Din3_negedge, - PeriodData => periodcheckinfo_Din3, - Violation => tviol_Din3_Din3, + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24256,8 +25823,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din3_ipd'last_event, - PathDelay => tpd_Din3_PADDI, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24266,69 +25833,69 @@ end Structure; --- entity Din_2_B +-- entity MAin_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_2_B is + entity MAin_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_2_B"; + InstancePath : string := "MAin_4_B"; - tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din2 : VitalDelayType := 0 ns; - tpw_Din2_posedge : VitalDelayType := 0 ns; - tpw_Din2_negedge : VitalDelayType := 0 ns); + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din2: in Std_logic); + port (PADDI: out Std_logic; MAin4: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; - end Din_2_B; + end MAin_4_B; - architecture Structure of Din_2_B is + architecture Structure of MAin_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din2_ipd : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_2: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din2_ipd); + MAin_pad_4: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din2_Din2 : x01 := '0'; - VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din2_ipd, - TestSignalName => "Din2", - Period => tperiod_Din2, - PulseWidthHigh => tpw_Din2_posedge, - PulseWidthLow => tpw_Din2_negedge, - PeriodData => periodcheckinfo_Din2, - Violation => tviol_Din2_Din2, + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24340,8 +25907,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din2_ipd'last_event, - PathDelay => tpd_Din2_PADDI, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24350,69 +25917,69 @@ end Structure; --- entity Din_1_B +-- entity MAin_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_1_B is + entity MAin_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_1_B"; + InstancePath : string := "MAin_3_B"; - tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din1 : VitalDelayType := 0 ns; - tpw_Din1_posedge : VitalDelayType := 0 ns; - tpw_Din1_negedge : VitalDelayType := 0 ns); + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din1: in Std_logic); + port (PADDI: out Std_logic; MAin3: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; - end Din_1_B; + end MAin_3_B; - architecture Structure of Din_1_B is + architecture Structure of MAin_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din1_ipd : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_1: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din1_ipd); + MAin_pad_3: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din1_Din1 : x01 := '0'; - VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din1_ipd, - TestSignalName => "Din1", - Period => tperiod_Din1, - PulseWidthHigh => tpw_Din1_posedge, - PulseWidthLow => tpw_Din1_negedge, - PeriodData => periodcheckinfo_Din1, - Violation => tviol_Din1_Din1, + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24424,8 +25991,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din1_ipd'last_event, - PathDelay => tpd_Din1_PADDI, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24434,69 +26001,69 @@ end Structure; --- entity Din_0_B +-- entity MAin_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity Din_0_B is + entity MAin_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "Din_0_B"; + InstancePath : string := "MAin_2_B"; - tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_Din0 : VitalDelayType := 0 ns; - tpw_Din0_posedge : VitalDelayType := 0 ns; - tpw_Din0_negedge : VitalDelayType := 0 ns); + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; Din0: in Std_logic); + port (PADDI: out Std_logic; MAin2: in Std_logic); - ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; - end Din_0_B; + end MAin_2_B; - architecture Structure of Din_0_B is + architecture Structure of MAin_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal Din0_ipd : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - Din_pad_0: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>Din0_ipd); + MAin_pad_2: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_Din0_Din0 : x01 := '0'; - VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => Din0_ipd, - TestSignalName => "Din0", - Period => tperiod_Din0, - PulseWidthHigh => tpw_Din0_posedge, - PulseWidthLow => tpw_Din0_negedge, - PeriodData => periodcheckinfo_Din0, - Violation => tviol_Din0_Din0, + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24508,8 +26075,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => Din0_ipd'last_event, - PathDelay => tpd_Din0_PADDI, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24518,69 +26085,69 @@ end Structure; --- entity nCCASB +-- entity MAin_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity nCCASB is + entity MAin_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "nCCASB"; + InstancePath : string := "MAin_1_B"; - tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); - tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_nCCASS : VitalDelayType := 0 ns; - tpw_nCCASS_posedge : VitalDelayType := 0 ns; - tpw_nCCASS_negedge : VitalDelayType := 0 ns); + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; nCCASS: in Std_logic); + port (PADDI: out Std_logic; MAin1: in Std_logic); - ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; - end nCCASB; + end MAin_1_B; - architecture Structure of nCCASB is + architecture Structure of MAin_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal nCCASS_ipd : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - nCCAS_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + MAin_pad_1: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; - VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => nCCASS_ipd, - TestSignalName => "nCCASS", - Period => tperiod_nCCASS, - PulseWidthHigh => tpw_nCCASS_posedge, - PulseWidthLow => tpw_nCCASS_negedge, - PeriodData => periodcheckinfo_nCCASS, - Violation => tviol_nCCASS_nCCASS, + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24592,8 +26159,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, - PathDelay => tpd_nCCASS_PADDI, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24602,69 +26169,69 @@ end Structure; --- entity nCRASB +-- entity MAin_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; - entity nCRASB is + entity MAin_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; - InstancePath : string := "nCRASB"; + InstancePath : string := "MAin_0_B"; - tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); - tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_nCRASS : VitalDelayType := 0 ns; - tpw_nCRASS_posedge : VitalDelayType := 0 ns; - tpw_nCRASS_negedge : VitalDelayType := 0 ns); + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); - port (PADDI: out Std_logic; nCRASS: in Std_logic); + port (PADDI: out Std_logic; MAin0: in Std_logic); - ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; - end nCRASB; + end MAin_0_B; - architecture Structure of nCRASB is + architecture Structure of MAin_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; - signal nCRASS_ipd : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; - component xo2iobuf0069 + component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin - nCRAS_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + MAin_pad_0: xo2iobuf0086 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN - VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); END BLOCK; - VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; - VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; - VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( - TestSignal => nCRASS_ipd, - TestSignalName => "nCRASS", - Period => tperiod_nCRASS, - PulseWidthHigh => tpw_nCRASS_posedge, - PulseWidthLow => tpw_nCRASS_negedge, - PeriodData => periodcheckinfo_nCRASS, - Violation => tviol_nCRASS_nCRASS, + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, @@ -24676,260 +26243,8 @@ VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, - PathDelay => tpd_nCRASS_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity nFWEB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity nFWEB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "nFWEB"; - - tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); - tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_nFWES : VitalDelayType := 0 ns; - tpw_nFWES_posedge : VitalDelayType := 0 ns; - tpw_nFWES_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; nFWES: in Std_logic); - - ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; - - end nFWEB; - - architecture Structure of nFWEB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal nFWES_ipd : std_logic := 'X'; - - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - nFWE_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>nFWES_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_nFWES_nFWES : x01 := '0'; - VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => nFWES_ipd, - TestSignalName => "nFWES", - Period => tperiod_nFWES, - PulseWidthHigh => tpw_nFWES_posedge, - PulseWidthLow => tpw_nFWES_negedge, - PeriodData => periodcheckinfo_nFWES, - Violation => tviol_nFWES_nFWES, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, - PathDelay => tpd_nFWES_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity RCLKB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity RCLKB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "RCLKB"; - - tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); - tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_RCLKS : VitalDelayType := 0 ns; - tpw_RCLKS_posedge : VitalDelayType := 0 ns; - tpw_RCLKS_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; RCLKS: in Std_logic); - - ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; - - end RCLKB; - - architecture Structure of RCLKB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal RCLKS_ipd : std_logic := 'X'; - - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - RCLK_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>RCLKS_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; - VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => RCLKS_ipd, - TestSignalName => "RCLKS", - Period => tperiod_RCLKS, - PulseWidthHigh => tpw_RCLKS_posedge, - PulseWidthLow => tpw_RCLKS_negedge, - PeriodData => periodcheckinfo_RCLKS, - Violation => tviol_RCLKS_RCLKS, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, - PathDelay => tpd_RCLKS_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity UFMSDOB - library IEEE, vital2000, MACHXO2; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use MACHXO2.COMPONENTS.ALL; - - entity UFMSDOB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "UFMSDOB"; - - tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); - tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_UFMSDOS : VitalDelayType := 0 ns; - tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; - tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; UFMSDOS: in Std_logic); - - ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; - - end UFMSDOB; - - architecture Structure of UFMSDOB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal UFMSDOS_ipd : std_logic := 'X'; - - component xo2iobuf0069 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - UFMSDO_pad: xo2iobuf0069 - port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; - VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => UFMSDOS_ipd, - TestSignalName => "UFMSDOS", - Period => tperiod_UFMSDOS, - PulseWidthHigh => tpw_UFMSDOS_posedge, - PulseWidthLow => tpw_UFMSDOS_negedge, - PeriodData => periodcheckinfo_UFMSDOS, - Violation => tviol_UFMSDOS_UFMSDOS, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, - PathDelay => tpd_UFMSDOS_PADDI, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); @@ -24952,7 +26267,7 @@ nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; RBA: out Std_logic_vector (1 downto 0); RA: out Std_logic_vector (11 downto 0); - RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RD: out Std_logic_vector (7 downto 0); nRCS: out Std_logic; RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; @@ -24963,303 +26278,296 @@ end RAM2GS; architecture Structure of RAM2GS is - signal FS_14: Std_logic; - signal FS_13: Std_logic; - signal n81: Std_logic; - signal n82: Std_logic; - signal RCLK_c: Std_logic; - signal n1998: Std_logic; - signal n1999: Std_logic; - signal FS_12: Std_logic; - signal FS_11: Std_logic; - signal n83: Std_logic; - signal n84: Std_logic; - signal n1997: Std_logic; - signal FS_8: Std_logic; - signal FS_7: Std_logic; - signal n87: Std_logic; - signal n88: Std_logic; - signal n1995: Std_logic; - signal n1996: Std_logic; - signal FS_6: Std_logic; - signal FS_5: Std_logic; - signal n89: Std_logic; - signal n90: Std_logic; - signal n1994: Std_logic; - signal FS_2: Std_logic; - signal FS_1: Std_logic; - signal n93: Std_logic; - signal n94: Std_logic; - signal n1992: Std_logic; - signal n1993: Std_logic; signal FS_0: Std_logic; - signal n95: Std_logic; - signal CASr2: Std_logic; - signal CASr3: Std_logic; - signal FS_10: Std_logic; - signal FS_9: Std_logic; - signal n85: Std_logic; - signal n86: Std_logic; + signal FS_s_0: Std_logic; + signal RCLK_c: Std_logic; + signal FS_cry_0: Std_logic; signal FS_17: Std_logic; - signal n78: Std_logic; - signal n2000: Std_logic; - signal FS_4: Std_logic; - signal FS_3: Std_logic; - signal n91: Std_logic; - signal n92: Std_logic; + signal FS_s_17: Std_logic; + signal FS_cry_16: Std_logic; signal FS_16: Std_logic; signal FS_15: Std_logic; - signal n79: Std_logic; - signal n80: Std_logic; - signal Din_c_4: Std_logic; - signal Din_c_6: Std_logic; - signal Din_c_1: Std_logic; - signal Din_c_7: Std_logic; - signal n2382: Std_logic; - signal n8: Std_logic; - signal n2225: Std_logic; - signal n2180: Std_logic; - signal ADSubmitted_N_246: Std_logic; - signal PHI2_N_120_enable_2: Std_logic; - signal C1Submitted_N_237: Std_logic; - signal PHI2_c: Std_logic; + signal FS_s_16: Std_logic; + signal FS_s_15: Std_logic; + signal FS_cry_14: Std_logic; + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal FS_s_14: Std_logic; + signal FS_s_13: Std_logic; + signal FS_cry_12: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal FS_s_12: Std_logic; + signal FS_s_11: Std_logic; + signal FS_cry_10: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal FS_s_10: Std_logic; + signal FS_s_9: Std_logic; + signal FS_cry_8: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal FS_s_8: Std_logic; + signal FS_s_7: Std_logic; + signal FS_cry_6: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal FS_s_6: Std_logic; + signal FS_s_5: Std_logic; + signal FS_cry_4: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal FS_s_4: Std_logic; + signal FS_s_3: Std_logic; + signal FS_cry_2: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal FS_s_2: Std_logic; + signal FS_s_1: Std_logic; + signal CmdEnable17_5: Std_logic; + signal CmdEnable17_4: Std_logic; + signal ADWR: Std_logic; + signal CmdEnable16: Std_logic; + signal CmdEnable17: Std_logic; + signal un1_ADWR: Std_logic; signal ADSubmitted: Std_logic; - signal n26: Std_logic; - signal MAin_c_5: Std_logic; - signal n22: Std_logic; + signal ADSubmitted_r: Std_logic; + signal PHI2_c: Std_logic; + signal un1_Bank_1: Std_logic; signal MAin_c_2: Std_logic; - signal MAin_c_1: Std_logic; + signal CmdEnable16_5: Std_logic; + signal C1WR_3: Std_logic; signal C1Submitted: Std_logic; - signal n2365: Std_logic; + signal C1Submitted_s: Std_logic; signal nFWE_c: Std_logic; - signal n1398: Std_logic; signal nCCAS_c: Std_logic; - signal nCCAS_N_3: Std_logic; + signal nCCAS_c_i: Std_logic; signal CASr: Std_logic; - signal n2254: Std_logic; - signal Din_c_5: Std_logic; - signal n2191: Std_logic; - signal n2183: Std_logic; - signal n15_adj_1: Std_logic; - signal n2208: Std_logic; - signal n2363: Std_logic; - signal CmdEnable_N_248: Std_logic; - signal PHI2_N_120_enable_1: Std_logic; + signal RD_1_i: Std_logic; + signal CASr2: Std_logic; + signal S_1: Std_logic; + signal RASr2: Std_logic; + signal IS_3: Std_logic; + signal CO0: Std_logic; + signal N_166_i: Std_logic; + signal Ready_0_sqmuxa_0_a3_2: Std_logic; signal CmdEnable: Std_logic; - signal n2447_001_BUF1: Std_logic; - signal PHI2_N_120_enable_7: Std_logic; - signal CmdSubmitted: Std_logic; - signal n1314: Std_logic; - signal n8MEGEN: Std_logic; - signal Din_c_0: Std_logic; - signal Cmdn8MEGEN_N_264: Std_logic; - signal PHI2_N_120_enable_6: Std_logic; - signal Cmdn8MEGEN: Std_logic; + signal un1_CMDWR: Std_logic; + signal CmdEnable_s: Std_logic; + signal N_36: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_1: Std_logic; + signal N_94: Std_logic; + signal N_60: Std_logic; + signal N_59: Std_logic; + signal LEDEN: Std_logic; + signal N_14_i: Std_logic; + signal XOR8MEG18: Std_logic; + signal CmdLEDEN: Std_logic; signal Din_c_3: Std_logic; - signal n2373: Std_logic; + signal CmdSubmitted: Std_logic; + signal CmdSubmitted_1_sqmuxa: Std_logic; + signal N_412_0: Std_logic; + signal CmdUFMCLK_1_sqmuxa: Std_logic; + signal n8MEGEN: Std_logic; + signal Cmdn8MEGEN_4_u_i_0: Std_logic; + signal N_12_i: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal MAin_c_1: Std_logic; + signal ADWR_6: Std_logic; + signal ADWR_3: Std_logic; + signal nFWE_c_i: Std_logic; signal nCRAS_c: Std_logic; signal FWEr: Std_logic; - signal CBR: Std_logic; - signal n2447_000_BUF1: Std_logic; - signal RCLK_c_enable_28: Std_logic; + signal CMDWR_2: Std_logic; + signal Ready: Std_logic; + signal N_151: Std_logic; + signal IS_0: Std_logic; + signal N_60_i_i: Std_logic; + signal RA10s_i: Std_logic; + signal IS_2: Std_logic; + signal IS_1: Std_logic; + signal N_180_i: Std_logic; + signal IS_n1_0_x2: Std_logic; + signal N_48_i: Std_logic; + signal N_58_i_i: Std_logic; + signal N_137_5: Std_logic; + signal N_137_3: Std_logic; signal InitReady: Std_logic; - signal n2447: Std_logic; - signal RCLK_c_enable_16: Std_logic; - signal LEDEN: Std_logic; - signal nCRAS_c_inv: Std_logic; + signal InitReady3: Std_logic; + signal N_413_0: Std_logic; + signal N_74_i: Std_logic; + signal N_28: Std_logic; + signal CBR: Std_logic; + signal nCRAS_c_i_0: Std_logic; signal RASr: Std_logic; signal LED_c: Std_logic; - signal RASr2: Std_logic; - signal nRowColSel_N_35: Std_logic; - signal nRCAS_N_165: Std_logic; - signal Ready: Std_logic; - signal n2381: Std_logic; - signal nRCS_N_139: Std_logic; - signal n2036: Std_logic; - signal nRWE_N_177: Std_logic; - signal RA_0S: Std_logic; - signal XOR8MEG: Std_logic; - signal RA11_N_184: Std_logic; - signal RA_c: Std_logic; - signal n6_adj_2: Std_logic; - signal PHI2r2: Std_logic; - signal PHI2r3: Std_logic; - signal n15_adj_4: Std_logic; - signal RCKEEN_N_121: Std_logic; - signal RCLK_c_enable_6: Std_logic; + signal S_0_i_o2_1: Std_logic; + signal RCKEEN_8_u_1_0: Std_logic; + signal RCKEEN_8_u_0_0: Std_logic; + signal RCKEEN_8: Std_logic; signal RCKEEN: Std_logic; - signal RCLK_c_enable_10: Std_logic; + signal Ready_fast: Std_logic; + signal CROW_c_1: Std_logic; signal RASr3: Std_logic; - signal RCKE_N_132: Std_logic; - signal PHI2r: Std_logic; + signal RCKE_2: Std_logic; signal RCKE_c: Std_logic; - signal n2447_002_BUF1: Std_logic; - signal Ready_N_292: Std_logic; - signal n2267: Std_logic; - signal n13_adj_6: Std_logic; - signal CmdUFMCLK: Std_logic; - signal n1893: Std_logic; - signal UFMCLK_N_224: Std_logic; - signal n2366: Std_logic; - signal UFMCLK_c: Std_logic; - signal n10: Std_logic; - signal n7: Std_logic; - signal n4: Std_logic; - signal CmdUFMSDI: Std_logic; - signal n2174: Std_logic; - signal UFMSDI_N_231: Std_logic; - signal UFMSDI_c: Std_logic; - signal n2260: Std_logic; - signal Din_c_2: Std_logic; - signal XOR8MEG_N_110: Std_logic; - signal PHI2_N_120_enable_3: Std_logic; - signal n2375: Std_logic; - signal UFMSDO_c: Std_logic; - signal n2367: Std_logic; - signal n8MEGEN_N_91: Std_logic; - signal RCLK_c_enable_15: Std_logic; - signal nRCS_N_142: Std_logic; - signal nRCAS_N_166: Std_logic; - signal n2371: Std_logic; - signal nRCAS_N_161: Std_logic; - signal nRCAS_c: Std_logic; - signal nRCS_N_141: Std_logic; - signal nRCS_N_137: Std_logic; - signal nRCS_N_136: Std_logic; - signal nRCS_c: Std_logic; - signal n2379: Std_logic; - signal nRRAS_N_156: Std_logic; - signal nRRAS_c: Std_logic; - signal nRWE_N_178: Std_logic; - signal n1765: Std_logic; - signal nRWE_N_171: Std_logic; - signal RCLK_c_enable_5: Std_logic; - signal nRWE_c: Std_logic; - signal nRowColSel_N_34: Std_logic; - signal nRowColSel_N_33: Std_logic; - signal n2376: Std_logic; - signal n1060: Std_logic; - signal n2372: Std_logic; - signal n917: Std_logic; - signal nRowColSel: Std_logic; - signal nRowColSel_N_32: Std_logic; - signal n827: Std_logic; - signal n2227: Std_logic; - signal n1406: Std_logic; - signal Bank_3: Std_logic; - signal Bank_6: Std_logic; - signal n2287: Std_logic; - signal n13: Std_logic; - signal n2374: Std_logic; - signal n2368: Std_logic; - signal CmdUFMCS: Std_logic; - signal n64: Std_logic; - signal nUFMCS_N_199: Std_logic; - signal nUFMCS_c: Std_logic; - signal n6_adj_3: Std_logic; - signal Ready_N_296: Std_logic; - signal n2204: Std_logic; - signal n2369: Std_logic; + signal RBAd_0_1: Std_logic; + signal N_158: Std_logic; + signal N_414_0: Std_logic; + signal Ready_0_sqmuxa: Std_logic; + signal N_415_0: Std_logic; signal MAin_c_0: Std_logic; - signal PHI2_N_120_enable_8: Std_logic; - signal Bank_5: Std_logic; - signal n2277: Std_logic; - signal Bank_2: Std_logic; - signal n2220: Std_logic; + signal RowAd_0_1: Std_logic; + signal RowAd_0_0: Std_logic; signal RowA_0: Std_logic; signal RowA_1: Std_logic; - signal n2370: Std_logic; - signal n2228: Std_logic; - signal n732: Std_logic; - signal n733: Std_logic; - signal RCLK_c_enable_27: Std_logic; - signal n2055: Std_logic; - signal MAin_c_9: Std_logic; - signal MAin_c_8: Std_logic; - signal RowA_8: Std_logic; - signal RowA_9: Std_logic; - signal n2210: Std_logic; - signal nRWE_N_182: Std_logic; - signal nRCS_N_146: Std_logic; - signal n728: Std_logic; - signal n729: Std_logic; - signal n727: Std_logic; - signal n730: Std_logic; - signal n2378: Std_logic; - signal n726: Std_logic; - signal n12: Std_logic; - signal MAin_c_4: Std_logic; - signal RowA_4: Std_logic; - signal RowA_5: Std_logic; - signal n1277: Std_logic; - signal n4_adj_7: Std_logic; - signal n2377: Std_logic; - signal n738: Std_logic; - signal n737: Std_logic; - signal n14: Std_logic; - signal n15: Std_logic; - signal n6: Std_logic; - signal CROW_c_1: Std_logic; - signal CROW_c_0: Std_logic; - signal RBA_c_0: Std_logic; - signal RBA_c_1: Std_logic; - signal n7_adj_5: Std_logic; - signal n2362: Std_logic; - signal WRD_6: Std_logic; - signal WRD_7: Std_logic; - signal WRD_4: Std_logic; - signal WRD_5: Std_logic; - signal WRD_0: Std_logic; - signal WRD_1: Std_logic; signal MAin_c_3: Std_logic; + signal RowAd_0_3: Std_logic; + signal RowAd_0_2: Std_logic; signal RowA_2: Std_logic; signal RowA_3: Std_logic; - signal WRD_2: Std_logic; - signal WRD_3: Std_logic; - signal RA_1_9: Std_logic; - signal Bank_0: Std_logic; - signal RDQML_c: Std_logic; - signal Bank_1: Std_logic; - signal n734: Std_logic; - signal n735: Std_logic; - signal RA_1_8: Std_logic; - signal RDQMH_c: Std_logic; - signal Bank_4: Std_logic; + signal MAin_c_5: Std_logic; + signal MAin_c_4: Std_logic; + signal RowAd_0_5: Std_logic; + signal RowAd_0_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; signal MAin_c_7: Std_logic; - signal RowA_7: Std_logic; - signal RA_1_7: Std_logic; - signal Bank_7: Std_logic; signal MAin_c_6: Std_logic; + signal RowAd_0_7: Std_logic; + signal RowAd_0_6: Std_logic; signal RowA_6: Std_logic; - signal RA_1_6: Std_logic; - signal RA_1_5: Std_logic; - signal RA_1_0: Std_logic; - signal RA_1_4: Std_logic; - signal RA_1_1: Std_logic; - signal RA_1_3: Std_logic; - signal RA_1_2: Std_logic; - signal n984: Std_logic; - signal n736: Std_logic; - signal Dout_c: Std_logic; - signal Dout_0S: Std_logic; - signal Dout_1S: Std_logic; - signal Dout_2S: Std_logic; - signal Dout_3S: Std_logic; - signal Dout_4S: Std_logic; - signal Dout_5S: Std_logic; - signal Dout_6S: Std_logic; + signal RowA_7: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowAd_0_9: Std_logic; + signal RowAd_0_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal nRCAS_0_sqmuxa_1: Std_logic; + signal CmdUFMSDI: Std_logic; + signal N_145: Std_logic; + signal UFMSDI_ens2_i_a0: Std_logic; + signal nUFMCS15: Std_logic; + signal UFMSDI_c: Std_logic; + signal UFMSDI_RNO: Std_logic; + signal N_141_i: Std_logic; + signal Din_c_7: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_4: Std_logic; + signal un1_Din_3: Std_logic; + signal XOR8MEG_3_u_1: Std_logic; + signal XOR8MEG: Std_logic; + signal Din_c_0: Std_logic; + signal XOR8MEG_3: Std_logic; + signal Bank_4: Std_logic; + signal Bank_3: Std_logic; + signal Bank_1: Std_logic; + signal Bank_0: Std_logic; + signal UFMSDO_c: Std_logic; + signal N_131: Std_logic; + signal N_26: Std_logic; + signal un1_Bank_1_4: Std_logic; + signal CASr3: Std_logic; + signal N_168: Std_logic; + signal nRowColSel_0_0: Std_logic; + signal nRRAS_0_sqmuxa: Std_logic; + signal nRowColSel: Std_logic; + signal UFMCLK_r_i_a2_2_2: Std_logic; + signal CmdUFMCS: Std_logic; + signal nUFMCS_c: Std_logic; + signal nUFMCS_s_0_m4_yy: Std_logic; + signal nUFMCS_s_0_N_5_i: Std_logic; + signal N_129: Std_logic; + signal d_m3_0_a2_0: Std_logic; + signal CmdUFMCLK: Std_logic; + signal i1_i: Std_logic; + signal N_50: Std_logic; + signal N_154: Std_logic; + signal un1_nRCAS_6_sqmuxa_i_0: Std_logic; + signal N_45: Std_logic; + signal N_146_i_1: Std_logic; + signal N_27_i_1: Std_logic; + signal N_146_i: Std_logic; + signal nRRAS_5_u_i_0: Std_logic; + signal N_24_i: Std_logic; + signal nRWE_s_i_a3_1_0: Std_logic; + signal nRWE_s_i_tz_0: Std_logic; + signal PHI2r3: Std_logic; + signal PHI2r2: Std_logic; + signal un1_PHI2r3_0: Std_logic; + signal N_140: Std_logic; + signal un1_FS_14_i_a2_0_1: Std_logic; + signal N_139_8: Std_logic; + signal N_139_6: Std_logic; + signal N_139: Std_logic; + signal un1_FS_13_i_a2_1: Std_logic; + signal UFMSDI_ens2_i_a2_4_2: Std_logic; + signal N_34: Std_logic; + signal ADWR_2: Std_logic; + signal N_24: Std_logic; + signal N_27_i_sn: Std_logic; + signal N_153: Std_logic; + signal C1WR_1: Std_logic; + signal UFMSDI_ens2_i_o2_0_3: Std_logic; + signal PHI2r: Std_logic; + signal i2_i: Std_logic; + signal N_27_i: Std_logic; + signal Din_c_2: Std_logic; + signal CmdEnable16_4: Std_logic; + signal CmdEnable16_3: Std_logic; + signal Bank_2: Std_logic; + signal Bank_7: Std_logic; + signal un1_Bank_1_3: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal nRWE_0io_RNO_1: Std_logic; + signal nRWE_0io_RNO_0: Std_logic; + signal N_147_i: Std_logic; + signal RA_c_9: Std_logic; + signal RDQML_c: Std_logic; + signal RA_c_8: Std_logic; + signal RDQMH_c: Std_logic; + signal RA_c_0: Std_logic; + signal RA_c_7: Std_logic; + signal RA_c_1: Std_logic; + signal RA_c_6: Std_logic; + signal RA_c_2: Std_logic; + signal RA_c_5: Std_logic; + signal RA_c_3: Std_logic; + signal RA_c_4: Std_logic; + signal CROW_c_0: Std_logic; + signal RA11d_0: Std_logic; + signal RBAd_0_0: Std_logic; + signal WRD_0: Std_logic; + signal UFMSDI_c_n0: Std_logic; + signal UFMCLK_c: Std_logic; + signal nUFMCS_c_n1: Std_logic; + signal nRCAS_c: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_c: Std_logic; + signal RCKE_c_n2: Std_logic; + signal nRCS_c: Std_logic; + signal WRD_7: Std_logic; + signal WRD_6: Std_logic; + signal WRD_5: Std_logic; + signal WRD_4: Std_logic; + signal WRD_3: Std_logic; + signal WRD_2: Std_logic; + signal WRD_1: Std_logic; + signal RA_c_11: Std_logic; + signal RA_c_10: Std_logic; + signal RBA_c_1: Std_logic; + signal RBA_c_0: Std_logic; signal VCCI: Std_logic; component SLICE_0 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic; FCO: out Std_logic); + port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; + F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_1 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic; FCO: out Std_logic); + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); end component; component SLICE_2 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; @@ -25280,8 +26588,9 @@ Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_5 - port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_6 @@ -25291,8 +26600,10 @@ Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_7 - port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_8 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; @@ -25307,96 +26618,181 @@ Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_10 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; - component SLICE_15 + component SLICE_13 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_14 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_17 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_18 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_19 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_20 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_21 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_22 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_23 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_25 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_26 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_27 + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_29 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_31 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_16 - port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_32 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; - component SLICE_19 + component SLICE_33 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_34 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_36 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_37 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_38 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_39 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_40 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_41 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_42 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; - component SLICE_20 - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component SLICE_24 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_25 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_26 - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component SLICE_27 - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component SLICE_30 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_32 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_33 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_35 + component SLICE_43 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; - component SLICE_36 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_37 - port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; component SLICE_44 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; @@ -25404,390 +26800,356 @@ port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_46 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_47 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_48 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); end component; component SLICE_50 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_51 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_52 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_53 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_54 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_55 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_56 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_57 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_59 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_61 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; - component SLICE_62 + component SLICE_58 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); end component; - component SLICE_64 + component SLICE_59 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_60 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_62 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_63 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_64 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_65 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_66 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_67 - port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component SLICE_68 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_69 - port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; - component SLICE_70 + component SLICE_66 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_67 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; - component i30_SLICE_71 + component SLICE_69 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_71 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_72 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); end component; component SLICE_73 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_74 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); end component; component SLICE_75 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); end component; component SLICE_76 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_77 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; - component SLICE_78 + component SLICE_77 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_79 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); end component; component SLICE_80 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_81 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); + F0: out Std_logic; F1: out Std_logic); end component; component SLICE_82 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); end component; component SLICE_83 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); end component; component SLICE_84 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); end component; component SLICE_85 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_86 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_87 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_88 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_89 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_90 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_91 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_92 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_93 - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_94 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; - component SLICE_95 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_96 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_97 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_98 - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_99 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic); - end component; - component SLICE_100 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component SLICE_101 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_102 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_103 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_104 - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component SLICE_105 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component SLICE_106 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component RD_7_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD7: inout Std_logic); - end component; - component RD_6_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD6: inout Std_logic); - end component; - component RD_5_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD5: inout Std_logic); - end component; - component RD_4_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD4: inout Std_logic); - end component; - component RD_3_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD3: inout Std_logic); - end component; - component RD_2_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD2: inout Std_logic); - end component; - component RD_1_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD1: inout Std_logic); - end component; component RD_0_B - port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; - RD0: inout Std_logic); + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic); end component; - component Dout_7_B - port (PADDO: in Std_logic; Dout7: out Std_logic); - end component; - component Dout_6_B - port (PADDO: in Std_logic; Dout6: out Std_logic); - end component; - component Dout_5_B - port (PADDO: in Std_logic; Dout5: out Std_logic); - end component; - component Dout_4_B - port (PADDO: in Std_logic; Dout4: out Std_logic); - end component; - component Dout_3_B - port (PADDO: in Std_logic; Dout3: out Std_logic); - end component; - component Dout_2_B - port (PADDO: in Std_logic; Dout2: out Std_logic); - end component; - component Dout_1_B - port (PADDO: in Std_logic; Dout1: out Std_logic); + component RD_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component Dout_0_B port (PADDO: in Std_logic; Dout0: out Std_logic); end component; - component LEDB - port (PADDO: in Std_logic; LEDS: out Std_logic); + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); end component; - component RBA_1_B - port (PADDO: in Std_logic; RBA1: out Std_logic); + component PHI2_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; - component RBA_0_B - port (PADDO: in Std_logic; RBA0: out Std_logic); + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + component UFMSDIB + port (IOLDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component UFMSDI_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component UFMCLKB + port (IOLDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMCLK_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; + CLK: in Std_logic); + end component; + component nUFMCSB + port (IOLDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component nUFMCS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component nRCASB + port (IOLDO: in Std_logic; nRCASS: out Std_logic); + end component; + component nRCAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRRASB + port (IOLDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRRAS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component nRWEB + port (IOLDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRWE_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RCKEB + port (IOLDO: in Std_logic; RCKES: out Std_logic); + end component; + component RCKE_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component nRCSB + port (IOLDO: in Std_logic; nRCSS: out Std_logic); + end component; + component nRCS_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_7_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic); + end component; + component RD_7_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_6_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic); + end component; + component RD_6_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_5_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic); + end component; + component RD_5_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_4_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic); + end component; + component RD_4_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_3_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic); + end component; + component RD_3_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_2_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic); + end component; + component RD_2_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); + end component; + component RD_1_B + port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic); + end component; + component RD_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RA_11_B - port (PADDO: in Std_logic; RA11: out Std_logic); + port (IOLDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_11_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RA_10_B - port (PADDO: in Std_logic; RA10: out Std_logic); + port (IOLDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_10_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic); end component; component RA_9_B port (PADDO: in Std_logic; RA9: out Std_logic); @@ -25819,38 +27181,107 @@ component RA_0_B port (PADDO: in Std_logic; RA0: out Std_logic); end component; - component nRCSB - port (PADDO: in Std_logic; nRCSS: out Std_logic); + component RBA_1_B + port (IOLDO: in Std_logic; RBA1: out Std_logic); end component; - component RCKEB - port (PADDO: in Std_logic; RCKES: out Std_logic); + component RBA_1_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; - component nRWEB - port (PADDO: in Std_logic; nRWES: out Std_logic); + component RBA_0_B + port (IOLDO: in Std_logic; RBA0: out Std_logic); end component; - component nRRASB - port (PADDO: in Std_logic; nRRASS: out Std_logic); + component RBA_0_MGIOL + port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; - component nRCASB - port (PADDO: in Std_logic; nRCASS: out Std_logic); + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); end component; - component RDQMHB - port (PADDO: in Std_logic; RDQMHS: out Std_logic); + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); end component; - component RDQMLB - port (PADDO: in Std_logic; RDQMLS: out Std_logic); + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); end component; - component nUFMCSB - port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); end component; - component UFMCLKB - port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); end component; - component UFMSDIB - port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); end component; - component PHI2B - port (PADDI: out Std_logic; PHI2S: in Std_logic); + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_7_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_6_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_5_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_4_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_3_MGIOL + port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_2_MGIOL + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_1_MGIOL + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component Din_0_MGIOL + port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + INP: out Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); end component; component MAin_9_B port (PADDI: out Std_logic; MAin9: in Std_logic); @@ -25882,442 +27313,477 @@ component MAin_0_B port (PADDI: out Std_logic; MAin0: in Std_logic); end component; - component CROW_1_B - port (PADDI: out Std_logic; CROW1: in Std_logic); - end component; - component CROW_0_B - port (PADDI: out Std_logic; CROW0: in Std_logic); - end component; - component Din_7_B - port (PADDI: out Std_logic; Din7: in Std_logic); - end component; - component Din_6_B - port (PADDI: out Std_logic; Din6: in Std_logic); - end component; - component Din_5_B - port (PADDI: out Std_logic; Din5: in Std_logic); - end component; - component Din_4_B - port (PADDI: out Std_logic; Din4: in Std_logic); - end component; - component Din_3_B - port (PADDI: out Std_logic; Din3: in Std_logic); - end component; - component Din_2_B - port (PADDI: out Std_logic; Din2: in Std_logic); - end component; - component Din_1_B - port (PADDI: out Std_logic; Din1: in Std_logic); - end component; - component Din_0_B - port (PADDI: out Std_logic; Din0: in Std_logic); - end component; - component nCCASB - port (PADDI: out Std_logic; nCCASS: in Std_logic); - end component; - component nCRASB - port (PADDI: out Std_logic; nCRASS: in Std_logic); - end component; - component nFWEB - port (PADDI: out Std_logic; nFWES: in Std_logic); - end component; - component RCLKB - port (PADDI: out Std_logic; RCLKS: in Std_logic); - end component; - component UFMSDOB - port (PADDI: out Std_logic; UFMSDOS: in Std_logic); - end component; begin SLICE_0I: SLICE_0 - port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c, - FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999); + port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0, + FCO=>FS_cry_0); SLICE_1I: SLICE_1 - port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c, - FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998); + port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16, + F0=>FS_s_17, Q0=>FS_17); SLICE_2I: SLICE_2 - port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c, - FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996); + port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c, + FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16, + FCO=>FS_cry_16); SLICE_3I: SLICE_3 - port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c, - FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995); + port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c, + FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14, + FCO=>FS_cry_14); SLICE_4I: SLICE_4 - port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c, - FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993); + port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c, + FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12, + FCO=>FS_cry_12); SLICE_5I: SLICE_5 - port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95, - Q1=>FS_0, FCO=>n1992); + port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c, + FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10, + FCO=>FS_cry_10); SLICE_6I: SLICE_6 - port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c, - FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997); + port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c, + FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8, + FCO=>FS_cry_8); SLICE_7I: SLICE_7 - port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78, - Q0=>FS_17); + port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c, + FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6, + FCO=>FS_cry_6); SLICE_8I: SLICE_8 - port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c, - FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994); + port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c, + FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4, + FCO=>FS_cry_4); SLICE_9I: SLICE_9 - port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c, - FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000); + port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c, + FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2, + FCO=>FS_cry_2); SLICE_10I: SLICE_10 - port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382, - C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246, - CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c, - F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8); - SLICE_15I: SLICE_15 - port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, - C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398, - LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398, - Q0=>C1Submitted, F1=>n2365); - SLICE_16I: SLICE_16 - port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c, - F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2); + port map (C1=>CmdEnable17_5, B1=>CmdEnable17_4, A1=>ADWR, + D0=>CmdEnable16, C0=>CmdEnable17, B0=>un1_ADWR, + A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c, + F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17); + SLICE_13I: SLICE_13 + port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>CmdEnable16_5, A1=>C1WR_3, + C0=>CmdEnable16, B0=>un1_ADWR, A0=>C1Submitted, + DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s, + Q0=>C1Submitted, F1=>CmdEnable16); + SLICE_14I: SLICE_14 + port map (B1=>nFWE_c, A1=>nCCAS_c, A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, + CLK=>RCLK_c, F0=>nCCAS_c_i, Q0=>CASr, F1=>RD_1_i, Q1=>CASr2); + SLICE_17I: SLICE_17 + port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, + DI0=>N_166_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_166_i, Q0=>CO0, + F1=>Ready_0_sqmuxa_0_a3_2); + SLICE_18I: SLICE_18 + port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, + B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, + M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable); SLICE_19I: SLICE_19 - port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1, - C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248, - CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248, - Q0=>CmdEnable, F1=>n15_adj_1); + port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_1, D0=>N_94, C0=>N_60, + B0=>N_59, A0=>LEDEN, DI0=>N_14_i, CE=>XOR8MEG18, CLK=>PHI2_c, + F0=>N_14_i, Q0=>CmdLEDEN, F1=>N_60); SLICE_20I: SLICE_20 - port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, - F0=>n2447_001_BUF1, Q0=>CmdSubmitted); + port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, + B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_412_0, + CLK=>PHI2_c, F0=>N_412_0, Q0=>CmdSubmitted, + F1=>CmdUFMCLK_1_sqmuxa); + SLICE_21I: SLICE_21 + port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_3, C0=>n8MEGEN, B0=>N_94, + A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_12_i, CE=>XOR8MEG18, + CLK=>PHI2_c, F0=>N_12_i, Q0=>Cmdn8MEGEN, F1=>N_94); + SLICE_22I: SLICE_22 + port map (D1=>nFWE_c, C1=>MAin_c_1, B1=>ADWR_6, A1=>ADWR_3, A0=>nFWE_c, + DI0=>nFWE_c_i, CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, + F1=>CMDWR_2); + SLICE_23I: SLICE_23 + port map (D1=>Ready, C1=>N_151, B1=>IS_3, A1=>IS_0, C0=>Ready, B0=>N_151, + A0=>IS_0, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0, + F1=>RA10s_i); SLICE_24I: SLICE_24 - port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, - B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, - CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, - Q0=>Cmdn8MEGEN, F1=>n1314); + port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, DI1=>N_180_i, + DI0=>IS_n1_0_x2, CE=>N_48_i, CLK=>RCLK_c, F0=>IS_n1_0_x2, + Q0=>IS_1, F1=>N_180_i, Q1=>IS_2); SLICE_25I: SLICE_25 - port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373, - M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180, - Q1=>CBR); + port map (D0=>IS_0, C0=>IS_1, B0=>IS_2, A0=>IS_3, DI0=>N_58_i_i, + CE=>N_48_i, CLK=>RCLK_c, F0=>N_58_i_i, Q0=>IS_3); SLICE_26I: SLICE_26 - port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c, - F0=>n2447_000_BUF1, Q0=>InitReady); + port map (D1=>N_137_5, C1=>N_137_3, B1=>FS_16, A1=>FS_10, B0=>InitReady, + A0=>InitReady3, DI0=>N_413_0, CLK=>RCLK_c, F0=>N_413_0, + Q0=>InitReady, F1=>InitReady3); SLICE_27I: SLICE_27 - port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447, - Q0=>LEDEN); - SLICE_30I: SLICE_30 - port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv, - M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c, + port map (B0=>InitReady, A0=>CmdLEDEN, DI0=>N_74_i, CE=>N_28, + CLK=>RCLK_c, F0=>N_74_i, Q0=>LEDEN); + SLICE_29I: SLICE_29 + port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, A0=>nCRAS_c, DI0=>nCRAS_c_i_0, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c, Q1=>RASr2); + SLICE_31I: SLICE_31 + port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, D0=>Ready, + C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, + CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_0_0); SLICE_32I: SLICE_32 - port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165, - C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036, - LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381); + port map (B1=>Ready_fast, A1=>CROW_c_1, D0=>RCKEEN, C0=>RASr3, B0=>RASr2, + A0=>RASr, DI0=>RCKE_2, M1=>RASr2, CLK=>RCLK_c, F0=>RCKE_2, + Q0=>RCKE_c, F1=>RBAd_0_1, Q1=>RASr3); SLICE_33I: SLICE_33 - port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, - B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, - CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2); + port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>InitReady, C0=>N_158, + B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_414_0, + CLK=>RCLK_c, F0=>N_414_0, Q0=>Ready, F1=>N_158); + SLICE_34I: SLICE_34 + port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_158, A1=>InitReady, + B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_415_0, CLK=>RCLK_c, + F0=>N_415_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa); SLICE_35I: SLICE_35 - port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, - C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121, - CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, - F1=>RCLK_c_enable_10); + port map (B1=>Ready_fast, A1=>MAin_c_1, B0=>Ready_fast, A0=>MAin_c_0, + DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0, + Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1); SLICE_36I: SLICE_36 - port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, - M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2); + port map (B1=>Ready_fast, A1=>MAin_c_3, B0=>Ready_fast, A0=>MAin_c_2, + DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2, + Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3); SLICE_37I: SLICE_37 - port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, - F0=>n2447_002_BUF1, Q0=>Ready); + port map (B1=>Ready_fast, A1=>MAin_c_5, B0=>Ready_fast, A0=>MAin_c_4, + DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4, + Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5); + SLICE_38I: SLICE_38 + port map (B1=>Ready_fast, A1=>MAin_c_7, B0=>Ready_fast, A0=>MAin_c_6, + DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6, + Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7); + SLICE_39I: SLICE_39 + port map (B1=>Ready_fast, A1=>MAin_c_9, B0=>Ready_fast, A0=>MAin_c_8, + DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8, + Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9); + SLICE_40I: SLICE_40 + port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR, B0=>S_1, + A0=>CO0, DI0=>S_0_i_o2_1, LSR=>RASr2, CLK=>RCLK_c, + F0=>S_0_i_o2_1, Q0=>S_1, F1=>nRCAS_0_sqmuxa_1); + SLICE_41I: SLICE_41 + port map (D1=>CmdUFMSDI, C1=>N_145, B1=>UFMSDI_ens2_i_a0, A1=>nUFMCS15, + B0=>nUFMCS15, A0=>UFMSDI_c, DI0=>UFMSDI_RNO, M0=>N_141_i, + CLK=>RCLK_c, OFX0=>UFMSDI_RNO, Q0=>UFMSDI_c); + SLICE_42I: SLICE_42 + port map (D1=>Din_c_7, C1=>Din_c_6, B1=>Din_c_5, A1=>Din_c_4, + D0=>un1_Din_3, C0=>XOR8MEG_3_u_1, B0=>XOR8MEG, A0=>Din_c_0, + DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, + Q0=>XOR8MEG, F1=>un1_Din_3); + SLICE_43I: SLICE_43 + port map (D1=>Bank_4, C1=>Bank_3, B1=>Bank_1, A1=>Bank_0, C0=>UFMSDO_c, + B0=>InitReady, A0=>Cmdn8MEGEN, DI0=>N_131, CE=>N_26, + CLK=>RCLK_c, F0=>N_131, Q0=>n8MEGEN, F1=>un1_Bank_1_4); SLICE_44I: SLICE_44 - port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady, - B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224, - CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, - F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893); + port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, + B0=>N_168, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, + CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_168); SLICE_45I: SLICE_45 - port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady, - B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231, - CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, - F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174); + port map (D1=>UFMCLK_r_i_a2_2_2, C1=>nUFMCS15, B1=>InitReady, + A1=>CmdUFMCS, D0=>nUFMCS_c, C0=>nUFMCS_s_0_m4_yy, B0=>nUFMCS15, + A0=>N_141_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, + F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS_s_0_m4_yy); + SLICE_46I: SLICE_46 + port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>C1WR_3, A1=>ADWR, + D0=>un1_ADWR, C0=>un1_Bank_1, B0=>MAin_c_2, A0=>CMDWR_2, + F0=>un1_CMDWR, F1=>un1_ADWR); + SLICE_47I: SLICE_47 + port map (D1=>N_129, C1=>InitReady, B1=>FS_11, A1=>FS_10, + D0=>d_m3_0_a2_0, C0=>nUFMCS15, B0=>InitReady, A0=>CmdUFMCLK, + F0=>i1_i, F1=>nUFMCS15); + SLICE_48I: SLICE_48 + port map (D1=>N_137_5, C1=>N_137_3, B1=>InitReady, A1=>FS_16, + C0=>UFMCLK_r_i_a2_2_2, B0=>N_50, A0=>InitReady, + F0=>d_m3_0_a2_0, F1=>UFMCLK_r_i_a2_2_2); + SLICE_49I: SLICE_49 + port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>Ready, + B0=>N_154, A0=>N_151, F0=>un1_nRCAS_6_sqmuxa_i_0, F1=>N_151); SLICE_50I: SLICE_50 - port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3, - C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110, - CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110, - Q0=>XOR8MEG, F1=>n2260); + port map (D1=>Din_c_0, C1=>Din_c_5, B1=>Cmdn8MEGEN, A1=>N_45, C0=>N_36, + B0=>Din_c_5, A0=>Din_c_3, F0=>N_45, F1=>Cmdn8MEGEN_4_u_i_0); + SLICE_51I: SLICE_51 + port map (C1=>S_1, B1=>un1_nRCAS_6_sqmuxa_i_0, A1=>CBR, D0=>S_1, + C0=>N_146_i_1, B0=>nRCAS_0_sqmuxa_1, A0=>N_27_i_1, F0=>N_146_i, + F1=>N_146_i_1); + SLICE_52I: SLICE_52 + port map (C1=>IS_1, B1=>IS_2, A1=>IS_3, D0=>IS_0, C0=>N_151, B0=>N_154, + A0=>nRRAS_5_u_i_0, F0=>N_24_i, F1=>N_154); + SLICE_53I: SLICE_53 + port map (D1=>nRWE_s_i_a3_1_0, C1=>nRRAS_0_sqmuxa, B1=>RCKE_c, A1=>RASr2, + C0=>CO0, B0=>S_1, A0=>Ready, F0=>nRRAS_0_sqmuxa, + F1=>nRWE_s_i_tz_0); + SLICE_54I: SLICE_54 + port map (B1=>PHI2r3, A1=>PHI2r2, D0=>un1_PHI2r3_0, C0=>N_140, + B0=>InitReady, A0=>CmdSubmitted, F0=>N_28, F1=>un1_PHI2r3_0); + SLICE_55I: SLICE_55 + port map (C1=>un1_FS_14_i_a2_0_1, B1=>N_139_8, A1=>N_139_6, + D0=>un1_PHI2r3_0, C0=>N_139, B0=>InitReady, A0=>CmdSubmitted, + F0=>N_26, F1=>N_139); + SLICE_56I: SLICE_56 + port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>un1_FS_13_i_a2_1, + B0=>N_139_8, A0=>N_139_6, F0=>N_140, F1=>un1_FS_13_i_a2_1); SLICE_57I: SLICE_57 - port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN, - C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91, - CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91, - Q0=>n8MEGEN, F1=>n2367); + port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, + D0=>un1_Bank_1, C0=>MAin_c_2, B0=>CmdEnable, A0=>CMDWR_2, + F0=>XOR8MEG18, F1=>CmdSubmitted_1_sqmuxa); + SLICE_58I: SLICE_58 + port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, + D0=>UFMSDI_ens2_i_a2_4_2, C0=>N_129, B0=>N_34, A0=>InitReady, + F0=>UFMSDI_ens2_i_a0, F1=>UFMSDI_ens2_i_a2_4_2); SLICE_59I: SLICE_59 - port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142, - D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371, - DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c, - F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166); + port map (C1=>N_129, B1=>InitReady, A1=>FS_8, D0=>N_145, C0=>FS_11, + B0=>FS_9, A0=>FS_4, F0=>N_139_8, F1=>N_145); + SLICE_60I: SLICE_60 + port map (B1=>MAin_c_0, A1=>MAin_c_7, D0=>un1_Bank_1, C0=>MAin_c_1, + B0=>ADWR_3, A0=>ADWR_2, F0=>ADWR, F1=>ADWR_3); SLICE_61I: SLICE_61 - port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c, - C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136, - CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, - F1=>nRCS_N_141); + port map (C1=>S_1, B1=>N_24, A1=>CBR, D0=>nRRAS_5_u_i_0, C0=>N_154, + B0=>N_151, A0=>IS_0, F0=>N_24, F1=>N_27_i_sn); SLICE_62I: SLICE_62 - port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139, - D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137, - DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c, - F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137); + port map (B1=>IS_2, A1=>IS_1, D0=>Ready, C0=>N_153, B0=>N_151, A0=>IS_0, + F0=>nRWE_s_i_a3_1_0, F1=>N_153); + SLICE_63I: SLICE_63 + port map (B1=>nFWE_c, A1=>MAin_c_7, D0=>MAin_c_1, C0=>MAin_c_0, + B0=>C1WR_1, A0=>ADWR_6, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, + F0=>C1WR_3, Q0=>Bank_0, F1=>C1WR_1, Q1=>Bank_1); SLICE_64I: SLICE_64 - port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready, - B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171, - CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, - F1=>n1765); + port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_15, D0=>N_129, + C0=>FS_11, B0=>FS_4, A0=>FS_1, F0=>N_50, F1=>N_129); SLICE_65I: SLICE_65 - port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060, - B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5, - CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060); + port map (B1=>nUFMCS15, A1=>N_141_i, D0=>PHI2r3, C0=>PHI2r2, + B0=>InitReady, A0=>CmdSubmitted, M1=>PHI2r2, M0=>PHI2r, + CLK=>RCLK_c, F0=>N_141_i, Q0=>PHI2r2, F1=>i2_i, Q1=>PHI2r3); SLICE_66I: SLICE_66 - port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32, - A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c, - F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227); + port map (D1=>Ready, C1=>N_27_i_sn, B1=>N_27_i_1, A1=>N_24_i, D0=>FWEr, + C0=>CO0, B0=>CASr3, A0=>CASr2, F0=>N_27_i_1, F1=>N_27_i); SLICE_67I: SLICE_67 - port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406, - LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406, - Q0=>nRowColSel_N_33); + port map (D1=>MAin_c_6, C1=>MAin_c_5, B1=>MAin_c_4, A1=>MAin_c_3, + C0=>nFWE_c, B0=>MAin_c_2, A0=>ADWR_6, F0=>ADWR_2, F1=>ADWR_6); SLICE_68I: SLICE_68 - port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406, - LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287, - Q0=>nRowColSel_N_34, F1=>n13); + port map (B1=>Din_c_5, A1=>Din_c_0, D0=>Din_c_6, C0=>Din_c_2, + B0=>CmdEnable16_4, A0=>CmdEnable16_3, M0=>Din_c_2, CLK=>PHI2_c, + F0=>CmdEnable16_5, Q0=>Bank_2, F1=>CmdEnable16_3); SLICE_69I: SLICE_69 - port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2, - CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379, - Q1=>PHI2r3); + port map (B1=>Bank_7, A1=>Bank_2, D0=>un1_Bank_1_4, C0=>un1_Bank_1_3, + B0=>Bank_6, A0=>Bank_5, F0=>un1_Bank_1, F1=>un1_Bank_1_3); SLICE_70I: SLICE_70 - port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady, - C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199, - CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199, - Q0=>nUFMCS_c, F1=>n64); - i30_SLICE_71I: i30_SLICE_71 - port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, - B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4); + port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>CmdLEDEN, C0=>Din_c_7, + B0=>Din_c_6, A0=>Din_c_4, F0=>N_36, F1=>N_59); + SLICE_71I: SLICE_71 + port map (C1=>CO0, B1=>CASr3, A1=>CASr2, D0=>nRWE_s_i_tz_0, + C0=>nRWE_0io_RNO_1, B0=>nRWE_0io_RNO_0, A0=>nRCAS_0_sqmuxa_1, + F0=>N_147_i, F1=>nRWE_0io_RNO_0); SLICE_72I: SLICE_72 - port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2, - B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292); + port map (D1=>FS_17, C1=>FS_14, B1=>FS_13, A1=>FS_12, D0=>FS_17, + C0=>FS_15, B0=>FS_13, A0=>FS_12, F0=>N_137_5, + F1=>UFMSDI_ens2_i_o2_0_3); SLICE_73I: SLICE_73 - port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2, - C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204, - F1=>PHI2_N_120_enable_8); + port map (D1=>Din_c_7, C1=>Din_c_4, B1=>Din_c_3, A1=>Din_c_1, + D0=>Din_c_7, C0=>Din_c_5, B0=>Din_c_4, A0=>Din_c_1, M0=>CASr2, + CLK=>RCLK_c, F0=>CmdEnable17_5, Q0=>CASr3, F1=>CmdEnable16_4); SLICE_74I: SLICE_74 - port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c, - C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0, - LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26, - Q1=>RowA_1); + port map (D1=>LEDEN, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_1, D0=>Din_c_6, + C0=>Din_c_3, B0=>Din_c_2, A0=>Din_c_0, M0=>nCCAS_c_i, + CLK=>nCRAS_c, F0=>CmdEnable17_4, Q0=>CBR, F1=>XOR8MEG_3_u_1); SLICE_75I: SLICE_75 - port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3, - A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27, - CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177); + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, + A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c); SLICE_76I: SLICE_76 - port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368, - B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, - CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368, - Q1=>RowA_9); + port map (D1=>S_1, C1=>Ready, B1=>FWEr, A1=>CBR, D0=>S_1, C0=>FWEr, + B0=>CO0, A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>nRWE_0io_RNO_1); SLICE_77I: SLICE_77 - port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5, - D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191, - F1=>n2210); + port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, B0=>Ready, + A0=>N_151, F0=>N_48_i, F1=>nRRAS_5_u_i_0); SLICE_78I: SLICE_78 - port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146, - B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729, - CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728, - F1=>nRWE_N_178, Q1=>n727); + port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>FS_9, B0=>FS_7, + A0=>FS_5, F0=>N_34, F1=>un1_FS_14_i_a2_0_1); SLICE_79I: SLICE_79 - port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c, - B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177, - CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2, - Q0=>n730, F1=>n2369, Q1=>n729); + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, + A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c); SLICE_80I: SLICE_80 - port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375, - A0=>n10, F0=>n2366, F1=>n2375); + port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, + B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>RA_c_7); SLICE_81I: SLICE_81 - port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378, - B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727, - CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726, - F1=>n2378, Q1=>Ready_N_296); + port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, + B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_6); SLICE_82I: SLICE_82 - port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6, - A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, - CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6, - Q1=>RowA_5); + port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, + B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_5); SLICE_83I: SLICE_83 - port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1, - C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277, - F1=>PHI2_N_120_enable_3); + port map (C1=>nRowColSel, B1=>RowA_4, A1=>MAin_c_4, C0=>nRowColSel, + B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_4); SLICE_84I: SLICE_84 - port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7, - C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165, - CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15, - Q0=>n738, F1=>n2377, Q1=>n737); + port map (B1=>Ready_fast, A1=>CROW_c_0, D0=>n8MEGEN, C0=>XOR8MEG, + B0=>Ready_fast, A0=>Din_c_6, F0=>RA11d_0, F1=>RBAd_0_0); SLICE_85I: SLICE_85 - port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15, - B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267); - SLICE_86I: SLICE_86 - port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15, - A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7, - Q0=>PHI2r, F1=>n14, Q1=>RASr3); - SLICE_87I: SLICE_87 - port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33, - A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready, - M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6, - Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1); - SLICE_88I: SLICE_88 - port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted, - A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2, - M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237, - Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7); - SLICE_89I: SLICE_89 - port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3, - C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4, - CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4, - F1=>PHI2_N_120_enable_7, Q1=>WRD_5); - SLICE_90I: SLICE_90 - port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7, - C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1, - M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208, - Q1=>WRD_1); - SLICE_91I: SLICE_91 - port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0, - B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, - CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3); - SLICE_92I: SLICE_92 - port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, - D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2, - M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2, - F1=>RCLK_c_enable_27, Q1=>WRD_3); - SLICE_93I: SLICE_93 - port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, - A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9, - Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1); - SLICE_94I: SLICE_94 - port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35, - C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5, - F1=>n2372); - SLICE_95I: SLICE_95 - port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1, - B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7); - SLICE_96I: SLICE_96 - port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR, - F0=>nRCS_N_146, F1=>n2376); - SLICE_97I: SLICE_97 - port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2, - A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27, - CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733); - SLICE_98I: SLICE_98 - port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8, - A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296, - CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139, - F1=>RDQMH_c, Q1=>nRCAS_N_165); - SLICE_99I: SLICE_99 - port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7, - C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0, - CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7, - Q0=>CmdUFMSDI, F1=>n22); - SLICE_100I: SLICE_100 - port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6, - C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2, - M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6, - Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS); - SLICE_101I: SLICE_101 - port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, - B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6, - CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7); - SLICE_102I: SLICE_102 - port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, - B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4, - CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5); - SLICE_103I: SLICE_103 - port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, - B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2, - CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3); - SLICE_104I: SLICE_104 - port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369, - M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, - F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7); - SLICE_105I: SLICE_105 - port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12, - A0=>FS_13, F0=>n12, F1=>n4); - SLICE_106I: SLICE_106 - port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736, - M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228, - Q0=>n736, F1=>n2382, Q1=>n735); - RD_7_I: RD_7_B - port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); - RD_6_I: RD_6_B - port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); - RD_5_I: RD_5_B - port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); - RD_4_I: RD_4_B - port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); - RD_3_I: RD_3_B - port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); - RD_2_I: RD_2_B - port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); - RD_1_I: RD_1_B - port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + port map (D1=>FS_10, C1=>FS_7, B1=>FS_6, A1=>FS_1, B0=>FS_14, A0=>FS_11, + F0=>N_137_3, F1=>N_139_6); RD_0_I: RD_0_B - port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); - Dout_7_I: Dout_7_B - port map (PADDO=>Dout_c, Dout7=>Dout(7)); - Dout_6_I: Dout_6_B - port map (PADDO=>Dout_0S, Dout6=>Dout(6)); - Dout_5_I: Dout_5_B - port map (PADDO=>Dout_1S, Dout5=>Dout(5)); - Dout_4_I: Dout_4_B - port map (PADDO=>Dout_2S, Dout4=>Dout(4)); - Dout_3_I: Dout_3_B - port map (PADDO=>Dout_3S, Dout3=>Dout(3)); - Dout_2_I: Dout_2_B - port map (PADDO=>Dout_4S, Dout2=>Dout(2)); - Dout_1_I: Dout_1_B - port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + port map (IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0)); + RD_0_MGIOLI: RD_0_MGIOL + port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c); Dout_0_I: Dout_0_B - port map (PADDO=>Dout_6S, Dout0=>Dout(0)); - LEDI: LEDB - port map (PADDO=>LED_c, LEDS=>LED); - RBA_1_I: RBA_1_B - port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); - RBA_0_I: RBA_0_B - port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); - RA_11_I: RA_11_B - port map (PADDO=>RA_c, RA11=>RA(11)); - RA_10_I: RA_10_B - port map (PADDO=>RA_0S, RA10=>RA(10)); - RA_9_I: RA_9_B - port map (PADDO=>RA_1_9, RA9=>RA(9)); - RA_8_I: RA_8_B - port map (PADDO=>RA_1_8, RA8=>RA(8)); - RA_7_I: RA_7_B - port map (PADDO=>RA_1_7, RA7=>RA(7)); - RA_6_I: RA_6_B - port map (PADDO=>RA_1_6, RA6=>RA(6)); - RA_5_I: RA_5_B - port map (PADDO=>RA_1_5, RA5=>RA(5)); - RA_4_I: RA_4_B - port map (PADDO=>RA_1_4, RA4=>RA(4)); - RA_3_I: RA_3_B - port map (PADDO=>RA_1_3, RA3=>RA(3)); - RA_2_I: RA_2_B - port map (PADDO=>RA_1_2, RA2=>RA(2)); - RA_1_I: RA_1_B - port map (PADDO=>RA_1_1, RA1=>RA(1)); - RA_0_I: RA_0_B - port map (PADDO=>RA_1_0, RA0=>RA(0)); - nRCSI: nRCSB - port map (PADDO=>nRCS_c, nRCSS=>nRCS); - RCKEI: RCKEB - port map (PADDO=>RCKE_c, RCKES=>RCKE); - nRWEI: nRWEB - port map (PADDO=>nRWE_c, nRWES=>nRWE); - nRRASI: nRRASB - port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); - nRCASI: nRCASB - port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); - RDQMHI: RDQMHB - port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); - RDQMLI: RDQMLB - port map (PADDO=>RDQML_c, RDQMLS=>RDQML); - nUFMCSI: nUFMCSB - port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); - UFMCLKI: UFMCLKB - port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); - UFMSDII: UFMSDIB - port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + port map (PADDO=>MAin_c_3, Dout0=>Dout(0)); PHI2I: PHI2B port map (PADDI=>PHI2_c, PHI2S=>PHI2); + PHI2_MGIOLI: PHI2_MGIOL + port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + UFMSDII: UFMSDIB + port map (IOLDO=>UFMSDI_c_n0, UFMSDIS=>UFMSDI); + UFMSDI_MGIOLI: UFMSDI_MGIOL + port map (IOLDO=>UFMSDI_c_n0, OPOS=>UFMSDI_RNO, CLK=>RCLK_c); + UFMCLKI: UFMCLKB + port map (IOLDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMCLK_MGIOLI: UFMCLK_MGIOL + port map (IOLDO=>UFMCLK_c, OPOS=>i1_i, CE=>i2_i, CLK=>RCLK_c); + nUFMCSI: nUFMCSB + port map (IOLDO=>nUFMCS_c_n1, nUFMCSS=>nUFMCS); + nUFMCS_MGIOLI: nUFMCS_MGIOL + port map (IOLDO=>nUFMCS_c_n1, OPOS=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + nRCASI: nRCASB + port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS); + nRCAS_MGIOLI: nRCAS_MGIOL + port map (IOLDO=>nRCAS_c, OPOS=>N_146_i, CLK=>RCLK_c); + nRRASI: nRRASB + port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS); + nRRAS_MGIOLI: nRRAS_MGIOL + port map (IOLDO=>nRRAS_c, OPOS=>N_24_i, CLK=>RCLK_c); + nRWEI: nRWEB + port map (IOLDO=>nRWE_c, nRWES=>nRWE); + nRWE_MGIOLI: nRWE_MGIOL + port map (IOLDO=>nRWE_c, OPOS=>N_147_i, CLK=>RCLK_c); + RCKEI: RCKEB + port map (IOLDO=>RCKE_c_n2, RCKES=>RCKE); + RCKE_MGIOLI: RCKE_MGIOL + port map (IOLDO=>RCKE_c_n2, OPOS=>RCKE_2, CLK=>RCLK_c); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + nRCSI: nRCSB + port map (IOLDO=>nRCS_c, nRCSS=>nRCS); + nRCS_MGIOLI: nRCS_MGIOL + port map (IOLDO=>nRCS_c, OPOS=>N_27_i, CLK=>RCLK_c); + RD_7_I: RD_7_B + port map (IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7)); + RD_7_MGIOLI: RD_7_MGIOL + port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c); + RD_6_I: RD_6_B + port map (IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6)); + RD_6_MGIOLI: RD_6_MGIOL + port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c); + RD_5_I: RD_5_B + port map (IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5)); + RD_5_MGIOLI: RD_5_MGIOL + port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c); + RD_4_I: RD_4_B + port map (IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4)); + RD_4_MGIOLI: RD_4_MGIOL + port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c); + RD_3_I: RD_3_B + port map (IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3)); + RD_3_MGIOLI: RD_3_MGIOL + port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c); + RD_2_I: RD_2_B + port map (IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2)); + RD_2_MGIOLI: RD_2_MGIOL + port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c); + RD_1_I0: RD_1_B + port map (IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1)); + RD_1_MGIOLI: RD_1_MGIOL + port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c); + RA_11_I: RA_11_B + port map (IOLDO=>RA_c_11, RA11=>RA(11)); + RA_11_MGIOLI: RA_11_MGIOL + port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c); + RA_10_I: RA_10_B + port map (IOLDO=>RA_c_10, RA10=>RA(10)); + RA_10_MGIOLI: RA_10_MGIOL + port map (IOLDO=>RA_c_10, OPOS=>N_153, LSR=>RA10s_i, CLK=>RCLK_c); + RA_9_I: RA_9_B + port map (PADDO=>RA_c_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_c_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_c_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_c_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_c_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_c_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_c_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_c_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_c_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_c_0, RA0=>RA(0)); + RBA_1_I: RBA_1_B + port map (IOLDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_1_MGIOLI: RBA_1_MGIOL + port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c); + RBA_0_I: RBA_0_B + port map (IOLDO=>RBA_c_0, RBA0=>RBA(0)); + RBA_0_MGIOLI: RBA_0_MGIOL + port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + Dout_7_I: Dout_7_B + port map (PADDO=>nCRAS_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>MAin_c_9, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>MAin_c_8, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>MAin_c_7, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>MAin_c_6, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>MAin_c_5, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>MAin_c_4, Dout1=>Dout(1)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_7_MGIOLI: Din_7_MGIOL + port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_6_MGIOLI: Din_6_MGIOL + port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_5_MGIOLI: Din_5_MGIOL + port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_4_MGIOLI: Din_4_MGIOL + port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_3_MGIOLI: Din_3_MGIOL + port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_2_MGIOLI: Din_2_MGIOL + port map (DI=>Din_c_2, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, + INP=>CmdUFMCS); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_1_MGIOLI: Din_1_MGIOL + port map (DI=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, + INP=>CmdUFMCLK); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + Din_0_MGIOLI: Din_0_MGIOL + port map (DI=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, + INP=>CmdUFMSDI); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); MAin_9_I: MAin_9_B port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); MAin_8_I: MAin_8_B @@ -26338,36 +27804,6 @@ port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); MAin_0_I: MAin_0_B port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); - CROW_1_I: CROW_1_B - port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); - CROW_0_I: CROW_0_B - port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); - Din_7_I: Din_7_B - port map (PADDI=>Din_c_7, Din7=>Din(7)); - Din_6_I: Din_6_B - port map (PADDI=>Din_c_6, Din6=>Din(6)); - Din_5_I: Din_5_B - port map (PADDI=>Din_c_5, Din5=>Din(5)); - Din_4_I: Din_4_B - port map (PADDI=>Din_c_4, Din4=>Din(4)); - Din_3_I: Din_3_B - port map (PADDI=>Din_c_3, Din3=>Din(3)); - Din_2_I: Din_2_B - port map (PADDI=>Din_c_2, Din2=>Din(2)); - Din_1_I: Din_1_B - port map (PADDI=>Din_c_1, Din1=>Din(1)); - Din_0_I: Din_0_B - port map (PADDI=>Din_c_0, Din0=>Din(0)); - nCCASI: nCCASB - port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); - nCRASI: nCRASB - port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); - nFWEI: nFWEB - port map (PADDI=>nFWE_c, nFWES=>nFWE); - RCLKI: RCLKB - port map (PADDI=>RCLK_c, RCLKS=>RCLK); - UFMSDOI: UFMSDOB - port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); VHI_INST: VHI port map (Z=>VCCI); PUR_INST: PUR diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf index 76a02d9..593060e 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2GS") - (DATE "Tue Aug 15 05:03:26 2023") + (DATE "Tue Aug 15 22:56:32 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") @@ -17,19 +17,11 @@ (ABSOLUTE (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) ) ) (TIMINGCHECK (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -41,20 +33,12 @@ (INSTANCE SLICE_1) (DELAY (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) ) ) (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK @@ -147,13 +131,19 @@ (ABSOLUTE (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) ) ) (TIMINGCHECK (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -191,12 +181,20 @@ (INSTANCE SLICE_7) (DELAY (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) ) ) (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) ) (TIMINGCHECK @@ -261,7 +259,6 @@ (INSTANCE SLICE_10) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -273,27 +270,22 @@ ) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) (TIMINGCHECK (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) ) ) (CELL - (CELLTYPE "SLICE_15") - (INSTANCE SLICE_15) + (CELLTYPE "SLICE_13") + (INSTANCE SLICE_13) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -301,21 +293,20 @@ ) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) (TIMINGCHECK (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) ) ) (CELL - (CELLTYPE "SLICE_16") - (INSTANCE SLICE_16) + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) (DELAY (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) @@ -330,12 +321,59 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_17") + (INSTANCE SLICE_17) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18) + (DELAY + (ABSOLUTE + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) (CELL (CELLTYPE "SLICE_19") (INSTANCE SLICE_19) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -360,6 +398,12 @@ (INSTANCE SLICE_20) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -369,18 +413,16 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) ) ) (CELL - (CELLTYPE "SLICE_24") - (INSTANCE SLICE_24) + (CELLTYPE "SLICE_21") + (INSTANCE SLICE_21) (DELAY (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -397,16 +439,16 @@ ) ) (CELL - (CELLTYPE "SLICE_25") - (INSTANCE SLICE_25) + (CELLTYPE "SLICE_22") + (INSTANCE SLICE_22) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK @@ -415,119 +457,11 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) ) ) (CELL - (CELLTYPE "SLICE_26") - (INSTANCE SLICE_26) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_27") - (INSTANCE SLICE_27) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_30") - (INSTANCE SLICE_30) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_32") - (INSTANCE SLICE_32) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_33") - (INSTANCE SLICE_33) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_35") - (INSTANCE SLICE_35) + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) @@ -542,6 +476,29 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) ) (TIMINGCHECK @@ -550,8 +507,8 @@ ) ) (CELL - (CELLTYPE "SLICE_36") - (INSTANCE SLICE_36) + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) (DELAY (ABSOLUTE (IOPATH D0 F0 (367:431:495)(367:431:495)) @@ -559,6 +516,116 @@ (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_29") + (INSTANCE SLICE_29) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) @@ -571,11 +638,246 @@ (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) (CELL (CELLTYPE "SLICE_37") (INSTANCE SLICE_37) (DELAY (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_38") + (INSTANCE SLICE_38) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_39") + (INSTANCE SLICE_39) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + ) + ) + (CELL + (CELLTYPE "SLICE_40") + (INSTANCE SLICE_40) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_41") + (INSTANCE SLICE_41) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (457:589:721)(457:589:721)) + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_42") + (INSTANCE SLICE_42) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) @@ -597,6 +899,7 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -605,7 +908,6 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK @@ -633,22 +935,95 @@ ) (TIMINGCHECK (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) ) + (CELL + (CELLTYPE "SLICE_46") + (INSTANCE SLICE_46) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_47") + (INSTANCE SLICE_47) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_48") + (INSTANCE SLICE_48) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) (CELL (CELLTYPE "SLICE_50") (INSTANCE SLICE_50) (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_51") + (INSTANCE SLICE_51) + (DELAY + (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -656,16 +1031,81 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (CELL + (CELLTYPE "SLICE_52") + (INSTANCE SLICE_52) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + (CELL + (CELLTYPE "SLICE_53") + (INSTANCE SLICE_53) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_54") + (INSTANCE SLICE_54) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_55") + (INSTANCE SLICE_55) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) ) ) (CELL @@ -681,16 +1121,23 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) ) ) (CELL @@ -698,7 +1145,6 @@ (INSTANCE SLICE_59) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -706,16 +1152,21 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) ) ) (CELL @@ -723,31 +1174,6 @@ (INSTANCE SLICE_61) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_62") - (INSTANCE SLICE_62) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -755,12 +1181,41 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -772,23 +1227,15 @@ (INSTANCE SLICE_64) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_65") @@ -802,11 +1249,12 @@ (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) ) (TIMINGCHECK (WIDTH (posedge CLK) (1250:1250:1250)) @@ -818,44 +1266,31 @@ (INSTANCE SLICE_66) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_67") (INSTANCE SLICE_67) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_68") @@ -864,6 +1299,8 @@ (ABSOLUTE (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) @@ -871,11 +1308,8 @@ ) (TIMINGCHECK (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) @@ -887,19 +1321,12 @@ (ABSOLUTE (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_70") @@ -907,6 +1334,20 @@ (DELAY (ABSOLUTE (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_71") + (INSTANCE SLICE_71) + (DELAY + (ABSOLUTE (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -914,31 +1355,6 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "i30_SLICE_71") - (INSTANCE i30\/SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH D0 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) ) ) ) @@ -951,6 +1367,8 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -969,8 +1387,16 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) ) ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) ) (CELL (CELLTYPE "SLICE_74") @@ -986,19 +1412,14 @@ (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) (WIDTH (posedge CLK) (1250:1250:1250)) (WIDTH (negedge CLK) (1250:1250:1250)) ) (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) ) ) (CELL @@ -1006,31 +1427,20 @@ (INSTANCE SLICE_75) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_76") (INSTANCE SLICE_76) (DELAY (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) @@ -1038,21 +1448,8 @@ (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) - ) ) (CELL (CELLTYPE "SLICE_77") @@ -1063,8 +1460,6 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) @@ -1079,56 +1474,33 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_79") (INSTANCE SLICE_79) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_80") (INSTANCE SLICE_80) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1140,63 +1512,37 @@ (INSTANCE SLICE_81) (DELAY (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_82") (INSTANCE SLICE_82) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) - ) ) (CELL (CELLTYPE "SLICE_83") (INSTANCE SLICE_83) (DELAY (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) @@ -1208,26 +1554,14 @@ (INSTANCE SLICE_84) (DELAY (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) (IOPATH D0 F0 (367:431:495)(367:431:495)) (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) ) ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) ) (CELL (CELLTYPE "SLICE_85") @@ -1238,685 +1572,36 @@ (IOPATH C1 F1 (367:431:495)(367:431:495)) (IOPATH B1 F1 (367:431:495)(367:431:495)) (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) (IOPATH B0 F0 (367:431:495)(367:431:495)) (IOPATH A0 F0 (367:431:495)(367:431:495)) ) ) ) - (CELL - (CELLTYPE "SLICE_86") - (INSTANCE SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_87") - (INSTANCE SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) - ) - ) - (CELL - (CELLTYPE "SLICE_88") - (INSTANCE SLICE_88) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_89") - (INSTANCE SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_90") - (INSTANCE SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_91") - (INSTANCE SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) - ) - ) - (CELL - (CELLTYPE "SLICE_92") - (INSTANCE SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - ) - ) - (CELL - (CELLTYPE "SLICE_93") - (INSTANCE SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_94") - (INSTANCE SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_95") - (INSTANCE SLICE_95) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_96") - (INSTANCE SLICE_96) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_97") - (INSTANCE SLICE_97) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_98") - (INSTANCE SLICE_98) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_99") - (INSTANCE SLICE_99) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) - (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) - ) - ) - (CELL - (CELLTYPE "SLICE_100") - (INSTANCE SLICE_100) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - 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(TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7__MGIOL") + (INSTANCE Din\[7\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6__MGIOL") + (INSTANCE Din\[6\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5__MGIOL") + (INSTANCE Din\[5\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4__MGIOL") + (INSTANCE Din\[4\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3__MGIOL") + (INSTANCE Din\[3\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2__MGIOL") + (INSTANCE Din\[2\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223)) + (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1__MGIOL") + (INSTANCE Din\[1\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223)) + (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0__MGIOL") + (INSTANCE Din\[0\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223)) + (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52)) ) ) (CELL @@ -2301,7 +2618,7 @@ (INSTANCE CROW\[1\]_I) (DELAY (ABSOLUTE - (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH CROW1 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK @@ -2314,7 +2631,7 @@ (INSTANCE CROW\[0\]_I) (DELAY (ABSOLUTE - (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH CROW0 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK @@ -2323,172 +2640,133 @@ ) ) (CELL - (CELLTYPE "Din_7_") - (INSTANCE Din\[7\]_I) + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) (DELAY (ABSOLUTE - (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin9 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din7) (3330:3330:3330)) - (WIDTH (negedge Din7) (3330:3330:3330)) + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_6_") - (INSTANCE Din\[6\]_I) + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) (DELAY (ABSOLUTE - (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin8 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din6) (3330:3330:3330)) - (WIDTH (negedge Din6) (3330:3330:3330)) + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_5_") - (INSTANCE Din\[5\]_I) + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) (DELAY (ABSOLUTE - (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin7 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din5) (3330:3330:3330)) - (WIDTH (negedge Din5) (3330:3330:3330)) + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_4_") - (INSTANCE Din\[4\]_I) + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) (DELAY (ABSOLUTE - (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din4) (3330:3330:3330)) - (WIDTH (negedge Din4) (3330:3330:3330)) + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_3_") - (INSTANCE Din\[3\]_I) + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) (DELAY (ABSOLUTE - (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin5 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din3) (3330:3330:3330)) - (WIDTH (negedge Din3) (3330:3330:3330)) + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_2_") - (INSTANCE Din\[2\]_I) + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) (DELAY (ABSOLUTE - (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin4 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din2) (3330:3330:3330)) - (WIDTH (negedge Din2) (3330:3330:3330)) + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_1_") - (INSTANCE Din\[1\]_I) + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) (DELAY (ABSOLUTE - (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin3 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din1) (3330:3330:3330)) - (WIDTH (negedge Din1) (3330:3330:3330)) + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "Din_0_") - (INSTANCE Din\[0\]_I) + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) (DELAY (ABSOLUTE - (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin2 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge Din0) (3330:3330:3330)) - (WIDTH (negedge Din0) (3330:3330:3330)) + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "nCCAS") - (INSTANCE nCCAS_I) + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) (DELAY (ABSOLUTE - (IOPATH nCCAS PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge nCCAS) (3330:3330:3330)) - (WIDTH (negedge nCCAS) (3330:3330:3330)) + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) ) ) (CELL - (CELLTYPE "nCRAS") - (INSTANCE nCRAS_I) + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) (DELAY (ABSOLUTE - (IOPATH nCRAS PADDI (1223:1297:1372)(1223:1297:1372)) + (IOPATH MAin0 PADDI (1007:1069:1132)(1007:1069:1132)) ) ) (TIMINGCHECK - (WIDTH (posedge nCRAS) (3330:3330:3330)) - (WIDTH (negedge nCRAS) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nFWE") - (INSTANCE nFWE_I) - (DELAY - (ABSOLUTE - (IOPATH nFWE PADDI (1223:1297:1372)(1223:1297:1372)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nFWE) (3330:3330:3330)) - (WIDTH (negedge nFWE) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "RCLK") - (INSTANCE RCLK_I) - (DELAY - (ABSOLUTE - (IOPATH RCLK PADDI (1223:1297:1372)(1223:1297:1372)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge RCLK) (3330:3330:3330)) - (WIDTH (negedge RCLK) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "UFMSDO") - (INSTANCE UFMSDO_I) - (DELAY - (ABSOLUTE - (IOPATH UFMSDO PADDI (1223:1297:1372)(1223:1297:1372)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge UFMSDO) (3330:3330:3330)) - (WIDTH (negedge UFMSDO) (3330:3330:3330)) + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) ) ) (CELL @@ -2497,15 +2775,9 @@ (DELAY (ABSOLUTE (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_76/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_82/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 SLICE_85/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_85/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_56/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_78/A1 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) @@ -2516,660 +2788,695 @@ (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) - (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_73/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI UFMSDI_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI UFMCLK_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nUFMCS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI RCKE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_76/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_85/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_105/B0 (0:0:0)(0:0:0)) (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_76/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_85/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT 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Din\[7\]_I/PADDI SLICE_42/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI Din\[7\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_42/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_68/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_42/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42/F1 SLICE_42/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_42/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42/Q0 SLICE_42/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42/Q0 SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_42/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_63/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_43/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q1 SLICE_43/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_43/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55/F0 SLICE_43/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F1 SLICE_69/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/Q0 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/Q0 SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_53/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_53/F0 SLICE_53/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_80/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_81/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_82/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_48/F1 SLICE_45/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_48/F1 SLICE_48/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_45/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/Q0 SLICE_45/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 nUFMCS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_47/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_58/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_59/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_48/F0 SLICE_47/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_47/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_47/F0 UFMCLK_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_48/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52/F1 SLICE_49/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52/F1 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F0 SLICE_51/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F0 SLICE_50/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_51/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_51/F0 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_52/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52/F0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_52/F0 nRRAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_53/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_53/F1 SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q1 SLICE_54/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_54/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54/F1 SLICE_54/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_54/F1 SLICE_55/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_54/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_55/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_55/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_55/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_56/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55/F1 SLICE_55/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/F1 SLICE_58/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_58/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_60/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_66/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F1 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_MGIOL/IN SLICE_65/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 UFMCLK_MGIOL/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 nRCS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_71/F1 SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_71/F0 nRWE_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 RBA\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDI_MGIOL/IOLDO UFMSDI_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT UFMCLK_MGIOL/IOLDO UFMCLK_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nUFMCS_MGIOL/IOLDO nUFMCS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RCKE_MGIOL/IOLDO RCKE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (0:0:0)(0:0:0)) ) ) ) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo index 49fcc79..c0bd4e2 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd -// Netlist created on Tue Aug 15 05:03:24 2023 -// Netlist written on Tue Aug 15 05:03:26 2023 +// Netlist created on Tue Aug 15 22:56:31 2023 +// Netlist written on Tue Aug 15 22:56:32 2023 // Design is for device LCMXO2-640HC // Design is for package TQFP100 // Design is for performance grade 4 @@ -22,377 +22,426 @@ module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, output LED; output [1:0] RBA; output [11:0] RA; + output [7:0] RD; output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; - inout [7:0] RD; - wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84, - n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90, - n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3, - FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16, - FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225, - n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237, - PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1, - C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254, - Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248, - PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7, - CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, - PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR, - \n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447, - RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2, - nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036, - nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3, - n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10, - RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292, - n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c, - n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2, - XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367, - n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371, - nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c, - n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171, - RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376, - n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406, - Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199, - nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0, - PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1, - n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8, - RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730, - n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377, - n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, - n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3, - RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734, - n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7, - MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3, - RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4, - Dout_5, Dout_6, VCCI; + wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , + \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , + CmdEnable17_5, CmdEnable17_4, ADWR, CmdEnable16, CmdEnable17, + un1_ADWR, ADSubmitted, ADSubmitted_r, PHI2_c, un1_Bank_1, \MAin_c[2] , + CmdEnable16_5, C1WR_3, C1Submitted, C1Submitted_s, nFWE_c, nCCAS_c, + nCCAS_c_i, CASr, RD_1_i, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_166_i, + Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, N_36, + \Din_c[5] , \Din_c[1] , N_94, N_60, N_59, LEDEN, N_14_i, XOR8MEG18, + CmdLEDEN, \Din_c[3] , CmdSubmitted, CmdSubmitted_1_sqmuxa, N_412_0, + CmdUFMCLK_1_sqmuxa, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, Cmdn8MEGEN, + \MAin_c[1] , ADWR_6, ADWR_3, nFWE_c_i, nCRAS_c, FWEr, CMDWR_2, Ready, + N_151, \IS[0] , N_60_i_i, RA10s_i, \IS[2] , \IS[1] , N_180_i, + IS_n1_0_x2, N_48_i, N_58_i_i, N_137_5, N_137_3, InitReady, InitReady3, + N_413_0, N_74_i, N_28, CBR, nCRAS_c_i_0, RASr, LED_c, \S_0_i_o2[1] , + RCKEEN_8_u_1_0, RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, Ready_fast, + \CROW_c[1] , RASr3, RCKE_2, RCKE_c, \RBAd_0[1] , N_158, N_414_0, + Ready_0_sqmuxa, N_415_0, \MAin_c[0] , \RowAd_0[1] , \RowAd_0[0] , + \RowA[0] , \RowA[1] , \MAin_c[3] , \RowAd_0[3] , \RowAd_0[2] , + \RowA[2] , \RowA[3] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , + \RowAd_0[4] , \RowA[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , + \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , + \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , + nRCAS_0_sqmuxa_1, CmdUFMSDI, N_145, UFMSDI_ens2_i_a0, nUFMCS15, + UFMSDI_c, UFMSDI_RNO, N_141_i, \Din_c[7] , \Din_c[6] , \Din_c[4] , + un1_Din_3, XOR8MEG_3_u_1, XOR8MEG, \Din_c[0] , XOR8MEG_3, \Bank[4] , + \Bank[3] , \Bank[1] , \Bank[0] , UFMSDO_c, N_131, N_26, un1_Bank_1_4, + CASr3, N_168, nRowColSel_0_0, nRRAS_0_sqmuxa, nRowColSel, + UFMCLK_r_i_a2_2_2, CmdUFMCS, nUFMCS_c, nUFMCS_s_0_m4_yy, + nUFMCS_s_0_N_5_i, N_129, d_m3_0_a2_0, CmdUFMCLK, i1_i, N_50, N_154, + un1_nRCAS_6_sqmuxa_i_0, N_45, N_146_i_1, N_27_i_1, N_146_i, + nRRAS_5_u_i_0, N_24_i, nRWE_s_i_a3_1_0, nRWE_s_i_tz_0, PHI2r3, PHI2r2, + un1_PHI2r3_0, N_140, un1_FS_14_i_a2_0_1, N_139_8, N_139_6, N_139, + un1_FS_13_i_a2_1, UFMSDI_ens2_i_a2_4_2, N_34, ADWR_2, N_24, N_27_i_sn, + N_153, C1WR_1, UFMSDI_ens2_i_o2_0_3, PHI2r, i2_i, N_27_i, \Din_c[2] , + CmdEnable16_4, CmdEnable16_3, \Bank[2] , \Bank[7] , un1_Bank_1_3, + \Bank[6] , \Bank[5] , nRWE_0io_RNO_1, nRWE_0io_RNO_0, N_147_i, + \RA_c[9] , RDQML_c, \RA_c[8] , RDQMH_c, \RA_c[0] , \RA_c[7] , + \RA_c[1] , \RA_c[6] , \RA_c[2] , \RA_c[5] , \RA_c[3] , \RA_c[4] , + \CROW_c[0] , RA11d_0, \RBAd_0[0] , \WRD[0] , \UFMSDI_c$n0 , UFMCLK_c, + \nUFMCS_c$n1 , nRCAS_c, nRRAS_c, nRWE_c, \RCKE_c$n2 , nRCS_c, + \WRD[7] , \WRD[6] , \WRD[5] , \WRD[4] , \WRD[3] , \WRD[2] , \WRD[1] , + \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI; - SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c), - .FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999)); - SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c), - .FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998)); - SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c), - .FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996)); - SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c), - .FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995)); - SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c), - .FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993)); - SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3), - .F1(n95), .Q1(FS_0), .FCO(n1992)); - SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c), - .FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997)); - SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78), - .Q0(FS_17)); - SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c), - .FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994)); - SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c), - .FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000)); - SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7), - .D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246), - .CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c), - .F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8)); - SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), - .D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398), - .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted), - .F1(n2365)); - SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c), - .F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2)); - SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183), - .D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363), - .DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), - .F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1)); - SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7), - .CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted)); - SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), - .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), - .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), - .Q0(Cmdn8MEGEN), .F1(n1314)); - SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c), - .DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr), - .F1(n2180), .Q1(CBR)); - SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28), - .CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady)); - SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c), - .F0(n2447), .Q0(LEDEN)); - SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), - .DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr), + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c), + .FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] )); + SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ), + .DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), + .Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] )); + SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_10 SLICE_10( .C1(CmdEnable17_5), .B1(CmdEnable17_4), .A1(ADWR), + .D0(CmdEnable16), .C0(CmdEnable17), .B0(un1_ADWR), .A0(ADSubmitted), + .DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted), + .F1(CmdEnable17)); + SLICE_13 SLICE_13( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(CmdEnable16_5), + .A1(C1WR_3), .C0(CmdEnable16), .B0(un1_ADWR), .A0(C1Submitted), + .DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted), + .F1(CmdEnable16)); + SLICE_14 SLICE_14( .B1(nFWE_c), .A1(nCCAS_c), .A0(nCCAS_c), .DI0(nCCAS_c_i), + .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .F1(RD_1_i), + .Q1(CASr2)); + SLICE_17 SLICE_17( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), + .B0(\S[1] ), .A0(CO0), .DI0(N_166_i), .LSR(RASr2), .CLK(RCLK_c), + .F0(N_166_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2)); + SLICE_18 SLICE_18( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), + .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), + .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable)); + SLICE_19 SLICE_19( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[1] ), .D0(N_94), + .C0(N_60), .B0(N_59), .A0(LEDEN), .DI0(N_14_i), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), .F1(N_60)); + SLICE_20 SLICE_20( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), + .DI0(N_412_0), .CLK(PHI2_c), .F0(N_412_0), .Q0(CmdSubmitted), + .F1(CmdUFMCLK_1_sqmuxa)); + SLICE_21 SLICE_21( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(n8MEGEN), + .B0(N_94), .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18), + .CLK(PHI2_c), .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(N_94)); + SLICE_22 SLICE_22( .D1(nFWE_c), .C1(\MAin_c[1] ), .B1(ADWR_6), .A1(ADWR_3), + .A0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), + .F1(CMDWR_2)); + SLICE_23 SLICE_23( .D1(Ready), .C1(N_151), .B1(\IS[3] ), .A1(\IS[0] ), + .C0(Ready), .B0(N_151), .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), + .F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i)); + SLICE_24 SLICE_24( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), + .A0(\IS[0] ), .DI1(N_180_i), .DI0(IS_n1_0_x2), .CE(N_48_i), .CLK(RCLK_c), + .F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_180_i), .Q1(\IS[2] )); + SLICE_25 SLICE_25( .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), + .DI0(N_58_i_i), .CE(N_48_i), .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] )); + SLICE_26 SLICE_26( .D1(N_137_5), .C1(N_137_3), .B1(\FS[16] ), .A1(\FS[10] ), + .B0(InitReady), .A0(InitReady3), .DI0(N_413_0), .CLK(RCLK_c), .F0(N_413_0), + .Q0(InitReady), .F1(InitReady3)); + SLICE_27 SLICE_27( .B0(InitReady), .A0(CmdLEDEN), .DI0(N_74_i), .CE(N_28), + .CLK(RCLK_c), .F0(N_74_i), .Q0(LEDEN)); + SLICE_29 SLICE_29( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), + .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), .F1(LED_c), .Q1(RASr2)); - SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2), - .D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036), - .LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381)); - SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), - .B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), - .F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2)); - SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2), - .A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady), - .DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121), - .Q0(RCKEEN), .F1(RCLK_c_enable_10)); - SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr), - .DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c), - .Q1(PHI2r2)); - SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c), - .F0(\n2447\002/BUF1 ), .Q0(Ready)); - SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4), - .C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224), - .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224), - .Q0(UFMCLK_c), .F1(n1893)); - SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4), - .C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231), - .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231), - .Q0(UFMSDI_c), .F1(n2174)); - SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4), - .D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110), - .CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), - .F1(n2260)); - SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10), - .D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady), - .DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91), - .Q0(n8MEGEN), .F1(n2367)); - SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2), - .A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165), - .A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c), - .F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166)); - SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2), - .A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137), - .DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136), - .Q0(nRCS_c), .F1(nRCS_N_141)); - SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady), - .A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379), - .A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c), - .F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137)); - SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready), - .B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5), - .CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765)); - SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376), - .C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5), - .CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060)); - SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32), - .A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827), - .Q0(nRowColSel_N_32), .F1(n2227)); - SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406), - .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33)); - SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6), - .M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287), - .Q0(nRowColSel_N_34), .F1(n13)); - SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374), - .M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379), - .Q1(PHI2r3)); - SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11), - .D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6), - .DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199), - .Q0(nUFMCS_c), .F1(n64)); - i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR), - .D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR), - .M0(nRowColSel_N_35), .OFX0(n15_adj_4)); - SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3), - .A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3), - .F1(Ready_N_292)); - SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369), - .D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204), - .F1(PHI2_N_120_enable_8)); - SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2), - .D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1), - .M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0), - .F1(n26), .Q1(RowA_1)); - SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5), - .B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27), - .CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177)); - SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady), - .C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8), - .LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368), - .Q1(RowA_9)); - SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5), - .D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191), - .F1(n2210)); - SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060), - .A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729), - .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728), - .F1(nRWE_N_178), .Q1(n727)); - SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1), - .C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177), - .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730), - .F1(n2369), .Q1(n729)); - SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady), - .B0(n2375), .A0(n10), .F0(n2366), .F1(n2375)); - SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378), - .B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727), - .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726), - .F1(n2378), .Q1(Ready_N_296)); - SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11), - .B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), - .CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6), - .Q1(RowA_5)); - SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228), - .D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277), - .F1(PHI2_N_120_enable_3)); - SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3), - .D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738), - .M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c), - .F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737)); - SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16), - .C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267)); - SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13), - .B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7), - .Q0(PHI2r), .F1(n14), .Q1(RASr3)); - SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33), - .A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1), - .M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0), - .F1(RCLK_c_enable_6), .Q1(RBA_c_1)); - SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted), - .A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2), - .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237), - .Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7)); - SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220), - .D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5), - .M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4), - .F1(PHI2_N_120_enable_7), .Q1(WRD_5)); - SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7), - .C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0), - .CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1)); - SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1), - .C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2), - .LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362), - .Q1(RowA_3)); - SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady), - .A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady), - .A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371), - .Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3)); - SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), - .B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), - .F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1)); - SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35), - .C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5), - .F1(n2372)); - SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2), - .C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7)); - SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3), - .A0(CBR), .F0(nRCS_N_146), .F1(n2376)); - SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2), - .A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c), - .F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733)); - SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), - .B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296), - .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139), - .F1(RDQMH_c), .Q1(nRCAS_N_165)); - SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7), - .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0), - .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI), - .F1(n22)); - SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6), - .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1), - .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK), - .F1(n2277), .Q1(CmdUFMCS)); - SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), - .C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6), - .CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7)); - SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), - .C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4), - .CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5)); - SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), - .C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2), - .CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3)); - SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26), - .A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c), - .F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7)); - SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15), - .B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4)); - SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c), - .M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228), - .Q0(n736), .F1(n2382), .Q1(n735)); - RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); - RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); - RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); - RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); - RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); - RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); - RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); - RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); - Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); - Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); - Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); - Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); - Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); - Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); - Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); - Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); - LED LED_I( .PADDO(LED_c), .LED(LED)); - RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); - RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); - RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); - RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); - RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); - RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); - RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); - RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); - RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); - RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); - RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); - RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); - RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); - RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); - nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); - RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); - nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); - nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); - nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); - RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); - RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); - nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); - UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); - UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + SLICE_31 SLICE_31( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), + .A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(CBR), + .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), + .F1(RCKEEN_8_u_0_0)); + SLICE_32 SLICE_32( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(RCKEEN), + .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(RASr2), .CLK(RCLK_c), + .F0(RCKE_2), .Q0(RCKE_c), .F1(\RBAd_0[1] ), .Q1(RASr3)); + SLICE_33 SLICE_33( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), + .C0(N_158), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_414_0), + .CLK(RCLK_c), .F0(N_414_0), .Q0(Ready), .F1(N_158)); + SLICE_34 SLICE_34( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_158), + .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_415_0), + .CLK(RCLK_c), .F0(N_415_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa)); + SLICE_35 SLICE_35( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), + .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), + .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] )); + SLICE_36 SLICE_36( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), + .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), + .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] )); + SLICE_37 SLICE_37( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), + .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), + .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] )); + SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), + .A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), + .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] )); + SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), + .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), + .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] )); + SLICE_40 SLICE_40( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR), + .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), + .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1)); + SLICE_41 SLICE_41( .D1(CmdUFMSDI), .C1(N_145), .B1(UFMSDI_ens2_i_a0), + .A1(nUFMCS15), .B0(nUFMCS15), .A0(UFMSDI_c), .DI0(UFMSDI_RNO), + .M0(N_141_i), .CLK(RCLK_c), .OFX0(UFMSDI_RNO), .Q0(UFMSDI_c)); + SLICE_42 SLICE_42( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), + .A1(\Din_c[4] ), .D0(un1_Din_3), .C0(XOR8MEG_3_u_1), .B0(XOR8MEG), + .A0(\Din_c[0] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), + .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(un1_Din_3)); + SLICE_43 SLICE_43( .D1(\Bank[4] ), .C1(\Bank[3] ), .B1(\Bank[1] ), + .A1(\Bank[0] ), .C0(UFMSDO_c), .B0(InitReady), .A0(Cmdn8MEGEN), + .DI0(N_131), .CE(N_26), .CLK(RCLK_c), .F0(N_131), .Q0(n8MEGEN), + .F1(un1_Bank_1_4)); + SLICE_44 SLICE_44( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), + .C0(Ready), .B0(N_168), .A0(CO0), .DI0(nRowColSel_0_0), + .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), + .F1(N_168)); + SLICE_45 SLICE_45( .D1(UFMCLK_r_i_a2_2_2), .C1(nUFMCS15), .B1(InitReady), + .A1(CmdUFMCS), .D0(nUFMCS_c), .C0(nUFMCS_s_0_m4_yy), .B0(nUFMCS15), + .A0(N_141_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), + .Q0(nUFMCS_c), .F1(nUFMCS_s_0_m4_yy)); + SLICE_46 SLICE_46( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(C1WR_3), .A1(ADWR), + .D0(un1_ADWR), .C0(un1_Bank_1), .B0(\MAin_c[2] ), .A0(CMDWR_2), + .F0(un1_CMDWR), .F1(un1_ADWR)); + SLICE_47 SLICE_47( .D1(N_129), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), + .D0(d_m3_0_a2_0), .C0(nUFMCS15), .B0(InitReady), .A0(CmdUFMCLK), .F0(i1_i), + .F1(nUFMCS15)); + SLICE_48 SLICE_48( .D1(N_137_5), .C1(N_137_3), .B1(InitReady), .A1(\FS[16] ), + .C0(UFMCLK_r_i_a2_2_2), .B0(N_50), .A0(InitReady), .F0(d_m3_0_a2_0), + .F1(UFMCLK_r_i_a2_2_2)); + SLICE_49 SLICE_49( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), + .D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_151), + .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_151)); + SLICE_50 SLICE_50( .D1(\Din_c[0] ), .C1(\Din_c[5] ), .B1(Cmdn8MEGEN), + .A1(N_45), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), .F0(N_45), + .F1(Cmdn8MEGEN_4_u_i_0)); + SLICE_51 SLICE_51( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR), + .D0(\S[1] ), .C0(N_146_i_1), .B0(nRCAS_0_sqmuxa_1), .A0(N_27_i_1), + .F0(N_146_i), .F1(N_146_i_1)); + SLICE_52 SLICE_52( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(\IS[0] ), + .C0(N_151), .B0(N_154), .A0(nRRAS_5_u_i_0), .F0(N_24_i), .F1(N_154)); + SLICE_53 SLICE_53( .D1(nRWE_s_i_a3_1_0), .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), + .A1(RASr2), .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), + .F1(nRWE_s_i_tz_0)); + SLICE_54 SLICE_54( .B1(PHI2r3), .A1(PHI2r2), .D0(un1_PHI2r3_0), .C0(N_140), + .B0(InitReady), .A0(CmdSubmitted), .F0(N_28), .F1(un1_PHI2r3_0)); + SLICE_55 SLICE_55( .C1(un1_FS_14_i_a2_0_1), .B1(N_139_8), .A1(N_139_6), + .D0(un1_PHI2r3_0), .C0(N_139), .B0(InitReady), .A0(CmdSubmitted), + .F0(N_26), .F1(N_139)); + SLICE_56 SLICE_56( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), + .C0(un1_FS_13_i_a2_1), .B0(N_139_8), .A0(N_139_6), .F0(N_140), + .F1(un1_FS_13_i_a2_1)); + SLICE_57 SLICE_57( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(XOR8MEG18), .D0(un1_Bank_1), .C0(\MAin_c[2] ), .B0(CmdEnable), + .A0(CMDWR_2), .F0(XOR8MEG18), .F1(CmdSubmitted_1_sqmuxa)); + SLICE_58 SLICE_58( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), + .D0(UFMSDI_ens2_i_a2_4_2), .C0(N_129), .B0(N_34), .A0(InitReady), + .F0(UFMSDI_ens2_i_a0), .F1(UFMSDI_ens2_i_a2_4_2)); + SLICE_59 SLICE_59( .C1(N_129), .B1(InitReady), .A1(\FS[8] ), .D0(N_145), + .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_139_8), .F1(N_145)); + SLICE_60 SLICE_60( .B1(\MAin_c[0] ), .A1(\MAin_c[7] ), .D0(un1_Bank_1), + .C0(\MAin_c[1] ), .B0(ADWR_3), .A0(ADWR_2), .F0(ADWR), .F1(ADWR_3)); + SLICE_61 SLICE_61( .C1(\S[1] ), .B1(N_24), .A1(CBR), .D0(nRRAS_5_u_i_0), + .C0(N_154), .B0(N_151), .A0(\IS[0] ), .F0(N_24), .F1(N_27_i_sn)); + SLICE_62 SLICE_62( .B1(\IS[2] ), .A1(\IS[1] ), .D0(Ready), .C0(N_153), + .B0(N_151), .A0(\IS[0] ), .F0(nRWE_s_i_a3_1_0), .F1(N_153)); + SLICE_63 SLICE_63( .B1(nFWE_c), .A1(\MAin_c[7] ), .D0(\MAin_c[1] ), + .C0(\MAin_c[0] ), .B0(C1WR_1), .A0(ADWR_6), .M1(\Din_c[1] ), + .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_3), .Q0(\Bank[0] ), .F1(C1WR_1), + .Q1(\Bank[1] )); + SLICE_64 SLICE_64( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[15] ), + .D0(N_129), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .F0(N_50), + .F1(N_129)); + SLICE_65 SLICE_65( .B1(nUFMCS15), .A1(N_141_i), .D0(PHI2r3), .C0(PHI2r2), + .B0(InitReady), .A0(CmdSubmitted), .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), + .F0(N_141_i), .Q0(PHI2r2), .F1(i2_i), .Q1(PHI2r3)); + SLICE_66 SLICE_66( .D1(Ready), .C1(N_27_i_sn), .B1(N_27_i_1), .A1(N_24_i), + .D0(FWEr), .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_27_i_1), .F1(N_27_i)); + SLICE_67 SLICE_67( .D1(\MAin_c[6] ), .C1(\MAin_c[5] ), .B1(\MAin_c[4] ), + .A1(\MAin_c[3] ), .C0(nFWE_c), .B0(\MAin_c[2] ), .A0(ADWR_6), .F0(ADWR_2), + .F1(ADWR_6)); + SLICE_68 SLICE_68( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\Din_c[6] ), + .C0(\Din_c[2] ), .B0(CmdEnable16_4), .A0(CmdEnable16_3), .M0(\Din_c[2] ), + .CLK(PHI2_c), .F0(CmdEnable16_5), .Q0(\Bank[2] ), .F1(CmdEnable16_3)); + SLICE_69 SLICE_69( .B1(\Bank[7] ), .A1(\Bank[2] ), .D0(un1_Bank_1_4), + .C0(un1_Bank_1_3), .B0(\Bank[6] ), .A0(\Bank[5] ), .F0(un1_Bank_1), + .F1(un1_Bank_1_3)); + SLICE_70 SLICE_70( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), + .A1(CmdLEDEN), .C0(\Din_c[7] ), .B0(\Din_c[6] ), .A0(\Din_c[4] ), + .F0(N_36), .F1(N_59)); + SLICE_71 SLICE_71( .C1(CO0), .B1(CASr3), .A1(CASr2), .D0(nRWE_s_i_tz_0), + .C0(nRWE_0io_RNO_1), .B0(nRWE_0io_RNO_0), .A0(nRCAS_0_sqmuxa_1), + .F0(N_147_i), .F1(nRWE_0io_RNO_0)); + SLICE_72 SLICE_72( .D1(\FS[17] ), .C1(\FS[14] ), .B1(\FS[13] ), + .A1(\FS[12] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), + .F0(N_137_5), .F1(UFMSDI_ens2_i_o2_0_3)); + SLICE_73 SLICE_73( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), + .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[5] ), .B0(\Din_c[4] ), + .A0(\Din_c[1] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdEnable17_5), .Q0(CASr3), + .F1(CmdEnable16_4)); + SLICE_74 SLICE_74( .D1(LEDEN), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .D0(\Din_c[6] ), .C0(\Din_c[3] ), .B0(\Din_c[2] ), + .A0(\Din_c[0] ), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CmdEnable17_4), + .Q0(CBR), .F1(XOR8MEG_3_u_1)); + SLICE_75 SLICE_75( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c)); + SLICE_76 SLICE_76( .D1(\S[1] ), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(\S[1] ), + .C0(FWEr), .B0(CO0), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(nRWE_0io_RNO_1)); + SLICE_77 SLICE_77( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), + .B0(Ready), .A0(N_151), .F0(N_48_i), .F1(nRRAS_5_u_i_0)); + SLICE_78 SLICE_78( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), + .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .F0(N_34), + .F1(un1_FS_14_i_a2_0_1)); + SLICE_79 SLICE_79( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), + .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c)); + SLICE_80 SLICE_80( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), + .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), + .F1(\RA_c[7] )); + SLICE_81 SLICE_81( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), + .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), + .F1(\RA_c[6] )); + SLICE_82 SLICE_82( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), + .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), + .F1(\RA_c[5] )); + SLICE_83 SLICE_83( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ), + .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), + .F1(\RA_c[4] )); + SLICE_84 SLICE_84( .B1(Ready_fast), .A1(\CROW_c[0] ), .D0(n8MEGEN), + .C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0), + .F1(\RBAd_0[0] )); + SLICE_85 SLICE_85( .D1(\FS[10] ), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[1] ), + .B0(\FS[14] ), .A0(\FS[11] ), .F0(N_137_3), .F1(N_139_6)); + RD_0_ \RD[0]_I ( .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0])); + RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), + .CLK(nCCAS_c)); + Dout_0_ \Dout[0]_I ( .PADDO(\MAin_c[3] ), .Dout0(Dout[0])); PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); - MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); - MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); - MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); - MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); - MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); - MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); - MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); - MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); - MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); - MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); - CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); - CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); - Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); - Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); - Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); - Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); - Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); - Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); - Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); - Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); - nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); - nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); - nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); - RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r)); UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + UFMSDI UFMSDI_I( .IOLDO(\UFMSDI_c$n0 ), .UFMSDI(UFMSDI)); + UFMSDI_MGIOL UFMSDI_MGIOL( .IOLDO(\UFMSDI_c$n0 ), .OPOS(UFMSDI_RNO), + .CLK(RCLK_c)); + UFMCLK UFMCLK_I( .IOLDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMCLK_MGIOL UFMCLK_MGIOL( .IOLDO(UFMCLK_c), .OPOS(i1_i), .CE(i2_i), + .CLK(RCLK_c)); + nUFMCS nUFMCS_I( .IOLDO(\nUFMCS_c$n1 ), .nUFMCS(nUFMCS)); + nUFMCS_MGIOL nUFMCS_MGIOL( .IOLDO(\nUFMCS_c$n1 ), .OPOS(nUFMCS_s_0_N_5_i), + .CLK(RCLK_c)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS)); + nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_146_i), .CLK(RCLK_c)); + nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS)); + nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_24_i), .CLK(RCLK_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_147_i), .CLK(RCLK_c)); + RCKE RCKE_I( .IOLDO(\RCKE_c$n2 ), .RCKE(RCKE)); + RCKE_MGIOL RCKE_MGIOL( .IOLDO(\RCKE_c$n2 ), .OPOS(RCKE_2), .CLK(RCLK_c)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS)); + nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_27_i), .CLK(RCLK_c)); + RD_7_ \RD[7]_I ( .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7])); + RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), + .CLK(nCCAS_c)); + RD_6_ \RD[6]_I ( .IOLDO(\WRD[6] ), .PADDT(RD_1_i), .RD6(RD[6])); + RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ), + .CLK(nCCAS_c)); + RD_5_ \RD[5]_I ( .IOLDO(\WRD[5] ), .PADDT(RD_1_i), .RD5(RD[5])); + RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ), + .CLK(nCCAS_c)); + RD_4_ \RD[4]_I ( .IOLDO(\WRD[4] ), .PADDT(RD_1_i), .RD4(RD[4])); + RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ), + .CLK(nCCAS_c)); + RD_3_ \RD[3]_I ( .IOLDO(\WRD[3] ), .PADDT(RD_1_i), .RD3(RD[3])); + RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ), + .CLK(nCCAS_c)); + RD_2_ \RD[2]_I ( .IOLDO(\WRD[2] ), .PADDT(RD_1_i), .RD2(RD[2])); + RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ), + .CLK(nCCAS_c)); + RD_1_ \RD[1]_I ( .IOLDO(\WRD[1] ), .PADDT(RD_1_i), .RD1(RD[1])); + RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ), + .CLK(nCCAS_c)); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0), + .CLK(PHI2_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_153), .LSR(RA10s_i), + .CLK(RCLK_c)); + RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1])); + RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ), + .CLK(nCRAS_c)); + RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0])); + RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ), + .CLK(nCRAS_c)); + LED LED_I( .PADDO(LED_c), .LED(LED)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + Dout_7_ \Dout[7]_I ( .PADDO(nCRAS_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(\MAin_c[9] ), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(\MAin_c[8] ), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(\MAin_c[7] ), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(\MAin_c[6] ), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(\MAin_c[5] ), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(\MAin_c[4] ), .Dout1(Dout[1])); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] )); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] )); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] )); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] )); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] )); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CE(CmdUFMCLK_1_sqmuxa), + .CLK(PHI2_c), .IN(CmdUFMCS)); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), + .CLK(PHI2_c), .IN(CmdUFMCLK)); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), + .CLK(PHI2_c), .IN(CmdUFMSDI)); + CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0])); + MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0])); VHI VHI_INST( .Z(VCCI)); PUR PUR_INST( .PUR(VCCI)); GSR GSR_INST( .GSR(VCCI)); endmodule -module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; - vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -419,36 +468,26 @@ module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hfaaa; - defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -456,16 +495,26 @@ module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -487,16 +536,26 @@ module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -521,13 +580,13 @@ endmodule module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -549,51 +608,47 @@ module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule -module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hF000; - defparam inst1.INIT1 = 16'h0555; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -615,21 +670,30 @@ module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule -module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), - .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), - .CO1()); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -637,26 +701,16 @@ module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); endmodule -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'hfaaa; - defparam inst1.INIT1 = 16'h0000; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -681,13 +735,13 @@ endmodule module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify @@ -709,19 +763,19 @@ module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); endmodule -module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module SLICE_10 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -730,31 +784,21 @@ module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40003 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; + ROM16X1A #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module inverter ( input I, output Z ); @@ -762,14 +806,15 @@ module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule -module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_13 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + lut40004 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); @@ -778,49 +823,42 @@ module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40005 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); +module SLICE_14 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + lut40006 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40007 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -832,85 +870,117 @@ module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); endmodule +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_17 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40008 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40009 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0010 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module lut40008 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40009 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40010 ( input A, B, C, D, output Z ); +module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; endmodule -module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; +module SLICE_18 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); + wire GNDI, \SLICE_18/SLICE_18_K1_H1 , \SLICE_18/CmdEnable_s/GATE_H0 , VCCI, + CLK_NOTIN, DI0_dly, CLK_dly; - lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); + lut40011 SLICE_18_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(\SLICE_18/SLICE_18_K1_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40012 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_18/CmdEnable_s/GATE_H0 )); + vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + selmux2 SLICE_18_K0K1MUX( .D0(\SLICE_18/CmdEnable_s/GATE_H0 ), + .D1(\SLICE_18/SLICE_18_K1_H1 ), .SD(M0), .Z(OFX0)); specify + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40011 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_19 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40013 CmdLEDEN_4_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40014 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); @@ -932,209 +1002,123 @@ module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40013 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; - - lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - endspecify - + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40014 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module SLICE_20 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); + lut40015 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; - - lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); endspecify endmodule module lut40015 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40016 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40017 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40016 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40017 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_22 ( input D1, C1, B1, A1, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40018 CMDWR_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40007 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); endspecify endmodule module lut40018 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40019 ( input A, B, C, D, output Z ); +module SLICE_23 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + lut40019 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -1148,6 +1132,45 @@ module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40021 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40022 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -1155,58 +1178,30 @@ module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, endmodule -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40021 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; +module lut40022 ( input A, B, C, D, output Z ); - lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40023 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); @@ -1216,52 +1211,105 @@ module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); endmodule -module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output - F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - module lut40023 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module SLICE_26 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; - lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40004 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40024 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_29 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40025 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40007 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40026 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); @@ -1273,7 +1321,290 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40028 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40030 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40028 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40028 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_37 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40024 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40028 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly; + + lut40024 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + endspecify + +endmodule + +module SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40015 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0010 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -1283,18 +1614,54 @@ module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40024 ( input A, B, C, D, output Z ); +module SLICE_41 ( input D1, C1, B1, A1, B0, A0, DI0, M0, CLK, output OFX0, Q0 ); + wire \SLICE_41/SLICE_41_K1_H1 , GNDI, \SLICE_41/UFMSDI_RNO/GATE_H0 , VCCI, + DI0_dly, CLK_dly; + + lut40033 SLICE_41_K1( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\SLICE_41/SLICE_41_K1_H1 )); + lut40034 \UFMSDI_RNO/GATE ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(\SLICE_41/UFMSDI_RNO/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_41_K0K1MUX( .D0(\SLICE_41/UFMSDI_RNO/GATE_H0 ), + .D1(\SLICE_41/SLICE_41_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify - ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40035 un1_Din_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 XOR8MEG_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); @@ -1318,257 +1685,38 @@ module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output endmodule -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40035 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40036 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40004 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -1577,20 +1725,26 @@ endmodule module lut40037 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40038 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0010 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -1606,75 +1760,21 @@ endmodule module lut40038 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - - lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40039 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + lut40040 nUFMCS_s_0_m4_yy( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0042 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); @@ -1690,7 +1790,6 @@ module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -1699,80 +1798,52 @@ endmodule module lut40040 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40041 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5F4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); - wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; +module vmuxregsre0042 ( input D0, D1, SD, SP, CK, LSR, output Q ); - lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\i30/SLICE_71/i30/GATE_H0 )); - selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), - .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40043 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40044 un1_CMDWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40043 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40044 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40035 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 UFMCLK_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -1787,126 +1858,23 @@ module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - module lut40045 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0B00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_48 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40015 UFMCLK_r_i_a2_2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 UFMCLK_0io_RNO_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -1916,64 +1884,16 @@ endmodule module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40019 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -1981,30 +1901,53 @@ module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40049 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_50 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40048 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40050 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2017,158 +1960,80 @@ endmodule module lut40050 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40051 ( input A, B, C, D, output Z ); - lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40052 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40053 nRRAS_5_u_i_0_RNILD5I( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40052 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40053 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40054 ( input A, B, C, D, output Z ); +module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40054 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - - lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40056 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40057 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -2181,129 +2046,22 @@ endmodule module lut40056 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40057 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; +module SLICE_55 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut4 un1_FS_14_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + lut40057 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2311,74 +2069,64 @@ module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40058 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 un1_FS_13_i_a2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40058 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40059 ( input A, B, C, D, output Z ); +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + lut40059 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 XOR8MEG18( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40060 UFMSDI_ens2_i_a0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - endspecify - -endmodule - -module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2386,45 +2134,23 @@ module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40060 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40061 ( input A, B, C, D, output Z ); +module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - - lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40013 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + lut40015 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2432,36 +2158,97 @@ module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule -module lut40062 ( input A, B, C, D, output Z ); +module SLICE_60 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40028 ADWR_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40004 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40061 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40006 RA10_2_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40063 nRWE_s_i_a3_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40064 C1WR_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + lut40008 C1WR_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank_0io[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + vmuxregsre \Bank_0io[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -2475,41 +2262,19 @@ module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ) endmodule -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40064 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40052 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -2523,15 +2288,21 @@ endmodule module lut40065 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_65 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40006 UFMCLK_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40066 PHI2r3_RNITCN41( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2540,34 +2311,10 @@ module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -2576,236 +2323,87 @@ endmodule module lut40066 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + lut40067 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; - - lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40067 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; - lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40004 ADWR_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40016 ADWR_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly; + + lut40064 CmdEnable16_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \Bank_0io[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_69 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40056 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40004 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -2818,255 +2416,435 @@ module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40069 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 Cmdn8MEGEN_4_u_i_o2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40071 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40073 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly; + + lut40058 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 CmdEnable17_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly; - xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), - .PADI(RD7)); + lut40074 XOR8MEG_3_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); +module lut40074 ( input A, B, C, D, output Z ); - IBPD INST1( .I(PADI), .O(Z)); - OBZPD INST2( .I(I), .T(T), .O(PAD)); + ROM16X1A #(16'h040C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); +module lut40075 ( input A, B, C, D, output Z ); - xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), - .PADI(RD6)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40076 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); +module lut40076 ( input A, B, C, D, output Z ); - xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), - .PADI(RD5)); + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40078 nRWE_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); +module lut40078 ( input A, B, C, D, output Z ); - xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), - .PADI(RD4)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40080 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); +module lut40080 ( input A, B, C, D, output Z ); - xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), - .PADI(RD3)); + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40035 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40082 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); +module lut40082 ( input A, B, C, D, output Z ); - xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), - .PADI(RD2)); + ROM16X1A #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40024 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); +module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), - .PADI(RD1)); + lut40077 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); +module SLICE_81 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; - xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), - .PADI(RD0)); + lut40077 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40077 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_83 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40077 \un9_RA[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_84 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40028 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40058 un1_FS_13_i_a2_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 InitReady3_0_a2_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RD_0_ ( input IOLDO, PADDT, output RD0 ); + + xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .PAD(RD0)); + + specify + (IOLDO => RD0) = (0:0:0,0:0:0); (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); endspecify endmodule -module Dout_7_ ( input PADDO, output Dout7 ); - wire GNDI; +module xo2iobuf ( input I, T, output PAD ); - xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + OBW INST1( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => Dout7) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); endspecify endmodule -module xo2iobuf0068 ( input I, T, output PAD ); - - OBZPD INST5( .I(I), .T(T), .O(PAD)); -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - wire GNDI; - - xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify +module mfflsre ( input D0, SP, CK, LSR, output Q ); + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; endmodule module Dout_0_ ( input PADDO, output Dout0 ); - wire GNDI; - xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); - gnd DRIVEGND( .PWR0(GNDI)); + xo2iobuf0084 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); specify (PADDO => Dout0) = (0:0:0,0:0:0); @@ -3074,309 +2852,14 @@ module Dout_0_ ( input PADDO, output Dout0 ); endmodule -module LED ( input PADDO, output LED ); - wire GNDI; - - xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RBA_1_ ( input PADDO, output RBA1 ); - wire GNDI; - - xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RBA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RBA_0_ ( input PADDO, output RBA0 ); - wire GNDI; - - xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RBA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_11_ ( input PADDO, output RA11 ); - wire GNDI; - - xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_10_ ( input PADDO, output RA10 ); - wire GNDI; - - xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_9_ ( input PADDO, output RA9 ); - wire GNDI; - - xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_8_ ( input PADDO, output RA8 ); - wire GNDI; - - xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_7_ ( input PADDO, output RA7 ); - wire GNDI; - - xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_6_ ( input PADDO, output RA6 ); - wire GNDI; - - xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_5_ ( input PADDO, output RA5 ); - wire GNDI; - - xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_4_ ( input PADDO, output RA4 ); - wire GNDI; - - xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_3_ ( input PADDO, output RA3 ); - wire GNDI; - - xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_2_ ( input PADDO, output RA2 ); - wire GNDI; - - xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_1_ ( input PADDO, output RA1 ); - wire GNDI; - - xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RA_0_ ( input PADDO, output RA0 ); - wire GNDI; - - xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRCS ( input PADDO, output nRCS ); - wire GNDI; - - xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRCS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RCKE ( input PADDO, output RCKE ); - wire GNDI; - - xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RCKE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWE ( input PADDO, output nRWE ); - wire GNDI; - - xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRWE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRRAS ( input PADDO, output nRRAS ); - wire GNDI; - - xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRRAS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRCAS ( input PADDO, output nRCAS ); - wire GNDI; - - xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nRCAS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RDQMH ( input PADDO, output RDQMH ); - wire GNDI; - - xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RDQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RDQML ( input PADDO, output RDQML ); - wire GNDI; - - xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => RDQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nUFMCS ( input PADDO, output nUFMCS ); - wire GNDI; - - xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => nUFMCS) = (0:0:0,0:0:0); - endspecify - -endmodule - -module UFMCLK ( input PADDO, output UFMCLK ); - wire GNDI; - - xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => UFMCLK) = (0:0:0,0:0:0); - endspecify - -endmodule - -module UFMSDI ( input PADDO, output UFMSDI ); - wire GNDI; - - xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (PADDO => UFMSDI) = (0:0:0,0:0:0); - endspecify +module xo2iobuf0084 ( input I, output PAD ); + OB INST5( .I(I), .O(PAD)); endmodule module PHI2 ( output PADDI, input PHI2 ); - xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + xo2iobuf0085 PHI2_pad( .Z(PADDI), .PAD(PHI2)); specify (PHI2 => PADDI) = (0:0:0,0:0:0); @@ -3386,134 +2869,1088 @@ module PHI2 ( output PADDI, input PHI2 ); endmodule -module xo2iobuf0069 ( output Z, input PAD ); +module xo2iobuf0085 ( output Z, input PAD ); IBPD INST1( .I(PAD), .O(Z)); endmodule -module MAin_9_ ( output PADDI, input MAin9 ); +module PHI2_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; - xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (MAin9 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin9, 0:0:0); - $width (negedge MAin9, 0:0:0); + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module MAin_8_ ( output PADDI, input MAin8 ); +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); - xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + xo2iobuf0086 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); specify - (MAin8 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin8, 0:0:0); - $width (negedge MAin8, 0:0:0); + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); endspecify endmodule -module MAin_7_ ( output PADDI, input MAin7 ); +module xo2iobuf0086 ( output Z, input PAD ); - xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + IB INST1( .I(PAD), .O(Z)); +endmodule + +module UFMSDI ( input IOLDO, output UFMSDI ); + + xo2iobuf0084 UFMSDI_pad( .I(IOLDO), .PAD(UFMSDI)); specify - (MAin7 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin7, 0:0:0); - $width (negedge MAin7, 0:0:0); + (IOLDO => UFMSDI) = (0:0:0,0:0:0); endspecify endmodule -module MAin_6_ ( output PADDI, input MAin6 ); +module UFMSDI_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; - xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + mfflsre \UFMSDI$r0 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (MAin6 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin6, 0:0:0); - $width (negedge MAin6, 0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module MAin_5_ ( output PADDI, input MAin5 ); +module UFMCLK ( input IOLDO, output UFMCLK ); - xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + xo2iobuf0084 UFMCLK_pad( .I(IOLDO), .PAD(UFMCLK)); specify - (MAin5 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin5, 0:0:0); - $width (negedge MAin5, 0:0:0); + (IOLDO => UFMCLK) = (0:0:0,0:0:0); endspecify endmodule -module MAin_4_ ( output PADDI, input MAin4 ); +module UFMCLK_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + mfflsre UFMCLK_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (MAin4 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin4, 0:0:0); - $width (negedge MAin4, 0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module MAin_3_ ( output PADDI, input MAin3 ); +module nUFMCS ( input IOLDO, output nUFMCS ); - xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + xo2iobuf0084 nUFMCS_pad( .I(IOLDO), .PAD(nUFMCS)); specify - (MAin3 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin3, 0:0:0); - $width (negedge MAin3, 0:0:0); + (IOLDO => nUFMCS) = (0:0:0,0:0:0); endspecify endmodule -module MAin_2_ ( output PADDI, input MAin2 ); +module nUFMCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; - xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + mfflsre0087 \nUFMCS$r1 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (MAin2 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin2, 0:0:0); - $width (negedge MAin2, 0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module MAin_1_ ( output PADDI, input MAin1 ); +module mfflsre0087 ( input D0, SP, CK, LSR, output Q ); - xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RDQML ( input PADDO, output RDQML ); + + xo2iobuf0084 RDQML_pad( .I(PADDO), .PAD(RDQML)); specify - (MAin1 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin1, 0:0:0); - $width (negedge MAin1, 0:0:0); + (PADDO => RDQML) = (0:0:0,0:0:0); endspecify endmodule -module MAin_0_ ( output PADDI, input MAin0 ); +module RDQMH ( input PADDO, output RDQMH ); - xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + xo2iobuf0084 RDQMH_pad( .I(PADDO), .PAD(RDQMH)); specify - (MAin0 => PADDI) = (0:0:0,0:0:0); - $width (posedge MAin0, 0:0:0); - $width (negedge MAin0, 0:0:0); + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input IOLDO, output nRCAS ); + + xo2iobuf0084 nRCAS_pad( .I(IOLDO), .PAD(nRCAS)); + + specify + (IOLDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0087 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRRAS ( input IOLDO, output nRRAS ); + + xo2iobuf0084 nRRAS_pad( .I(IOLDO), .PAD(nRRAS)); + + specify + (IOLDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0087 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0084 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0087 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RCKE ( input IOLDO, output RCKE ); + + xo2iobuf0084 RCKE_pad( .I(IOLDO), .PAD(RCKE)); + + specify + (IOLDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RCKE$r2 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0086 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module nRCS ( input IOLDO, output nRCS ); + + xo2iobuf0084 nRCS_pad( .I(IOLDO), .PAD(nRCS)); + + specify + (IOLDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0087 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( input IOLDO, PADDT, output RD7 ); + + xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .PAD(RD7)); + + specify + (IOLDO => RD7) = (0:0:0,0:0:0); + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_7__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_6_ ( input IOLDO, PADDT, output RD6 ); + + xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .PAD(RD6)); + + specify + (IOLDO => RD6) = (0:0:0,0:0:0); + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_6__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_5_ ( input IOLDO, PADDT, output RD5 ); + + xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .PAD(RD5)); + + specify + (IOLDO => RD5) = (0:0:0,0:0:0); + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_5__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_4_ ( input IOLDO, PADDT, output RD4 ); + + xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .PAD(RD4)); + + specify + (IOLDO => RD4) = (0:0:0,0:0:0); + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_4__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_3_ ( input IOLDO, PADDT, output RD3 ); + + xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .PAD(RD3)); + + specify + (IOLDO => RD3) = (0:0:0,0:0:0); + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_3__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_2_ ( input IOLDO, PADDT, output RD2 ); + + xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .PAD(RD2)); + + specify + (IOLDO => RD2) = (0:0:0,0:0:0); + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_2__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RD_1_ ( input IOLDO, PADDT, output RD1 ); + + xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .PAD(RD1)); + + specify + (IOLDO => RD1) = (0:0:0,0:0:0); + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module RD_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0084 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0084 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0088 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0088 ( input D0, SP, CK, LSR, output Q ); + + FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + + xo2iobuf0084 \RA_pad[9] ( .I(PADDO), .PAD(RA9)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + + xo2iobuf0084 \RA_pad[8] ( .I(PADDO), .PAD(RA8)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + + xo2iobuf0084 \RA_pad[7] ( .I(PADDO), .PAD(RA7)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + + xo2iobuf0084 \RA_pad[6] ( .I(PADDO), .PAD(RA6)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + + xo2iobuf0084 \RA_pad[5] ( .I(PADDO), .PAD(RA5)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + + xo2iobuf0084 \RA_pad[4] ( .I(PADDO), .PAD(RA4)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0084 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + + xo2iobuf0084 \RA_pad[2] ( .I(PADDO), .PAD(RA2)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + + xo2iobuf0084 \RA_pad[1] ( .I(PADDO), .PAD(RA1)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0084 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input IOLDO, output RBA1 ); + + xo2iobuf0084 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1)); + + specify + (IOLDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module RBA_0_ ( input IOLDO, output RBA0 ); + + xo2iobuf0084 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0)); + + specify + (IOLDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; + + mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0089 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0089 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0090 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0090 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0090 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0090 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + + xo2iobuf0084 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + + xo2iobuf0084 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + + xo2iobuf0084 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + + xo2iobuf0084 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + + xo2iobuf0084 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + + xo2iobuf0084 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + + xo2iobuf0084 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0086 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_7__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0086 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_6__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0086 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_5__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0086 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_4__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0086 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_3__MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0086 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_2__MGIOL ( input DI, CE, CLK, output IN ); + wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly; + + smuxlregsre CmdUFMCS( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0086 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_1__MGIOL ( input DI, CE, CLK, output IN ); + wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly; + + smuxlregsre CmdUFMCLK( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0086 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Din_0__MGIOL ( input DI, CE, CLK, output IN ); + wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly; + + smuxlregsre CmdUFMSDI( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(IN)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CROW_1_ ( output PADDI, input CROW1 ); - xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + xo2iobuf0086 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1)); specify (CROW1 => PADDI) = (0:0:0,0:0:0); @@ -3525,7 +3962,7 @@ endmodule module CROW_0_ ( output PADDI, input CROW0 ); - xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + xo2iobuf0086 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0)); specify (CROW0 => PADDI) = (0:0:0,0:0:0); @@ -3535,158 +3972,122 @@ module CROW_0_ ( output PADDI, input CROW0 ); endmodule -module Din_7_ ( output PADDI, input Din7 ); +module MAin_9_ ( output PADDI, input MAin9 ); - xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); + xo2iobuf0086 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9)); specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); endspecify endmodule -module Din_6_ ( output PADDI, input Din6 ); +module MAin_8_ ( output PADDI, input MAin8 ); - xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); + xo2iobuf0086 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8)); specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); endspecify endmodule -module Din_5_ ( output PADDI, input Din5 ); +module MAin_7_ ( output PADDI, input MAin7 ); - xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); + xo2iobuf0086 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7)); specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); endspecify endmodule -module Din_4_ ( output PADDI, input Din4 ); +module MAin_6_ ( output PADDI, input MAin6 ); - xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); + xo2iobuf0086 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6)); specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); endspecify endmodule -module Din_3_ ( output PADDI, input Din3 ); +module MAin_5_ ( output PADDI, input MAin5 ); - xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); + xo2iobuf0086 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5)); specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); endspecify endmodule -module Din_2_ ( output PADDI, input Din2 ); +module MAin_4_ ( output PADDI, input MAin4 ); - xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); + xo2iobuf0086 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4)); specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); endspecify endmodule -module Din_1_ ( output PADDI, input Din1 ); +module MAin_3_ ( output PADDI, input MAin3 ); - xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); + xo2iobuf0086 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3)); specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); endspecify endmodule -module Din_0_ ( output PADDI, input Din0 ); +module MAin_2_ ( output PADDI, input MAin2 ); - xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); + xo2iobuf0086 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2)); specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); endspecify endmodule -module nCCAS ( output PADDI, input nCCAS ); +module MAin_1_ ( output PADDI, input MAin1 ); - xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + xo2iobuf0086 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1)); specify - (nCCAS => PADDI) = (0:0:0,0:0:0); - $width (posedge nCCAS, 0:0:0); - $width (negedge nCCAS, 0:0:0); + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); endspecify endmodule -module nCRAS ( output PADDI, input nCRAS ); +module MAin_0_ ( output PADDI, input MAin0 ); - xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + xo2iobuf0086 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0)); specify - (nCRAS => PADDI) = (0:0:0,0:0:0); - $width (posedge nCRAS, 0:0:0); - $width (negedge nCRAS, 0:0:0); - endspecify - -endmodule - -module nFWE ( output PADDI, input nFWE ); - - xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); - - specify - (nFWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nFWE, 0:0:0); - $width (negedge nFWE, 0:0:0); - endspecify - -endmodule - -module RCLK ( output PADDI, input RCLK ); - - xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); - - specify - (RCLK => PADDI) = (0:0:0,0:0:0); - $width (posedge RCLK, 0:0:0); - $width (negedge RCLK, 0:0:0); - endspecify - -endmodule - -module UFMSDO ( output PADDI, input UFMSDO ); - - xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); - - specify - (UFMSDO => PADDI) = (0:0:0,0:0:0); - $width (posedge UFMSDO, 0:0:0); - $width (negedge UFMSDO, 0:0:0); + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); endspecify endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html index 06c3af4..8148b08 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html @@ -14,29 +14,29 @@ Design Information Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr - RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One - Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i - mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_ - LCMXO2_640HC.lpf -c 0 -gui -msgset + -ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd + -pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D: + /OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640 + HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2- + 640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-640HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 08/15/23 05:03:24 +Mapped on: 08/15/23 23:30:05 Design Summary - Number of registers: 102 out of 877 (12%) - PFU registers: 102 out of 640 (16%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 75 out of 320 (23%) - SLICEs as Logic/ROM: 75 out of 320 (23%) + Number of registers: 93 out of 877 (11%) + PFU registers: 64 out of 640 (10%) + PIO registers: 29 out of 237 (12%) + Number of SLICEs: 81 out of 320 (25%) + SLICEs as Logic/ROM: 81 out of 320 (25%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 143 out of 640 (22%) - Number used as logic LUTs: 123 + Number of LUT4s: 159 out of 640 (25%) + Number used as logic LUTs: 139 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -60,51 +60,39 @@ Mapped on: 08/15/23 05:03:24 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 - Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_6: 4 loads, 4 LSLICEs - Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 ) + Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 6 + Net XOR8MEG18: 3 loads, 3 LSLICEs + Net i2_i: 1 loads, 0 LSLICEs - Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_10: 3 loads, 3 LSLICEs - Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_16: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net RCLK_c_enable_15: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs - Net Ready_N_292: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs - Number of LSRs: 7 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_177: 1 loads, 1 LSLICEs - Net C1Submitted_N_237: 2 loads, 2 LSLICEs - Net n2366: 2 loads, 2 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_28: 1 loads, 1 LSLICEs + Net N_188_i: 2 loads, 2 LSLICEs + Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs + Number of LSRs: 3 + Net RA10s_i: 1 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net Ready: 18 loads - Net InitReady: 15 loads - Net RASr2: 15 loads - Net nRowColSel_N_35: 13 loads + Net InitReady: 17 loads + Net Ready: 15 loads + Net Ready_fast: 14 loads + Net Din_c[5]: 12 loads Net nRowColSel: 12 loads - Net Din_c_4: 10 loads - Net MAin_c_1: 10 loads - Net Din_c_5: 9 loads - Net MAin_c_0: 9 loads - Net Din_c_0: 8 loads + Net S[1]: 12 loads + Net RASr2: 10 loads + Net CO0: 9 loads + Net Din_c[3]: 9 loads + Net Din_c[4]: 9 loads - Number of warnings: 0 + Number of warnings: 6 Number of errors: 0 @@ -113,7 +101,18 @@ Mapped on: 08/15/23 05:03:24 Design Errors/Warnings - No errors or warnings present. +WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad. +WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad. +WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad. +WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. +WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. +WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its + primitive type or preference due to command option or architecture + limitation. The register was packed into SLICE instead. @@ -123,167 +122,161 @@ Mapped on: 08/15/23 05:03:24 | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS25 | | +| RD[0] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS25 | | +| Dout[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS33 | IN | -| RD[5] | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS25 | | +| UFMSDO | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS25 | | +| UFMSDI | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS25 | | +| UFMCLK | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS25 | | +| nUFMCS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS25 | | +| RDQML | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS25 | | +| RDQMH | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS25 | | +| nRCAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS25 | | +| nRRAS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS25 | | +| nRWE | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS25 | | +| RCKE | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS25 | | +| RCLK | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS25 | | +| nRCS | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS25 | | +| RD[7] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVCMOS25 | | +| RD[6] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVCMOS25 | | +| RD[5] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVCMOS25 | | +| RD[4] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVCMOS25 | | +| RD[3] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVCMOS25 | | +| RD[2] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVCMOS25 | | +| RD[1] | BIDIR | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVCMOS25 | | +| RA[11] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVCMOS25 | | +| RA[10] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVCMOS25 | | +| RA[9] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVCMOS25 | | +| RA[8] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVCMOS25 | | +| RA[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[3] | OUTPUT | LVCMOS25 | | +| RA[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVCMOS25 | | +| RA[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVCMOS25 | | +| RA[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | -| RA[0] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVCMOS25 | | +| RA[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVCMOS25 | | +| RA[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVCMOS25 | | +| RA[0] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVCMOS25 | | +| RBA[1] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVCMOS25 | | +| RBA[0] | OUTPUT | LVCMOS33 | OUT | +---------------------+-----------+-----------+------------+ -| RDQMH | OUTPUT | LVCMOS25 | | +| LED | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVCMOS25 | | +| nFWE | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nUFMCS | OUTPUT | LVCMOS25 | | +| nCRAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMCLK | OUTPUT | LVCMOS25 | | +| nCCAS | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMSDI | OUTPUT | LVCMOS25 | | +| Dout[7] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVCMOS25 | | +| Dout[6] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVCMOS25 | | +| Dout[5] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVCMOS25 | | +| Dout[4] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVCMOS25 | | +| Dout[3] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVCMOS25 | | +| Dout[2] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVCMOS25 | | +| Dout[1] | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVCMOS25 | | +| Din[7] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVCMOS25 | | +| Din[6] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[2] | INPUT | LVCMOS25 | | +| Din[5] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVCMOS25 | | +| Din[4] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVCMOS25 | | +| Din[3] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVCMOS25 | | +| Din[2] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVCMOS25 | | +| Din[1] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS25 | | +| Din[0] | INPUT | LVCMOS33 | IN | +---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVCMOS25 | | +| CROW[1] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS25 | | +| CROW[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS25 | | +| MAin[9] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | -| Din[3] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS25 | | +| MAin[7] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVCMOS25 | | +| MAin[6] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS25 | | +| MAin[5] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVCMOS25 | | +| MAin[4] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVCMOS25 | | +| MAin[3] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVCMOS25 | | +| MAin[2] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVCMOS25 | | +| MAin[1] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ -| UFMSDO | INPUT | LVCMOS25 | | +| MAin[0] | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ Removed logic -Block i2 undriven or does not drive anything - clipped. Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_120 was merged into signal PHI2_c -Signal n1407 was merged into signal nRowColSel_N_34 -Signal n2380 was merged into signal Ready -Signal n1408 was merged into signal nRowColSel_N_35 -Signal nRWE_N_176 was merged into signal nRWE_N_177 -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. -Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. -Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. -Block i2046 was optimized away. -Block i1118_1_lut was optimized away. -Block i637_1_lut_rep_31 was optimized away. -Block i1119_1_lut was optimized away. -Block nRWE_I_50_1_lut was optimized away. -Block i1 was optimized away. +Signal nCRAS_c_i was merged into signal nCRAS_c +Signal RASr2_i was merged into signal RASr2 +Signal XOR8MEG.CN was merged into signal PHI2_c +Signal GND undriven or does not drive anything - clipped. +Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. +Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. +Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. +Signal N_1 undriven or does not drive anything - clipped. +Block nCRAS_pad_RNIBPVB was optimized away. +Block RASr2_RNIAFR1 was optimized away. +Block XOR8MEG.CN was optimized away. +Block GND was optimized away. @@ -294,7 +287,7 @@ Block i1 was optimized away. Total CPU Time: 0 secs Total REAL Time: 0 secs - Peak Memory Usage: 35 MB + Peak Memory Usage: 36 MB @@ -304,6 +297,13 @@ Block i1 was optimized away. + + + + + + + Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm new file mode 100644 index 0000000..8f7f539 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm @@ -0,0 +1,9 @@ + + + syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_ngd.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html index 635ff81..b7156b7 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html @@ -14,89 +14,89 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.39 -Tue Aug 15 05:03:32 2023 +Tue Aug 15 23:30:09 2023 Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ -| CROW[0] | 10/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVCMOS25_IN | PL6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVCMOS25_IN | PT6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVCMOS25_IN | PT6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVCMOS25_IN | PT6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVCMOS25_IN | PT6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVCMOS25_IN | PL2B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVCMOS25_IN | PL2A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVCMOS25_OUT | PT11D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[1] | 86/0 | LVCMOS25_OUT | PT9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[2] | 87/0 | LVCMOS25_OUT | PT9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[3] | 85/0 | LVCMOS25_OUT | PT9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[4] | 83/0 | LVCMOS25_OUT | PT10B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[5] | 84/0 | LVCMOS25_OUT | PT10A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[6] | 78/0 | LVCMOS25_OUT | PT11A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| Dout[7] | 82/0 | LVCMOS25_OUT | PT10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| LED | 34/2 | LVCMOS25_OUT | PB6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVCMOS25_IN | PL7B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVCMOS25_IN | PL7A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVCMOS25_IN | PL6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVCMOS25_IN | PL7C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVCMOS25_IN | PL6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVCMOS25_IN | PL7D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVCMOS25_IN | PB6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVCMOS25_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVCMOS25_OUT | PR3D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[11] | 59/1 | LVCMOS25_OUT | PR6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[1] | 67/1 | LVCMOS25_OUT | PR3C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[2] | 69/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[3] | 71/1 | LVCMOS25_OUT | PR2C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[5] | 70/1 | LVCMOS25_OUT | PR2D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[6] | 68/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[0] | 58/1 | LVCMOS25_OUT | PR6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RBA[1] | 60/1 | LVCMOS25_OUT | PR6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCKE | 53/1 | LVCMOS25_OUT | PR7B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVCMOS25_OUT | PR7D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RDQML | 48/2 | LVCMOS25_OUT | PB14C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS25_BIDI | PB10A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS25_BIDI | PB10B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS25_BIDI | PB10C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS25_BIDI | PB10D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS25_BIDI | PB12A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS25_BIDI | PB12B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS25_BIDI | PB12C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS25_BIDI | PB12D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| UFMCLK | 29/2 | LVCMOS25_OUT | PB4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDI | 30/2 | LVCMOS25_OUT | PB4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| UFMSDO | 27/2 | LVCMOS25_IN | PB4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCCAS | 9/3 | LVCMOS25_IN | PL3C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVCMOS25_IN | PL6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 28/2 | LVCMOS25_IN | PB4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVCMOS25_OUT | PR7C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRCS | 57/1 | LVCMOS25_OUT | PR6D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRRAS | 54/1 | LVCMOS25_OUT | PR7A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nRWE | 49/2 | LVCMOS25_OUT | PB14D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -| nUFMCS | 77/0 | LVCMOS25_OUT | PT11C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | -+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| UFMSDI | 29/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS33_IN | PB4A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | +| nUFMCS | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ Vccio by Bank: +------+-------+ | Bank | Vccio | +------+-------+ -| 0 | 2.5V | -| 1 | 2.5V | -| 2 | 2.5V | -| 3 | 2.5V | +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | 3.3V | +| 3 | 3.3V | +------+-------+ @@ -110,85 +110,85 @@ Vccio by Bank: +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ | Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2A | | | | -| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2B | | | | -| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL2C | PCLKT3_2 | | | +| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | +| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | +| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | | 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | | 7/3 | unused, PULL:DOWN | | | PL3A | | | | -| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3B | | | | -| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL3C | | | | -| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL3D | | | | -| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | -| 15/3 | unused, PULL:DOWN | | | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL6A | | | | -| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL6B | | | | -| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL6C | | | | -| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL6D | | | | -| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL7A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL7B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL7C | | | | -| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL7D | | | | -| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4A | CSSPIN | | | -| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4B | | | | -| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB4C | | | | -| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB4D | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | +| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS33_IN | PB4A | CSSPIN | | | +| 28/2 | UFMCLK | LOCATED | LVCMOS33_OUT | PB4B | | | | +| 29/2 | UFMSDI | LOCATED | LVCMOS33_OUT | PB4C | | | | +| 30/2 | nUFMCS | LOCATED | LVCMOS33_OUT | PB4D | | | | | 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6B | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB6C | PCLKT2_0 | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | | 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB12D | | | | +| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | | 45/2 | unused, PULL:DOWN | | | PB14A | | | | | 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB14C | SN | | | -| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB14D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR7D | | | | -| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR7C | | | | -| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR7B | | | | -| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR7A | | | | -| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR6D | | | | -| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR6C | | | | -| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR6A | | | | -| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0 | | | -| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0 | | | -| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | | | | -| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | | | | -| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR3D | | | | -| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR3C | | | | -| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR3B | | | | -| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR3A | | | | -| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR2D | | | | -| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR2C | | | | -| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | | | | -| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | | | | -| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT11D | DONE | | | -| 77/0 | nUFMCS | | LVCMOS25_OUT | PT11C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT11A | | | | +| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | +| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | +| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | +| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | +| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | +| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | +| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | +| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | +| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | +| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | +| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | +| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | | 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT10C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT10B | | | | -| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT10A | | | | -| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT9B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT9A | PCLKT0_1 | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | | 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | | 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | | 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | | 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT6D | | | | -| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT6C | | | | -| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT6B | | | | -| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT6A | | | | +| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | | PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ @@ -264,17 +264,17 @@ LOCATE COMP "RD[4]" SITE "40"; LOCATE COMP "RD[5]" SITE "41"; LOCATE COMP "RD[6]" SITE "42"; LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "UFMCLK" SITE "29"; -LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMCLK" SITE "28"; +LOCATE COMP "UFMSDI" SITE "29"; LOCATE COMP "UFMSDO" SITE "27"; LOCATE COMP "nCCAS" SITE "9"; LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nFWE" SITE "15"; LOCATE COMP "nRCAS" SITE "52"; LOCATE COMP "nRCS" SITE "57"; LOCATE COMP "nRRAS" SITE "54"; LOCATE COMP "nRWE" SITE "49"; -LOCATE COMP "nUFMCS" SITE "77"; +LOCATE COMP "nUFMCS" SITE "30"; @@ -286,7 +286,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:34 2023 +Tue Aug 15 23:30:11 2023 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html index f7c9130..f197974 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:28 2023 +Tue Aug 15 23:30:05 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -5.122 452301 0.304 0 07 Completed +5_1 * 0 5.827 0 0.304 0 06 Completed * : Design saved. -Total (real) run time for 1-seed: 7 secs +Total (real) run time for 1-seed: 6 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -Tue Aug 15 05:03:28 2023 +Tue Aug 15 23:30:05 2023 Best Par Run @@ -65,43 +65,44 @@ Ignore Preference Error(s): True PIO (prelim) 67+4(JTAG)/80 89% used 67+4(JTAG)/79 90% bonded + IOLOGIC 29/80 36% used - SLICE 75/320 23% used + SLICE 81/320 25% used -Number of Signals: 285 -Number of Connections: 674 -WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. +Number of Signals: 292 +Number of Connections: 703 Pin Constraint Summary: - 66 out of 67 pins locked (98% locked). + 67 out of 67 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 40) - PHI2_c (driver: PHI2, clk load #: 13) + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 18) WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. -The following 1 signal is selected to use the secondary clock routing resources: - nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) +The following 2 signals are selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0) + nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset. -. Starting Placer Phase 0. -............. +........... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. -............... -Placer score = 121531. +.................... +Placer score = 41844. Finished Placer Phase 1. REAL time: 4 secs Starting Placer Phase 2. . -Placer score = 119079 +Placer score = 41803 Finished Placer Phase 2. REAL time: 4 secs @@ -110,17 +111,18 @@ Finished Placer Phase 2. REAL time: 4 secs Global Clock Resources: CLK_PIN : 0 out of 8 (0%) - General PIO: 3 out of 80 (3%) + General PIO: 4 out of 80 (5%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 - SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0 + SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 PRIMARY : 2 out of 8 (25%) - SECONDARY: 1 out of 8 (12%) + SECONDARY: 2 out of 8 (25%) @@ -135,27 +137,23 @@ I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ -| 0 | 14 / 19 ( 73%) | 2.5V | - | -| 1 | 20 / 20 (100%) | 2.5V | - | -| 2 | 16 / 20 ( 80%) | 2.5V | - | -| 3 | 17 / 20 ( 85%) | 2.5V | - | +| 0 | 13 / 19 ( 68%) | 3.3V | - | +| 1 | 20 / 20 (100%) | 3.3V | - | +| 2 | 16 / 20 ( 80%) | 3.3V | - | +| 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 3 secs Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. -0 connections routed; 674 unrouted. +0 connections routed; 703 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 +Completed router resource preassignment. Real time: 6 secs -Completed router resource preassignment. Real time: 7 secs - -Start NBR router at 05:03:35 08/15/23 +Start NBR router at 23:30:11 08/15/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -170,78 +168,63 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 05:03:35 08/15/23 +Start NBR special constraint process at 23:30:11 08/15/23 -Start NBR section for initial routing at 05:03:35 08/15/23 +Start NBR section for initial routing at 23:30:11 08/15/23 Level 1, iteration 1 -2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.914ns/-481.988ns; real time: 7 secs +0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.016ns/0.000ns; real time: 6 secs Level 2, iteration 1 -7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.988ns/-424.953ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 6 secs Level 3, iteration 1 -12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; -Estimated worst slack/total negative slack<setup>: -5.118ns/-455.640ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 6.058ns/0.000ns; real time: 6 secs Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; -Estimated worst slack/total negative slack<setup>: -5.122ns/-465.237ns; real time: 7 secs +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:03:35 08/15/23 +Start NBR section for normal routing at 23:30:11 08/15/23 Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.992ns/-461.186ns; real time: 7 secs +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs Level 4, iteration 2 -3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.992ns/-460.933ns; real time: 7 secs -Level 4, iteration 3 -2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 5 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23 + +Start NBR section for re-routing at 23:30:11 08/15/23 Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for re-routing at 05:03:35 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs - -Start NBR section for post-routing at 05:03:35 08/15/23 +Start NBR section for post-routing at 23:30:11 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 260 (38.58%) - Estimated worst slack<setup> : -5.122ns - Timing score<setup> : 452301 + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack<setup> : 5.827ns + Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. -WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. - Signal=nCCAS_c loads=6 clock_loads=4 - -Total CPU time 7 secs -Total REAL time: 7 secs +Total CPU time 5 secs +Total REAL time: 6 secs Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. +End of route. 703 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 -Timing score: 452301 +Timing score: 0 Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. @@ -251,14 +234,14 @@ All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack<setup/<ns>> = -5.122 -PAR_SUMMARY::Timing score<setup/<ns>> = 452.301 +PAR_SUMMARY::Worst slack<setup/<ns>> = 5.827 +PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 7 secs -Total REAL time to completion: 7 secs +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt new file mode 100644 index 0000000..ac8269d --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt @@ -0,0 +1,59 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 + +# Written on Tue Aug 15 23:12:43 2023 + +##### FILES SYNTAX CHECKED ############################################## +Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +--------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 +======================================================================================= + + +Clock Load Summary +****************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +RCLK 48 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) +======================================================================================== diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt.db b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt.db new file mode 100644 index 0000000000000000000000000000000000000000..33612a25abcc09ccda948d7859cc45d1eae869ad GIT binary patch literal 8192 zcmeI#y$ZrW3Y@Gy=5 literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html index d0630a7..136bdcc 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html @@ -14,7 +14,7 @@ Module Name: RAM2GS_LCMXO2_640HC Synthesis: -Lattice LSE +SynplifyPro Implementation Name: @@ -62,7 +62,7 @@ Updated: -2023/08/15 05:03:41 +2023/08/15 23:33:06 Implementation Location: diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html new file mode 100644 index 0000000..b5301ad --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html @@ -0,0 +1,1029 @@ + +Synthesis Report + + +

    Synthesis Report
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEPC
+
+# Tue Aug 15 23:12:41 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2GS
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Aug 15 23:12:41 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Aug 15 23:12:41 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Aug 15 23:12:41 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Aug 15 23:12:42 2023
+
+###########################################################]
+# Tue Aug 15 23:12:42 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+
+Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
+@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "1" on instance nUFMCS.
+@N: FX493 |Applying initial value "0" on instance UFMSDI.
+@N: FX493 |Applying initial value "0" on instance UFMCLK.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock        Clock                Clock
+Level     Clock     Frequency     Period        Type         Group                Load 
+---------------------------------------------------------------------------------------
+0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
+                                                                                       
+0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
+                                                                                       
+0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                       
+0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
+=======================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+RCLK      48        RCLK(port)      CASr2.C         -                 -                 
+                                                                                        
+PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                        
+nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                        
+nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   48         nRWE           
+@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Aug 15 23:12:44 2023
+
+###########################################################]
+# Tue Aug 15 23:12:44 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -2.34ns		 128 /        89
+   2		0h:00m:01s		    -2.34ns		 140 /        89
+   3		0h:00m:01s		    -2.34ns		 140 /        89
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+Timing driven replication report
+Added 1 Registers via timing driven replication
+Added 0 LUTs via timing driven replication
+
+   4		0h:00m:01s		    -2.04ns		 140 /        90
+
+
+   5		0h:00m:01s		    -2.04ns		 141 /        90
+   6		0h:00m:01s		    -2.04ns		 141 /        90
+   7		0h:00m:01s		    -2.04ns		 141 /        90
+   8		0h:00m:01s		    -2.04ns		 141 /        90
+   9		0h:00m:01s		    -2.04ns		 141 /        90
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
+
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Tue Aug 15 23:12:47 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        3
+Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -2.389
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
+RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+--------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
+--------------------------------------------------------------------------------------------------------------
+RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
+PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
+==============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                 Starting                                            Arrival            
+Instance         Reference     Type         Pin     Net              Time        Slack  
+                 Clock                                                                  
+----------------------------------------------------------------------------------------
+CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
+CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
+CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
+CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
+Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
+CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
+Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
+Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
+Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
+Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                Starting                                                Required            
+Instance        Reference     Type         Pin     Net                  Time         Slack  
+                Clock                                                                       
+--------------------------------------------------------------------------------------------
+UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
+nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
+UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
+LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
+n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
+LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
+n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
+UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
+ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
+C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.917
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -2.389
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMCLK_0io / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
+CmdSubmitted         Net          -        -       -         -           4         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
+N_141_i              Net          -        -       -         -           3         
+UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
+UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
+i2_i                 Net          -        -       -         -           1         
+UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
+===================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.917
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.829
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            nUFMCS / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin      Pin               Arrival     No. of    
+Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------
+CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
+CmdSubmitted         Net          -        -       -         -           4         
+PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
+PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
+N_141_i              Net          -        -       -         -           3         
+nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
+nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
+nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
+nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
+===================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.462
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.462
+
+    - Propagation time:                      3.214
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.751
+
+    Number of logic level(s):                2
+    Starting point:                          CmdSubmitted / Q
+    Ending point:                            UFMSDI / D
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
+CmdSubmitted        Net          -        -       -         -           4         
+PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
+PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
+N_141_i             Net          -        -       -         -           3         
+UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
+UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
+UFMSDI_RNO          Net          -        -       -         -           1         
+UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+               Starting                                         Arrival           
+Instance       Reference     Type        Pin     Net            Time        Slack 
+               Clock                                                              
+----------------------------------------------------------------------------------
+Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
+LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
+n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
+FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
+FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
+InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+==================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required           
+Instance       Reference     Type         Pin     Net            Time         Slack 
+               Clock                                                                
+------------------------------------------------------------------------------------
+RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
+RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
+RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
+RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
+RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
+RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
+RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
+RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
+RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
+RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
+====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[0] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[0]          Net          -        -       -         -           1         
+RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[9] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
+RowAd_0[9]         Net          -        -       -         -           1         
+RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[8] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[8]         Net          -        -       -         -           1         
+RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                   Arrival           
+Instance     Reference     Type        Pin     Net      Time        Slack 
+             Clock                                                        
+--------------------------------------------------------------------------
+CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
+FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
+==========================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required           
+Instance       Reference     Type         Pin     Net                Time         Slack 
+               Clock                                                                    
+----------------------------------------------------------------------------------------
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
+nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
+nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.909
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.821
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
+CBR                       Net          -        -       -         -           7         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
+N_179_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+========================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.909
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.821
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRWE_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
+CBR                       Net          -        -       -         -           7         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
+N_180_i                   Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+========================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.853
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.765
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
+FWEr                    Net          -        -       -         -           4         
+nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
+nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
+N_27_i_1                Net          -        -       -         -           2         
+nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
+nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
+N_179_i                 Net          -        -       -         -           1         
+nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
+======================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 90 of 640 (14%)
+PIC Latch:       0
+I/O cells:       67
+
+
+Details:
+BB:             8
+CCU2D:          10
+FD1P3AX:        11
+FD1S3AX:        49
+FD1S3AY:        1
+FD1S3IX:        3
+GSR:            1
+IB:             26
+IFS1P3DX:       9
+INV:            7
+OB:             33
+OFS1P3BX:       4
+OFS1P3DX:       12
+OFS1P3JX:       1
+ORCALUT4:       135
+PFUMX:          1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Aug 15 23:12:47 2023
+
+###########################################################]
+
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+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf new file mode 100644 index 0000000..2b0f89b --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf @@ -0,0 +1,24 @@ +# +# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R. +# + +# Period Constraints +FREQUENCY PORT "PHI2" 2.9 MHz; +FREQUENCY PORT "nCCAS" 2.9 MHz; +FREQUENCY PORT "nCRAS" 2.9 MHz; +FREQUENCY PORT "RCLK" 62.5 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl new file mode 100644 index 0000000..04a6c81 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl @@ -0,0 +1,65 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file + +#device options +set_option -technology MACHXO2 +set_option -part LCMXO2_640HC +set_option -package TG100C +set_option -speed_grade -4 + +#compilation/mapping options +set_option -symbolic_fsm_compiler true +set_option -resource_sharing true + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 70 +set_option -maxfan 1000 +set_option -auto_constrain_io 0 +set_option -disable_io_insertion false +set_option -retiming false; set_option -pipe false +set_option -force_gsr auto +set_option -compiler_compatible 0 +set_option -dup false + +add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc} +set_option -default_enum_encoding default + +#simulation options + + +#timing analysis options +set_option -num_critical_paths 3 + + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#synplifyPro options +set_option -fix_gated_and_generated_clocks 1 +set_option -update_models_cp 0 +set_option -resolve_multiple_driver 0 + + +set_option -seqshift_no_replicate 0 + +#-- add_file options +set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC} +add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v} + +#-- top module name +set_option -top_module RAM2GS + +#-- set result format/file last +project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi} + +#-- error message log file +project -log_file {RAM2GS_LCMXO2_640HC_impl1.srf} + +#-- set any command lines input by customer + + +#-- run Synplify with 'arrange HDL file' +project -run -clean diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp2.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp4.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp8.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html index ea92308..0a00dda 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 +Tue Aug 15 22:56:32 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,15 +41,18 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • -     459 items scored, 245 timing errors detected. -Warning: 139.762MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 170 items scored, 0 timing errors detected. +Report: 47.214MHz is the maximum frequency for this preference. -
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • -     113 items scored, 104 timing errors detected. -Warning: 50.592MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. +Report: 150.150MHz is the maximum frequency for this preference. + +
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. +Report: 150.150MHz is the maximum frequency for this preference. + +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 590 items scored, 0 timing errors detected. +Report: 86.296MHz is the maximum frequency for this preference. -Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- @@ -57,87 +60,131 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 245 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 3.815ns +Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i13 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + Delay: 10.424ns (36.2% logic, 63.8% route), 7 logic levels. Constraint Details: - 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + 10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns Physical Path Details: - Data path SLICE_0 to SLICE_57: + Data path Din[3]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 -CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 -ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 -CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 -ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 -CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 -ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 e 1.234 *n[3]_MGIOL.IN to SLICE_43.C1 Bank[3] +CTOF_DEL --- 0.495 SLICE_43.C1 to SLICE_43.F1 SLICE_43 +ROUTE 1 e 1.234 SLICE_43.F1 to SLICE_69.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 SLICE_69.D0 to SLICE_69.F0 SLICE_69 +ROUTE 5 e 1.234 SLICE_69.F0 to SLICE_60.D0 un1_Bank_1 +CTOF_DEL --- 0.495 SLICE_60.D0 to SLICE_60.F0 SLICE_60 +ROUTE 2 e 1.234 SLICE_60.F0 to SLICE_46.A1 ADWR +CTOF_DEL --- 0.495 SLICE_46.A1 to SLICE_46.F1 SLICE_46 +ROUTE 3 e 0.480 SLICE_46.F1 to SLICE_46.D0 un1_ADWR +CTOF_DEL --- 0.495 SLICE_46.D0 to SLICE_46.F0 SLICE_46 +ROUTE 1 e 1.234 SLICE_46.F0 to SLICE_18.C0 un1_CMDWR +CTOOFX_DEL --- 0.721 SLICE_18.C0 to SLICE_18.OFX0 SLICE_18 +ROUTE 1 e 0.001 SLICE_18.OFX0 to SLICE_18.DI0 CmdEnable_s (to PHI2_c) -------- - 6.873 (28.2% logic, 71.8% route), 4 logic levels. + 10.424 (36.2% logic, 63.8% route), 7 logic levels. -Warning: 139.762MHz is the maximum frequency for this preference. +Report: 47.214MHz is the maximum frequency for this preference. ================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 104 timing errors detected. +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 4.412ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels. Constraint Details: - 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less - 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + 11.306ns physical path delay SLICE_1 to SLICE_27 meets + 16.000ns delay constraint less + 0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_1 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 -CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 -ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 -CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 -ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 -CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 -ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 -CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 -ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 -CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 -ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_1.Q0 to SLICE_72.D1 FS[17] +CTOF_DEL --- 0.495 SLICE_72.D1 to SLICE_72.F1 SLICE_72 +ROUTE 1 e 1.234 SLICE_72.F1 to SLICE_64.C1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 SLICE_64.C1 to SLICE_64.F1 SLICE_64 +ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_59.C1 N_129 +CTOF_DEL --- 0.495 SLICE_59.C1 to SLICE_59.F1 SLICE_59 +ROUTE 2 e 0.480 SLICE_59.F1 to SLICE_59.D0 N_145 +CTOF_DEL --- 0.495 SLICE_59.D0 to SLICE_59.F0 SLICE_59 +ROUTE 2 e 1.234 SLICE_59.F0 to SLICE_56.B0 N_139_8 +CTOF_DEL --- 0.495 SLICE_56.B0 to SLICE_56.F0 SLICE_56 +ROUTE 1 e 1.234 SLICE_56.F0 to SLICE_54.C0 N_140 +CTOF_DEL --- 0.495 SLICE_54.C0 to SLICE_54.F0 SLICE_54 +ROUTE 1 e 1.234 SLICE_54.F0 to SLICE_27.CE N_28 (to RCLK_c) -------- - 9.577 (30.6% logic, 69.4% route), 6 logic levels. + 11.306 (30.3% logic, 69.7% route), 7 logic levels. -Warning: 50.592MHz is the maximum frequency for this preference. +Report: 86.296MHz is the maximum frequency for this preference. Report Summary -------------- @@ -145,21 +192,18 @@ Warning: 50.592MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.214 MHz| 7 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 86.296 MHz| 7 | | | ---------------------------------------------------------------------------- -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 78| 22.35% - | | | ----------------------------------------------------------------------------- +All preferences were met. Clock Domains Analysis @@ -167,14 +211,20 @@ n26 | 8| 78| 22.35% Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -187,8 +237,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -200,14 +250,14 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing summary (Setup): --------------- -Timing errors: 349 Score: 848079 -Cumulative negative slack: 584487 +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 +Tue Aug 15 22:56:32 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -226,9 +276,13 @@ Report level: verbose report, limited to 1 item per preference Preference Summary -
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    • 459 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 170 items scored, 0 timing errors detected. -
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    • 113 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. + +
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. + +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 590 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -237,40 +291,8 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.351ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. - - Constraint Details: - - 0.332ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) - -------- - 0.332 (40.1% logic, 59.9% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -278,38 +300,86 @@ Passed: The following path meets requirements by 0.447ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. Constraint Details: - 0.434ns physical path delay SLICE_15 to SLICE_15 meets + 0.434ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns Physical Path Details: - Data path SLICE_15 to SLICE_15: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted -CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 -ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted +CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10 +ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c) -------- 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_14.Q0 to SLICE_14.M1 CASr (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- @@ -322,14 +392,20 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -342,8 +418,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -358,16 +434,16 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage) Timing summary (Setup and Hold): --------------- -Timing errors: 349 (setup), 0 (hold) -Score: 848079 (setup), 0 (hold) -Cumulative negative slack: 584487 (584487+0) +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html index 7c66cde..4a10516 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 +Tue Aug 15 22:56:39 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -41,15 +41,18 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (264 errors)
    • -     459 items scored, 264 timing errors detected. -Warning: 160.205MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 170 items scored, 0 timing errors detected. +Report: 55.475MHz is the maximum frequency for this preference. -
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (85 errors)
    • -     113 items scored, 85 timing errors detected. -Warning: 65.729MHz is the maximum frequency for this preference. +
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. +Report: 150.150MHz is the maximum frequency for this preference. + +
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. +Report: 150.150MHz is the maximum frequency for this preference. + +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 590 items scored, 0 timing errors detected. +Report: 101.286MHz is the maximum frequency for this preference. -Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- @@ -57,1045 +60,1125 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 264 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 2.902ns +Passed: The following path meets requirements by 163.401ns (weighted slack = 326.802ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in UFMSDI_417 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 6.076ns (40.0% logic, 60.0% route), 5 logic levels. + Delay: 8.950ns (28.6% logic, 71.4% route), 5 logic levels. Constraint Details: - 6.076ns physical path delay SLICE_1 to SLICE_45 exceeds - 3.340ns delay constraint less + 8.950ns physical path delay Din[3]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.401ns Physical Path Details: - Data path SLICE_1 to SLICE_45: + Data path Din[3]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 -CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 -CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 -ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 -CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 -ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 -CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 6.076 (40.0% logic, 60.0% route), 5 logic levels. + 8.950 (28.6% logic, 71.4% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_45: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.710ns +Passed: The following path meets requirements by 163.452ns (weighted slack = 326.904ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i14 (from RCLK_c +) - Destination: FF Data in UFMSDI_417 (to RCLK_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.884ns (41.3% logic, 58.7% route), 5 logic levels. + Delay: 8.899ns (28.7% logic, 71.3% route), 5 logic levels. Constraint Details: - 5.884ns physical path delay SLICE_0 to SLICE_45 exceeds - 3.340ns delay constraint less + 8.899ns physical path delay Din[7]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.452ns Physical Path Details: - Data path SLICE_0 to SLICE_45: + Data path Din[7]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q1 SLICE_0 (from RCLK_c) -ROUTE 5 0.792 R6C8D.Q1 to R4C8D.C1 FS_14 -CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 -CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 -ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 -CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 -ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 -CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 -ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7] +CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.884 (41.3% logic, 58.7% route), 5 logic levels. + 8.899 (28.7% logic, 71.3% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_0: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_45: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.665ns +Passed: The following path meets requirements by 163.522ns (weighted slack = 327.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CASr2_383 (from RCLK_c +) - Destination: FF Data in nRCS_396 (to RCLK_c +) + Source: FF Q Bank_0io[4] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.839ns (41.7% logic, 58.3% route), 5 logic levels. + Delay: 8.829ns (29.0% logic, 71.0% route), 5 logic levels. Constraint Details: - 5.839ns physical path delay SLICE_16 to SLICE_61 exceeds - 3.340ns delay constraint less + 8.829ns physical path delay Din[4]_MGIOL to Din[0]_MGIOL meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns + 0.063ns CE_SET requirement (totaling 172.351ns) by 163.522ns Physical Path Details: - Data path SLICE_16 to SLICE_61: + Data path Din[4]_MGIOL to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C9B.CLK to R4C9B.Q1 SLICE_16 (from RCLK_c) -ROUTE 3 1.000 R4C9B.Q1 to R6C9D.A0 CASr2 -CTOF_DEL --- 0.495 R6C9D.A0 to R6C9D.F0 SLICE_96 -ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 -CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 -ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 -CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 -ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 -CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 -ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4] +CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.839 (41.7% logic, 58.3% route), 5 logic levels. + 8.829 (29.0% logic, 71.0% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_16: + Source Clock Path PHI2 to Din[4]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C9B.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_61: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.621ns +Passed: The following path meets requirements by 163.573ns (weighted slack = 327.146ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.679ns (34.1% logic, 65.9% route), 4 logic levels. + Delay: 8.502ns (44.4% logic, 55.6% route), 7 logic levels. Constraint Details: - 5.679ns physical path delay SLICE_9 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns + 8.502ns physical path delay Din[3]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.573ns Physical Path Details: - Data path SLICE_9 to SLICE_57: + Data path Din[3]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.793 R4C8A.F0 to R4C8B.C1 n10 -CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 SLICE_57 -ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 -CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.679 (34.1% logic, 65.9% route), 4 logic levels. + 8.502 (44.4% logic, 55.6% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.513ns +Passed: The following path meets requirements by 163.624ns (weighted slack = 327.248ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i12 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[7] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.571ns (34.8% logic, 65.2% route), 4 logic levels. + Delay: 8.451ns (44.6% logic, 55.4% route), 7 logic levels. Constraint Details: - 5.571ns physical path delay SLICE_1 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns + 8.451ns physical path delay Din[7]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.624ns Physical Path Details: - Data path SLICE_1 to SLICE_57: + Data path Din[7]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) -ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 -CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 -ROUTE 3 1.021 R4C8D.F1 to R4C8B.B1 n2375 -CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_57 -ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 -CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7] +CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.571 (34.8% logic, 65.2% route), 4 logic levels. + 8.451 (44.6% logic, 55.4% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_1: + Source Clock Path PHI2 to Din[7]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.487ns +Passed: The following path meets requirements by 163.694ns (weighted slack = 327.388ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i3 (from RCLK_c +) - Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + Source: FF Q Bank_0io[4] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.545ns (34.9% logic, 65.1% route), 4 logic levels. + Delay: 8.381ns (45.0% logic, 55.0% route), 7 logic levels. Constraint Details: - 5.545ns physical path delay SLICE_8 to SLICE_57 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns + 8.381ns physical path delay Din[4]_MGIOL to SLICE_18 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 163.694ns Physical Path Details: - Data path SLICE_8 to SLICE_57: + Data path Din[4]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7C.CLK to R6C7C.Q0 SLICE_8 (from RCLK_c) -ROUTE 2 1.306 R6C7C.Q0 to R4C7D.A1 FS_3 -CTOF_DEL --- 0.495 R4C7D.A1 to R4C7D.F1 SLICE_86 -ROUTE 1 1.004 R4C7D.F1 to R4C7D.B0 n14 -CTOF_DEL --- 0.495 R4C7D.B0 to R4C7D.F0 SLICE_86 -ROUTE 1 0.645 R4C7D.F0 to R4C8C.D0 n4_adj_7 -CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_84 -ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c) +ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4] +CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.545 (34.9% logic, 65.1% route), 4 logic levels. + 8.381 (45.0% logic, 55.0% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_8: + Source Clock Path PHI2 to Din[4]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C7C.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_57: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.479ns +Passed: The following path meets requirements by 163.812ns (weighted slack = 327.624ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in nUFMCS_415 (to RCLK_c +) + Source: FF Q Bank_0io[0] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.653ns (43.0% logic, 57.0% route), 5 logic levels. + Delay: 8.712ns (27.9% logic, 72.1% route), 5 logic levels. Constraint Details: - 5.653ns physical path delay SLICE_9 to SLICE_70 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns + 8.712ns physical path delay SLICE_63 to Din[0]_MGIOL meets + 172.414ns delay constraint less + -0.173ns skew and + 0.063ns CE_SET requirement (totaling 172.524ns) by 163.812ns Physical Path Details: - Data path SLICE_9 to SLICE_70: + Data path SLICE_63 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.640 R4C8A.F0 to R4C9D.D1 n10 -CTOF_DEL --- 0.495 R4C9D.D1 to R4C9D.F1 SLICE_76 -ROUTE 2 0.635 R4C9D.F1 to R4C9A.D1 n2368 -CTOF_DEL --- 0.495 R4C9A.D1 to R4C9A.F1 SLICE_70 -ROUTE 1 0.626 R4C9A.F1 to R4C9A.D0 n64 -CTOF_DEL --- 0.495 R4C9A.D0 to R4C9A.F0 SLICE_70 -ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 nUFMCS_N_199 (to RCLK_c) +REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c) +ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0] +CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.653 (43.0% logic, 57.0% route), 5 logic levels. + 8.712 (27.9% logic, 72.1% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to SLICE_63: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_70: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C9A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.452ns +Passed: The following path meets requirements by 163.984ns (weighted slack = 327.968ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i15 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) + Source: FF Q Bank_0io[0] (from PHI2_c +) + Destination: FF Data in CmdEnable (to PHI2_c -) - Delay: 5.626ns (43.2% logic, 56.8% route), 5 logic levels. + Delay: 8.264ns (44.1% logic, 55.9% route), 7 logic levels. Constraint Details: - 5.626ns physical path delay SLICE_9 to SLICE_44 exceeds - 3.340ns delay constraint less + 8.264ns physical path delay SLICE_63 to SLICE_18 meets + 172.414ns delay constraint less 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns + 0.166ns DIN_SET requirement (totaling 172.248ns) by 163.984ns Physical Path Details: - Data path SLICE_9 to SLICE_44: + Data path SLICE_63 to SLICE_18: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) -ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 -CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 -ROUTE 5 0.672 R4C8A.F0 to R4C8A.D1 n10 -CTOF_DEL --- 0.495 R4C8A.D1 to R4C8A.F1 SLICE_85 -ROUTE 1 0.766 R4C8A.F1 to R4C6B.C1 n2267 -CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_44 -ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 -CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) +REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c) +ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0] +CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR +CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46 +ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR +CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46 +ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR +CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) -------- - 5.626 (43.2% logic, 56.8% route), 5 logic levels. + 8.264 (44.1% logic, 55.9% route), 7 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_9: + Source Clock Path PHI2 to SLICE_63: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_44: + Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.438ns +Passed: The following path meets requirements by 164.041ns (weighted slack = 328.082ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CASr3_384 (from RCLK_c +) - Destination: FF Data in nRCS_396 (to RCLK_c +) + Source: FF Q Bank_0io[3] (from PHI2_c +) + Destination: FF Data in ADSubmitted (to PHI2_c -) - Delay: 5.612ns (43.3% logic, 56.7% route), 5 logic levels. + Delay: 8.034ns (38.0% logic, 62.0% route), 6 logic levels. Constraint Details: - 5.612ns physical path delay SLICE_5 to SLICE_61 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns + 8.034ns physical path delay Din[3]_MGIOL to SLICE_10 meets + 172.414ns delay constraint less + 0.173ns skew and + 0.166ns DIN_SET requirement (totaling 172.075ns) by 164.041ns Physical Path Details: - Data path SLICE_5 to SLICE_61: + Data path Din[3]_MGIOL to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) -ROUTE 2 0.773 R6C7A.Q0 to R6C9D.C0 CASr3 -CTOF_DEL --- 0.495 R6C9D.C0 to R6C9D.F0 SLICE_96 -ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 -CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 -ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 -CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 -ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 -CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 -ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) +C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c) +ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3] +CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43 +ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4 +CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60 +ROUTE 2 0.758 R4C8D.F0 to R3C8B.C1 ADWR +CTOF_DEL --- 0.495 R3C8B.C1 to R3C8B.F1 SLICE_10 +ROUTE 2 1.013 R3C8B.F1 to R3C8B.B0 CmdEnable17 +CTOF_DEL --- 0.495 R3C8B.B0 to R3C8B.F0 SLICE_10 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c) -------- - 5.612 (43.3% logic, 56.7% route), 5 logic levels. + 8.034 (38.0% logic, 62.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_5: + Source Clock Path PHI2 to Din[3]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C7A.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_61: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C8B.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.423ns +Passed: The following path meets requirements by 164.046ns (weighted slack = 328.092ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q FS_610__i13 (from RCLK_c +) - Destination: FF Data in UFMCLK_416 (to RCLK_c +) + Source: FF Q Bank_0io[2] (from PHI2_c +) + Destination: FF Data in CmdUFMSDI (to PHI2_c -) - Delay: 5.597ns (43.5% logic, 56.5% route), 5 logic levels. + Delay: 8.478ns (28.7% logic, 71.3% route), 5 logic levels. Constraint Details: - 5.597ns physical path delay SLICE_0 to SLICE_44 exceeds - 3.340ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns + 8.478ns physical path delay SLICE_68 to Din[0]_MGIOL meets + 172.414ns delay constraint less + -0.173ns skew and + 0.063ns CE_SET requirement (totaling 172.524ns) by 164.046ns Physical Path Details: - Data path SLICE_0 to SLICE_44: + Data path SLICE_68 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q0 SLICE_0 (from RCLK_c) -ROUTE 3 1.433 R6C8D.Q0 to R6C6C.B0 FS_13 -CTOF_DEL --- 0.495 R6C6C.B0 to R6C6C.F0 SLICE_105 -ROUTE 1 0.315 R6C6C.F0 to R6C6A.D1 n12 -CTOF_DEL --- 0.495 R6C6A.D1 to R6C6A.F1 SLICE_82 -ROUTE 3 0.981 R6C6A.F1 to R4C6B.D1 n13_adj_6 -CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 SLICE_44 -ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 -CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 -ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) +REG_DEL --- 0.452 R3C9C.CLK to R3C9C.Q0 SLICE_68 (from PHI2_c) +ROUTE 1 1.079 R3C9C.Q0 to R3C6A.C1 Bank[2] +CTOF_DEL --- 0.495 R3C6A.C1 to R3C6A.F1 SLICE_69 +ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69 +ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1 +CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57 +ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20 +ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c) -------- - 5.597 (43.5% logic, 56.5% route), 5 logic levels. + 8.478 (28.7% logic, 71.3% route), 5 logic levels. Clock Skew Details: - Source Clock Path RCLK to SLICE_0: + Source Clock Path PHI2 to SLICE_68: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c +ROUTE 19 3.539 8.PADDI to R3C9C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.539 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path RCLK to SLICE_44: + Destination Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c +ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. + 3.712 (0.0% logic, 100.0% route), 0 logic levels. -Warning: 160.205MHz is the maximum frequency for this preference. +Report: 55.475MHz is the maximum frequency for this preference. ================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 85 timing errors detected. +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- -Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns) +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCCAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 338.168ns + The internal maximum frequency of the following component is 150.150 MHz + + Logical Details: Cell type Pin name Component name + + Destination: PIO PAD nCRAS + + Delay: 6.660ns -- based on Minimum Pulse Width + +Report: 150.150MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 6.127ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 7.301ns (40.1% logic, 59.9% route), 6 logic levels. + Delay: 9.591ns (35.7% logic, 64.3% route), 7 logic levels. Constraint Details: - 7.301ns physical path delay SLICE_103 to SLICE_19 exceeds - 5.047ns delay constraint less + 9.591ns physical path delay SLICE_4 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.127ns Physical Path Details: - Data path SLICE_103 to SLICE_19: + Data path SLICE_4 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12] +CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 7.301 (40.1% logic, 59.9% route), 6 logic levels. + 9.591 (35.7% logic, 64.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) +Passed: The following path meets requirements by 6.287ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + Delay: 9.431ns (36.3% logic, 63.7% route), 7 logic levels. Constraint Details: - 6.946ns physical path delay SLICE_103 to SLICE_10 exceeds - 5.047ns delay constraint less + 9.431ns physical path delay SLICE_1 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.287ns Physical Path Details: - Data path SLICE_103 to SLICE_10: + Data path SLICE_1 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17] +CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.946 (35.0% logic, 65.0% route), 5 logic levels. + 9.431 (36.3% logic, 63.7% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) +Passed: The following path meets requirements by 6.319ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + Delay: 9.399ns (36.4% logic, 63.6% route), 7 logic levels. Constraint Details: - 6.946ns physical path delay SLICE_103 to SLICE_15 exceeds - 5.047ns delay constraint less + 9.399ns physical path delay SLICE_3 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.319ns Physical Path Details: - Data path SLICE_103 to SLICE_15: + Data path SLICE_3 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) -ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 -CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13] +CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.946 (35.0% logic, 65.0% route), 5 logic levels. + 9.399 (36.4% logic, 63.6% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_103: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns) +Passed: The following path meets requirements by 6.646ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[14] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.901ns (42.4% logic, 57.6% route), 6 logic levels. + Delay: 9.072ns (37.7% logic, 62.3% route), 7 logic levels. Constraint Details: - 6.901ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less + 9.072ns physical path delay SLICE_3 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.646ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_3 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 0.658 R6C4D.Q1 to R6C5D.D1 FS[14] +CTOF_DEL --- 0.495 R6C5D.D1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.901 (42.4% logic, 57.6% route), 6 logic levels. + 9.072 (37.7% logic, 62.3% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns) +Passed: The following path meets requirements by 6.977ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.832ns (42.8% logic, 57.2% route), 6 logic levels. + Delay: 8.741ns (39.1% logic, 60.9% route), 7 logic levels. Constraint Details: - 6.832ns physical path delay SLICE_101 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.741ns physical path delay SLICE_4 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 6.977ns Physical Path Details: - Data path SLICE_101 to SLICE_19: + Data path SLICE_4 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q1 SLICE_101 (from PHI2_c) -ROUTE 1 0.744 R4C7C.Q1 to R5C7B.C1 Bank_7 -CTOF_DEL --- 0.495 R5C7B.C1 to R5C7B.F1 SLICE_100 -ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 -CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12] +CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.832 (42.8% logic, 57.2% route), 6 logic levels. + 8.741 (39.1% logic, 60.9% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns) +Passed: The following path meets requirements by 7.097ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[16] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.821ns (42.9% logic, 57.1% route), 6 logic levels. + Delay: 8.621ns (34.0% logic, 66.0% route), 6 logic levels. Constraint Details: - 6.821ns physical path delay SLICE_102 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.621ns physical path delay SLICE_2 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.097ns Physical Path Details: - Data path SLICE_102 to SLICE_19: + Data path SLICE_2 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C6A.CLK to R5C6A.Q0 SLICE_102 (from PHI2_c) -ROUTE 1 0.766 R5C6A.Q0 to R5C8D.C1 Bank_4 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 -CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 -ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 -CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c) +ROUTE 4 1.017 R6C5A.Q1 to R6C5C.B1 FS[16] +CTOF_DEL --- 0.495 R6C5C.B1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.821 (42.9% logic, 57.1% route), 6 logic levels. + 8.621 (34.0% logic, 66.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_102: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns) +Passed: The following path meets requirements by 7.137ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[17] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.711ns (43.6% logic, 56.4% route), 6 logic levels. + Delay: 8.581ns (39.9% logic, 60.1% route), 7 logic levels. Constraint Details: - 6.711ns physical path delay SLICE_93 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.581ns physical path delay SLICE_1 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.137ns Physical Path Details: - Data path SLICE_93 to SLICE_19: + Data path SLICE_1 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q0 SLICE_93 (from PHI2_c) -ROUTE 1 0.623 R5C8C.Q0 to R5C7B.D1 Bank_0 -CTOF_DEL --- 0.495 R5C7B.D1 to R5C7B.F1 SLICE_100 -ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 -CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c) +ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17] +CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.711 (43.6% logic, 56.4% route), 6 logic levels. + 8.581 (39.9% logic, 60.1% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns) +Passed: The following path meets requirements by 7.169ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in n8MEGEN (to RCLK_c +) - Delay: 6.681ns (43.8% logic, 56.2% route), 6 logic levels. + Delay: 8.549ns (40.0% logic, 60.0% route), 7 logic levels. Constraint Details: - 6.681ns physical path delay SLICE_93 to SLICE_19 exceeds - 5.047ns delay constraint less + 8.549ns physical path delay SLICE_3 to SLICE_43 meets + 16.000ns delay constraint less 0.000ns skew and - 0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.169ns Physical Path Details: - Data path SLICE_93 to SLICE_19: + Data path SLICE_3 to SLICE_43: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.626 R5C8C.Q1 to R5C8D.D1 Bank_1 -CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 -CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 -ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 -CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 -CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13] +CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72 +ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3 +CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8 +CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55 +ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139 +CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55 +ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c) -------- - 6.681 (43.8% logic, 56.2% route), 6 logic levels. + 8.549 (40.0% logic, 60.0% route), 7 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path RCLK to SLICE_43: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) +Passed: The following path meets requirements by 7.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in UFMCLK_0io (to RCLK_c +) - Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + Delay: 8.739ns (27.8% logic, 72.2% route), 5 logic levels. Constraint Details: - 6.546ns physical path delay SLICE_101 to SLICE_10 exceeds - 5.047ns delay constraint less - 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + 8.739ns physical path delay SLICE_4 to UFMCLK_MGIOL meets + 16.000ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 16.020ns) by 7.281ns Physical Path Details: - Data path SLICE_101 to SLICE_10: + Data path SLICE_4 to UFMCLK_MGIOL: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 1.434 R6C4C.Q1 to R6C5D.B0 FS[12] +CTOF_DEL --- 0.495 R6C5D.B0 to R6C5D.F0 SLICE_72 +ROUTE 2 1.902 R6C5D.F0 to R5C5C.A1 N_137_5 +CTOF_DEL --- 0.495 R5C5C.A1 to R5C5C.F1 SLICE_48 +ROUTE 2 0.982 R5C5C.F1 to R5C5C.A0 UFMCLK_r_i_a2_2_2 +CTOF_DEL --- 0.495 R5C5C.A0 to R5C5C.F0 SLICE_48 +ROUTE 1 0.693 R5C5C.F0 to R5C5D.B0 d_m3_0_a2_0 +CTOF_DEL --- 0.495 R5C5D.B0 to R5C5D.F0 SLICE_47 +ROUTE 1 1.296 R5C5D.F0 to IOL_B4C.OPOS i1_i (to RCLK_c) -------- - 6.546 (37.2% logic, 62.8% route), 5 logic levels. + 8.739 (27.8% logic, 72.2% route), 5 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_10: + Destination Clock Path RCLK to UFMCLK_MGIOL: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 39 3.243 62.PADDI to IOL_B4C.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.243 (0.0% logic, 100.0% route), 0 logic levels. -Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) +Passed: The following path meets requirements by 7.354ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q FS[15] (from RCLK_c +) + Destination: FF Data in LEDEN (to RCLK_c +) - Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + Delay: 8.364ns (35.0% logic, 65.0% route), 6 logic levels. Constraint Details: - 6.546ns physical path delay SLICE_101 to SLICE_15 exceeds - 5.047ns delay constraint less + 8.364ns physical path delay SLICE_2 to SLICE_27 meets + 16.000ns delay constraint less 0.000ns skew and - 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + 0.282ns CE_SET requirement (totaling 15.718ns) by 7.354ns Physical Path Details: - Data path SLICE_101 to SLICE_15: + Data path SLICE_2 to SLICE_27: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) -ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 -CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 -ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 -CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 -ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 -CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 -ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 -CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 -ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) +REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 0.760 R6C5A.Q0 to R6C5C.C1 FS[15] +CTOF_DEL --- 0.495 R6C5C.C1 to R6C5C.F1 SLICE_64 +ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129 +CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59 +ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145 +CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59 +ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8 +CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56 +ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140 +CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54 +ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c) -------- - 6.546 (37.2% logic, 62.8% route), 5 logic levels. + 8.364 (35.0% logic, 65.0% route), 6 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_101: + Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_27: Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. + 3.070 (0.0% logic, 100.0% route), 0 logic levels. -Warning: 65.729MHz is the maximum frequency for this preference. +Report: 101.286MHz is the maximum frequency for this preference. Report Summary -------------- @@ -1103,31 +1186,18 @@ Warning: 65.729MHz is the maximum frequency for this preference. Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 160.205 MHz| 5 * +FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 55.475 MHz| 5 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 65.729 MHz| 6 * +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 101.286 MHz| 7 | | | ---------------------------------------------------------------------------- -2 preferences(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -n26 | 8| 63| 18.05% - | | | -n1996 | 1| 49| 14.04% - | | | -n1997 | 1| 46| 13.18% - | | | -n1995 | 1| 45| 12.89% - | | | -n1998 | 1| 38| 10.89% - | | | -n1994 | 1| 37| 10.60% - | | | ----------------------------------------------------------------------------- +All preferences were met. Clock Domains Analysis @@ -1135,14 +1205,20 @@ Critical Nets | Loads| Errors| % of total Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -1155,8 +1231,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -1168,14 +1244,14 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing summary (Setup): --------------- -Timing errors: 349 Score: 452301 -Cumulative negative slack: 370485 +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 +Tue Aug 15 22:56:39 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -1194,9 +1270,13 @@ Report level: verbose report, limited to 10 items per preference Preference Summary -
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    • 459 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    • 170 items scored, 0 timing errors detected. -
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    • 113 items scored, 0 timing errors detected. +
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. + +
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    • 0 items scored, 0 timing errors detected. + +
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    • 590 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS @@ -1205,444 +1285,8 @@ BLOCK RESETPATHS ================================================================================ -Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; - 459 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_106 to SLICE_106 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_106 to SLICE_106: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8D.CLK to R3C8D.Q0 SLICE_106 (from RCLK_c) -ROUTE 1 0.152 R3C8D.Q0 to R3C8D.M1 n736 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_106: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr_382 (from RCLK_c +) - Destination: FF Data in CASr2_383 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_16 to SLICE_16 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_16 to SLICE_16: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_16 (from RCLK_c) -ROUTE 1 0.152 R4C9B.Q0 to R4C9B.M1 CASr (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i8 (from RCLK_c +) - Destination: FF Data in IS_FSM__i9 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_75 to SLICE_75 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_75 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.152 R3C9D.Q0 to R3C9D.M1 n732 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i10 (from RCLK_c +) - Destination: FF Data in IS_FSM__i11 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_79 to SLICE_79 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_79 to SLICE_79: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_79 (from RCLK_c) -ROUTE 1 0.152 R5C8B.Q0 to R5C8B.M1 n730 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_79: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_79: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i14 (from RCLK_c +) - Destination: FF Data in IS_FSM__i15 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_81 to SLICE_81 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_81 to SLICE_81: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C9C.CLK to R6C9C.Q0 SLICE_81 (from RCLK_c) -ROUTE 1 0.152 R6C9C.Q0 to R6C9C.M1 n726 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_81: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i7 (from RCLK_c +) - Destination: FF Data in IS_FSM__i8 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_97 to SLICE_75 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q1 SLICE_97 (from RCLK_c) -ROUTE 1 0.152 R3C9A.Q1 to R3C9D.M0 n733 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i6 (from RCLK_c +) - Destination: FF Data in IS_FSM__i7 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_97 to SLICE_97 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_97: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_97 (from RCLK_c) -ROUTE 1 0.152 R3C9A.Q0 to R3C9A.M1 n734 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RASr_379 (from RCLK_c +) - Destination: FF Data in RASr2_380 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_30 to SLICE_30 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_30 to SLICE_30: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_30 (from RCLK_c) -ROUTE 2 0.154 R5C10B.Q0 to R5C10B.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r2_377 (from RCLK_c +) - Destination: FF Data in PHI2r3_378 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_36 to SLICE_69 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_36 to SLICE_69: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10A.CLK to R4C10A.Q1 SLICE_36 (from RCLK_c) -ROUTE 3 0.154 R4C10A.Q1 to R4C10C.M1 PHI2r2 (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_36: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C10A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_69: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R4C10C.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.307ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i0 (from RCLK_c +) - Destination: FF Data in IS_FSM__i1 (to RCLK_c +) - - Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. - - Constraint Details: - - 0.288ns physical path delay SLICE_98 to SLICE_98 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.307ns - - Physical Path Details: - - Data path SLICE_98 to SLICE_98: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C11A.CLK to R6C11A.Q0 SLICE_98 (from RCLK_c) -ROUTE 4 0.155 R6C11A.Q0 to R6C11A.M1 nRCS_N_139 (to RCLK_c) - -------- - 0.288 (46.2% logic, 53.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; - 113 items scored, 0 timing errors detected. +Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; + 170 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- @@ -1650,471 +1294,914 @@ Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.366ns physical path delay SLICE_15 to SLICE_15 meets + 0.366ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_15 to SLICE_15: + Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 C1Submitted -CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_15 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 ADSubmitted +CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_10 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.851ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in XOR8MEG_408 (to PHI2_c -) - - Delay: 0.823ns (28.4% logic, 71.6% route), 2 logic levels. - - Constraint Details: - - 0.823ns physical path delay SLICE_19 to SLICE_50 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.851ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.332 R5C9D.Q0 to R5C6B.D1 CmdEnable -CTOF_DEL --- 0.101 R5C6B.D1 to R5C6B.F1 SLICE_83 -ROUTE 1 0.257 R5C6B.F1 to R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c) - -------- - 0.823 (28.4% logic, 71.6% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_50: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.906ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_407 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) - - Delay: 0.878ns (26.7% logic, 73.3% route), 2 logic levels. - - Constraint Details: - - 0.878ns physical path delay SLICE_10 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.906ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_10 (from PHI2_c) -ROUTE 1 0.501 R3C8A.Q0 to R5C9A.B1 ADSubmitted -CTOF_DEL --- 0.101 R5C9A.B1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) - -------- - 0.878 (26.7% logic, 73.3% route), 2 logic levels. - Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8A.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 0.937ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q C1Submitted_406 (from PHI2_c -) - Destination: FF Data in CmdEnable_405 (to PHI2_c -) + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in C1Submitted (to PHI2_c -) - Delay: 0.909ns (48.0% logic, 52.0% route), 4 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 0.909ns physical path delay SLICE_15 to SLICE_19 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_13 to SLICE_13 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.937ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_15 to SLICE_19: + Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.136 R3C8B.Q0 to R3C9B.D1 C1Submitted -CTOF_DEL --- 0.101 R3C9B.D1 to R3C9B.F1 SLICE_77 -ROUTE 1 0.056 R3C9B.F1 to R3C9A.C1 n2210 -CTOF_DEL --- 0.101 R3C9A.C1 to R3C9A.F1 SLICE_97 -ROUTE 1 0.138 R3C9A.F1 to R5C9A.C1 n7_adj_5 -CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_88 -ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c) +ROUTE 2 0.132 R3C8A.Q0 to R3C8A.A0 C1Submitted +CTOF_DEL --- 0.101 R3C8A.A0 to R3C8A.F0 SLICE_13 +ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 C1Submitted_s (to PHI2_c) -------- - 0.909 (48.0% logic, 52.0% route), 4 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_15: + Source Clock Path PHI2 to SLICE_13: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_19: + Destination Clock Path PHI2 to SLICE_13: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 1.059ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) - FF CmdUFMCLK_413 + Source: FF Q CmdSubmitted (from PHI2_c -) + Destination: FF Data in CmdSubmitted (to PHI2_c -) - Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 1.031ns physical path delay SLICE_19 to SLICE_100 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_20 to SLICE_20 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_19 to SLICE_100: + Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 -CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 -ROUTE 2 0.260 R5C6D.F1 to R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c) +REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_20 (from PHI2_c) +ROUTE 4 0.132 R4C8B.Q0 to R4C8B.A0 CmdSubmitted +CTOF_DEL --- 0.101 R4C8B.A0 to R4C8B.F0 SLICE_20 +ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 N_412_0 (to PHI2_c) -------- - 1.031 (32.5% logic, 67.5% route), 3 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_19: + Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_100: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C7B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.059ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) - - Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. - - Constraint Details: - - 1.031ns physical path delay SLICE_19 to SLICE_99 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.059ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 -CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 -ROUTE 2 0.260 R5C6D.F1 to R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c) - -------- - 1.031 (32.5% logic, 67.5% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_99: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.106ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) - - Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. - - Constraint Details: - - 1.078ns physical path delay SLICE_19 to SLICE_20 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.106ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 -CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 -ROUTE 2 0.138 R5C7D.F0 to R3C7C.D1 n2220 -CTOF_DEL --- 0.101 R3C7C.D1 to R3C7C.F1 SLICE_89 -ROUTE 1 0.143 R3C7C.F1 to R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c) - -------- - 1.078 (40.4% logic, 59.6% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C7D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 1.106ns +Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q CmdEnable_405 (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + Source: FF Q XOR8MEG (from PHI2_c -) + Destination: FF Data in XOR8MEG (to PHI2_c -) - Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: - 1.078ns physical path delay SLICE_19 to SLICE_24 meets - -0.028ns CE_HLD and + 0.366ns physical path delay SLICE_42 to SLICE_42 meets + -0.013ns DIN_HLD and 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: - Data path SLICE_19 to SLICE_24: + Data path SLICE_42 to SLICE_42: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) -ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable -CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 -ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 -CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 -ROUTE 2 0.138 R5C7D.F0 to R3C7C.D0 n2220 -CTOF_DEL --- 0.101 R3C7C.D0 to R3C7C.F0 SLICE_89 -ROUTE 1 0.143 R3C7C.F0 to R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c) +REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_42 (from PHI2_c) +ROUTE 2 0.132 R5C9B.Q0 to R5C9B.A0 XOR8MEG +CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_42 +ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 XOR8MEG_3 (to PHI2_c) -------- - 1.078 (40.4% logic, 59.6% route), 4 logic levels. + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.435ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.422ns (68.5% logic, 31.5% route), 2 logic levels. + + Constraint Details: + + 0.422ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.435ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 3 0.133 R3C8C.Q0 to R3C8C.A0 CmdEnable +CTOOFX_DEL --- 0.156 R3C8C.A0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.422 (68.5% logic, 31.5% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.440ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.427ns (67.7% logic, 32.3% route), 2 logic levels. + + Constraint Details: + + 0.427ns physical path delay SLICE_10 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.440ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c) +ROUTE 2 0.138 R3C8B.Q0 to R3C8C.C1 ADSubmitted +CTOOFX_DEL --- 0.156 R3C8C.C1 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.427 (67.7% logic, 32.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.526ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.513ns (56.3% logic, 43.7% route), 2 logic levels. + + Constraint Details: + + 0.513ns physical path delay SLICE_13 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.526ns + + Physical Path Details: + + Data path SLICE_13 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c) +ROUTE 2 0.224 R3C8A.Q0 to R3C8C.B0 C1Submitted +CTOOFX_DEL --- 0.156 R3C8C.B0 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.513 (56.3% logic, 43.7% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_13: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.527ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable (from PHI2_c -) + Destination: FF Data in CmdEnable (to PHI2_c -) + + Delay: 0.514ns (56.2% logic, 43.8% route), 2 logic levels. + + Constraint Details: + + 0.514ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.527ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c) +ROUTE 3 0.225 R3C8C.Q0 to R3C8C.B1 CmdEnable +CTOOFX_DEL --- 0.156 R3C8C.B1 to R3C8C.OFX0 SLICE_18 +ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c) + -------- + 0.514 (56.2% logic, 43.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.616ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDEN (from PHI2_c -) + Destination: FF Data in CmdLEDEN (to PHI2_c -) + + Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels. + + Constraint Details: + + 0.603ns physical path delay SLICE_19 to SLICE_19 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.616ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.212 R5C8B.Q0 to R5C8A.A1 CmdLEDEN +CTOF_DEL --- 0.101 R5C8A.A1 to R5C8A.F1 SLICE_70 +ROUTE 1 0.056 R5C8A.F1 to R5C8B.C0 N_59 +CTOF_DEL --- 0.101 R5C8B.C0 to R5C8B.F0 SLICE_19 +ROUTE 1 0.000 R5C8B.F0 to R5C8B.DI0 N_14_i (to PHI2_c) + -------- + 0.603 (55.6% logic, 44.4% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_24: + Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C7B.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns) +Passed: The following path meets requirements by 0.702ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q XOR8MEG_408 (from PHI2_c -) - Destination: FF Data in RA11_385 (to PHI2_c +) + Source: FF Q Cmdn8MEGEN (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) - Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels. + Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels. Constraint Details: - 0.444ns physical path delay SLICE_50 to SLICE_33 meets + 0.689ns physical path delay SLICE_21 to SLICE_21 meets -0.013ns DIN_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.060ns) by 5.504ns + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.702ns Physical Path Details: - Data path SLICE_50 to SLICE_33: + Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C6A.CLK to R4C6A.Q0 SLICE_50 (from PHI2_c) -ROUTE 1 0.210 R4C6A.Q0 to R4C6C.A0 XOR8MEG -CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_33 -ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 RA11_N_184 (to PHI2_c) +REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_21 (from PHI2_c) +ROUTE 2 0.224 R5C8D.Q0 to R5C8C.B1 Cmdn8MEGEN +CTOF_DEL --- 0.101 R5C8C.B1 to R5C8C.F1 SLICE_50 +ROUTE 1 0.130 R5C8C.F1 to R5C8D.A0 Cmdn8MEGEN_4_u_i_0 +CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_21 +ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 N_12_i (to PHI2_c) -------- - 0.444 (52.7% logic, 47.3% route), 2 logic levels. + 0.689 (48.6% logic, 51.4% route), 3 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_50: + Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_33: + Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C6C.CLK PHI2_c +ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c -------- 1.240 (0.0% logic, 100.0% route), 0 logic levels. -Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns) +================================================================================ +Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; + 590 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in C1Submitted_406 (to PHI2_c -) + Source: FF Q CASr (from RCLK_c +) + Destination: FF Data in CASr2 (to RCLK_c +) - Delay: 0.839ns (52.0% logic, 48.0% route), 4 logic levels. + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: - 0.839ns physical path delay SLICE_93 to SLICE_15 meets - -0.013ns DIN_HLD and - -5.047ns delay constraint less - 0.000ns skew requirement (totaling -5.060ns) by 5.899ns + 0.285ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: - Data path SLICE_93 to SLICE_15: + Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) -ROUTE 1 0.133 R5C8C.Q1 to R5C8D.D1 Bank_1 -CTOF_DEL --- 0.101 R5C8D.D1 to R5C8D.F1 SLICE_99 -ROUTE 2 0.214 R5C8D.F1 to R3C8B.A1 n22 -CTOF_DEL --- 0.101 R3C8B.A1 to R3C8B.F1 SLICE_15 -ROUTE 1 0.056 R3C8B.F1 to R3C8B.C0 n2365 -CTOF_DEL --- 0.101 R3C8B.C0 to R3C8B.F0 SLICE_15 -ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) +REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_14 (from RCLK_c) +ROUTE 1 0.152 R5C9A.Q0 to R5C9A.M1 CASr (to RCLK_c) -------- - 0.839 (52.0% logic, 48.0% route), 4 logic levels. + 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: - Source Clock Path PHI2 to SLICE_93: + Source Clock Path RCLK to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c +ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. + 1.059 (0.0% logic, 100.0% route), 0 logic levels. - Destination Clock Path PHI2 to SLICE_15: + Destination Clock Path RCLK to SLICE_14: Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c +ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.309ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr (from RCLK_c +) + Destination: FF Data in RASr2 (to RCLK_c +) + + Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels. + + Constraint Details: + + 0.290ns physical path delay SLICE_29 to SLICE_29 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.309ns + + Physical Path Details: + + Data path SLICE_29 to SLICE_29: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q0 SLICE_29 (from RCLK_c) +ROUTE 2 0.157 R6C12B.Q0 to R6C12B.M1 RASr (to RCLK_c) + -------- + 0.290 (45.9% logic, 54.1% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2 (from RCLK_c +) + Destination: FF Data in RASr3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_29 to SLICE_32 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_29 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q1 SLICE_29 (from RCLK_c) +ROUTE 10 0.159 R6C12B.Q1 to R6C12A.M1 RASr2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_29: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C12A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.311ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2 (from RCLK_c +) + Destination: FF Data in PHI2r3 (to RCLK_c +) + + Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. + + Constraint Details: + + 0.292ns physical path delay SLICE_65 to SLICE_65 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.311ns + + Physical Path Details: + + Data path SLICE_65 to SLICE_65: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C4B.CLK to R4C4B.Q0 SLICE_65 (from RCLK_c) +ROUTE 3 0.159 R4C4B.Q0 to R4C4B.M1 PHI2r2 (to RCLK_c) + -------- + 0.292 (45.5% logic, 54.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_65: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_65: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[0] (from RCLK_c +) + Destination: FF Data in FS[0] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_0 to SLICE_0 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C3A.CLK to R6C3A.Q1 SLICE_0 (from RCLK_c) +ROUTE 3 0.132 R6C3A.Q1 to R6C3A.A1 FS[0] +CTOF_DEL --- 0.101 R6C3A.A1 to R6C3A.F1 SLICE_0 +ROUTE 1 0.000 R6C3A.F1 to R6C3A.DI1 FS_s[0] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[13] (from RCLK_c +) + Destination: FF Data in FS[13] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_3 to SLICE_3 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_3: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c) +ROUTE 3 0.132 R6C4D.Q0 to R6C4D.A0 FS[13] +CTOF_DEL --- 0.101 R6C4D.A0 to R6C4D.F0 SLICE_3 +ROUTE 1 0.000 R6C4D.F0 to R6C4D.DI0 FS_s[13] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Ready_fast (from RCLK_c +) + Destination: FF Data in Ready_fast (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_34 to SLICE_34 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_34 to SLICE_34: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C13C.CLK to R4C13C.Q0 SLICE_34 (from RCLK_c) +ROUTE 14 0.132 R4C13C.Q0 to R4C13C.A0 Ready_fast +CTOF_DEL --- 0.101 R4C13C.A0 to R4C13C.F0 SLICE_34 +ROUTE 1 0.000 R4C13C.F0 to R4C13C.DI0 N_415_0 (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from RCLK_c +) + Destination: FF Data in FS[12] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_4 to SLICE_4 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_4 to SLICE_4: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c) +ROUTE 3 0.132 R6C4C.Q1 to R6C4C.A1 FS[12] +CTOF_DEL --- 0.101 R6C4C.A1 to R6C4C.F1 SLICE_4 +ROUTE 1 0.000 R6C4C.F1 to R6C4C.DI1 FS_s[12] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_4: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q nUFMCS (from RCLK_c +) + Destination: FF Data in nUFMCS (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_45 to SLICE_45 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_45 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5A.CLK to R5C5A.Q0 SLICE_45 (from RCLK_c) +ROUTE 1 0.130 R5C5A.Q0 to R5C5A.A0 nUFMCS_c +CTOF_DEL --- 0.101 R5C5A.A0 to R5C5A.F0 SLICE_45 +ROUTE 2 0.002 R5C5A.F0 to R5C5A.DI0 nUFMCS_s_0_N_5_i (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[9] (from RCLK_c +) + Destination: FF Data in FS[9] (to RCLK_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_5 to SLICE_5 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_5: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C4B.CLK to R6C4B.Q0 SLICE_5 (from RCLK_c) +ROUTE 3 0.132 R6C4B.Q0 to R6C4B.A0 FS[9] +CTOF_DEL --- 0.101 R6C4B.A0 to R6C4B.F0 SLICE_5 +ROUTE 1 0.000 R6C4B.F0 to R6C4B.DI0 FS_s[9] (to RCLK_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- @@ -2122,9 +2209,13 @@ ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | -FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 +FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 | | | -FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 +FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 + | | | +FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- @@ -2137,14 +2228,20 @@ All preferences were met. Found 4 clocks: -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12 No transfer within this clock domain is found -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 - Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 + Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD @@ -2157,8 +2254,8 @@ Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19 + Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD @@ -2173,16 +2270,16 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Timing errors: 0 Score: 0 Cumulative negative slack: 0 -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) +Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage) Timing summary (Setup and Hold): --------------- -Timing errors: 349 (setup), 0 (hold) -Score: 452301 (setup), 0 (hold) -Cumulative negative slack: 370485 (370485+0) +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC/impl1/automake.log index 93ca373..574ca7b 100644 --- a/CPLD/LCMXO2-640HC/impl1/automake.log +++ b/CPLD/LCMXO2-640HC/impl1/automake.log @@ -1,255 +1,5 @@ -synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj" -synthesis: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 15 05:03:22 2023 - - -Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml - - -Synthesis options: -The -a option is MachXO2. -The -s option is 4. -The -t option is TQFP100. -The -d option is LCMXO2-640HC. -Using package TQFP100. -Using performance grade 4. - - -########################################################## - -### Lattice Family : MachXO2 - -### Device : LCMXO2-640HC - -### Package : TQFP100 - -### Speed : 4 - -########################################################## - - - - -Optimization goal = Balanced -Top-level module name = RAM2GS. -Target frequency = 200.000000 MHz. -Maximum fanout = 1000. -Timing path count = 3 -BRAM utilization = 100.000000 % -DSP usage = true -DSP utilization = 100.000000 % -fsm_encoding_style = auto -resolve_mixed_drivers = 0 -fix_gated_clocks = 1 - -Mux style = Auto -Use Carry Chain = true -carry_chain_length = 0 -Loop Limit = 1950. -Use IO Insertion = TRUE -Use IO Reg = AUTO - -Resource Sharing = TRUE -Propagate Constants = TRUE -Remove Duplicate Registers = TRUE -force_gsr = auto -ROM style = auto -RAM style = auto -The -comp option is FALSE. -The -syn option is FALSE. --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) --p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added) --p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) -Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v -NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd --sdc option: SDC file input not used. --lpf option: Output file option is ON. -Hardtimer checking is enabled (default). The -dt option is not used. -The -r option is OFF. [ Remove LOC Properties is OFF. ] -Technology check ok... - -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Compile design. -Compile Design Begin -Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Top module name (Verilog): RAM2GS - - - - -Last elaborated design is RAM2GS() -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Top-level module name = RAM2GS. - -original encoding -> new encoding (one-hot encoding) - - 0000 -> 0000000000000001 - - 0001 -> 0000000000000010 - - 0010 -> 0000000000000100 - - 0011 -> 0000000000001000 - - 0100 -> 0000000000010000 - - 0101 -> 0000000000100000 - - 0110 -> 0000000001000000 - - 0111 -> 0000000010000000 - - 1000 -> 0000000100000000 - - 1001 -> 0000001000000000 - - 1010 -> 0000010000000000 - - 1011 -> 0000100000000000 - - 1100 -> 0001000000000000 - - 1101 -> 0010000000000000 - - 1110 -> 0100000000000000 - - 1111 -> 1000000000000000 - - -original encoding -> new encoding (one-hot encoding) - - 00 -> 0001 - - 01 -> 0010 - - 10 -> 0100 - - 11 -> 1000 - - - - -GSR will not be inferred because no asynchronous signal was found in the netlist. - -Applying 200.000000 MHz constraint to all clocks - - -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 309 blocks expanded -completed the first expansion -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. - -################### Begin Area Report (RAM2GS)###################### -Number of register bits => 102 of 877 (11 % ) -BB => 8 -CCU2D => 10 -FD1P3AX => 29 -FD1P3AY => 5 -FD1P3IX => 3 -FD1S3AX => 47 -FD1S3IX => 14 -FD1S3JX => 4 -GSR => 1 -IB => 26 -INV => 3 -LUT4 => 122 -OB => 33 -PFUMX => 1 -################### End Area Report ################## - -################### Begin BlackBox Report ###################### -TSALL => 1 -################### End BlackBox Report ################## - -################### Begin Clock Report ###################### -Clock Nets -Number of Clocks: 4 - Net : RCLK_c, loads : 62 - Net : PHI2_c, loads : 11 - Net : nCCAS_c, loads : 2 - Net : nCRAS_c, loads : 2 -Clock Enable Nets -Number of Clock Enables: 14 -Top 10 highest fanout Clock Enables: - Net : RCLK_c_enable_27, loads : 16 - Net : RCLK_c_enable_6, loads : 4 - Net : PHI2_N_120_enable_8, loads : 3 - Net : RCLK_c_enable_10, loads : 3 - Net : RCLK_c_enable_5, loads : 2 - Net : PHI2_N_120_enable_3, loads : 1 - Net : Ready_N_292, loads : 1 - Net : PHI2_N_120_enable_2, loads : 1 - Net : RCLK_c_enable_15, loads : 1 - Net : PHI2_N_120_enable_6, loads : 1 -Highest fanout non-clock nets -Top 10 highest fanout non-clock nets: - Net : RCLK_c_enable_27, loads : 16 - Net : InitReady, loads : 15 - Net : nCRAS_c__inv, loads : 15 - Net : RASr2, loads : 14 - Net : nRowColSel_N_35, loads : 13 - Net : n2380, loads : 13 - Net : nRowColSel, loads : 12 - Net : Ready, loads : 12 - Net : Din_c_4, loads : 10 - Net : MAin_c_1, loads : 10 -################### End Clock Report ################## - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - - -Peak Memory Usage: 53.555 MB - --------------------------------------------------------------- -Elapsed CPU time for LSE flow : 0.828 secs --------------------------------------------------------------- - -map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0 +map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial -ioreg b "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0 map: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. @@ -279,19 +29,27 @@ Removing unused logic... Optimizing... +1 CCU2 constant inputs absorbed. + + + + + + + Design Summary: - Number of registers: 102 out of 877 (12%) - PFU registers: 102 out of 640 (16%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 75 out of 320 (23%) - SLICEs as Logic/ROM: 75 out of 320 (23%) + Number of registers: 93 out of 877 (11%) + PFU registers: 64 out of 640 (10%) + PIO registers: 29 out of 237 (12%) + Number of SLICEs: 81 out of 320 (25%) + SLICEs as Logic/ROM: 81 out of 320 (25%) SLICEs as RAM: 0 out of 240 (0%) SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 143 out of 640 (22%) - Number used as logic LUTs: 123 + Number of LUT4s: 159 out of 640 (25%) + Number used as logic LUTs: 139 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 @@ -313,225 +71,46 @@ Design Summary: 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 - Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_6: 4 loads, 4 LSLICEs - Net RCLK_c_enable_5: 2 loads, 2 LSLICEs - Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_10: 3 loads, 3 LSLICEs - Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_16: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net RCLK_c_enable_15: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs - Net Ready_N_292: 1 loads, 1 LSLICEs - Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs - Number of LSRs: 7 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_177: 1 loads, 1 LSLICEs - Net C1Submitted_N_237: 2 loads, 2 LSLICEs - Net n2366: 2 loads, 2 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 ) + Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) + Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 6 + Net XOR8MEG18: 3 loads, 3 LSLICEs + Net i2_i: 1 loads, 0 LSLICEs + Net N_26: 1 loads, 1 LSLICEs + Net N_28: 1 loads, 1 LSLICEs + Net N_188_i: 2 loads, 2 LSLICEs + Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs + Number of LSRs: 3 + Net RA10s_i: 1 loads, 0 LSLICEs + Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs + Net RASr2: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: - Net Ready: 18 loads - Net InitReady: 15 loads - Net RASr2: 15 loads - Net nRowColSel_N_35: 13 loads + Net InitReady: 17 loads + Net Ready: 15 loads + Net Ready_fast: 14 loads + Net Din_c[5]: 12 loads Net nRowColSel: 12 loads - Net Din_c_4: 10 loads - Net MAin_c_1: 10 loads - Net Din_c_5: 9 loads - Net MAin_c_0: 9 loads - Net Din_c_0: 8 loads + Net S[1]: 12 loads + Net RASr2: 10 loads + Net CO0: 9 loads + Net Din_c[3]: 9 loads + Net Din_c[4]: 9 loads - Number of warnings: 0 + Number of warnings: 6 Number of errors: 0 Total CPU Time: 0 secs Total REAL Time: 0 secs -Peak Memory Usage: 35 MB +Peak Memory Usage: 36 MB Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd. -ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" - -Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. - -trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 349 Score: 848079 -Cumulative negative slack: 584487 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:25 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 349 (setup), 0 (hold) -Score: 848079 (setup), 0 (hold) -Cumulative negative slack: 584487 (584487+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 41 MB - - -ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" -w -neg -ldbanno: version Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. - - -Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. -Writing Verilog netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 37 MB - -ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" -w -neg -ldbanno: version Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. - - -Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. -Writing VHDL netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvho.vho -Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 36 MB - mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd" ---- MParTrce Tool ---- @@ -539,7 +118,7 @@ Removing old design directory at request of -rem command line option to this pro Running par. Please wait . . . Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -Tue Aug 15 05:03:28 2023 +Tue Aug 15 23:30:05 2023 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf @@ -565,43 +144,44 @@ Device utilization summary: PIO (prelim) 67+4(JTAG)/80 89% used 67+4(JTAG)/79 90% bonded + IOLOGIC 29/80 36% used - SLICE 75/320 23% used + SLICE 81/320 25% used -Number of Signals: 285 -Number of Connections: 674 - +Number of Signals: 292 +Number of Connections: 703 Pin Constraint Summary: - 66 out of 67 pins locked (98% locked). + 67 out of 67 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 40) - PHI2_c (driver: PHI2, clk load #: 13) + RCLK_c (driver: RCLK, clk load #: 39) + PHI2_c (driver: PHI2, clk load #: 18) -The following 1 signal is selected to use the secondary clock routing resources: - nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) +The following 2 signals are selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0) + nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) + No signal is selected as Global Set/Reset. -. Starting Placer Phase 0. -............. +........... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. -............... -Placer score = 121531. +.................... +Placer score = 41844. Finished Placer Phase 1. REAL time: 4 secs Starting Placer Phase 2. . -Placer score = 119079 +Placer score = 41803 Finished Placer Phase 2. REAL time: 4 secs @@ -609,17 +189,18 @@ Finished Placer Phase 2. REAL time: 4 secs Global Clock Resources: CLK_PIN : 0 out of 8 (0%) - General PIO: 3 out of 80 (3%) + General PIO: 4 out of 80 (5%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 - SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0 + SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 PRIMARY : 2 out of 8 (25%) - SECONDARY: 1 out of 8 (12%) + SECONDARY: 2 out of 8 (25%) --------------- End of Clock Report --------------- @@ -634,26 +215,23 @@ I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ -| 0 | 14 / 19 ( 73%) | 2.5V | - | -| 1 | 20 / 20 (100%) | 2.5V | - | -| 2 | 16 / 20 ( 80%) | 2.5V | - | -| 3 | 17 / 20 ( 85%) | 2.5V | - | +| 0 | 13 / 19 ( 68%) | 3.3V | - | +| 1 | 20 / 20 (100%) | 3.3V | - | +| 2 | 16 / 20 ( 80%) | 3.3V | - | +| 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 3 secs Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. -0 connections routed; 674 unrouted. +0 connections routed; 703 unrouted. Starting router resource preassignment - - +Completed router resource preassignment. Real time: 6 secs -Completed router resource preassignment. Real time: 7 secs - -Start NBR router at 05:03:35 08/15/23 +Start NBR router at 23:30:11 08/15/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -668,91 +246,77 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 05:03:35 08/15/23 +Start NBR special constraint process at 23:30:11 08/15/23 -Start NBR section for initial routing at 05:03:35 08/15/23 +Start NBR section for initial routing at 23:30:11 08/15/23 Level 1, iteration 1 -2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; -Estimated worst slack/total negative slack: -4.914ns/-481.988ns; real time: 7 secs +0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs Level 2, iteration 1 -7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; -Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs Level 3, iteration 1 -12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; -Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; +Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs +3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 05:03:35 08/15/23 +Start NBR section for normal routing at 23:30:11 08/15/23 Level 4, iteration 1 -6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs Level 4, iteration 2 -3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs -Level 4, iteration 3 -2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 4 -1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; -Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs -Level 4, iteration 5 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23 + +Start NBR section for re-routing at 23:30:11 08/15/23 Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs +0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; +Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs -Start NBR section for re-routing at 05:03:35 08/15/23 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; -Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs - -Start NBR section for post-routing at 05:03:35 08/15/23 +Start NBR section for post-routing at 23:30:11 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 260 (38.58%) - Estimated worst slack : -5.122ns - Timing score : 452301 + Number of connections with timing violations : 0 (0.00%) + Estimated worst slack : 5.827ns + Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - -Total CPU time 7 secs -Total REAL time: 7 secs +Total CPU time 5 secs +Total REAL time: 6 secs Completely routed. -End of route. 674 routed (100.00%); 0 unrouted. +End of route. 703 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 -Timing score: 452301 +Timing score: 0 Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -5.122 -PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 5.827 +PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 7 secs -Total REAL time to completion: 7 secs +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs par done! @@ -766,183 +330,6 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 -trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -Report Type: based on TRACE automatically generated preferences -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 349 Score: 452301 -Cumulative negative slack: 370485 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Tue Aug 15 05:03:36 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 349 (setup), 0 (hold) -Score: 452301 (setup), 0 (hold) -Cumulative negative slack: 370485 (370485+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 40 MB - - -iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -I/O Timing Report: -: version Diamond (64-bit) 3.12.1.454 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 4 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 5 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 6 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: M -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... -Done. - tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_640HC_impl1.prf" @@ -1030,4 +417,4 @@ Initialized UFM Pages: 0 Page. Total CPU Time: 1 secs Total REAL Time: 2 secs -Peak Memory Usage: 245 MB +Peak Memory Usage: 246 MB diff --git a/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr new file mode 100644 index 0000000..0441a4c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr @@ -0,0 +1,911 @@ +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEPC + +# Tue Aug 15 22:17:22 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) +Verilog syntax check successful! +Selecting top level module RAM2GS +@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) +Running optimization stage 2 on RAM2GS ....... +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB) + +For a summary of runtime and memory usage per design unit, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv + + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:17:22 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:17:22 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:17:23 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:17:24 2023 + +###########################################################] +Premap Report + +# Tue Aug 15 22:17:24 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) + +@A: MF827 |No constraint file specified. +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt +See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + +@N: FX493 |Applying initial value "0" on instance InitReady. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance RCKE. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCS. +@N: FX493 |Applying initial value "1" on instance nRRAS. +@N: FX493 |Applying initial value "0" on instance CmdUFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdUFMCS. +@N: FX493 |Applying initial value "0" on instance CmdUFMSDI. +@N: FX493 |Applying initial value "0" on instance C1Submitted. +@N: FX493 |Applying initial value "0" on instance CmdSubmitted. +@N: FX493 |Applying initial value "0" on instance ADSubmitted. +@N: FX493 |Applying initial value "0" on instance XOR8MEG. +@N: FX493 |Applying initial value "1" on instance nUFMCS. +@N: FX493 |Applying initial value "0" on instance UFMSDI. +@N: FX493 |Applying initial value "0" on instance UFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdEnable. +@N: FX493 |Applying initial value "1" on instance nRWE. + +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +------------------------------------------------------------------------------------------------- +0 - RAM2GS|RCLK 200.0 MHz 5.000 inferred Inferred_clkgroup_0 48 + +0 - RAM2GS|PHI2 200.0 MHz 5.000 inferred Inferred_clkgroup_1 19 + +0 - RAM2GS|nCRAS 200.0 MHz 5.000 inferred Inferred_clkgroup_2 14 + +0 - RAM2GS|nCCAS 200.0 MHz 5.000 inferred Inferred_clkgroup_3 8 +================================================================================================= + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +----------------------------------------------------------------------------------------------- +RAM2GS|RCLK 48 RCLK(port) CASr2.C - - + +RAM2GS|PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +RAM2GS|nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +RAM2GS|nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) +=============================================================================================== + +@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found inferred clock RAM2GS|RCLK which controls 48 sequential elements including nRWE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":288:1:288:6|Found inferred clock RAM2GS|PHI2 which controls 19 sequential elements including CmdEnable. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Found inferred clock RAM2GS|nCRAS which controls 14 sequential elements including RowA[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. +@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":123:1:123:6|Found inferred clock RAM2GS|nCCAS which controls 8 sequential elements including WRD[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 RCLK port 48 nRWE +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 173MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Aug 15 22:17:26 2023 + +###########################################################] +Map & Optimize Report + +# Tue Aug 15 22:17:26 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 129MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 167MB peak: 167MB) + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: FX493 |Applying initial value "0" on instance IS[0]. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance IS[1]. +@N: FX493 |Applying initial value "0" on instance IS[2]. +@N: FX493 |Applying initial value "0" on instance IS[3]. + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s -2.87ns 132 / 89 + 2 0h:00m:01s -2.87ns 142 / 89 + 3 0h:00m:01s -2.50ns 140 / 89 + 4 0h:00m:01s -2.50ns 139 / 89 + 5 0h:00m:01s -2.50ns 139 / 89 + 6 0h:00m:01s -2.50ns 140 / 89 +@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":98:1:98:6|Replicating instance Bank[5] (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing. +@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":98:1:98:6|Replicating instance Bank[7] (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing. +Timing driven replication report +Added 2 Registers via timing driven replication +Added 0 LUTs via timing driven replication + + 7 0h:00m:01s -1.81ns 164 / 91 + 8 0h:00m:01s -1.74ns 164 / 91 + 9 0h:00m:01s -1.71ns 165 / 91 + 10 0h:00m:01s -1.37ns 167 / 91 + 11 0h:00m:01s -2.03ns 168 / 91 + + 12 0h:00m:01s -1.83ns 166 / 91 + 13 0h:00m:01s -2.00ns 167 / 91 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 177MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 177MB peak: 177MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 177MB) + +Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 184MB) + +@W: MT420 |Found inferred clock RAM2GS|RCLK with period 5.00ns. Please declare a user-defined clock on port RCLK. +@W: MT420 |Found inferred clock RAM2GS|PHI2 with period 5.00ns. Please declare a user-defined clock on port PHI2. +@W: MT420 |Found inferred clock RAM2GS|nCRAS with period 5.00ns. Please declare a user-defined clock on port nCRAS. +@W: MT420 |Found inferred clock RAM2GS|nCCAS with period 5.00ns. Please declare a user-defined clock on port nCCAS. + + +##### START OF TIMING REPORT #####[ +# Timing report written on Tue Aug 15 22:17:29 2023 +# + + +Top view: RAM2GS +Requested Frequency: 200.0 MHz +Wire load mode: top +Paths requested: 3 +Constraint File(s): +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: -2.370 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------------- +RAM2GS|PHI2 200.0 MHz 102.7 MHz 5.000 9.740 -2.370 inferred Inferred_clkgroup_1 +RAM2GS|RCLK 200.0 MHz 185.7 MHz 5.000 5.385 -0.385 inferred Inferred_clkgroup_0 +RAM2GS|nCCAS 200.0 MHz NA 5.000 NA NA inferred Inferred_clkgroup_3 +RAM2GS|nCRAS 200.0 MHz NA 5.000 NA NA inferred Inferred_clkgroup_2 +====================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------------------- +RAM2GS|RCLK RAM2GS|RCLK | 5.000 -0.385 | No paths - | No paths - | No paths - +RAM2GS|RCLK RAM2GS|PHI2 | Diff grp - | No paths - | Diff grp - | No paths - +RAM2GS|PHI2 RAM2GS|RCLK | No paths - | No paths - | No paths - | Diff grp - +RAM2GS|PHI2 RAM2GS|PHI2 | No paths - | 5.000 -0.639 | 2.500 -2.370 | 2.500 0.864 +RAM2GS|nCRAS RAM2GS|RCLK | No paths - | No paths - | No paths - | Diff grp - +==================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: RAM2GS|PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +--------------------------------------------------------------------------------------------- +Bank_fast_0io[5] RAM2GS|PHI2 IFS1P3DX Q Bank_fast[5] 1.044 -2.370 +Bank_0io[2] RAM2GS|PHI2 IFS1P3DX Q Bank[2] 1.220 -1.457 +Bank_0io[6] RAM2GS|PHI2 IFS1P3DX Q Bank[6] 1.204 -1.441 +Bank_0io[0] RAM2GS|PHI2 IFS1P3DX Q Bank[0] 0.972 -1.429 +Bank_0io[1] RAM2GS|PHI2 IFS1P3DX Q Bank[1] 0.972 -1.429 +Bank_0io[3] RAM2GS|PHI2 IFS1P3DX Q Bank[3] 0.972 -1.429 +Bank_0io[4] RAM2GS|PHI2 IFS1P3DX Q Bank[4] 0.972 -1.429 +Bank_fast_0io[7] RAM2GS|PHI2 IFS1P3DX Q Bank_fast[7] 1.148 -1.385 +Bank[5] RAM2GS|PHI2 FD1S3AX Q Bank[5] 1.148 -1.345 +Bank[7] RAM2GS|PHI2 FD1S3AX Q Bank[7] 1.108 -1.305 +============================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------------ +CmdSubmitted RAM2GS|PHI2 FD1S3AX D N_377_0 2.589 -2.370 +CmdLEDEN RAM2GS|PHI2 FD1S3AX D CmdLEDENe_0 2.589 -1.429 +Cmdn8MEGEN RAM2GS|PHI2 FD1S3AX D Cmdn8MEGENe_0 2.589 -1.429 +XOR8MEG RAM2GS|PHI2 FD1S3AX D XOR8MEGe_0 2.589 -1.429 +ADSubmitted RAM2GS|PHI2 FD1S3AX D ADSubmitted_r 2.589 -1.365 +C1Submitted RAM2GS|PHI2 FD1S3AX D C1Submitted_s 2.589 -1.365 +CmdUFMCLK RAM2GS|PHI2 FD1S3AX D CmdUFMCLKe_0 2.589 -1.365 +CmdUFMCS RAM2GS|PHI2 FD1S3AX D CmdUFMCSe_0 2.589 -1.365 +CmdUFMSDI RAM2GS|PHI2 FD1S3AX D CmdUFMSDIe_0 2.589 -1.353 +CmdEnable RAM2GS|PHI2 FD1S3AX D CmdEnable_s 2.589 -1.337 +========================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 2.500 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 2.589 + + - Propagation time: 4.959 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -2.370 + + Number of logic level(s): 4 + Starting point: Bank_fast_0io[5] / Q + Ending point: CmdSubmitted / D + The start point is clocked by RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK + The end point is clocked by RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +Bank_fast_0io[5] IFS1P3DX Q Out 1.044 1.044 r - +Bank_fast[5] Net - - - - 2 +Bank_fast_0io_RNI2FJ23[5] ORCALUT4 A In 0.000 1.044 r - +Bank_fast_0io_RNI2FJ23[5] ORCALUT4 Z Out 1.089 2.133 r - +g0_17_1 Net - - - - 2 +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 D In 0.000 2.133 r - +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 Z Out 1.193 3.325 f - +un1_ADWR_i_o3_12 Net - - - - 4 +CmdSubmitted_1_sqmuxa ORCALUT4 D In 0.000 3.325 f - +CmdSubmitted_1_sqmuxa ORCALUT4 Z Out 1.017 4.342 r - +CmdSubmitted_1_sqmuxa Net - - - - 1 +CmdSubmitted_RNO ORCALUT4 A In 0.000 4.342 r - +CmdSubmitted_RNO ORCALUT4 Z Out 0.617 4.959 r - +N_377_0 Net - - - - 1 +CmdSubmitted FD1S3AX D In 0.000 4.959 r - +============================================================================================ + + +Path information for path number 2: + Requested Period: 2.500 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 2.589 + + - Propagation time: 4.046 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.457 + + Number of logic level(s): 3 + Starting point: Bank_0io[2] / Q + Ending point: CmdSubmitted / D + The start point is clocked by RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK + The end point is clocked by RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +Bank_0io[2] IFS1P3DX Q Out 1.220 1.220 r - +Bank[2] Net - - - - 8 +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 A In 0.000 1.220 r - +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 Z Out 1.193 2.413 r - +un1_ADWR_i_o3_12 Net - - - - 4 +CmdSubmitted_1_sqmuxa ORCALUT4 D In 0.000 2.413 r - +CmdSubmitted_1_sqmuxa ORCALUT4 Z Out 1.017 3.429 f - +CmdSubmitted_1_sqmuxa Net - - - - 1 +CmdSubmitted_RNO ORCALUT4 A In 0.000 3.429 f - +CmdSubmitted_RNO ORCALUT4 Z Out 0.617 4.046 f - +N_377_0 Net - - - - 1 +CmdSubmitted FD1S3AX D In 0.000 4.046 f - +============================================================================================ + + +Path information for path number 3: + Requested Period: 2.500 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 2.589 + + - Propagation time: 4.030 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.441 + + Number of logic level(s): 3 + Starting point: Bank_0io[6] / Q + Ending point: CmdSubmitted / D + The start point is clocked by RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK + The end point is clocked by RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------------- +Bank_0io[6] IFS1P3DX Q Out 1.204 1.204 r - +Bank[6] Net - - - - 7 +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 B In 0.000 1.204 r - +Bank_fast_0io_RNIV4MF3[7] ORCALUT4 Z Out 1.193 2.397 f - +un1_ADWR_i_o3_12 Net - - - - 4 +CmdSubmitted_1_sqmuxa ORCALUT4 D In 0.000 2.397 f - +CmdSubmitted_1_sqmuxa ORCALUT4 Z Out 1.017 3.413 r - +CmdSubmitted_1_sqmuxa Net - - - - 1 +CmdSubmitted_RNO ORCALUT4 A In 0.000 3.413 r - +CmdSubmitted_RNO ORCALUT4 Z Out 0.617 4.030 r - +N_377_0 Net - - - - 1 +CmdSubmitted FD1S3AX D In 0.000 4.030 r - +============================================================================================ + + + + +==================================== +Detailed Report for Clock: RAM2GS|RCLK +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +FS[0] RAM2GS|RCLK FD1S3AX Q FS[0] 1.044 -0.385 +FS[1] RAM2GS|RCLK FD1S3AX Q FS[1] 1.108 -0.306 +FS[12] RAM2GS|RCLK FD1S3AX Q FS[12] 1.148 -0.279 +FS[14] RAM2GS|RCLK FD1S3AX Q FS[14] 1.148 -0.279 +FS[15] RAM2GS|RCLK FD1S3AX Q FS[15] 1.148 -0.279 +FS[2] RAM2GS|RCLK FD1S3AX Q FS[2] 1.044 -0.242 +FS[4] RAM2GS|RCLK FD1S3AX Q FS[4] 1.108 -0.164 +FS[3] RAM2GS|RCLK FD1S3AX Q FS[3] 1.044 -0.100 +InitReady RAM2GS|RCLK FD1S3AX Q InitReady 1.272 -0.082 +FS[5] RAM2GS|RCLK FD1S3AX Q FS[5] 1.108 -0.021 +================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------- +FS[17] RAM2GS|RCLK FD1S3AX D FS_s[17] 4.894 -0.385 +UFMSDI RAM2GS|RCLK FD1S3AX D UFMSDI_RNO 5.462 -0.279 +FS[15] RAM2GS|RCLK FD1S3AX D FS_s[15] 4.894 -0.242 +FS[16] RAM2GS|RCLK FD1S3AX D FS_s[16] 4.894 -0.242 +FS[13] RAM2GS|RCLK FD1S3AX D FS_s[13] 4.894 -0.100 +FS[14] RAM2GS|RCLK FD1S3AX D FS_s[14] 4.894 -0.100 +UFMCLK RAM2GS|RCLK FD1S3AX D N_16_i 5.089 -0.082 +nUFMCS RAM2GS|RCLK FD1S3AY D nUFMCS_s_0 5.089 -0.038 +FS[11] RAM2GS|RCLK FD1S3AX D FS_s[11] 4.894 0.043 +FS[12] RAM2GS|RCLK FD1S3AX D FS_s[12] 4.894 0.043 +=================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 5.000 + - Setup time: 0.106 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 4.894 + + - Propagation time: 5.280 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.385 + + Number of logic level(s): 10 + Starting point: FS[0] / Q + Ending point: FS[17] / D + The start point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + The end point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------- +FS[0] FD1S3AX Q Out 1.044 1.044 r - +FS[0] Net - - - - 2 +FS_cry_0[0] CCU2D A1 In 0.000 1.044 r - +FS_cry_0[0] CCU2D COUT Out 1.544 2.588 r - +FS_cry[0] Net - - - - 1 +FS_cry_0[1] CCU2D CIN In 0.000 2.588 r - +FS_cry_0[1] CCU2D COUT Out 0.143 2.731 r - +FS_cry[2] Net - - - - 1 +FS_cry_0[3] CCU2D CIN In 0.000 2.731 r - +FS_cry_0[3] CCU2D COUT Out 0.143 2.874 r - +FS_cry[4] Net - - - - 1 +FS_cry_0[5] CCU2D CIN In 0.000 2.874 r - +FS_cry_0[5] CCU2D COUT Out 0.143 3.017 r - +FS_cry[6] Net - - - - 1 +FS_cry_0[7] CCU2D CIN In 0.000 3.017 r - +FS_cry_0[7] CCU2D COUT Out 0.143 3.159 r - +FS_cry[8] Net - - - - 1 +FS_cry_0[9] CCU2D CIN In 0.000 3.159 r - +FS_cry_0[9] CCU2D COUT Out 0.143 3.302 r - +FS_cry[10] Net - - - - 1 +FS_cry_0[11] CCU2D CIN In 0.000 3.302 r - +FS_cry_0[11] CCU2D COUT Out 0.143 3.445 r - +FS_cry[12] Net - - - - 1 +FS_cry_0[13] CCU2D CIN In 0.000 3.445 r - +FS_cry_0[13] CCU2D COUT Out 0.143 3.588 r - +FS_cry[14] Net - - - - 1 +FS_cry_0[15] CCU2D CIN In 0.000 3.588 r - +FS_cry_0[15] CCU2D COUT Out 0.143 3.731 r - +FS_cry[16] Net - - - - 1 +FS_s_0[17] CCU2D CIN In 0.000 3.731 r - +FS_s_0[17] CCU2D S0 Out 1.549 5.280 r - +FS_s[17] Net - - - - 1 +FS[17] FD1S3AX D In 0.000 5.280 r - +================================================================================ + + +Path information for path number 2: + Requested Period: 5.000 + - Setup time: 0.106 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 4.894 + + - Propagation time: 5.201 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.306 + + Number of logic level(s): 9 + Starting point: FS[1] / Q + Ending point: FS[17] / D + The start point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + The end point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------- +FS[1] FD1S3AX Q Out 1.108 1.108 r - +FS[1] Net - - - - 3 +FS_cry_0[1] CCU2D A0 In 0.000 1.108 r - +FS_cry_0[1] CCU2D COUT Out 1.544 2.652 r - +FS_cry[2] Net - - - - 1 +FS_cry_0[3] CCU2D CIN In 0.000 2.652 r - +FS_cry_0[3] CCU2D COUT Out 0.143 2.795 r - +FS_cry[4] Net - - - - 1 +FS_cry_0[5] CCU2D CIN In 0.000 2.795 r - +FS_cry_0[5] CCU2D COUT Out 0.143 2.938 r - +FS_cry[6] Net - - - - 1 +FS_cry_0[7] CCU2D CIN In 0.000 2.938 r - +FS_cry_0[7] CCU2D COUT Out 0.143 3.081 r - +FS_cry[8] Net - - - - 1 +FS_cry_0[9] CCU2D CIN In 0.000 3.081 r - +FS_cry_0[9] CCU2D COUT Out 0.143 3.224 r - +FS_cry[10] Net - - - - 1 +FS_cry_0[11] CCU2D CIN In 0.000 3.224 r - +FS_cry_0[11] CCU2D COUT Out 0.143 3.366 r - +FS_cry[12] Net - - - - 1 +FS_cry_0[13] CCU2D CIN In 0.000 3.366 r - +FS_cry_0[13] CCU2D COUT Out 0.143 3.509 r - +FS_cry[14] Net - - - - 1 +FS_cry_0[15] CCU2D CIN In 0.000 3.509 r - +FS_cry_0[15] CCU2D COUT Out 0.143 3.652 r - +FS_cry[16] Net - - - - 1 +FS_s_0[17] CCU2D CIN In 0.000 3.652 r - +FS_s_0[17] CCU2D S0 Out 1.549 5.201 r - +FS_s[17] Net - - - - 1 +FS[17] FD1S3AX D In 0.000 5.201 r - +================================================================================ + + +Path information for path number 3: + Requested Period: 5.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 5.462 + + - Propagation time: 5.741 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.279 + + Number of logic level(s): 5 + Starting point: FS[12] / Q + Ending point: UFMSDI / D + The start point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + The end point is clocked by RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------------- +FS[12] FD1S3AX Q Out 1.148 1.148 r - +FS[12] Net - - - - 4 +UFMSDI_ens2_i_o4_N_2L1 ORCALUT4 A In 0.000 1.148 r - +UFMSDI_ens2_i_o4_N_2L1 ORCALUT4 Z Out 1.017 2.165 f - +UFMSDI_ens2_i_o4_N_2L1 Net - - - - 1 +UFMSDI_ens2_i_o4 ORCALUT4 D In 0.000 2.165 f - +UFMSDI_ens2_i_o4 ORCALUT4 Z Out 1.153 3.317 r - +N_29 Net - - - - 3 +nUFMCS15_0_a2 ORCALUT4 D In 0.000 3.317 r - +nUFMCS15_0_a2 ORCALUT4 Z Out 1.193 4.510 f - +nUFMCS15 Net - - - - 4 +UFMSDI_RNO_0 ORCALUT4 B In 0.000 4.510 f - +UFMSDI_RNO_0 ORCALUT4 Z Out 1.017 5.527 r - +UFMSDI_RNO_0 Net - - - - 1 +UFMSDI_RNO PFUMX ALUT In 0.000 5.527 r - +UFMSDI_RNO PFUMX Z Out 0.214 5.741 r - +UFMSDI_RNO Net - - - - 1 +UFMSDI FD1S3AX D In 0.000 5.741 r - +========================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 184MB) + + +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 184MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 91 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + + +Details: +BB: 8 +CCU2D: 10 +FD1P3AX: 2 +FD1S3AX: 50 +FD1S3AY: 1 +FD1S3IX: 3 +GSR: 1 +IB: 26 +IFS1P3DX: 9 +IFS1P3IX: 10 +IFS1P3JX: 2 +INV: 7 +OB: 33 +OFS1P3BX: 4 +OFS1P3DX: 8 +OFS1P3IX: 1 +OFS1P3JX: 1 +ORCALUT4: 163 +PFUMX: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 65MB peak: 184MB) + +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Tue Aug 15 22:17:29 2023 + +###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm new file mode 100644 index 0000000..6eeb0c4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm @@ -0,0 +1,35 @@ +%%% protect protected_file +@EG +- +]17p0Osk0CksRsPC#MHF=3"4j +"> +!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> +S +S"/ +S1S +SF<1kCsOR"b=BD:\#\OO8lHNF\M8d.34\M#$b#LNCH\DLD\PFko\lOs_NlbH3RP"Nd=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S +S"/ +S1S< +S/k1Fs#OC>S + +<-!-R8vFkRDCs0FFR>-- +)S + + + +< +S!R--vkF8D7CRCMVHHF0HM-R->< +S7RCVMI="F3s ).qvtP13CDsHFRo"DP="CDsHF>o" +SqS"/ + + + + +/S<7>CV +]sC + +@ diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/impl1.areasrr new file mode 100644 index 0000000..41b5352 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/impl1.areasrr @@ -0,0 +1,29 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.verilog + +Register bits: 90 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 11 100.0 + FD1S3AX 49 100.0 + FD1S3AY 1 100.0 + FD1S3IX 3 100.0 + GSR 1 100.0 + IB 26 100.0 + IFS1P3DX 9 100.0 + INV 7 100.0 + OB 33 100.0 + OFS1P3BX 4 100.0 + OFS1P3DX 12 100.0 + OFS1P3JX 1 100.0 + ORCALUT4 135 100.0 + PFUMX 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 314 diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.edi b/CPLD/LCMXO2-640HC/impl1/impl1.edi new file mode 100644 index 0000000..298000b --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/impl1.edi @@ -0,0 +1,2989 @@ +(edif RAM2GS + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2023 8 15 22 34 24) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell CCU2D (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A0 (direction INPUT)) + (port B0 (direction INPUT)) + (port C0 (direction INPUT)) + (port D0 (direction INPUT)) + (port A1 (direction INPUT)) + (port B1 (direction INPUT)) + (port C1 (direction INPUT)) + (port D1 (direction INPUT)) + (port CIN (direction INPUT)) + (port COUT (direction OUTPUT)) + (port S0 (direction OUTPUT)) + (port S1 (direction OUTPUT)) + ) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0000")) + (property INIT0 (string "0000")) + ) + ) + (cell BB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port B (direction INOUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell OB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell FD1S3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AY (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3JX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3BX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell ORCALUT4 (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell PFUMX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port ALUT (direction INPUT)) + (port BLUT (direction INPUT)) + (port C0 (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell RAM2GS (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port PHI2 (direction INPUT)) + (port (array (rename main "MAin[9:0]") 10) (direction INPUT)) + (port (array (rename crow "CROW[1:0]") 2) (direction INPUT)) + (port (array (rename din "Din[7:0]") 8) (direction INPUT)) + (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) + (port nCCAS (direction INPUT)) + (port nCRAS (direction INPUT)) + (port nFWE (direction INPUT)) + (port LED (direction OUTPUT)) + (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT)) + (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) + (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) + (port nRCS (direction OUTPUT)) + (port RCLK (direction INPUT)) + (port RCKE (direction OUTPUT)) + (port nRWE (direction OUTPUT)) + (port nRRAS (direction OUTPUT)) + (port nRCAS (direction OUTPUT)) + (port RDQMH (direction OUTPUT)) + (port RDQML (direction OUTPUT)) + (port nUFMCS (direction OUTPUT)) + (port UFMCLK (direction OUTPUT)) + (port UFMSDI (direction OUTPUT)) + (port UFMSDO (direction INPUT)) + ) + (contents + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))")) + ) + (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) + ) + (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (B+A)+C A))")) + ) + (instance UFMSDI_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) + (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!B !A))")) + ) + (instance UFMSDI_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A)")) + ) + (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "TRUE")) + ) + (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + ) + (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance UFMCLK_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA11_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT))) + ) + (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C B))")) + ) + (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+A)+D (!C (!B+A)))")) + ) + (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance UFMCLK_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B+A)))")) + ) + (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance CmdEnable17_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)+C (B !A))+D (!C+!A))")) + ) + (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C !A)")) + ) + (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !A+C (B !A))")) + ) + (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(B+A)))")) + ) + (instance un1_FS_13_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_FS_14_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance un1_CmdEnable20_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) + ) + (instance UFMCLK_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A))")) + ) + (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(!B+!A)))")) + ) + (instance nRWE_s_i_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))")) + ) + (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C (!B A)+C !B))")) + ) + (instance C1WR_7_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance un1_CmdEnable20_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !A)+D (!C (!B !A)+C !A))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))")) + ) + (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance nUFMCS_s_0_m4_yy (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))")) + ) + (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))")) + ) + (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D A)")) + ) + (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))")) + ) + (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))")) + ) + (instance nRCAS_r_i_a3_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D !C+D (C (!B A)))")) + ) + (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) + ) + (instance un1_CmdEnable20_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance C1WR_7_0_o3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(C+(B+!A)))")) + ) + (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)+C !A))")) + ) + (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+!A))")) + ) + (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B !A))")) + ) + (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (!B A))")) + ) + (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+(B A)))")) + ) + (instance CmdEnable16_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+A))")) + ) + (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !B)+D (C+(B+A)))")) + ) + (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance XOR8MEG_3_u_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance C1Submitted_s_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+!A))")) + ) + (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance UFMCLK_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance CmdEnable16_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A)))")) + ) + (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance C1WR_7_0_o3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D+(!C+(!B+!A)))")) + ) + (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_CmdEnable20_0_o3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(!B+!A))")) + ) + (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A)))")) + ) + (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance CmdEnable17_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_0 "un9_RA_i_m3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_1 "un9_RA_i_m3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_2 "un9_RA_i_m3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_3 "un9_RA_i_m3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_4 "un9_RA_i_m3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_5 "un9_RA_i_m3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_6 "un9_RA_i_m3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_7 "un9_RA_i_m3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance (rename un9_RA_i_m3_9 "un9_RA_i_m3[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C A)")) + ) + (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C (B A))")) + ) + (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B A+B !A)")) + ) + (instance un1_PHI2r3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B !A)")) + ) + (instance C1WR_7_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance CmdEnable17_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))")) + ) + (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) + ) + (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C !B+C (!B !A)))")) + ) + (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C (!B !A))")) + ) + (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D A)")) + ) + (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+A)+D (!C A+C !B))")) + ) + (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))")) + ) + (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A))+D (!B A))")) + ) + (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance nRRAS_5_u_i_0_RNILD5I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))")) + ) + (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x5002")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_15 "FS_cry_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (net CBR (joined + (portRef Q (instanceRef CBR)) + (portRef A (instanceRef nRCS_0io_RNO_0)) + (portRef A (instanceRef nRWE_0io_RNO_1)) + (portRef A (instanceRef nRCAS_0io_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u)) + (portRef B (instanceRef nRowColSel_0_0_a3_0)) + (portRef A (instanceRef LED_pad_RNO)) + (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + )) + (net C1Submitted (joined + (portRef Q (instanceRef C1Submitted)) + (portRef A (instanceRef C1Submitted_s_0)) + (portRef A (instanceRef un1_CmdEnable20_0_a2_1)) + )) + (net (rename Bank_2 "Bank[2]") (joined + (portRef Q (instanceRef Bank_0io_2)) + (portRef B (instanceRef C1WR_7_0_o3_6)) + )) + (net Ready (joined + (portRef Q (instanceRef Ready)) + (portRef B (instanceRef IS_RNO_0)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D)) + (portRef D (instanceRef nRCS_0io_RNO)) + (portRef C (instanceRef nRWE_0io_RNO_1)) + (portRef D (instanceRef RCKEEN_8_u)) + (portRef D (instanceRef nRowColSel_0_0_a3_0)) + (portRef D (instanceRef nRRAS_5_u_i_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef C (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef A (instanceRef Ready_RNO)) + (portRef A (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef S_RNICVV51_0)) + )) + (net n8MEGEN (joined + (portRef Q (instanceRef n8MEGEN)) + (portRef D (instanceRef RA11d)) + (portRef C (instanceRef Cmdn8MEGEN_RNO)) + )) + (net CO0 (joined + (portRef Q (instanceRef S_0)) + (portRef D (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef nRWE_0io_RNO_0)) + (portRef B (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef S_0_i_o2_1)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef A (instanceRef S_RNO_0)) + (portRef C (instanceRef nRCAS_r_i_a3_1_1_tz)) + (portRef A (instanceRef nRowColSel_0_0)) + (portRef C (instanceRef S_RNICVV51_0)) + )) + (net (rename S_1 "S[1]") (joined + (portRef Q (instanceRef S_1)) + (portRef C (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef nRCS_0io_RNO_0)) + (portRef D (instanceRef nRWE_0io_RNO_1)) + (portRef C (instanceRef nRCAS_0io_RNO_0)) + (portRef D (instanceRef nRCAS_0io_RNO)) + (portRef D (instanceRef RCKEEN_8_u_1_0)) + (portRef B (instanceRef S_0_i_o2_1)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef B (instanceRef S_RNO_0)) + (portRef D (instanceRef nRowColSel_0_0)) + (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0)) + (portRef B (instanceRef S_RNICVV51_0)) + )) + (net RASr2 (joined + (portRef Q (instanceRef RASr2)) + (portRef A (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef B (instanceRef RCKE_2_0)) + (portRef B (instanceRef nRRAS_5_u_i_0)) + (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3)) + (portRef A (instanceRef nRWE_s_i_tz_0)) + (portRef D (instanceRef RASr3)) + (portRef B (instanceRef RCKEEN_8_u_0_0)) + (portRef A (instanceRef RASr2_RNIAFR1)) + )) + (net InitReady (joined + (portRef Q (instanceRef InitReady)) + (portRef B (instanceRef IS_0_sqmuxa_0_o2_0)) + (portRef B (instanceRef n8MEGEN_5_i_m2)) + (portRef B (instanceRef LEDEN_RNO)) + (portRef B (instanceRef UFMCLK_r_i_a2_2_2)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef B (instanceRef PHI2r3_RNITCN41)) + (portRef B (instanceRef nUFMCS_s_0_m4_yy)) + (portRef C (instanceRef nUFMCS15_0_a2)) + (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0)) + (portRef A (instanceRef UFMSDI_ens2_i_a0)) + (portRef A (instanceRef UFMCLK_0io_RNO_1)) + (portRef B (instanceRef un1_FS_13_i_0)) + (portRef B (instanceRef un1_FS_14_i_0)) + (portRef B (instanceRef UFMCLK_0io_RNO)) + (portRef B (instanceRef InitReady_RNO)) + (portRef D (instanceRef Ready_RNO)) + (portRef C (instanceRef RCKEEN_8_u_0_0)) + )) + (net FWEr (joined + (portRef Q (instanceRef FWEr)) + (portRef B (instanceRef nRWE_0io_RNO_1)) + (portRef C (instanceRef RCKEEN_8_u_1_0)) + (portRef C (instanceRef nRowColSel_0_0_a3_0)) + (portRef D (instanceRef nRCAS_r_i_a3_1_1_tz)) + )) + (net CASr3 (joined + (portRef Q (instanceRef CASr3)) + (portRef B (instanceRef nRWE_0io_RNO_0)) + (portRef A (instanceRef nRowColSel_0_0_a3_0)) + (portRef B (instanceRef nRCAS_r_i_a3_1_1_tz)) + )) + (net (rename IS_0 "IS[0]") (joined + (portRef Q (instanceRef IS_0)) + (portRef A (instanceRef IS_RNO_0)) + (portRef D (instanceRef nRRAS_5_u_i_0_RNILD5I)) + (portRef A (instanceRef IS_n1_0_x2)) + (portRef A (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef IS_RNO_2)) + (portRef A (instanceRef nRRAS_5_u_i)) + (portRef A (instanceRef nRWE_s_i_a3_1_0)) + (portRef D (instanceRef IS_RNO_3)) + (portRef A (instanceRef RA10_0io_RNO)) + )) + (net (rename IS_3 "IS[3]") (joined + (portRef Q (instanceRef IS_3)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef RA10_0io_RNO_0)) + (portRef A (instanceRef IS_RNO_3)) + )) + (net (rename IS_2 "IS[2]") (joined + (portRef Q (instanceRef IS_2)) + (portRef C (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef C (instanceRef IS_RNO_2)) + (portRef C (instanceRef nRWE_s_i_a3_1_0)) + (portRef B (instanceRef RA10_0io_RNO_0)) + (portRef B (instanceRef IS_RNO_3)) + )) + (net (rename IS_1 "IS[1]") (joined + (portRef Q (instanceRef IS_1)) + (portRef B (instanceRef IS_n1_0_x2)) + (portRef B (instanceRef Ready_0_sqmuxa_0_o2)) + (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2)) + (portRef B (instanceRef IS_RNO_2)) + (portRef B (instanceRef nRWE_s_i_a3_1_0)) + (portRef A (instanceRef RA10_0io_RNO_0)) + (portRef C (instanceRef IS_RNO_3)) + )) + (net (rename FS_5 "FS[5]") (joined + (portRef Q (instanceRef FS_5)) + (portRef A0 (instanceRef FS_cry_0_5)) + (portRef D (instanceRef un1_FS_14_i_a2_0_1)) + (portRef D (instanceRef un1_FS_13_i_a2_1)) + (portRef A (instanceRef UFMSDI_ens2_i_o2)) + )) + (net (rename FS_6 "FS[6]") (joined + (portRef Q (instanceRef FS_6)) + (portRef A1 (instanceRef FS_cry_0_5)) + (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef B (instanceRef un1_FS_13_i_a2_6)) + )) + (net (rename FS_7 "FS[7]") (joined + (portRef Q (instanceRef FS_7)) + (portRef A0 (instanceRef FS_cry_0_7)) + (portRef C (instanceRef un1_FS_13_i_a2_6)) + (portRef B (instanceRef UFMSDI_ens2_i_o2)) + )) + (net (rename FS_8 "FS[8]") (joined + (portRef Q (instanceRef FS_8)) + (portRef A1 (instanceRef FS_cry_0_7)) + (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0)) + )) + (net (rename FS_9 "FS[9]") (joined + (portRef Q (instanceRef FS_9)) + (portRef A0 (instanceRef FS_cry_0_9)) + (portRef C (instanceRef UFMSDI_ens2_i_o2)) + (portRef B (instanceRef un1_FS_13_i_a2_8)) + )) + (net (rename FS_0 "FS[0]") (joined + (portRef Q (instanceRef FS_0)) + (portRef A1 (instanceRef FS_cry_0_0)) + (portRef A (instanceRef un1_FS_14_i_a2_0_1)) + (portRef A (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_1 "FS[1]") (joined + (portRef Q (instanceRef FS_1)) + (portRef A0 (instanceRef FS_cry_0_1)) + (portRef A (instanceRef un1_FS_13_i_a2_6)) + (portRef A (instanceRef UFMCLK_r_i_m2)) + )) + (net (rename FS_2 "FS[2]") (joined + (portRef Q (instanceRef FS_2)) + (portRef A1 (instanceRef FS_cry_0_1)) + (portRef B (instanceRef un1_FS_14_i_a2_0_1)) + (portRef B (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_3 "FS[3]") (joined + (portRef Q (instanceRef FS_3)) + (portRef A0 (instanceRef FS_cry_0_3)) + (portRef C (instanceRef un1_FS_14_i_a2_0_1)) + (portRef C (instanceRef un1_FS_13_i_a2_1)) + )) + (net (rename FS_10 "FS[10]") (joined + (portRef Q (instanceRef FS_10)) + (portRef A1 (instanceRef FS_cry_0_9)) + (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef D (instanceRef un1_FS_13_i_a2_6)) + (portRef A (instanceRef InitReady3_0_a2)) + (portRef A (instanceRef nUFMCS15_0_a2)) + )) + (net (rename FS_11 "FS[11]") (joined + (portRef Q (instanceRef FS_11)) + (portRef A0 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef InitReady3_0_a2_3)) + (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef C (instanceRef UFMCLK_r_i_m2)) + (portRef B (instanceRef nUFMCS15_0_a2)) + (portRef C (instanceRef un1_FS_13_i_a2_8)) + )) + (net (rename FS_12 "FS[12]") (joined + (portRef Q (instanceRef FS_12)) + (portRef A1 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef A (instanceRef InitReady3_0_a2_5)) + )) + (net (rename FS_13 "FS[13]") (joined + (portRef Q (instanceRef FS_13)) + (portRef A0 (instanceRef FS_cry_0_13)) + (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef B (instanceRef InitReady3_0_a2_5)) + )) + (net (rename FS_14 "FS[14]") (joined + (portRef Q (instanceRef FS_14)) + (portRef A1 (instanceRef FS_cry_0_13)) + (portRef B (instanceRef InitReady3_0_a2_3)) + (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3)) + )) + (net (rename FS_15 "FS[15]") (joined + (portRef Q (instanceRef FS_15)) + (portRef A0 (instanceRef FS_cry_0_15)) + (portRef C (instanceRef InitReady3_0_a2_5)) + (portRef A (instanceRef UFMSDI_ens2_i_o2_0)) + )) + (net (rename FS_16 "FS[16]") (joined + (portRef Q (instanceRef FS_16)) + (portRef A1 (instanceRef FS_cry_0_15)) + (portRef B (instanceRef InitReady3_0_a2)) + (portRef B (instanceRef UFMSDI_ens2_i_o2_0)) + (portRef A (instanceRef UFMCLK_r_i_a2_2_2)) + )) + (net (rename FS_17 "FS[17]") (joined + (portRef Q (instanceRef FS_17)) + (portRef A0 (instanceRef FS_s_0_17)) + (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef D (instanceRef InitReady3_0_a2_5)) + )) + (net PHI2r2 (joined + (portRef Q (instanceRef PHI2r2)) + (portRef A (instanceRef un1_PHI2r3_0)) + (portRef C (instanceRef PHI2r3_RNITCN41)) + (portRef D (instanceRef PHI2r3)) + )) + (net CmdUFMCS (joined + (portRef Q (instanceRef CmdUFMCS)) + (portRef A (instanceRef nUFMCS_s_0_m4_yy)) + )) + (net CASr2 (joined + (portRef Q (instanceRef CASr2)) + (portRef A (instanceRef nRWE_0io_RNO_0)) + (portRef A (instanceRef RCKEEN_8_u_1_0)) + (portRef A (instanceRef nRCAS_r_i_a3_1_1_tz)) + (portRef D (instanceRef CASr3)) + )) + (net CASr (joined + (portRef Q (instanceRef CASr)) + (portRef D (instanceRef CASr2)) + )) + (net PHI2r (joined + (portRef Q (instanceRef PHI2r_0io)) + (portRef D (instanceRef PHI2r2)) + )) + (net RASr (joined + (portRef Q (instanceRef RASr)) + (portRef A (instanceRef RCKE_2_0)) + (portRef D (instanceRef RASr2)) + )) + (net (rename Bank_0 "Bank[0]") (joined + (portRef Q (instanceRef Bank_0io_0)) + (portRef A (instanceRef C1WR_7_0_o3_6)) + )) + (net (rename Bank_1 "Bank[1]") (joined + (portRef Q (instanceRef Bank_0io_1)) + (portRef A (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_3 "Bank[3]") (joined + (portRef Q (instanceRef Bank_0io_3)) + (portRef B (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_4 "Bank[4]") (joined + (portRef Q (instanceRef Bank_0io_4)) + (portRef C (instanceRef C1WR_7_0_o3_7)) + )) + (net (rename Bank_5 "Bank[5]") (joined + (portRef Q (instanceRef Bank_0io_5)) + (portRef D (instanceRef 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un9_RA_i_m3_5)) + )) + (net (rename RowA_6 "RowA[6]") (joined + (portRef Q (instanceRef RowA_6)) + (portRef B (instanceRef un9_RA_i_m3_6)) + )) + (net (rename RowA_7 "RowA[7]") (joined + (portRef Q (instanceRef RowA_7)) + (portRef B (instanceRef un9_RA_i_m3_7)) + )) + (net (rename RowA_8 "RowA[8]") (joined + (portRef Q (instanceRef RowA_8)) + (portRef B (instanceRef un9_RA_8)) + )) + (net (rename RowA_9 "RowA[9]") (joined + (portRef Q (instanceRef RowA_9)) + (portRef B (instanceRef un9_RA_i_m3_9)) + )) + (net (rename WRD_0 "WRD[0]") (joined + (portRef Q (instanceRef WRD_0io_0)) + (portRef I (instanceRef RD_pad_0)) + )) + (net (rename WRD_1 "WRD[1]") (joined + (portRef Q (instanceRef WRD_0io_1)) + (portRef I (instanceRef RD_pad_1)) + )) + (net (rename WRD_2 "WRD[2]") (joined + (portRef Q (instanceRef WRD_0io_2)) + (portRef I (instanceRef RD_pad_2)) + )) + (net (rename WRD_3 "WRD[3]") (joined + (portRef Q (instanceRef WRD_0io_3)) + (portRef I (instanceRef RD_pad_3)) + )) + (net (rename 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FS_cry_0_3)) + )) + (net (rename FS_s_2 "FS_s[2]") (joined + (portRef S1 (instanceRef FS_cry_0_1)) + (portRef D (instanceRef FS_2)) + )) + (net (rename FS_s_3 "FS_s[3]") (joined + (portRef S0 (instanceRef FS_cry_0_3)) + (portRef D (instanceRef FS_3)) + )) + (net (rename FS_cry_4 "FS_cry[4]") (joined + (portRef COUT (instanceRef FS_cry_0_3)) + (portRef CIN (instanceRef FS_cry_0_5)) + )) + (net (rename FS_s_4 "FS_s[4]") (joined + (portRef S1 (instanceRef FS_cry_0_3)) + (portRef D (instanceRef FS_4)) + )) + (net (rename FS_s_5 "FS_s[5]") (joined + (portRef S0 (instanceRef FS_cry_0_5)) + (portRef D (instanceRef FS_5)) + )) + (net (rename FS_cry_6 "FS_cry[6]") (joined + (portRef COUT (instanceRef FS_cry_0_5)) + (portRef CIN (instanceRef FS_cry_0_7)) + )) + (net (rename FS_s_6 "FS_s[6]") (joined + (portRef S1 (instanceRef FS_cry_0_5)) + (portRef D (instanceRef FS_6)) + )) + (net (rename FS_s_7 "FS_s[7]") (joined + (portRef S0 (instanceRef FS_cry_0_7)) + (portRef D (instanceRef FS_7)) + )) + (net (rename FS_cry_8 "FS_cry[8]") (joined + (portRef COUT (instanceRef FS_cry_0_7)) + (portRef CIN (instanceRef FS_cry_0_9)) + )) + (net (rename FS_s_8 "FS_s[8]") (joined + (portRef S1 (instanceRef FS_cry_0_7)) + (portRef D (instanceRef FS_8)) + )) + (net (rename FS_s_9 "FS_s[9]") (joined + (portRef S0 (instanceRef FS_cry_0_9)) + (portRef D (instanceRef FS_9)) + )) + (net (rename FS_cry_10 "FS_cry[10]") (joined + (portRef COUT (instanceRef FS_cry_0_9)) + (portRef CIN (instanceRef FS_cry_0_11)) + )) + (net (rename FS_s_10 "FS_s[10]") (joined + (portRef S1 (instanceRef FS_cry_0_9)) + (portRef D (instanceRef FS_10)) + )) + (net (rename FS_s_11 "FS_s[11]") (joined + (portRef S0 (instanceRef FS_cry_0_11)) + (portRef D (instanceRef FS_11)) + )) + (net (rename FS_cry_12 "FS_cry[12]") (joined + (portRef COUT (instanceRef FS_cry_0_11)) + (portRef CIN (instanceRef FS_cry_0_13)) + )) + (net (rename FS_s_12 "FS_s[12]") (joined + (portRef S1 (instanceRef FS_cry_0_11)) + (portRef D (instanceRef FS_12)) + )) + (net (rename FS_s_13 "FS_s[13]") (joined + (portRef S0 (instanceRef FS_cry_0_13)) + (portRef D (instanceRef FS_13)) + )) + (net (rename FS_cry_14 "FS_cry[14]") (joined + (portRef COUT (instanceRef FS_cry_0_13)) + (portRef CIN (instanceRef FS_cry_0_15)) + )) + (net (rename FS_s_14 "FS_s[14]") (joined + (portRef S1 (instanceRef FS_cry_0_13)) + (portRef D (instanceRef FS_14)) + )) + (net (rename FS_s_15 "FS_s[15]") (joined + (portRef S0 (instanceRef FS_cry_0_15)) + (portRef D (instanceRef FS_15)) + )) + (net (rename FS_cry_16 "FS_cry[16]") (joined + (portRef COUT (instanceRef FS_cry_0_15)) + (portRef CIN (instanceRef FS_s_0_17)) + )) + (net (rename FS_s_16 "FS_s[16]") (joined + (portRef S1 (instanceRef FS_cry_0_15)) + (portRef D (instanceRef FS_16)) + )) + (net (rename FS_s_17 "FS_s[17]") (joined + (portRef S0 (instanceRef FS_s_0_17)) + (portRef D (instanceRef FS_17)) + )) + (net RA10s_i (joined + (portRef Z (instanceRef RA10_0io_RNO_0)) + (portRef PD (instanceRef RA10_0io)) + )) + (net un1_PHI2r3_0 (joined + (portRef Z (instanceRef un1_PHI2r3_0)) + (portRef D (instanceRef un1_FS_13_i_0)) + (portRef D (instanceRef un1_FS_14_i_0)) + )) + (net Cmdn8MEGEN_4_u_i_0 (joined + (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0)) + (portRef A (instanceRef Cmdn8MEGEN_RNO)) + )) + (net CmdLEDEN_4_u_i_0 (joined + (portRef Z (instanceRef CmdLEDEN_4_u_i_0)) + (portRef A (instanceRef CmdLEDEN_RNO)) + )) + (net d_m3_0_a2_0 (joined + (portRef Z (instanceRef UFMCLK_0io_RNO_1)) + (portRef D (instanceRef UFMCLK_0io_RNO)) + )) + (net XOR8MEG_3_u_0_a2_0_2 (joined + (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0_2)) + (portRef D (instanceRef XOR8MEG_3_u_0_0)) + )) + (net UFMSDI_ens2_i_o2_0_3 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3)) + (portRef C (instanceRef UFMSDI_ens2_i_o2_0)) + )) + (net Ready_0_sqmuxa_0_a3_2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a3)) + (portRef B (instanceRef Ready_RNO)) + )) + (net C1WR_7_0_o3_0 (joined + (portRef Z (instanceRef C1WR_7_0_o3_0)) + (portRef C (instanceRef C1WR_7_0_o3_6)) + )) + (net C1WR_7_0_o3_6 (joined + (portRef Z (instanceRef C1WR_7_0_o3_6)) + (portRef C (instanceRef C1WR_7_0_o3)) + )) + (net C1WR_7_0_o3_7 (joined + (portRef Z (instanceRef C1WR_7_0_o3_7)) + (portRef D (instanceRef C1WR_7_0_o3)) + )) + (net nRWE_s_i_tz_0 (joined + (portRef Z (instanceRef nRWE_s_i_tz_0)) + (portRef D (instanceRef nRWE_0io_RNO)) + )) + (net UFMSDI_ens2_i_a2_4_2 (joined + (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2)) + (portRef D (instanceRef UFMSDI_ens2_i_a0)) + )) + (net nRRAS_5_u_i_0 (joined + (portRef Z (instanceRef nRRAS_5_u_i_0)) + (portRef A (instanceRef nRRAS_5_u_i_0_RNILD5I)) + (portRef D (instanceRef nRRAS_5_u_i)) + )) + (net un1_CmdEnable20_0_o3_0_1 (joined + (portRef Z (instanceRef un1_CmdEnable20_0_o3_0_1)) + (portRef D (instanceRef un1_CmdEnable20_0_o3_0)) + )) + (net CMDWR_2 (joined + (portRef Z (instanceRef CMDWR_2)) + (portRef A (instanceRef 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(joined + (portRef O (instanceRef RBA_pad_0)) + (portRef (member rba 1)) + )) + (net (rename RBA_c_1 "RBA_c[1]") (joined + (portRef Q (instanceRef RBA_0io_1)) + (portRef I (instanceRef RBA_pad_1)) + )) + (net (rename RBA_1 "RBA[1]") (joined + (portRef O (instanceRef RBA_pad_1)) + (portRef (member rba 0)) + )) + (net (rename RA_c_0 "RA_c[0]") (joined + (portRef Z (instanceRef un9_RA_i_m3_0)) + (portRef I (instanceRef RA_pad_0)) + )) + (net (rename RA_0 "RA[0]") (joined + (portRef O (instanceRef RA_pad_0)) + (portRef (member ra 11)) + )) + (net (rename RA_c_1 "RA_c[1]") (joined + (portRef Z (instanceRef un9_RA_i_m3_1)) + (portRef I (instanceRef RA_pad_1)) + )) + (net (rename RA_1 "RA[1]") (joined + (portRef O (instanceRef RA_pad_1)) + (portRef (member ra 10)) + )) + (net (rename RA_c_2 "RA_c[2]") (joined + (portRef Z (instanceRef un9_RA_i_m3_2)) + (portRef I (instanceRef RA_pad_2)) + )) + (net (rename RA_2 "RA[2]") (joined + (portRef O (instanceRef RA_pad_2)) + (portRef (member ra 9)) + )) + (net (rename RA_c_3 "RA_c[3]") (joined + (portRef Z (instanceRef un9_RA_i_m3_3)) + (portRef I (instanceRef RA_pad_3)) + )) + (net (rename RA_3 "RA[3]") (joined + (portRef O (instanceRef RA_pad_3)) + (portRef (member ra 8)) + )) + (net (rename RA_c_4 "RA_c[4]") (joined + (portRef Z (instanceRef un9_RA_i_m3_4)) + (portRef I (instanceRef RA_pad_4)) + )) + (net (rename RA_4 "RA[4]") (joined + (portRef O (instanceRef RA_pad_4)) + (portRef (member ra 7)) + )) + (net (rename RA_c_5 "RA_c[5]") (joined + (portRef Z (instanceRef un9_RA_i_m3_5)) + (portRef I (instanceRef RA_pad_5)) + )) + (net (rename RA_5 "RA[5]") (joined + (portRef O (instanceRef RA_pad_5)) + (portRef (member ra 6)) + )) + (net (rename RA_c_6 "RA_c[6]") (joined + (portRef Z (instanceRef un9_RA_i_m3_6)) + (portRef I (instanceRef RA_pad_6)) + )) + (net (rename RA_6 "RA[6]") (joined + (portRef O (instanceRef RA_pad_6)) + (portRef (member ra 5)) + )) + (net (rename RA_c_7 "RA_c[7]") (joined + (portRef Z (instanceRef un9_RA_i_m3_7)) + (portRef I (instanceRef RA_pad_7)) + )) + (net (rename RA_7 "RA[7]") (joined + (portRef O (instanceRef RA_pad_7)) + (portRef (member ra 4)) + )) + (net (rename RA_c_8 "RA_c[8]") (joined + (portRef Z (instanceRef un9_RA_8)) + (portRef I (instanceRef RA_pad_8)) + )) + (net (rename RA_8 "RA[8]") (joined + (portRef O (instanceRef RA_pad_8)) + (portRef (member ra 3)) + )) + (net (rename RA_c_9 "RA_c[9]") (joined + (portRef Z (instanceRef un9_RA_i_m3_9)) + (portRef I (instanceRef RA_pad_9)) + )) + (net (rename RA_9 "RA[9]") (joined + (portRef O (instanceRef RA_pad_9)) + (portRef (member ra 2)) + )) + (net (rename RA_c_10 "RA_c[10]") (joined + (portRef Q (instanceRef RA10_0io)) + (portRef I (instanceRef RA_pad_10)) + )) + (net (rename RA_10 "RA[10]") (joined + (portRef O (instanceRef RA_pad_10)) + (portRef (member ra 1)) + )) + (net (rename RA_c_11 "RA_c[11]") (joined + (portRef Q (instanceRef RA11_0io)) + (portRef I (instanceRef RA_pad_11)) + )) + (net (rename RA_11 "RA[11]") (joined + (portRef O (instanceRef RA_pad_11)) + (portRef (member ra 0)) + )) + (net (rename RD_in_0 "RD_in[0]") (joined + (portRef O (instanceRef RD_pad_0)) + (portRef I (instanceRef Dout_pad_0)) + )) + (net (rename RD_0 "RD[0]") (joined + (portRef B (instanceRef RD_pad_0)) + (portRef (member rd 7)) + )) + (net (rename RD_in_1 "RD_in[1]") (joined + (portRef O (instanceRef RD_pad_1)) + (portRef I (instanceRef Dout_pad_1)) + )) + (net (rename RD_1 "RD[1]") (joined + (portRef B (instanceRef RD_pad_1)) + (portRef (member rd 6)) + )) + (net (rename RD_in_2 "RD_in[2]") (joined + (portRef O (instanceRef RD_pad_2)) + (portRef I (instanceRef Dout_pad_2)) + )) + (net (rename RD_2 "RD[2]") (joined + (portRef B (instanceRef RD_pad_2)) + (portRef (member rd 5)) + )) + (net (rename RD_in_3 "RD_in[3]") (joined + (portRef O (instanceRef RD_pad_3)) + (portRef I (instanceRef Dout_pad_3)) + )) + (net (rename RD_3 "RD[3]") (joined + (portRef B (instanceRef RD_pad_3)) + (portRef (member rd 4)) + )) + (net (rename RD_in_4 "RD_in[4]") (joined + (portRef O (instanceRef RD_pad_4)) + (portRef I (instanceRef Dout_pad_4)) + )) + (net (rename RD_4 "RD[4]") (joined + (portRef B (instanceRef RD_pad_4)) + (portRef (member rd 3)) + )) + (net (rename RD_in_5 "RD_in[5]") (joined + (portRef O (instanceRef RD_pad_5)) + (portRef I (instanceRef Dout_pad_5)) + )) + (net (rename RD_5 "RD[5]") (joined + (portRef B (instanceRef RD_pad_5)) + (portRef (member rd 2)) + )) + (net (rename RD_in_6 "RD_in[6]") (joined + (portRef O (instanceRef RD_pad_6)) + (portRef I (instanceRef Dout_pad_6)) + )) + (net (rename RD_6 "RD[6]") (joined + (portRef B (instanceRef RD_pad_6)) + (portRef (member rd 1)) + )) + (net (rename RD_in_7 "RD_in[7]") (joined + (portRef O (instanceRef RD_pad_7)) + (portRef I (instanceRef Dout_pad_7)) + )) + (net (rename RD_7 "RD[7]") (joined + (portRef B (instanceRef RD_pad_7)) + (portRef (member rd 0)) + )) + (net nRCS_c (joined + (portRef Q (instanceRef nRCS_0io)) + (portRef I (instanceRef nRCS_pad)) + )) + (net nRCS (joined + (portRef O (instanceRef nRCS_pad)) + (portRef nRCS) + )) + (net RCLK_c (joined + (portRef O (instanceRef RCLK_pad)) + (portRef CK (instanceRef CASr)) + (portRef CK (instanceRef CASr2)) + (portRef CK (instanceRef CASr3)) + (portRef CK (instanceRef FS_17)) + (portRef CK (instanceRef FS_16)) + (portRef CK (instanceRef FS_15)) + (portRef CK (instanceRef FS_14)) + (portRef CK (instanceRef FS_13)) + (portRef CK (instanceRef FS_12)) + (portRef CK (instanceRef FS_11)) + (portRef CK (instanceRef FS_10)) + (portRef CK (instanceRef FS_9)) + (portRef CK (instanceRef FS_8)) + (portRef CK (instanceRef FS_7)) + (portRef CK (instanceRef FS_6)) + (portRef CK (instanceRef FS_5)) + (portRef CK (instanceRef FS_4)) + (portRef CK (instanceRef FS_3)) + (portRef CK (instanceRef FS_2)) + (portRef CK (instanceRef FS_1)) + (portRef CK (instanceRef FS_0)) + (portRef CK (instanceRef IS_3)) + (portRef CK (instanceRef IS_2)) + (portRef CK (instanceRef IS_1)) + (portRef CK (instanceRef IS_0)) + (portRef CK (instanceRef InitReady)) + (portRef CK (instanceRef LEDEN)) + (portRef CK (instanceRef PHI2r2)) + (portRef CK (instanceRef PHI2r3)) + (portRef CK (instanceRef RASr)) + (portRef CK (instanceRef RASr2)) + (portRef CK (instanceRef RASr3)) + (portRef CK (instanceRef RCKE)) + (portRef CK (instanceRef RCKEEN)) + (portRef CK (instanceRef Ready)) + (portRef CK (instanceRef Ready_fast)) + (portRef CK (instanceRef S_1)) + (portRef CK (instanceRef S_0)) + (portRef CK (instanceRef UFMSDI)) + (portRef CK (instanceRef n8MEGEN)) + (portRef CK (instanceRef nRowColSel)) + (portRef CK (instanceRef nUFMCS)) + (portRef SCLK (instanceRef RA10_0io)) + (portRef SCLK (instanceRef UFMCLK_0io)) + (portRef SCLK (instanceRef nRCAS_0io)) + (portRef SCLK (instanceRef nRCS_0io)) + (portRef SCLK (instanceRef nRRAS_0io)) + (portRef SCLK (instanceRef nRWE_0io)) + (portRef SCLK (instanceRef PHI2r_0io)) + )) + (net RCLK (joined + (portRef RCLK) + (portRef I (instanceRef RCLK_pad)) + )) + (net RCKE_c (joined + (portRef Q (instanceRef RCKE)) + (portRef C (instanceRef nRRAS_5_u_i_0)) + (portRef B (instanceRef nRWE_s_i_tz_0)) + (portRef I (instanceRef RCKE_pad)) + )) + (net RCKE (joined + (portRef O (instanceRef RCKE_pad)) + (portRef RCKE) + )) + (net nRWE_c (joined + (portRef Q (instanceRef nRWE_0io)) + (portRef I (instanceRef nRWE_pad)) + )) + (net nRWE (joined + (portRef O (instanceRef nRWE_pad)) + (portRef nRWE) + )) + (net nRRAS_c (joined + (portRef Q (instanceRef nRRAS_0io)) + (portRef I (instanceRef nRRAS_pad)) + )) + (net nRRAS (joined + (portRef O (instanceRef nRRAS_pad)) + (portRef nRRAS) + )) + (net nRCAS_c (joined + (portRef Q (instanceRef nRCAS_0io)) + (portRef I (instanceRef nRCAS_pad)) + )) + (net nRCAS (joined + (portRef O (instanceRef nRCAS_pad)) + (portRef nRCAS) + )) + (net RDQMH_c (joined + (portRef Z (instanceRef RDQMH_pad_RNO)) + (portRef I (instanceRef RDQMH_pad)) + )) + (net RDQMH (joined + (portRef O (instanceRef RDQMH_pad)) + (portRef RDQMH) + )) + (net RDQML_c (joined + (portRef Z (instanceRef RDQML_0)) + (portRef I (instanceRef RDQML_pad)) + )) + (net RDQML (joined + (portRef O (instanceRef RDQML_pad)) + (portRef RDQML) + )) + (net nUFMCS_c (joined + (portRef Q (instanceRef nUFMCS)) + (portRef D (instanceRef nUFMCS_s_0_N_5_i)) + (portRef I (instanceRef nUFMCS_pad)) + )) + (net nUFMCS (joined + (portRef O (instanceRef nUFMCS_pad)) + (portRef nUFMCS) + )) + (net UFMCLK_c (joined + (portRef Q (instanceRef UFMCLK_0io)) + (portRef I (instanceRef UFMCLK_pad)) + )) + (net UFMCLK (joined + (portRef O (instanceRef UFMCLK_pad)) + (portRef UFMCLK) + )) + (net UFMSDI_c (joined + (portRef Q (instanceRef UFMSDI)) + (portRef I (instanceRef UFMSDI_pad)) + (portRef A (instanceRef UFMSDI_RNO_1)) + )) + (net UFMSDI (joined + (portRef O (instanceRef UFMSDI_pad)) + (portRef UFMSDI) + )) + (net UFMSDO_c (joined + (portRef O (instanceRef UFMSDO_pad)) + (portRef C (instanceRef n8MEGEN_5_i_m2)) + )) + (net UFMSDO (joined + (portRef UFMSDO) + (portRef I (instanceRef UFMSDO_pad)) + )) + (net N_415_0 (joined + (portRef Z (instanceRef CmdSubmitted_RNO)) + (portRef D (instanceRef CmdSubmitted)) + )) + (net N_416_0 (joined + (portRef Z (instanceRef InitReady_RNO)) + (portRef D (instanceRef InitReady)) + )) + (net N_417_0 (joined + (portRef Z (instanceRef Ready_RNO)) + (portRef D (instanceRef Ready)) + )) + (net N_418_0 (joined + (portRef Z (instanceRef Ready_fast_RNO)) + (portRef D (instanceRef Ready_fast)) + )) + (net nFWE_c_i (joined + (portRef Z (instanceRef FWEr_RNO)) + (portRef D (instanceRef FWEr)) + )) + (net nCRAS_c_i_0 (joined + (portRef Z (instanceRef RASr_RNO)) + (portRef D (instanceRef RASr)) + )) + (net nCCAS_c_i (joined + (portRef Z (instanceRef nCCAS_pad_RNISUR8)) + (portRef D (instanceRef CASr)) + (portRef D (instanceRef CBR)) + (portRef SCLK (instanceRef WRD_0io_7)) + (portRef SCLK (instanceRef WRD_0io_6)) + (portRef SCLK (instanceRef WRD_0io_5)) + (portRef SCLK (instanceRef WRD_0io_4)) + (portRef SCLK (instanceRef WRD_0io_3)) + (portRef SCLK (instanceRef WRD_0io_2)) + (portRef SCLK (instanceRef WRD_0io_1)) + (portRef SCLK (instanceRef WRD_0io_0)) + )) + (net (rename IS_i_0 "IS_i[0]") (joined + (portRef Z (instanceRef RA10_0io_RNO)) + (portRef D (instanceRef RA10_0io)) + )) + (net RASr2_i (joined + (portRef Z (instanceRef RASr2_RNIAFR1)) + (portRef CD (instanceRef S_1)) + (portRef CD (instanceRef S_0)) + )) + (net UFMSDI_RNO_1 (joined + (portRef Z (instanceRef UFMSDI_RNO_1)) + (portRef BLUT (instanceRef UFMSDI_RNO)) + )) + (net UFMSDI_RNO_0 (joined + (portRef Z (instanceRef UFMSDI_RNO_0)) + (portRef ALUT (instanceRef UFMSDI_RNO)) + )) + (net N_1 (joined + (portRef CIN (instanceRef FS_cry_0_0)) + )) + ) + (property orig_inst_of (string "RAM2GS")) + ) + ) + ) + (design RAM2GS (cellRef RAM2GS (libraryRef work)) + (property PART (string "lcmxo2_640hc-4") )) +) diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.fse b/CPLD/LCMXO2-640HC/impl1/impl1.fse new file mode 100644 index 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z1}sgD8_vjQnk0+~+}q5YxYY^Hl+MLz!JNLW4M)zsG5dQn8v+F!eceU!lDV1am=*2b zCxv-aiu4?_g;jq^h3RvcjcaC^lO`!XM-he=vxR2XWV&HiXf6vF{QJxnBj?_j{k@q@ zu)c1JQ7B>Y0%ntr*`&3zDaS%J{2a4ptOZEPm_LVErkNE^iq8S}D=cQ?npunKhS@}O ziRB~u%*G?<-kANpnN49xM6D~5IDCl@tYelNaoH$V&(6h|$t+x$Jcn7OnPr8b&1p&{ z7PCw=WBpBhtp5i90RR8ua!}v` S00030{{sN(^epAFAp!t-MWMw2 literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srr b/CPLD/LCMXO2-640HC/impl1/impl1.srr new file mode 100644 index 0000000..7df6e22 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/impl1.srr @@ -0,0 +1,1158 @@ +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEPC + +# Tue Aug 15 22:34:17 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@N: CG1349 : | Running Verilog Compiler in System Verilog mode + +@N: CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode + +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work) +Verilog syntax check successful! +Options changed - recompiling +Selecting top level module RAM2GS +@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work. +Running optimization stage 1 on RAM2GS ....... +Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) +Running optimization stage 2 on RAM2GS ....... +Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB) + +For a summary of runtime and memory usage per design unit, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv + + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:34:18 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level +@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:34:18 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:34:18 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level +@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Tue Aug 15 22:34:19 2023 + +###########################################################] +Premap Report + +# Tue Aug 15 22:34:20 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) + +Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc +@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt +See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) + +@N: FX493 |Applying initial value "0" on instance InitReady. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance RCKE. +@N: FX493 |Applying initial value "1" on instance nRCAS. +@N: FX493 |Applying initial value "0" on instance CmdLEDEN. +@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRCS. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "0" on instance n8MEGEN. +@N: FX493 |Applying initial value "1" on instance nRRAS. +@N: FX493 |Applying initial value "0" on instance CmdUFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdUFMCS. +@N: FX493 |Applying initial value "0" on instance CmdUFMSDI. +@N: FX493 |Applying initial value "0" on instance C1Submitted. +@N: FX493 |Applying initial value "0" on instance CmdSubmitted. +@N: FX493 |Applying initial value "0" on instance ADSubmitted. +@N: FX493 |Applying initial value "0" on instance XOR8MEG. +@N: FX493 |Applying initial value "1" on instance nUFMCS. +@N: FX493 |Applying initial value "0" on instance UFMSDI. +@N: FX493 |Applying initial value "0" on instance UFMCLK. +@N: FX493 |Applying initial value "0" on instance CmdEnable. +@N: FX493 |Applying initial value "1" on instance nRWE. + + +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS + +Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +--------------------------------------------------------------------------------------- +0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48 + +0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19 + +0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 + +0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 +======================================================================================= + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +RCLK 48 RCLK(port) CASr2.C - - + +PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) + +nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) + +nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) +======================================================================================== + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 RCLK port 48 nRWE +@KP:ckid0_1 PHI2 port 19 RA11 +@KP:ckid0_2 nCCAS port 8 WRD[7:0] +@KP:ckid0_3 nCRAS port 14 RowA[9:0] +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Aug 15 22:34:21 2023 + +###########################################################] +Map & Optimize Report + +# Tue Aug 15 22:34:22 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEPC + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) + +@N: MT204 |Auto Constrain mode is disabled because the following clocks are already defined: + + RCLK + PHI2 + nCRAS + nCCAS + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) + +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] +@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] +@N: FX493 |Applying initial value "0" on instance IS[0]. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance IS[1]. +@N: FX493 |Applying initial value "0" on instance IS[2]. +@N: FX493 |Applying initial value "0" on instance IS[3]. + +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:01s -2.34ns 128 / 89 + 2 0h:00m:01s -2.34ns 140 / 89 + 3 0h:00m:01s -2.34ns 140 / 89 +@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing. +Timing driven replication report +Added 1 Registers via timing driven replication +Added 0 LUTs via timing driven replication + + 4 0h:00m:01s -2.04ns 140 / 90 + + + 5 0h:00m:01s -2.04ns 141 / 90 + 6 0h:00m:01s -2.04ns 141 / 90 + 7 0h:00m:01s -2.04ns 141 / 90 + 8 0h:00m:01s -2.04ns 141 / 90 + 9 0h:00m:01s -2.04ns 141 / 90 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 177MB) + +Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB) + +@N: MT615 |Found clock RCLK with period 16.00ns +@N: MT615 |Found clock PHI2 with period 350.00ns +@N: MT615 |Found clock nCRAS with period 350.00ns +@N: MT615 |Found clock nCCAS with period 350.00ns + + +##### START OF TIMING REPORT #####[ +# Timing report written on Tue Aug 15 22:34:24 2023 +# + + +Top view: RAM2GS +Requested Frequency: 2.9 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: -2.389 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------- +PHI2 2.9 MHz 0.8 MHz 350.000 1186.150 -2.389 declared default_clkgroup +RCLK 62.5 MHz 18.4 MHz 16.000 54.224 -0.784 declared default_clkgroup +nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup +nCRAS 2.9 MHz 1.0 MHz 350.000 987.210 -1.821 declared default_clkgroup +=================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + +@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. +@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. +@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. +@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------------- +RCLK RCLK | 16.000 8.400 | No paths - | No paths - | No paths - +RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.636 | No paths - +RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths - +PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -2.389 +PHI2 PHI2 | No paths - | 350.000 345.378 | 175.000 167.920 | 175.000 173.428 +nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.821 +============================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: PHI2 +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.148 -2.389 +CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 0.972 -1.517 +CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 0.972 -0.740 +CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044 -0.572 +Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -0.572 +CmdUFMCLK PHI2 FD1P3AX Q CmdUFMCLK 0.972 -0.500 +Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.920 +Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.920 +Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.920 +Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.920 +======================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------------------------- +UFMCLK_0io PHI2 OFS1P3DX SP i2_i 0.528 -2.389 +nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i 1.089 -1.829 +UFMSDI PHI2 FD1S3AX D UFMSDI_RNO 1.462 -1.751 +LEDEN PHI2 FD1P3AX SP N_28 0.528 -1.236 +n8MEGEN PHI2 FD1P3AX SP N_26 0.528 -1.236 +LEDEN PHI2 FD1P3AX D N_74_i 1.089 -0.572 +n8MEGEN PHI2 FD1P3AX D N_131 1.089 -0.572 +UFMCLK_0io PHI2 OFS1P3DX D i1_i 1.089 -0.500 +ADSubmitted PHI2 FD1S3AX D ADSubmitted_r_0 175.089 167.920 +C1Submitted PHI2 FD1S3AX D C1Submitted_s_0 175.089 167.920 +============================================================================================ + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : -2.389 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMCLK_0io / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMCLK_0io_RNO_0 ORCALUT4 A In 0.000 2.301 r - +UFMCLK_0io_RNO_0 ORCALUT4 Z Out 0.617 2.917 r - +i2_i Net - - - - 1 +UFMCLK_0io OFS1P3DX SP In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.917 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.829 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: nUFMCS / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.301 r - +nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.617 2.917 r - +nUFMCS_s_0_N_5_i Net - - - - 1 +nUFMCS FD1S3AY D In 0.000 2.917 r - +=================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.462 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.462 + + - Propagation time: 3.214 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.751 + + Number of logic level(s): 2 + Starting point: CmdSubmitted / Q + Ending point: UFMSDI / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.148 r - +PHI2r3_RNITCN41 ORCALUT4 Z Out 1.153 2.301 r - +N_141_i Net - - - - 3 +UFMSDI_RNO PFUMX C0 In 0.000 2.301 r - +UFMSDI_RNO PFUMX Z Out 0.913 3.214 r - +UFMSDI_RNO Net - - - - 1 +UFMSDI FD1S3AX D In 0.000 3.214 r - +================================================================================== + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.605 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.517 + + Number of logic level(s): 2 + Starting point: CmdUFMCS / Q + Ending point: nUFMCS / D + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +----------------------------------------------------------------------------------- +CmdUFMCS FD1P3AX Q Out 0.972 0.972 r - +CmdUFMCS Net - - - - 1 +nUFMCS_s_0_m4_yy ORCALUT4 A In 0.000 0.972 r - +nUFMCS_s_0_m4_yy ORCALUT4 Z Out 1.017 1.989 r - +nUFMCS_s_0_m4_yy Net - - - - 1 +nUFMCS_s_0_N_5_i ORCALUT4 C In 0.000 1.989 r - +nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.617 2.605 f - +nUFMCS_s_0_N_5_i Net - - - - 1 +nUFMCS FD1S3AY D In 0.000 2.605 f - +=================================================================================== + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 0.528 + + - Propagation time: 1.765 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.236 + + Number of logic level(s): 1 + Starting point: CmdSubmitted / Q + Ending point: LEDEN / SP + The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CmdSubmitted FD1S3AX Q Out 1.148 1.148 r - +CmdSubmitted Net - - - - 4 +un1_FS_13_i_0 ORCALUT4 A In 0.000 1.148 r - +un1_FS_13_i_0 ORCALUT4 Z Out 0.617 1.765 r - +N_28 Net - - - - 1 +LEDEN FD1P3AX SP In 0.000 1.765 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: RCLK +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784 +LEDEN RCLK FD1P3AX Q LEDEN 1.108 -0.636 +n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.044 -0.572 +FS[12] RCLK FD1S3AX Q FS[12] 1.108 8.400 +FS[13] RCLK FD1S3AX Q FS[13] 1.108 8.400 +FS[14] RCLK FD1S3AX Q FS[14] 1.108 8.400 +FS[17] RCLK FD1S3AX Q FS[17] 1.108 8.400 +FS[16] RCLK FD1S3AX Q FS[16] 1.148 9.377 +FS[15] RCLK FD1S3AX Q FS[15] 1.108 9.417 +InitReady RCLK FD1S3AX Q InitReady 1.268 9.849 +================================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------------ +RBA_0io[0] RCLK OFS1P3DX D RBAd_0[0] 1.089 -0.784 +RBA_0io[1] RCLK OFS1P3DX D RBAd_0[1] 1.089 -0.784 +RowA[0] RCLK FD1S3AX D RowAd_0[0] 1.089 -0.784 +RowA[1] RCLK FD1S3AX D RowAd_0[1] 1.089 -0.784 +RowA[2] RCLK FD1S3AX D RowAd_0[2] 1.089 -0.784 +RowA[3] RCLK FD1S3AX D RowAd_0[3] 1.089 -0.784 +RowA[4] RCLK FD1S3AX D RowAd_0[4] 1.089 -0.784 +RowA[5] RCLK FD1S3AX D RowAd_0[5] 1.089 -0.784 +RowA[6] RCLK FD1S3AX D RowAd_0[6] 1.089 -0.784 +RowA[7] RCLK FD1S3AX D RowAd_0[7] 1.089 -0.784 +==================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[0] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[0] ORCALUT4 B In 0.000 1.256 r - +RBAd[0] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[0] Net - - - - 1 +RBA_0io[0] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[9] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[9] ORCALUT4 B In 0.000 1.256 r - +RowAd[9] ORCALUT4 Z Out 0.617 1.873 f - +RowAd_0[9] Net - - - - 1 +RowA[9] FD1S3AX D In 0.000 1.873 f - +================================================================================= + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[8] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[8] ORCALUT4 B In 0.000 1.256 r - +RowAd[8] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[8] Net - - - - 1 +RowA[8] FD1S3AX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RBA_0io[1] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RBAd[1] ORCALUT4 B In 0.000 1.256 r - +RBAd[1] ORCALUT4 Z Out 0.617 1.873 r - +RBAd_0[1] Net - - - - 1 +RBA_0io[1] OFS1P3DX D In 0.000 1.873 r - +================================================================================= + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 1.873 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -0.784 + + Number of logic level(s): 1 + Starting point: Ready_fast / Q + Ending point: RowA[6] / D + The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK + The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +Ready_fast FD1S3AX Q Out 1.256 1.256 r - +Ready_fast Net - - - - 14 +RowAd[6] ORCALUT4 B In 0.000 1.256 r - +RowAd[6] ORCALUT4 Z Out 0.617 1.873 r - +RowAd_0[6] Net - - - - 1 +RowA[6] FD1S3AX D In 0.000 1.873 r - +================================================================================= + + + + +==================================== +Detailed Report for Clock: nCRAS +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +-------------------------------------------------------------------------- +CBR nCRAS FD1S3AX Q CBR 1.204 -1.821 +FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.765 +========================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------- +nRCAS_0io nCRAS OFS1P3BX D N_179_i 1.089 -1.821 +nRWE_0io nCRAS OFS1P3BX D N_180_i 1.089 -1.821 +nRCS_0io nCRAS OFS1P3BX D N_27_i 1.089 -1.765 +nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.749 +RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693 +======================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 B In 0.000 2.293 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.909 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.909 f - +======================================================================================== + + +Path information for path number 2: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.909 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.821 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRWE_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.204 r - +nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.089 2.293 r - +nRCAS_0_sqmuxa_1 Net - - - - 2 +nRWE_0io_RNO ORCALUT4 A In 0.000 2.293 r - +nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.909 r - +N_180_i Net - - - - 1 +nRWE_0io OFS1P3BX D In 0.000 2.909 r - +======================================================================================== + + +Path information for path number 3: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.765 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCAS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.148 1.148 r - +FWEr Net - - - - 4 +nRCAS_r_i_a3_1_1_tz ORCALUT4 D In 0.000 1.148 r - +nRCAS_r_i_a3_1_1_tz ORCALUT4 Z Out 1.089 2.237 r - +N_27_i_1 Net - - - - 2 +nRCAS_0io_RNO ORCALUT4 A In 0.000 2.237 r - +nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.853 f - +N_179_i Net - - - - 1 +nRCAS_0io OFS1P3BX D In 0.000 2.853 f - +====================================================================================== + + +Path information for path number 4: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.853 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.765 + + Number of logic level(s): 2 + Starting point: FWEr / Q + Ending point: nRCS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +-------------------------------------------------------------------------------------- +FWEr FD1S3AX Q Out 1.148 1.148 r - +FWEr Net - - - - 4 +nRCAS_r_i_a3_1_1_tz ORCALUT4 D In 0.000 1.148 r - +nRCAS_r_i_a3_1_1_tz ORCALUT4 Z Out 1.089 2.237 r - +N_27_i_1 Net - - - - 2 +nRCS_0io_RNO ORCALUT4 B In 0.000 2.237 r - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.853 f - +N_27_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.853 f - +====================================================================================== + + +Path information for path number 5: + Requested Period: 1.000 + - Setup time: -0.089 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 1.089 + + - Propagation time: 2.837 + - Clock delay at starting point: 0.000 (ideal) + = Slack (non-critical) : -1.749 + + Number of logic level(s): 2 + Starting point: CBR / Q + Ending point: nRCS_0io / D + The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK + The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +CBR FD1S3AX Q Out 1.204 1.204 r - +CBR Net - - - - 7 +nRCS_0io_RNO_0 ORCALUT4 A In 0.000 1.204 r - +nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.221 f - +N_27_i_sn Net - - - - 1 +nRCS_0io_RNO ORCALUT4 C In 0.000 2.221 f - +nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.837 r - +N_27_i Net - - - - 1 +nRCS_0io OFS1P3BX D In 0.000 2.837 r - +================================================================================= + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + + +Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 90 of 640 (14%) +PIC Latch: 0 +I/O cells: 67 + + +Details: +BB: 8 +CCU2D: 10 +FD1P3AX: 11 +FD1S3AX: 49 +FD1S3AY: 1 +FD1S3IX: 3 +GSR: 1 +IB: 26 +IFS1P3DX: 9 +INV: 7 +OB: 33 +OFS1P3BX: 4 +OFS1P3DX: 12 +OFS1P3JX: 1 +ORCALUT4: 135 +PFUMX: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit 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    +
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N: :  | Running in 64-bit mode 
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Aug 15 22:24:08 2023
+
+###########################################################]
+
+