diff --git a/CPLD/LCMXO2-640HC-old/.run_manager.ini b/CPLD/LCMXO2-640HC-old/.run_manager.ini deleted file mode 100644 index 8c0aa7b..0000000 --- a/CPLD/LCMXO2-640HC-old/.run_manager.ini +++ /dev/null @@ -1,9 +0,0 @@ -[Runmanager] -Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) -windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) -headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) - -[impl1%3CStrategy1%3E] -isChecked=false -isHidden=false -isExpanded=false diff --git a/CPLD/LCMXO2-640HC-old/.setting.ini b/CPLD/LCMXO2-640HC-old/.setting.ini deleted file mode 100644 index 449a648..0000000 --- a/CPLD/LCMXO2-640HC-old/.setting.ini +++ /dev/null @@ -1,4 +0,0 @@ -[General] -Map.auto_tasks=MapTrace -Export.auto_tasks=IBIS, Bitgen, Jedecgen -PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO2-640HC-old/EFB.ipx b/CPLD/LCMXO2-640HC-old/EFB.ipx deleted file mode 100644 index 0954007..0000000 --- a/CPLD/LCMXO2-640HC-old/EFB.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/EFB.sort b/CPLD/LCMXO2-640HC-old/EFB.sort deleted file mode 100644 index 8437cdd..0000000 --- a/CPLD/LCMXO2-640HC-old/EFB.sort +++ /dev/null @@ -1 +0,0 @@ -EFB.v diff --git a/CPLD/LCMXO2-640HC-old/EFB.sym b/CPLD/LCMXO2-640HC-old/EFB.sym deleted file mode 100644 index 98635d3..0000000 Binary files a/CPLD/LCMXO2-640HC-old/EFB.sym and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf deleted file mode 100644 index c494afe..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf deleted file mode 100644 index 746bae4..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf +++ /dev/null @@ -1,215 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "62" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ; -IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -USE PRIMARY NET "PHI2_c" ; -USE PRIMARY NET "RCLK_c" ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 16.000000 ns ; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -USE PRIMARY NET "nCCAS_c" ; -USE PRIMARY NET "nCRAS_c" ; diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html deleted file mode 100644 index ee9c39f..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html +++ /dev/null @@ -1,112 +0,0 @@ - -Lattice TCL Log - - -
pn210817003052
-#Start recording tcl command: 8/16/2021 23:26:11
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
-prj_project save
-#Stop recording: 8/17/2021 00:30:52
-
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-
-pn210817054927
-#Start recording tcl command: 8/17/2021 00:30:55
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/17/2021 05:49:27
-
-
-
-pn210817062320
-#Start recording tcl command: 8/17/2021 05:49:30
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Synthesis -impl impl1
-prj_run Synthesis -impl impl1 -forceOne
-prj_run Map -impl impl1 -forceOne
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceOne
-#Stop recording: 8/17/2021 06:23:20
-
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-
- - diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr deleted file mode 100644 index ffbaf5f..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr +++ /dev/null @@ -1,6 +0,0 @@ -#Start recording tcl command: 8/16/2021 23:26:11 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse" -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v" -prj_project save -#Stop recording: 8/17/2021 00:30:52 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr deleted file mode 100644 index 76d8b28..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr +++ /dev/null @@ -1,9 +0,0 @@ -#Start recording tcl command: 8/17/2021 00:30:55 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -#Stop recording: 8/17/2021 05:49:27 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr deleted file mode 100644 index 9f6f1a8..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr +++ /dev/null @@ -1,24 +0,0 @@ -#Start recording tcl command: 8/17/2021 05:49:30 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Synthesis -impl impl1 -prj_run Synthesis -impl impl1 -forceOne -prj_run Map -impl impl1 -forceOne -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceOne -#Stop recording: 8/17/2021 06:23:20 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr deleted file mode 100644 index 21e57a4..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr +++ /dev/null @@ -1,6 +0,0 @@ -#Start recording tcl command: 10/9/2021 01:18:46 -#Project Location: C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Map -impl impl1 -forceAll -prj_run PAR -impl impl1 -forceAll -#Stop recording: 10/10/2021 06:41:44 diff --git a/CPLD/LCMXO2-640HC-old/impl1/.build_status b/CPLD/LCMXO2-640HC-old/impl1/.build_status deleted file mode 100644 index 9e3c1d3..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/.build_status +++ /dev/null @@ -1,46 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb deleted file mode 100644 index 7051715..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_rtl.vdb deleted file mode 100644 index aa285e9..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_rtl.vdb and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_tech.vdb deleted file mode 100644 index dd5c8cd..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_tech.vdb and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt deleted file mode 100644 index 0a575a4..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt +++ /dev/null @@ -1 +0,0 @@ -RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs b/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs deleted file mode 100644 index 4b06874..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs +++ /dev/null @@ -1,2837 +0,0 @@ -|************************************************************************ -| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2 -| Generate date: Tue Aug 17 06:21:03 2021 -|************************************************************************ -| IBIS File LibisMaker.ibs -| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation -| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor -| North Carolina State University, ERL, 2006 -|************************************************************************ -[IBIS ver] 3.2 -[File Name] RAM2GS_LCMXO2_640HC~.ibs -[File Rev] 3.5 -[Date] Thu Sep 10 07:33:23 PDT 2020 -[Source] Lattice Semiconductor cs200fl Process - LCMXO2-640HC FINAL - Lattice Semiconductor has worked hard to ensure the - models below are accurate and complete. However, the - data below was generated using simulation of the - input/output model files for the silicon. Therefore, - the data below is for reference and initial design - purposes only. -| - Lattice Semiconductor grants permission to use this - data for use in printed circuit design using this - Lattice programmable logic device. Other use of this - code, including the selling or duplication of any - portion is strictly prohibited. -| -| NAMING CONVENTION -| - The IBIS [Model] header is limited by the specification to a - total of characters. With such a set of characters available - for naming models it becomes important to attempt to - meaningfully encode the IO standards so they fit within the - twenty character limit. It would seem that twenty characters - would provide room enough for describing IO's. However, the - PLD IO structure continues to grow more and more complex. The - complexity is making the twenty characters insuffiently - descriptive. In order to overcome this issue the naming - convention described below is implemented to resolve the issue. -| -The twenty character space is managed as follows: - bbbvvvsdddprugtcoixx -| - b = standard - v = voltage (x.xx V) - s = slew code - d = drive (xx.x ma) - p = pullup code - r = series resistance or bank_vccio code - u = terminate to vcc code - g = terminate to gnd code - t = terminate to vtt code - c = common mode termination mode - o = diff resistor code - i = diff resistor current code - x = reserved -| -| - standard -| - lvcmos lvc - lvcmosd lvd - lvcmosr lvr - lvds25e lve - lvttl lvt - lvttld ltd - pci pci - sstl_I ss1 - sstl_II ss2 - sstld_I s1d - sstld_II s2d - hstl_i hs1 - hstl_ii hs2 - hstld_i h1d - hstld_ii h2d - lvds25 lvs - blvds25 blv - blvds25e blv - mlvds25 mlv - mlvds25e mlv - lvpecl33 lvp - lvpecl33e lvp - rsds25 rsd - rsds25e rse - mipi mip - mipi_lp mip - vref1 vr1 - vref2 vr2 - ref_res rer -| -| - slew - na a - fast f - slow s -| - pullmode - off a - pullup b - pulldown c - bushold d - clamp e - up_clamp f - down_clamp g - keeper_clamp h -| - impedance or Bank_vccio - off a - 25 b - 33 c - 50 d - 100 e - 3.3 f - 2.5 g - 1.8 h - 1.5 i - 1.2 j -| - termVCC - off a - 50 b - 100 c - 120 d -| - termGND - off a - 50 b - 100 c - 120 d -| - termVTT - off a - 60 b - 75 c - 120 d - 150 e - 210 f -| - VCMT - off a - VCMT b - VTT c - DDR-2 d -| - differential resistor - off a - 100 b -| - diff drive - NA a - 2.0 b - 3.5 c - 1.25 f - 2.5 g -| - Reserved IO type - in input only - ou output - io I/O - od Open drain - on Inverting differential I/O - (signal name only) - op Non-Inverting differential I/O - (signal name only) -| - Lattice Semiconductor Corporation - 5555 NE Moore Court - Hillsboro, OR 97214 - U.S.A -| - TEL: 1-800-Lattice (USA and Canada) - 408-826-6000 (other locations) -| - web: http://www.latticesemi.com/ - email: techsupport@latticesemi.com -| -| -| -[Disclaimer] This IBIS source code is intended as a design reference - which illustrates how the Lattice Semiconductor device operates. - It is the user's responsibility to verify their design for - consistency and functionality through the use of formal - verification methods. Lattice Semiconductor provides no warranty - regarding the use or functionality of this data. -| -[Copyright] Copyright 2007 by Lattice Semiconductor Corporation -| -| -|************************************************************************ -| Component XO2 -|************************************************************************ -| -[Component] XO2 -[Manufacturer] Lattice Semiconductor Corp. -[Package] -|TQFP100 -| variable typ min max -R_pkg 150.5m 124.0m 187.0m -L_pkg 6.27nH 5.50nH 7.16nH -C_pkg 0.95pF 0.87pF 1.07pF -| -[Pin] signal_name model_name R_pin L_pin C_pin -10 CROW[0] lvt330axxxefaaaaaain -16 CROW[1] lvt330axxxefaaaaaain -3 Din[0] lvt330axxxefaaaaaain -96 Din[1] lvt330axxxefaaaaaain -88 Din[2] lvt330axxxefaaaaaain -97 Din[3] lvt330axxxefaaaaaain -99 Din[4] lvt330axxxefaaaaaain -98 Din[5] lvt330axxxefaaaaaain -2 Din[6] lvt330axxxefaaaaaain -1 Din[7] lvt330axxxefaaaaaain -76 Dout[0] lvt330s040aaaaaaaaou -86 Dout[1] lvt330s040aaaaaaaaou -87 Dout[2] lvt330s040aaaaaaaaou -85 Dout[3] lvt330s040aaaaaaaaou -83 Dout[4] lvt330s040aaaaaaaaou -84 Dout[5] lvt330s040aaaaaaaaou -78 Dout[6] lvt330s040aaaaaaaaou -82 Dout[7] lvt330s040aaaaaaaaou -34 LED lvt330s160aaaaaaaaou -14 MAin[0] lvt330axxxefaaaaaain -12 MAin[1] lvt330axxxefaaaaaain -13 MAin[2] lvt330axxxefaaaaaain -21 MAin[3] lvt330axxxefaaaaaain -20 MAin[4] lvt330axxxefaaaaaain -19 MAin[5] lvt330axxxefaaaaaain -24 MAin[6] lvt330axxxefaaaaaain -18 MAin[7] lvt330axxxefaaaaaain -25 MAin[8] lvt330axxxefaaaaaain -32 MAin[9] lvt330axxxefaaaaaain -8 PHI2 lvt330axxxefaaaaaain -66 RA[0] lvt330s040aaaaaaaaou -64 RA[10] lvt330s040aaaaaaaaou -59 RA[11] lvt330s040aaaaaaaaou -67 RA[1] lvt330s040aaaaaaaaou -69 RA[2] lvt330s040aaaaaaaaou -71 RA[3] lvt330s040aaaaaaaaou -74 RA[4] lvt330s040aaaaaaaaou -70 RA[5] lvt330s040aaaaaaaaou -68 RA[6] lvt330s040aaaaaaaaou -75 RA[7] lvt330s040aaaaaaaaou -65 RA[8] lvt330s040aaaaaaaaou -62 RA[9] lvt330s040aaaaaaaaou -58 RBA[0] lvt330s040aaaaaaaaou -60 RBA[1] lvt330s040aaaaaaaaou -53 RCKE lvt330s040aaaaaaaaou -63 RCLK lvt330axxxefaaaaaain -51 RDQMH lvt330s040aaaaaaaaou -48 RDQML lvt330s040aaaaaaaaou -36 RD[0] lvt330s040haaaaaaaio -37 RD[1] lvt330s040haaaaaaaio -38 RD[2] lvt330s040haaaaaaaio -39 RD[3] lvt330s040haaaaaaaio -40 RD[4] lvt330s040haaaaaaaio -41 RD[5] lvt330s040haaaaaaaio -42 RD[6] lvt330s040haaaaaaaio -43 RD[7] lvt330s040haaaaaaaio -9 nCCAS lvt330axxxefaaaaaain -17 nCRAS lvt330axxxefaaaaaain -15 nFWE lvt330axxxefaaaaaain -52 nRCAS lvt330s040aaaaaaaaou -57 nRCS lvt330s040aaaaaaaaou -54 nRRAS lvt330s040aaaaaaaaou -49 nRWE lvt330s040aaaaaaaaou -|************************************************************************ -[Model] lvt330axxxefaaaaaain -Model_type Input -Polarity Non-Inverting -Enable Active-Low -Vinl = 0.8000V -Vinh = 2.0000V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A -0.9287A - -3.15 -0.8816A -0.8571A -0.9041A - -3.10 -0.8571A -0.8328A -0.8794A - -3.05 -0.8326A -0.8084A -0.8548A - -3.00 -0.8081A -0.7841A -0.8302A - -2.95 -0.7837A -0.7598A -0.8056A - -2.90 -0.7592A -0.7356A -0.781A - -2.85 -0.7348A -0.7113A -0.7565A - -2.80 -0.7104A -0.6872A -0.7319A - -2.75 -0.686A -0.663A -0.7074A - -2.70 -0.6617A -0.6389A -0.6829A - -2.65 -0.6374A -0.6149A -0.6584A - -2.60 -0.6131A -0.5909A -0.634A - -2.55 -0.5889A -0.5669A -0.6096A - -2.50 -0.5647A -0.5431A -0.5852A - -2.45 -0.5406A -0.5193A -0.5609A - -2.40 -0.5166A -0.4956A -0.5366A - -2.35 -0.4926A -0.472A -0.5124A - -2.30 -0.4687A -0.4485A -0.4882A - -2.25 -0.4449A -0.4251A -0.4641A - -2.20 -0.4211A -0.4019A -0.44A - -2.15 -0.3976A -0.3789A -0.4161A - -2.10 -0.3741A -0.3562A -0.3923A - -2.05 -0.3509A -0.3337A -0.3686A - -2.00 -0.3279A -0.3116A -0.3451A - -1.95 -0.3052A -0.2899A -0.3218A - -1.90 -0.283A -0.2689A -0.2988A - -1.85 -0.2612A -0.2486A -0.2762A - -1.80 -0.2402A -0.2294A -0.2543A - -1.75 -0.2204A -0.2116A -0.2332A - -1.70 -0.202A -0.1954A -0.2135A - -1.65 -0.1857A -0.181A -0.1959A - -1.60 -0.1717A -0.1682A -0.181A - -1.55 -0.1594A -0.1563A -0.1685A - -1.50 -0.1481A -0.1452A -0.1571A - -1.45 -0.1372A -0.1343A -0.1462A - -1.40 -0.1266A -0.1237A -0.1355A - -1.35 -0.1162A -0.1132A -0.125A - -1.30 -0.106A -0.1029A -0.1146A - -1.25 -95.9599mA -92.8329mA -0.1046A - -1.20 -86.1849mA -82.9339mA -94.9069mA - -1.15 -76.7349mA -73.2869mA -85.7379mA - -1.10 -67.7089mA -63.9519mA -77.2789mA - -1.05 -59.2439mA -55.0099mA -69.7479mA - -1.00 -51.5159mA -46.5729mA -63.2139mA - -0.95 -44.7119mA -38.7979mA -57.3089mA - -0.90 -38.8659mA -31.8819mA -51.2599mA - -0.85 -33.5299mA -25.9129mA -44.7209mA - -0.80 -28.2499mA -20.5839mA -37.9699mA - -0.75 -23.0669mA -15.7839mA -31.2789mA - -0.70 -18.0989mA -11.6329mA -24.8089mA - -0.65 -13.4569mA -8.1389mA -18.6889mA - -0.60 -9.2667mA -5.2646mA -13.0589mA - -0.55 -5.6915mA -3.0244mA -8.1194mA - -0.50 -2.937mA -1.4709mA -4.1747mA - -0.45 -1.1814mA -0.5866mA -1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.1216A 0.1237A 0.1238A - -3.15 0.1196A 0.1223A 0.1209A - -3.05 0.1173A 0.1206A 0.1178A - -2.95 0.1149A 0.1187A 0.1145A - -2.85 0.1124A 0.1167A 0.1111A - -2.75 0.1096A 0.1144A 0.1076A - -2.65 0.1067A 0.1119A 0.1038A - -2.55 0.1036A 0.1092A 99.9050mA - -2.45 0.1003A 0.1063A 95.7580mA - -2.35 96.7690mA 0.1032A 91.3580mA - -2.25 92.9860mA 99.8100mA 86.6530mA - -2.15 88.9230mA 96.2310mA 81.5730mA - -2.05 84.5480mA 92.4190mA 76.0140mA - -1.95 79.8300mA 88.3720mA 69.8490mA - -1.85 74.7460mA 84.0930mA 62.9770mA - -1.75 69.2870mA 79.5850mA 55.3980mA - -1.65 63.4650mA 74.8610mA 47.2410mA - -1.55 57.3080mA 69.9360mA 38.7130mA - -1.45 50.8520mA 64.8290mA 30.0630mA - -1.35 44.1410mA 59.5630mA 21.7860mA - -1.25 37.2260mA 54.1610mA 15.4630mA - -1.15 30.1740mA 48.6420mA 11.3590mA - -1.05 23.0900mA 43.0210mA 6.9249mA - -0.95 16.2170mA 37.3010mA 3.1428mA - -0.85 10.2220mA 31.4860mA 0.8130mA - -0.75 6.0667mA 25.5900mA 0.1206mA - -0.65 3.1215mA 19.6580mA 19.6640uA - -0.55 1.0958mA 13.7970mA 3.9127uA - -0.45 0.2189mA 8.2788mA 1.9769uA - -0.35 37.5650uA 3.8148mA 1.5352uA - -0.25 5.9156uA 1.3265mA 1.2603uA - -0.15 0.9342uA 0.3367mA 1.0262uA - -0.05 0.2497uA 63.0770uA 0.8243uA - 0.00 0.1905uA 26.3140uA 0.7347uA - 0.05 0.1661uA 10.7330uA 0.6522uA - 0.15 0.1377uA 1.6689uA 0.5077uA - 0.25 0.1149uA 0.2675uA 0.3882uA - 0.35 95.5840nA 94.4800nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2001nA 17.4270nA -0.8025nA - 1.55 4.6215nA 13.7460nA -4.4469nA - 1.65 1.0974nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8986nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2566nA -22.2600nA - 2.15 -16.3730nA -7.8413nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -| End [Model] lvt330axxxefaaaaaain -|************************************************************************ -[Model] lvt330s040aaaaaaaaou -Model_type Output -Polarity Non-Inverting -Enable Active-Low -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -11.9500mA -8.6650mA -15.6420mA - -3.20 -11.9500mA -8.6650mA -15.6420mA - -3.10 -11.9500mA -8.6650mA -15.6420mA - -3.00 -11.9500mA -8.6650mA -15.6420mA - -2.90 -11.9500mA -8.6650mA -15.6420mA - -2.80 -11.9500mA -8.6650mA -15.6420mA - -2.70 -11.9500mA -8.6650mA -15.6420mA - -2.60 -11.9500mA -8.6650mA -15.6420mA - -2.50 -11.9500mA -8.6650mA -15.6420mA - -2.40 -11.9500mA -8.6650mA -15.6420mA - -2.30 -11.9500mA -8.6650mA -15.6420mA - -2.20 -11.9500mA -8.6650mA -15.6420mA - -2.10 -11.9500mA -8.6650mA -15.6420mA - -2.00 -11.9500mA -8.6650mA -15.6420mA - -1.90 -11.9500mA -8.6650mA -15.6420mA - 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14.5410mA 9.9819mA 19.9070mA - 0.90 15.8560mA 10.8620mA 21.7440mA - 1.00 17.0540mA 11.6600mA 23.4200mA - 1.10 18.1290mA 12.3750mA 24.9200mA - 1.20 19.0710mA 13.0030mA 26.2250mA - 1.30 19.8710mA 13.5400mA 27.3150mA - 1.40 20.5280mA 13.9880mA 28.1920mA - 1.50 21.0520mA 14.3520mA 28.8770mA - 1.60 21.4690mA 14.6450mA 29.4110mA - 1.70 21.8020mA 14.8830mA 29.8330mA - 1.80 22.0750mA 15.0800mA 30.1740mA - 1.90 22.3020mA 15.2450mA 30.4550mA - 2.00 22.4950mA 15.3870mA 30.6940mA - 2.10 22.6630mA 15.5110mA 30.8990mA - 2.20 22.8110mA 15.6210mA 31.0780mA - 2.30 22.9430mA 15.7190mA 31.2379mA - 2.40 23.0630mA 15.8080mA 31.3819mA - 2.50 23.1710mA 15.8900mA 31.5119mA - 2.60 23.2710mA 15.9650mA 31.6318mA - 2.70 23.3639mA 16.0350mA 31.7418mA - 2.80 23.4499mA 16.0999mA 31.8447mA - 2.90 23.5309mA 16.1609mA 31.9406mA - 3.00 23.6069mA 16.2189mA 32.0305mA - 3.10 23.6789mA 16.2739mA 32.1163mA - 3.20 23.7478mA 16.3258mA 32.1981mA - 3.30 23.8138mA 16.3756mA 32.2769mA - 3.40 23.8786mA 16.4213mA 32.3557mA - 3.50 23.9417mA 16.4526mA 32.4354mA - 3.60 24.0002mA 16.6876mA 32.5189mA - 3.70 24.0309mA 17.3426mA 32.6070mA - 3.80 24.3774mA 19.1285mA 32.6921mA - 3.90 25.3543mA 22.9154mA 32.7222mA - 4.00 27.4942mA 28.3023mA 33.3062mA - 4.10 30.5709mA 34.3240mA 34.9817mA - 4.20 34.9446mA 40.5557mA 38.3579mA - 4.30 41.2761mA 46.8344mA 42.8549mA - 4.40 48.5706mA 53.0950mA 47.3478mA - 4.50 56.1500mA 59.3125mA 52.6274mA - 4.60 63.7762mA 65.4900mA 60.8279mA - 4.70 71.3464mA 71.6374mA 70.1182mA - 4.80 78.8056mA 77.7568mA 79.6014mA - 4.90 86.1136mA 83.8381mA 88.9754mA - 5.00 93.2445mA 89.8594mA 98.0452mA - 5.10 0.1002A 95.7986mA 0.1067A - 5.20 0.1069A 0.1016A 0.1148A - 5.30 0.1134A 0.1074A 0.1224A - 5.40 0.1197A 0.1130A 0.1298A - 5.50 0.1258A 0.1184A 0.1369A - 5.60 0.1318A 0.1237A 0.1439A - 5.70 0.1376A 0.1289A 0.1508A - 5.80 0.1432A 0.1340A 0.1576A - 5.90 0.1488A 0.1390A 0.1644A - 6.00 0.1544A 0.1438A 0.1712A - 6.10 0.1598A 0.1485A 0.1780A - 6.20 0.1652A 0.1530A 0.1848A - 6.30 0.1706A 0.1575A 0.1916A - 6.40 0.1760A 0.1620A 0.1984A - 6.50 0.1813A 0.1663A 0.2053A - 6.60 0.1867A 0.1705A 0.2122A -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| --3.30 0.1819A 0.1298A 0.2190A --3.20 0.1819A 0.1298A 0.2177A --3.10 0.1819A 0.1298A 0.2139A --3.00 0.1785A 0.1298A 0.2092A --2.90 0.1743A 0.1298A 0.2039A --2.80 0.1697A 0.1298A 0.1982A --2.70 0.1647A 0.1298A 0.1922A --2.60 0.1594A 0.1298A 0.1860A --2.50 0.1538A 0.1298A 0.1795A --2.40 0.1479A 0.1298A 0.1728A --2.30 0.1418A 0.1259A 0.1658A --2.20 0.1353A 0.1198A 0.1586A --2.10 0.1286A 0.1135A 0.1512A --2.00 0.1216A 0.1069A 0.1435A --1.90 0.1142A 0.1002A 0.1355A --1.80 0.1066A 93.3488mA 0.1271A --1.70 93.5831mA 86.3555mA 0.1182A --1.60 85.8190mA 79.2592mA 0.1088A --1.50 77.8471mA 72.0828mA 98.7659mA --1.40 69.6957mA 64.8453mA 88.3330mA --1.30 61.4020mA 57.5538mA 77.6100mA --1.20 53.0124mA 50.2142mA 66.7828mA --1.10 44.6065mA 42.8446mA 56.1774mA --1.00 36.3505mA 35.4829mA 46.7939mA --0.90 28.6912mA 28.2232mA 39.5361mA --0.80 22.4746mA 21.3014mA 32.3042mA --0.70 17.6024mA 15.3245mA 25.5251mA --0.60 13.5809mA 11.1535mA 19.7918mA --0.50 10.4816mA 8.4310mA 14.7443mA --0.40 8.0206mA 6.4251mA 11.9096mA --0.30 5.9614mA 4.6861mA 8.8891mA --0.20 3.9365mA 3.0816mA 5.8934mA --0.10 1.9506mA 1.5203mA 2.9319mA -0.00 -7.7700nA -3.4200nA -87.8000nA -0.10 -1.8904mA -1.4640mA -2.8585mA -0.20 -3.6938mA -2.8556mA -5.5960mA -0.30 -5.4106mA -4.1752mA -8.2131mA -0.40 -7.0415mA -5.4235mA -10.7106mA -0.50 -8.5871mA -6.6009mA -13.0875mA -0.60 -10.0478mA -7.7082mA -15.3464mA -0.70 -11.4233mA -8.7458mA -17.4873mA -0.80 -12.7164mA -9.7144mA -19.5102mA -0.90 -13.9250mA -10.6140mA -21.4151mA -1.00 -15.0511mA -11.4460mA -23.2041mA -1.10 -16.0947mA -12.2110mA -24.8771mA -1.20 -17.0567mA -12.9090mA -26.4350mA -1.30 -17.9380mA -13.5400mA -27.8770mA -1.40 -18.7378mA -14.1060mA -29.2060mA -1.50 -19.4578mA -14.6060mA -30.4200mA -1.60 -20.0982mA -15.0420mA -31.5220mA -1.70 -20.6608mA -15.4150mA -32.5110mA -1.80 -21.1446mA -15.7260mA -33.3890mA -1.90 -21.5526mA -15.9770mA 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-23.9301mA -17.3881mA -39.1532mA -4.60 -23.9301mA -17.3881mA -39.1532mA -4.70 -23.9301mA -17.3881mA -39.1532mA -4.80 -23.9301mA -17.3881mA -39.1532mA -4.90 -23.9301mA -17.3881mA -39.1532mA -5.00 -23.9301mA -17.3881mA -39.1532mA -5.10 -23.9301mA -17.3881mA -39.1532mA -5.20 -23.9301mA -17.3881mA -39.1532mA -5.30 -23.9301mA -17.3881mA -39.1532mA -5.40 -23.9301mA -17.3881mA -39.1532mA -5.50 -23.9301mA -17.3881mA -39.1532mA -5.60 -23.9301mA -17.3881mA -39.1532mA -5.70 -23.9301mA -17.3881mA -39.1532mA -5.80 -23.9301mA -17.3881mA -39.1532mA -5.90 -23.9301mA -17.3881mA -39.1532mA -6.00 -23.9301mA -17.3881mA -39.1532mA -6.10 -23.9301mA -17.3881mA -39.1532mA -6.20 -23.9301mA -17.3881mA -39.1532mA -6.30 -23.9301mA -17.3881mA -39.1532mA -6.40 -23.9301mA -17.3881mA -39.1532mA -6.50 -23.9301mA -17.3881mA -39.1532mA -6.55 -23.9301mA -17.3881mA -39.1532mA -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A 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-1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.6648mA 0.7494mA 0.5971mA - -3.15 0.5464mA 0.6392mA 0.4620mA - -3.05 0.4320mA 0.5325mA 0.3346mA - -2.95 0.3223mA 0.4288mA 0.2203mA - -2.85 0.2202mA 0.3288mA 0.1294mA - -2.75 0.1318mA 0.2341mA 72.8310uA - -2.65 67.1930uA 0.1484mA 47.8290uA - -2.55 33.3830uA 79.2120uA 38.1420uA - -2.45 21.1010uA 36.2260uA 33.4220uA - -2.35 16.7340uA 18.9530uA 30.1320uA - -2.25 14.6010uA 13.5620uA 27.2560uA - -2.15 13.0520uA 11.4690uA 24.5640uA - -2.05 11.6720uA 10.2210uA 22.0120uA - -1.95 10.3780uA 9.1893uA 19.5960uA - -1.85 9.1543uA 8.2396uA 17.3210uA - -1.75 8.0014uA 7.3461uA 15.1920uA - -1.65 6.9210uA 6.5045uA 13.2170uA - -1.55 5.9158uA 5.7141uA 11.4020uA - -1.45 4.9887uA 4.9753uA 9.7529uA - -1.35 4.1426uA 4.2887uA 8.2767uA - -1.25 3.3804uA 3.6548uA 6.9786uA - -1.15 2.7049uA 3.0746uA 5.8648uA - -1.05 2.1189uA 2.5487uA 4.9428uA - -0.95 1.6251uA 2.0780uA 4.2177uA - -0.85 1.2274uA 1.6631uA 3.6560uA - -0.75 0.9313uA 1.3051uA 3.6560uA - -0.65 0.7398uA 1.0056uA 3.6560uA - -0.55 0.6327uA 0.7679uA 3.6560uA - -0.45 0.5649uA 0.5968uA 1.9769uA - -0.35 0.5649uA 0.4927uA 1.5352uA - -0.25 0.5649uA 0.4380uA 1.2603uA - -0.15 0.5649uA 0.4056uA 1.0262uA - -0.05 0.2497uA 0.3924uA 0.8243uA - 0.00 0.1905uA 0.3924uA 0.7347uA - 0.05 0.1661uA 0.3924uA 0.6522uA - 0.15 0.1377uA 0.3924uA 0.5077uA - 0.25 0.1149uA 0.2673uA 0.3882uA - 0.35 95.5840nA 94.4790nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2001nA 17.4270nA -0.8025nA - 1.55 4.6216nA 13.7460nA -4.4469nA - 1.65 1.0975nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8985nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2565nA -22.2600nA - 2.15 -16.3730nA -7.8414nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -[Ramp] -| variable typ min max -dV/dt_r 0.7026/0.4330n 0.4966/0.5731n 1.0018/0.3242n -dV/dt_f 0.6827/0.4387n 0.4730/0.5599n 0.9168/0.3576n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 2.1621V 2.3517V 1.9420V -0.1010nS 2.1621V 2.3517V 1.9420V -0.2020nS 2.1621V 2.3517V 1.9420V -0.3030nS 2.1621V 2.3517V 1.9420V -0.4040nS 2.1621V 2.3517V 1.9420V -0.5051nS 2.1622V 2.3517V 2.2421V -0.6061nS 2.1615V 2.3517V 2.8060V -0.7071nS 2.2762V 2.3517V 3.1342V -0.8081nS 2.7361V 2.3522V 3.3164V -0.9091nS 2.9561V 2.3515V 3.3898V -1.0101nS 3.0907V 2.3704V 3.4244V -1.1111nS 3.1772V 2.6051V 3.4432V -1.2121nS 3.2242V 2.8360V 3.4539V -1.3131nS 3.2509V 2.9413V 3.4602V -1.4141nS 3.2670V 3.0020V 3.4639V -1.5152nS 3.2775V 3.0439V 3.4662V -1.6162nS 3.2845V 3.0714V 3.4676V -1.7172nS 3.2892V 3.0897V 3.4685V -1.8182nS 3.2924V 3.1025V 3.4690V -1.9192nS 3.2946V 3.1117V 3.4694V -2.0202nS 3.2961V 3.1186V 3.4696V -2.1212nS 3.2972V 3.1237V 3.4697V -2.2222nS 3.2980V 3.1276V 3.4698V -2.3232nS 3.2986V 3.1305V 3.4699V -2.4242nS 3.2989V 3.1327V 3.4699V -2.5253nS 3.2992V 3.1344V 3.4699V -2.6263nS 3.2994V 3.1356V 3.4699V -2.7273nS 3.2996V 3.1366V 3.4699V -2.8283nS 3.2997V 3.1373V 3.4699V -2.9293nS 3.2998V 3.1379V 3.4700V -3.0303nS 3.2998V 3.1383V 3.4699V -3.1313nS 3.2999V 3.1387V 3.4700V -3.2323nS 3.2999V 3.1390V 3.4699V -3.3333nS 3.2999V 3.1392V 3.4700V -3.4343nS 3.2999V 3.1393V 3.4699V -3.5354nS 3.2999V 3.1395V 3.4700V -3.6364nS 3.3000V 3.1396V 3.4699V -3.7374nS 3.3000V 3.1397V 3.4700V -3.8384nS 3.3000V 3.1397V 3.4700V -3.9394nS 3.3000V 3.1398V 3.4700V -4.0404nS 3.3000V 3.1398V 3.4700V -4.1414nS 3.3000V 3.1399V 3.4700V -4.2424nS 3.3000V 3.1399V 3.4700V -4.3434nS 3.3000V 3.1399V 3.4700V -4.4444nS 3.3000V 3.1400V 3.4700V -4.5455nS 3.3000V 3.1400V 3.4700V -4.6465nS 3.3000V 3.1399V 3.4700V -4.7475nS 3.3000V 3.1400V 3.4700V -4.8485nS 3.3000V 3.1400V 3.4700V -4.9495nS 3.3000V 3.1400V 3.4700V -5.0505nS 3.3000V 3.1400V 3.4700V -5.1515nS 3.3000V 3.1400V 3.4699V -5.2525nS 3.3000V 3.1400V 3.4700V -5.3535nS 3.3000V 3.1400V 3.4700V -5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4699V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4699V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4699V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4699V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4699V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 3.3000V 3.1400V 3.4700V -8.4848nS 3.3000V 3.1400V 3.4700V -8.5859nS 3.3000V 3.1400V 3.4700V -8.6869nS 3.3000V 3.1400V 3.4700V -8.7879nS 3.3000V 3.1400V 3.4700V -8.8889nS 3.3000V 3.1400V 3.4700V -8.9899nS 3.3000V 3.1400V 3.4700V -9.0909nS 3.3000V 3.1400V 3.4700V -9.1919nS 3.3000V 3.1400V 3.4700V -9.2929nS 3.3000V 3.1400V 3.4700V -9.3939nS 3.3000V 3.1400V 3.4700V -9.4949nS 3.3000V 3.1400V 3.4700V -9.5960nS 3.3000V 3.1400V 3.4700V -9.6970nS 3.3000V 3.1400V 3.4700V -9.7980nS 3.3000V 3.1400V 3.4700V -9.8990nS 3.3000V 3.1400V 3.4700V -10.0000nS 3.3000V 3.1400V 3.4700V -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 1.2884uV 1.5543uV 1.3225uV -0.1010nS 0.5355uV 0.8430uV 0.6254uV -0.2020nS -3.0614uV 0.1113uV 0.5701uV -0.3030nS 0.6806uV -1.9546uV 10.3860uV -0.4040nS 3.2624uV 1.2769uV -0.2118mV -0.5051nS 32.7230uV 1.5286uV -24.1640mV -0.6061nS -0.3955mV 2.8080uV -9.9395mV -0.7071nS -15.7200mV 17.6660uV 0.1561V -0.8081nS -19.9850mV 99.9200uV 0.5397V -0.9091nS -0.4586mV -0.2072mV 0.9226V -1.0101nS 88.3420mV -6.1838mV 1.2091V -1.1111nS 0.2478V -18.1000mV 1.3886V -1.2121nS 0.4471V -16.0430mV 1.4951V -1.3131nS 0.6318V -10.1180mV 1.5589V -1.4141nS 0.7749V 8.8815mV 1.5984V -1.5152nS 0.8766V 55.5920mV 1.6234V -1.6162nS 0.9465V 0.1340V 1.6394V -1.7172nS 0.9942V 0.2360V 1.6498V -1.8182nS 1.0272V 0.3461V 1.6566V -1.9192nS 1.0502V 0.4492V 1.6613V -2.0202nS 1.0667V 0.5367V 1.6638V -2.1212nS 1.0785V 0.6066V 1.6656V -2.2222nS 1.0871V 0.6605V 1.6667V -2.3232nS 1.0934V 0.7013V 1.6675V -2.4242nS 1.0979V 0.7318V 1.6680V -2.5253nS 1.1013V 0.7546V 1.6684V -2.6263nS 1.1038V 0.7716V 1.6687V -2.7273nS 1.1056V 0.7845V 1.6689V -2.8283nS 1.1069V 0.7942V 1.6691V -2.9293nS 1.1080V 0.8016V 1.6693V -3.0303nS 1.1087V 0.8073V 1.6693V -3.1313nS 1.1093V 0.8118V 1.6694V -3.2323nS 1.1097V 0.8152V 1.6695V -3.3333nS 1.1100V 0.8178V 1.6695V -3.4343nS 1.1103V 0.8199V 1.6695V -3.5354nS 1.1104V 0.8215V 1.6696V -3.6364nS 1.1105V 0.8228V 1.6695V -3.7374nS 1.1106V 0.8238V 1.6696V -3.8384nS 1.1107V 0.8246V 1.6696V -3.9394nS 1.1107V 0.8252V 1.6696V -4.0404nS 1.1108V 0.8257V 1.6696V -4.1414nS 1.1108V 0.8261V 1.6696V -4.2424nS 1.1108V 0.8265V 1.6696V -4.3434nS 1.1109V 0.8267V 1.6696V -4.4444nS 1.1109V 0.8269V 1.6696V -4.5455nS 1.1109V 0.8271V 1.6696V -4.6465nS 1.1109V 0.8272V 1.6696V -4.7475nS 1.1109V 0.8273V 1.6696V -4.8485nS 1.1109V 0.8274V 1.6696V -4.9495nS 1.1109V 0.8274V 1.6696V -5.0505nS 1.1109V 0.8276V 1.6696V -5.1515nS 1.1109V 0.8276V 1.6696V -5.2525nS 1.1109V 0.8276V 1.6696V -5.3535nS 1.1109V 0.8276V 1.6696V -5.4545nS 1.1109V 0.8276V 1.6696V -5.5556nS 1.1109V 0.8276V 1.6696V -5.6566nS 1.1109V 0.8276V 1.6696V -5.7576nS 1.1109V 0.8277V 1.6696V -5.8586nS 1.1109V 0.8277V 1.6696V -5.9596nS 1.1109V 0.8277V 1.6696V -6.0606nS 1.1109V 0.8277V 1.6696V -6.1616nS 1.1109V 0.8277V 1.6696V -6.2626nS 1.1109V 0.8277V 1.6696V -6.3636nS 1.1109V 0.8277V 1.6696V -6.4646nS 1.1109V 0.8277V 1.6696V -6.5657nS 1.1109V 0.8277V 1.6696V -6.6667nS 1.1110V 0.8277V 1.6696V -6.7677nS 1.1109V 0.8277V 1.6696V -6.8687nS 1.1109V 0.8277V 1.6696V -6.9697nS 1.1109V 0.8277V 1.6696V -7.0707nS 1.1110V 0.8277V 1.6696V -7.1717nS 1.1109V 0.8277V 1.6696V -7.2727nS 1.1110V 0.8277V 1.6696V -7.3737nS 1.1110V 0.8277V 1.6696V -7.4747nS 1.1110V 0.8277V 1.6696V -7.5758nS 1.1110V 0.8277V 1.6696V -7.6768nS 1.1110V 0.8277V 1.6696V -7.7778nS 1.1109V 0.8277V 1.6696V -7.8788nS 1.1110V 0.8277V 1.6696V -7.9798nS 1.1110V 0.8277V 1.6696V -8.0808nS 1.1110V 0.8277V 1.6696V -8.1818nS 1.1109V 0.8277V 1.6696V -8.2828nS 1.1110V 0.8277V 1.6696V -8.3838nS 1.1110V 0.8277V 1.6696V -8.4848nS 1.1110V 0.8277V 1.6696V -8.5859nS 1.1110V 0.8277V 1.6696V -8.6869nS 1.1110V 0.8277V 1.6696V -8.7879nS 1.1109V 0.8277V 1.6696V -8.8889nS 1.1109V 0.8277V 1.6696V -8.9899nS 1.1109V 0.8277V 1.6696V -9.0909nS 1.1109V 0.8277V 1.6696V -9.1919nS 1.1109V 0.8277V 1.6696V -9.2929nS 1.1109V 0.8277V 1.6696V -9.3939nS 1.1109V 0.8277V 1.6696V -9.4949nS 1.1109V 0.8277V 1.6696V -9.5960nS 1.1109V 0.8277V 1.6696V -9.6970nS 1.1110V 0.8277V 1.6696V -9.7980nS 1.1110V 0.8277V 1.6696V -9.8990nS 1.1110V 0.8277V 1.6696V -10.0000nS 1.1109V 0.8277V 1.6696V -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 1.1109V 0.8277V 1.6696V -0.1010nS 1.1109V 0.8277V 1.6696V -0.2020nS 1.1109V 0.8277V 1.6696V -0.3030nS 1.1110V 0.8277V 1.6696V -0.4040nS 1.1110V 0.8277V 1.6696V -0.5051nS 1.1109V 0.8277V 1.6644V -0.6061nS 1.1110V 0.8277V 1.0431V -0.7071nS 1.1113V 0.8277V 0.4157V -0.8081nS 0.9851V 0.8277V 0.1612V -0.9091nS 0.5727V 0.8276V 77.0900mV -1.0101nS 0.2814V 0.8282V 40.8740mV -1.1111nS 0.1329V 0.8285V 22.9430mV -1.2121nS 73.6840mV 0.7997V 12.4510mV -1.3131nS 43.0370mV 0.5895V 6.8313mV -1.4141nS 26.7550mV 0.3604V 3.7992mV -1.5152nS 17.0970mV 0.2116V 2.1510mV -1.6162nS 11.1140mV 0.1248V 1.2529mV -1.7172nS 7.2776mV 75.3210mV 0.7544mV -1.8182nS 4.8176mV 47.2290mV 0.4826mV -1.9192nS 3.1888mV 31.3570mV 0.3253mV -2.0202nS 2.1519mV 21.8020mV 0.2392mV -2.1212nS 1.4430mV 15.5850mV 0.1806mV -2.2222nS 1.0065mV 11.3310mV 0.1485mV -2.3232nS 0.6888mV 8.3187mV 0.1251mV -2.4242nS 0.5069mV 6.1527mV 0.1108mV -2.5253nS 0.3566mV 4.5704mV 0.1026mV -2.6263nS 0.2717mV 3.4134mV 96.2470uV -2.7273nS 0.1995mV 2.5569mV 87.3860uV -2.8283nS 0.1853mV 1.9272mV 82.9260uV -2.9293nS 0.1277mV 1.4565mV 68.6140uV -3.0303nS 0.1252mV 1.1098mV 60.2230uV -3.1313nS 89.5590uV 0.8485mV 49.7170uV -3.2323nS 94.4160uV 0.6561mV 56.7570uV -3.3333nS 49.7470uV 0.5093mV 54.1530uV -3.4343nS 57.0870uV 0.3863mV 49.3370uV -3.5354nS 52.4280uV 0.3073mV 42.7020uV -3.6364nS 77.0030uV 0.2451mV 40.7070uV -3.7374nS 46.1550uV 0.1875mV 33.9890uV -3.8384nS 63.3650uV 0.1621mV 34.0740uV -3.9394nS 31.9750uV 0.1378mV 27.5110uV -4.0404nS 46.0820uV 0.1176mV 33.5240uV -4.1414nS 14.0450uV 0.1002mV 26.4520uV -4.2424nS 30.8440uV 91.6770uV 22.6270uV -4.3434nS 23.9580uV 76.4830uV 15.2880uV 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-1.9192nS 2.2145V 2.6506V 1.9515V -2.0202nS 2.2003V 2.5809V 1.9484V -2.1212nS 2.1900V 2.5272V 1.9463V -2.2222nS 2.1826V 2.4862V 1.9450V -2.3232nS 2.1771V 2.4551V 1.9440V -2.4242nS 2.1731V 2.4314V 1.9434V -2.5253nS 2.1702V 2.4134V 1.9430V -2.6263nS 2.1681V 2.3996V 1.9427V -2.7273nS 2.1665V 2.3890V 1.9425V -2.8283nS 2.1654V 2.3808V 1.9424V -2.9293nS 2.1646V 2.3745V 1.9423V -3.0303nS 2.1639V 2.3696V 1.9422V -3.1313nS 2.1635V 2.3658V 1.9422V -3.2323nS 2.1631V 2.3628V 1.9421V -3.3333nS 2.1629V 2.3604V 1.9421V -3.4343nS 2.1627V 2.3586V 1.9421V -3.5354nS 2.1626V 2.3572V 1.9420V -3.6364nS 2.1625V 2.3560V 1.9421V -3.7374nS 2.1624V 2.3551V 1.9421V -3.8384nS 2.1623V 2.3544V 1.9421V -3.9394nS 2.1623V 2.3539V 1.9420V -4.0404nS 2.1622V 2.3534V 1.9420V -4.1414nS 2.1622V 2.3531V 1.9420V -4.2424nS 2.1622V 2.3528V 1.9420V -4.3434nS 2.1622V 2.3526V 1.9420V -4.4444nS 2.1622V 2.3524V 1.9420V -4.5455nS 2.1622V 2.3523V 1.9420V -4.6465nS 2.1622V 2.3522V 1.9420V -4.7475nS 2.1622V 2.3521V 1.9420V -4.8485nS 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2.3517V 1.9420V -7.8788nS 2.1621V 2.3517V 1.9420V -7.9798nS 2.1621V 2.3517V 1.9420V -8.0808nS 2.1621V 2.3517V 1.9420V -8.1818nS 2.1621V 2.3517V 1.9420V -8.2828nS 2.1621V 2.3517V 1.9420V -8.3838nS 2.1621V 2.3517V 1.9420V -8.4848nS 2.1621V 2.3517V 1.9420V -8.5859nS 2.1621V 2.3517V 1.9420V -8.6869nS 2.1621V 2.3517V 1.9420V -8.7879nS 2.1621V 2.3517V 1.9420V -8.8889nS 2.1621V 2.3517V 1.9420V -8.9899nS 2.1621V 2.3517V 1.9420V -9.0909nS 2.1621V 2.3517V 1.9420V -9.1919nS 2.1621V 2.3517V 1.9420V -9.2929nS 2.1621V 2.3517V 1.9420V -9.3939nS 2.1621V 2.3517V 1.9420V -9.4949nS 2.1621V 2.3517V 1.9420V -9.5960nS 2.1621V 2.3517V 1.9420V -9.6970nS 2.1621V 2.3517V 1.9420V -9.7980nS 2.1621V 2.3517V 1.9420V -9.8990nS 2.1621V 2.3517V 1.9420V -10.0000nS 2.1621V 2.3517V 1.9420V -| -| End [Model] lvt330s040aaaaaaaaou -|************************************************************************ -[Model] lvt330s040haaaaaaaio -Model_type I/O -Polarity Non-Inverting -Enable Active-Low -Vinl = 0.8000V -Vinh = 2.0000V -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -13.0175mA -9.4589mA -17.0245mA - -3.20 -12.9707mA -9.4248mA -16.9624mA - -3.10 -12.9240mA -9.3908mA -16.9003mA - -3.00 -12.8773mA -9.3568mA -16.8383mA - -2.90 -12.8305mA -9.3227mA -16.7762mA - -2.80 -12.7838mA -9.2887mA -16.7142mA - -2.70 -12.7370mA -9.2546mA -16.6521mA - -2.60 -12.6903mA -9.2206mA -16.5900mA - -2.50 -12.6435mA -9.1866mA -16.5280mA - -2.40 -12.5968mA -9.1525mA -16.4659mA - -2.30 -12.5500mA -9.1185mA -16.4038mA - -2.20 -12.5033mA -9.0845mA -16.3418mA - -2.10 -12.4566mA -9.0504mA -16.2797mA - -2.00 -12.4098mA -9.0164mA -16.2176mA - -1.90 -12.3631mA -8.9824mA -16.1556mA - -1.80 -12.3163mA -8.9483mA -16.0935mA - -1.70 -12.2696mA -8.9143mA -16.0314mA - -1.60 -12.2228mA -8.8803mA -15.9694mA - -1.50 -12.1761mA -8.8462mA -15.9073mA - -1.40 -12.1293mA -8.8122mA -15.8453mA - -1.30 -12.0826mA -8.7781mA -15.7832mA - -1.20 -12.0359mA -8.7441mA -15.7211mA - -1.10 -11.9891mA -8.7101mA -15.6591mA - -1.00 -11.9424mA -8.6760mA -15.5970mA - -0.90 -11.8920mA -8.6420mA -14.2580mA - -0.80 -11.2030mA -8.5040mA -13.3310mA - -0.70 -10.6640mA -8.3180mA -12.8580mA - -0.60 -10.1775mA -7.9085mA -12.5090mA - -0.50 -9.6242mA -7.2249mA -12.2652mA - -0.40 -8.4558mA -6.0810mA -11.1990mA - -0.30 -6.5017mA -4.6206mA -8.6527mA - -0.20 -4.3829mA -3.0989mA -5.8476mA - -0.10 -2.2159mA -1.5586mA -2.9656mA - 0.00 1.3970nA 1.1420nA 1.8430nA - 0.10 2.1875mA 1.5273mA 2.9429mA - 0.20 4.2657mA 2.9723mA 5.7511mA - 0.30 6.2349mA 4.3353mA 8.4238mA - 0.40 8.0952mA 5.6169mA 10.9612mA - 0.50 9.8472mA 6.8175mA 13.3613mA - 0.60 11.4909mA 7.9379mA 15.6250mA - 0.70 13.0251mA 8.9781mA 17.7500mA - 0.80 14.4502mA 9.9381mA 19.7321mA - 0.90 15.7635mA 10.8176mA 21.5658mA - 1.00 16.9605mA 11.6151mA 23.2399mA - 1.10 18.0347mA 12.3297mA 24.7385mA - 1.20 18.9760mA 12.9574mA 26.0423mA - 1.30 19.7754mA 13.4941mA 27.1313mA - 1.40 20.4319mA 13.9418mA 28.0074mA - 1.50 21.1825mA 14.4344mA 28.6916mA - 1.60 21.5959mA 14.7249mA 29.6115mA - 1.70 21.9250mA 14.9601mA 30.0279mA - 1.80 22.1935mA 15.1539mA 30.3626mA - 1.90 22.4157mA 15.3154mA 30.6368mA - 2.00 22.6034mA 15.4536mA 30.8683mA - 2.10 22.7656mA 15.5735mA 31.0653mA - 2.20 22.9074mA 15.6790mA 31.2357mA - 2.30 23.0328mA 15.7722mA 31.3865mA - 2.40 23.1458mA 15.8561mA 31.5207mA - 2.50 23.2463mA 15.9326mA 31.6404mA - 2.60 23.3383mA 16.0018mA 31.7495mA - 2.70 23.4230mA 16.0657mA 31.8480mA - 2.80 23.5002mA 16.1243mA 31.9389mA - 2.90 23.5720mA 16.1785mA 32.0223mA - 3.00 23.6383mA 16.2294mA 32.0991mA - 3.10 23.7003mA 16.2770mA 32.1714mA - 3.20 23.7588mA 16.3211mA 32.2390mA - 3.30 23.8138mA 16.3630mA 32.3031mA - 3.40 23.8674mA 16.4006mA 32.3667mA - 3.50 23.9193mA 16.4233mA 32.4306mA - 3.60 23.9674mA 16.4889mA 32.4982mA - 3.70 23.9882mA 16.5546mA 32.5708mA - 3.80 24.0840mA 16.6202mA 32.6441mA - 3.90 24.1798mA 16.6859mA 32.7359mA - 4.00 24.2756mA 16.7515mA 32.8665mA - 4.10 24.3714mA 16.8172mA 32.9972mA - 4.20 24.4672mA 16.8828mA 33.1278mA - 4.30 24.5630mA 16.9485mA 33.2584mA - 4.40 24.6588mA 17.0142mA 33.3891mA - 4.50 24.7546mA 17.0798mA 33.5197mA - 4.60 24.8504mA 17.1455mA 33.6503mA - 4.70 24.9462mA 17.2111mA 33.7810mA - 4.80 25.0420mA 17.2768mA 33.9116mA - 4.90 25.1378mA 17.3424mA 34.0423mA - 5.00 25.2336mA 17.4081mA 34.1729mA - 5.10 25.3294mA 17.4737mA 34.3035mA - 5.20 25.4252mA 17.5394mA 34.4342mA - 5.30 25.5210mA 17.6051mA 34.5648mA - 5.40 25.6168mA 17.6707mA 34.6955mA - 5.50 25.7126mA 17.7364mA 34.8261mA - 5.60 25.8084mA 17.8020mA 34.9567mA - 5.70 25.9042mA 17.8677mA 35.0874mA - 5.80 25.9999mA 17.9333mA 35.2180mA - 5.90 26.0957mA 17.9990mA 35.3486mA - 6.00 26.1915mA 18.0647mA 35.4793mA - 6.10 26.2873mA 18.1303mA 35.6099mA - 6.20 26.3831mA 18.1960mA 35.7406mA - 6.30 26.4789mA 18.2616mA 35.8712mA - 6.40 26.5747mA 18.3273mA 36.0018mA - 6.50 26.6705mA 18.3929mA 36.1325mA - 6.60 26.7663mA 18.4586mA 36.2631mA -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| --3.30 60.9662mA 46.6308mA 87.0217mA --3.20 60.7240mA 46.4472mA 86.7600mA --3.10 60.2994mA 46.2636mA 85.3500mA --3.00 59.0755mA 46.0800mA 83.1700mA --2.90 57.3963mA 45.5300mA 80.5900mA --2.80 55.4705mA 44.3800mA 77.7700mA --2.70 53.3739mA 42.9200mA 74.8000mA --2.60 51.1729mA 41.2800mA 71.7300mA --2.50 48.8960mA 39.5320mA 68.6000mA --2.40 46.5650mA 37.7130mA 65.4100mA --2.30 44.2113mA 35.8570mA 62.2000mA --2.20 41.8320mA 33.9950mA 58.9610mA --2.10 39.4555mA 32.1310mA 55.7110mA --2.00 37.1056mA 30.2880mA 52.4470mA --1.90 34.7793mA 28.4710mA 49.1720mA --1.80 32.5319mA 26.6850mA 45.8900mA --1.70 30.3631mA 24.9360mA 42.6060mA --1.60 28.2959mA 23.2280mA 39.3910mA --1.50 26.3236mA 21.5600mA 36.3540mA --1.40 24.4385mA 19.9360mA 33.5720mA --1.30 22.6312mA 18.3560mA 31.0630mA --1.20 20.8932mA 16.8240mA 28.8020mA --1.10 19.2273mA 15.3490mA 26.8550mA --1.00 17.6525mA 13.9360mA 25.6750mA --0.90 16.2417mA 12.5950mA 24.4660mA --0.80 14.9068mA 11.3600mA 21.3180mA --0.70 13.2931mA 10.2971mA 18.9703mA --0.60 11.6685mA 9.2483mA 16.9105mA --0.50 9.9513mA 7.8709mA 14.6683mA --0.40 7.9801mA 6.2914mA 11.8564mA --0.30 5.9303mA 4.6622mA 8.8439mA --0.20 3.9153mA 3.0657mA 5.8617mA --0.10 1.9400mA 1.5124mA 2.9160mA -0.00 -6.9700nA -2.5700nA -86.5000nA -0.10 -1.8799mA -1.4564mA -2.8429mA -0.20 -3.6735mA -2.8408mA -5.5653mA -0.30 -5.3808mA -4.1535mA -8.1679mA -0.40 -7.0025mA -5.3952mA -10.6515mA -0.50 -8.5393mA -6.5665mA -13.0149mA -0.60 -9.9917mA -7.6679mA -15.2608mA -0.70 -11.3594mA -8.6999mA -17.3894mA -0.80 -12.6449mA -9.6632mA -19.4005mA -0.90 -13.8465mA -10.5579mA -21.2942mA -1.00 -14.9659mA -11.3853mA -23.0724mA -1.10 -16.0032mA -12.1460mA -24.7353mA -1.20 -16.9593mA -12.8401mA -26.2837mA -1.30 -17.8352mA -13.4675mA -27.7167mA -1.40 -18.6299mA -14.0302mA -29.0372mA -1.50 -19.3454mA -14.5272mA -30.2434mA -1.60 -19.9815mA -14.9606mA -31.3381mA -1.70 -20.5404mA -15.3313mA -32.3204mA -1.80 -21.0208mA -15.7720mA -33.1924mA -1.90 -21.6437mA -16.0228mA -34.3429mA -2.00 -21.9782mA -16.2184mA -35.0021mA -2.10 -22.2442mA -16.3681mA -35.5553mA -2.20 -22.4522mA -16.4866mA -36.0104mA -2.30 -22.6203mA -16.5871mA -36.3794mA -2.40 -22.7636mA -16.6772mA -36.6831mA -2.50 -22.8919mA -16.7617mA -36.9446mA -2.60 -23.0116mA -16.8402mA -37.1814mA -2.70 -23.1247mA -16.9153mA -37.4005mA -2.80 -23.2299mA -16.9860mA -37.6054mA -2.90 -23.3289mA -17.0521mA -37.7972mA -3.00 -23.4225mA -17.1156mA -37.9765mA -3.10 -23.5107mA -17.1755mA -38.1452mA -3.20 -23.5932mA -17.2307mA -38.3020mA -3.30 -23.6690mA -17.2845mA -38.4487mA -3.40 -23.7421mA -17.3317mA -38.5851mA -3.50 -23.8099mA -17.3821mA -38.7103mA -3.60 -23.8639mA -17.4515mA -38.8302mA -3.70 -23.9593mA -17.5209mA -38.9459mA -3.80 -24.0548mA -17.5902mA -39.0277mA -3.90 -24.1501mA -17.6596mA -39.1834mA -4.00 -24.2455mA -17.7290mA -39.3392mA -4.10 -24.3409mA -17.7983mA -39.4949mA -4.20 -24.4363mA -17.8677mA -39.6506mA -4.30 -24.5317mA -17.9371mA -39.8063mA -4.40 -24.6271mA -18.0064mA -39.9620mA -4.50 -24.7225mA -18.0758mA -40.1178mA -4.60 -24.8179mA -18.1452mA -40.2735mA -4.70 -24.9133mA -18.2145mA -40.4292mA -4.80 -25.0087mA -18.2839mA -40.5849mA -4.90 -25.1041mA -18.3532mA -40.7406mA -5.00 -25.1995mA -18.4226mA -40.8964mA -5.10 -25.2949mA -18.4920mA -41.0521mA -5.20 -25.3902mA -18.5613mA -41.2078mA -5.30 -25.4857mA -18.6307mA -41.3635mA -5.40 -25.5810mA -18.7001mA -41.5192mA -5.50 -25.6765mA -18.7694mA -41.6750mA -5.60 -25.7719mA -18.8388mA -41.8307mA -5.70 -25.8673mA -18.9082mA -41.9864mA -5.80 -25.9627mA -18.9775mA -42.1421mA -5.90 -26.0580mA -19.0469mA -42.2978mA -6.00 -26.1535mA -19.1163mA -42.4536mA -6.10 -26.2488mA -19.1856mA -42.6093mA -6.20 -26.3443mA -19.2550mA -42.7650mA -6.30 -26.4396mA -19.3244mA -42.9207mA -6.40 -26.5350mA -19.3937mA -43.0764mA -6.50 -26.6305mA -19.4631mA -43.2322mA -6.55 -26.6781mA -19.4978mA -43.3100mA -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9552A -0.9302A -0.9778A - -3.25 -0.9306A -0.9058A -0.9532A - -3.20 -0.9061A -0.8814A -0.9285A - -3.15 -0.8815A -0.857A -0.9039A - -3.10 -0.857A -0.8327A -0.8792A - -3.05 -0.8325A -0.8083A -0.8546A - -3.00 -0.808A -0.784A -0.83A - -2.95 -0.7836A -0.7597A -0.8054A - -2.90 -0.7591A -0.7355A -0.7808A - -2.85 -0.7347A -0.7112A -0.7563A - -2.80 -0.7103A -0.6871A -0.7317A - -2.75 -0.6859A -0.6629A -0.7072A - -2.70 -0.6616A -0.6388A -0.6827A - -2.65 -0.6373A -0.6148A -0.6582A - -2.60 -0.613A -0.5908A -0.6338A - -2.55 -0.5888A -0.5668A -0.6094A - -2.50 -0.5646A -0.543A -0.585A - -2.45 -0.5405A -0.5192A -0.5607A - -2.40 -0.5165A -0.4955A -0.5364A - -2.35 -0.4925A -0.4719A -0.5122A - -2.30 -0.4686A -0.4484A -0.488A - -2.25 -0.4448A -0.425A -0.4639A - -2.20 -0.421A -0.4018A -0.4398A - -2.15 -0.3975A -0.3788A -0.4159A - -2.10 -0.374A -0.3561A -0.3921A - -2.05 -0.3508A -0.3336A -0.3684A - -2.00 -0.3278A -0.3115A -0.3449A - -1.95 -0.3051A -0.2898A -0.3216A - -1.90 -0.2829A -0.2688A -0.2986A - -1.85 -0.2611A -0.2485A -0.276A - -1.80 -0.2402A -0.2293A -0.2541A - -1.75 -0.2203A -0.2115A -0.233A - -1.70 -0.2019A -0.1953A -0.2133A - -1.65 -0.1856A -0.1809A -0.1957A - -1.60 -0.1716A -0.1681A -0.1809A - -1.55 -0.1593A -0.1563A -0.1683A - -1.50 -0.148A -0.1451A -0.157A - -1.45 -0.1371A -0.1342A -0.146A - -1.40 -0.1266A -0.1236A -0.1353A - -1.35 -0.1161A -0.1131A -0.1248A - -1.30 -0.1059A -0.1029A -0.1145A - -1.25 -95.8525mA -92.7685mA -0.1044A - -1.20 -86.0775mA -82.8695mA -94.7415mA - -1.15 -76.6285mA -73.2225mA -85.5735mA - -1.10 -67.6045mA -63.8875mA -77.1175mA - -1.05 -59.1405mA -54.9455mA -69.5895mA - -1.00 -51.4145mA -46.5095mA -63.0585mA - -0.95 -44.6125mA -38.7355mA -57.1555mA - -0.90 -38.7695mA -31.8215mA -51.1065mA - -0.85 -33.4345mA -25.8545mA -44.5675mA - -0.80 -28.1565mA -20.5265mA -37.8185mA - -0.75 -22.9755mA -15.7285mA -31.1295mA - -0.70 -18.0095mA -11.5805mA -24.6635mA - -0.65 -13.3705mA -8.0894mA -18.5475mA - -0.60 -9.185mA -5.219mA -12.9245mA - -0.55 -5.6163mA -2.9834mA -7.9946mA - -0.50 -2.8703mA -1.4348mA -4.0643mA - -0.45 -1.1245mA -0.5536mA -1.5008mA - -0.40 -0.308mA -0.1624mA -0.3485mA - -0.35 -35.6uA -20.3890uA -16.0uA - -0.30 0.0A 0.0A 0.0A - -0.25 0.0A 0.0A 0.0A - -0.20 0.0A 0.0A 0.0A - -0.15 0.0A 0.0A 0.0A - -0.10 0.0A 0.0A 0.0A - -0.05 0.0A 0.0A 0.0A - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.1221A 0.1248A 0.1242A - -3.15 0.1200A 0.1232A 0.1212A - -3.05 0.1178A 0.1215A 0.1181A - -2.95 0.1153A 0.1196A 0.1148A - -2.85 0.1128A 0.1174A 0.1114A - -2.75 0.1100A 0.1151A 0.1078A - -2.65 0.1071A 0.1126A 0.1041A - -2.55 0.1039A 0.1098A 0.1001A - -2.45 0.1006A 0.1069A 95.9680mA - -2.35 97.0630mA 0.1037A 91.5590mA - -2.25 93.2670mA 0.1003A 86.8480mA - -2.15 89.1920mA 96.7010mA 81.7630mA - -2.05 84.8070mA 92.8600mA 76.2010mA - -1.95 80.0800mA 88.7860mA 70.0340mA - -1.85 74.9870mA 84.4790mA 63.1570mA - -1.75 69.5180mA 79.9450mA 55.5700mA - -1.65 63.6850mA 75.1950mA 47.4010mA - -1.55 57.5160mA 70.2440mA 38.8580mA - -1.45 51.0440mA 65.1120mA 30.1910mA - -1.35 44.3150mA 59.8210mA 21.8920mA - -1.25 37.3820mA 54.3940mA 15.5340mA - -1.15 30.3110mA 48.8520mA 11.4230mA - -1.05 23.2090mA 43.2090mA 6.9858mA - -0.95 16.3160mA 37.4680mA 3.1948mA - -0.85 10.2960mA 31.6320mA 0.8600mA - -0.75 6.1213mA 25.7150mA 0.1694mA - -0.65 3.1679mA 19.7630mA 65.5350uA - -0.55 1.1362mA 13.8830mA 37.1010uA - -0.45 0.2574mA 8.3464mA 19.4580uA - -0.35 73.3430uA 3.8624mA 3.1206uA - -0.25 33.6580uA 1.3608mA -12.8040uA - -0.15 17.7650uA 0.3668mA -28.1570uA - -0.05 5.8276uA 90.2420uA -42.9420uA - 0.00 0.1897uA 50.8660uA -50.1210uA - 0.05 -5.3380uA 31.9340uA -57.1590uA - 0.15 -16.0560uA 15.1110uA -70.8070uA - 0.25 -26.3450uA 5.7330uA -83.8870uA - 0.35 -36.2070uA -2.2074uA -96.3970uA - 0.45 -45.6400uA -9.6847uA -0.1083mA - 0.55 -54.6440uA -16.8200uA -0.1197mA - 0.65 -63.2180uA -23.6240uA -0.1305mA - 0.75 -71.3610uA -30.0980uA -0.1407mA - 0.85 -79.0710uA -36.2430uA -0.1504mA - 0.95 -86.3480uA -42.0600uA -0.1594mA - 1.05 -93.1890uA -47.5470uA -0.1679mA - 1.15 -99.5930uA -52.7050uA -0.1758mA - 1.25 -0.1056mA -57.5350uA -0.1832mA - 1.35 -0.1111mA -62.0370uA -0.1899mA - 1.45 -0.1162mA -66.2090uA -0.1961mA - 1.55 -0.1208mA -70.0530uA -0.2016mA - 1.65 -0.1250mA -73.5690uA -0.2016mA - 1.75 -0.1287mA -76.7560uA -0.2016mA - 1.85 -0.1305mA -79.6150uA -0.2016mA - 1.95 -0.1305mA -82.1480uA -0.2016mA - 2.05 -0.1305mA -83.2920uA -0.2016mA - 2.15 -0.1305mA -83.2920uA -0.2016mA - 2.25 -0.1305mA -83.2920uA -0.2016mA - 2.35 -0.1305mA -83.2920uA -0.2016mA - 2.45 -0.1305mA -83.2920uA -0.2016mA - 2.55 -0.1305mA -83.2920uA -0.2016mA - 2.65 -0.1305mA -83.2920uA -0.2016mA - 2.75 -0.1305mA -83.2920uA -0.2016mA - 2.85 -0.1305mA -83.2920uA -0.2016mA - 2.95 -0.1305mA -83.2920uA -0.2016mA - 3.05 -0.1305mA -83.2920uA -0.2016mA - 3.15 -0.1305mA -83.2920uA -0.2016mA - 3.25 -0.1305mA -83.2920uA -0.2016mA - 6.60 -0.1305mA -83.292uA -0.2016mA -| -[Ramp] -| variable typ min max -dV/dt_r 0.7026/0.4330n 0.4966/0.5731n 1.0018/0.3242n -dV/dt_f 0.6827/0.4387n 0.4730/0.5599n 0.9168/0.3576n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 2.1621V 2.3517V 1.9420V -0.1010nS 2.1621V 2.3517V 1.9420V -0.2020nS 2.1621V 2.3517V 1.9420V -0.3030nS 2.1621V 2.3517V 1.9420V -0.4040nS 2.1621V 2.3517V 1.9420V -0.5051nS 2.1622V 2.3517V 2.2421V -0.6061nS 2.1615V 2.3517V 2.8060V -0.7071nS 2.2762V 2.3517V 3.1342V -0.8081nS 2.7361V 2.3522V 3.3164V -0.9091nS 2.9561V 2.3515V 3.3898V -1.0101nS 3.0907V 2.3704V 3.4244V -1.1111nS 3.1772V 2.6051V 3.4432V -1.2121nS 3.2242V 2.8360V 3.4539V -1.3131nS 3.2509V 2.9413V 3.4602V -1.4141nS 3.2670V 3.0020V 3.4639V -1.5152nS 3.2775V 3.0439V 3.4662V -1.6162nS 3.2845V 3.0714V 3.4676V -1.7172nS 3.2892V 3.0897V 3.4685V -1.8182nS 3.2924V 3.1025V 3.4690V -1.9192nS 3.2946V 3.1117V 3.4694V -2.0202nS 3.2961V 3.1186V 3.4696V -2.1212nS 3.2972V 3.1237V 3.4697V -2.2222nS 3.2980V 3.1276V 3.4698V -2.3232nS 3.2986V 3.1305V 3.4699V -2.4242nS 3.2989V 3.1327V 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-5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4699V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4699V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4699V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4699V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4699V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 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2.1622V 2.3519V 1.9420V -5.1515nS 2.1622V 2.3518V 1.9420V -5.2525nS 2.1622V 2.3518V 1.9420V -5.3535nS 2.1622V 2.3518V 1.9420V -5.4545nS 2.1622V 2.3518V 1.9420V -5.5556nS 2.1622V 2.3518V 1.9420V -5.6566nS 2.1622V 2.3517V 1.9420V -5.7576nS 2.1621V 2.3517V 1.9420V -5.8586nS 2.1621V 2.3517V 1.9420V -5.9596nS 2.1621V 2.3517V 1.9420V -6.0606nS 2.1621V 2.3517V 1.9420V -6.1616nS 2.1621V 2.3517V 1.9420V -6.2626nS 2.1621V 2.3517V 1.9420V -6.3636nS 2.1621V 2.3517V 1.9420V -6.4646nS 2.1621V 2.3517V 1.9420V -6.5657nS 2.1621V 2.3517V 1.9420V -6.6667nS 2.1622V 2.3517V 1.9420V -6.7677nS 2.1621V 2.3517V 1.9420V -6.8687nS 2.1621V 2.3517V 1.9420V -6.9697nS 2.1621V 2.3517V 1.9420V -7.0707nS 2.1621V 2.3517V 1.9420V -7.1717nS 2.1621V 2.3517V 1.9420V -7.2727nS 2.1621V 2.3517V 1.9420V -7.3737nS 2.1621V 2.3517V 1.9420V -7.4747nS 2.1621V 2.3517V 1.9420V -7.5758nS 2.1621V 2.3517V 1.9420V -7.6768nS 2.1621V 2.3517V 1.9420V -7.7778nS 2.1621V 2.3517V 1.9420V -7.8788nS 2.1621V 2.3517V 1.9420V -7.9798nS 2.1621V 2.3517V 1.9420V -8.0808nS 2.1621V 2.3517V 1.9420V -8.1818nS 2.1621V 2.3517V 1.9420V -8.2828nS 2.1621V 2.3517V 1.9420V -8.3838nS 2.1621V 2.3517V 1.9420V -8.4848nS 2.1621V 2.3517V 1.9420V -8.5859nS 2.1621V 2.3517V 1.9420V -8.6869nS 2.1621V 2.3517V 1.9420V -8.7879nS 2.1621V 2.3517V 1.9420V -8.8889nS 2.1621V 2.3517V 1.9420V -8.9899nS 2.1621V 2.3517V 1.9420V -9.0909nS 2.1621V 2.3517V 1.9420V -9.1919nS 2.1621V 2.3517V 1.9420V -9.2929nS 2.1621V 2.3517V 1.9420V -9.3939nS 2.1621V 2.3517V 1.9420V -9.4949nS 2.1621V 2.3517V 1.9420V -9.5960nS 2.1621V 2.3517V 1.9420V -9.6970nS 2.1621V 2.3517V 1.9420V -9.7980nS 2.1621V 2.3517V 1.9420V -9.8990nS 2.1621V 2.3517V 1.9420V -10.0000nS 2.1621V 2.3517V 1.9420V -| -| End [Model] lvt330s040haaaaaaaio -|************************************************************************ -[Model] lvt330s160aaaaaaaaou -Model_type Output -Polarity Non-Inverting -Enable Active-Low -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -46.0510mA -33.7410mA -59.5510mA - -3.20 -46.0510mA -33.7410mA -59.5510mA - -3.10 -46.0510mA -33.7410mA -59.5510mA - -3.00 -46.0510mA -33.7410mA -59.5510mA - -2.90 -46.0510mA -33.7410mA -59.5510mA - -2.80 -46.0510mA -33.7410mA -59.5510mA - -2.70 -46.0510mA -33.7410mA -59.5510mA - -2.60 -46.0510mA -33.7410mA -59.5510mA - -2.50 -46.0510mA -33.7410mA -59.5510mA - -2.40 -46.0510mA -33.7410mA -59.5510mA - -2.30 -46.0510mA -33.7410mA -59.5510mA - -2.20 -46.0510mA -33.7410mA -59.5510mA - -2.10 -46.0510mA -33.7410mA -59.5510mA - -2.00 -46.0510mA -33.7410mA -59.5510mA - -1.90 -46.0510mA -33.7410mA -59.5510mA - -1.80 -46.0510mA -33.7410mA -59.5510mA - -1.70 -46.0510mA -33.7410mA -59.5510mA - -1.60 -46.0510mA -33.7410mA -59.5510mA - -1.50 -46.0510mA -33.7410mA -59.5510mA - -1.40 -46.0510mA -33.7410mA -59.5510mA - -1.30 -46.0510mA -33.7410mA -59.5510mA - -1.20 -46.0510mA -33.7410mA -59.5510mA - -1.10 -46.0510mA -33.7410mA -59.5510mA - -1.00 -46.0510mA -33.7410mA -57.7460mA - -0.90 -45.1960mA -33.7410mA -53.3800mA - -0.80 -42.7900mA -33.0880mA -50.7690mA - -0.70 -40.7010mA -32.1190mA -48.9510mA - -0.60 -38.5892mA -30.1763mA -47.3570mA - -0.50 -35.7989mA -27.1490mA -45.2332mA - -0.40 -30.5530mA -22.5448mA -39.2561mA - -0.30 -23.3101mA -17.0730mA -30.0082mA - -0.20 -15.6753mA -11.4360mA -20.2124mA - -0.10 -7.9044mA -5.7449mA -10.2109mA - 0.00 9.1810nA 6.6370nA 14.6880nA - 0.10 7.8212mA 5.6449mA 10.1501mA - 0.20 15.3310mA 11.0300mA 19.9541mA - 0.30 22.5240mA 16.1530mA 29.4071mA - 0.40 29.3980mA 21.0130mA 38.5000mA - 0.50 35.9480mA 25.6080mA 47.2270mA - 0.60 42.1700mA 29.9370mA 55.5800mA - 0.70 48.0590mA 33.9980mA 63.5490mA - 0.80 53.6080mA 37.7880mA 71.1220mA - 0.90 58.8090mA 41.3050mA 78.2850mA - 1.00 63.6510mA 44.5440mA 85.0150mA - 1.10 68.1160mA 47.4970mA 91.2820mA - 1.20 72.1780mA 50.1540mA 97.0390mA - 1.30 75.8000mA 52.4980mA 0.1022A - 1.40 78.9390mA 54.5150mA 0.1067A - 1.50 81.5710mA 56.2010mA 0.1106A - 1.60 83.7180mA 57.5820mA 0.1137A - 1.70 85.4430mA 58.7040mA 0.1161A - 1.80 86.8340mA 59.6220mA 0.1181A - 1.90 87.9720mA 60.3850mA 0.1196A - 2.00 88.9210mA 61.0310mA 0.1209A - 2.10 89.7270mA 61.5880mA 0.1220A - 2.20 90.4240mA 62.0750mA 0.1229A - 2.30 91.0370mA 62.5080mA 0.1237A - 2.40 91.5820mA 62.8970mA 0.1244A - 2.50 92.0740mA 63.2500mA 0.1250A - 2.60 92.5210mA 63.5730mA 0.1256A - 2.70 92.9309mA 63.8720mA 0.1261A - 2.80 93.3099mA 64.1499mA 0.1266A - 2.90 93.6629mA 64.4089mA 0.1270A - 3.00 93.9929mA 64.6529mA 0.1274A - 3.10 94.3029mA 64.8829mA 0.1278A - 3.20 94.5958mA 65.1008mA 0.1281A - 3.30 94.8758mA 65.3076mA 0.1285A - 3.40 95.1436mA 65.5013mA 0.1288A - 3.50 95.4017mA 65.6576mA 0.1291A - 3.60 95.6462mA 65.9236mA 0.1294A - 3.70 95.8369mA 66.2546mA 0.1298A - 3.80 96.2034mA 67.0655mA 0.1301A - 3.90 96.5733mA 69.0584mA 0.1303A - 4.00 97.3652mA 73.2123mA 0.1309A - 4.10 99.2509mA 79.1820mA 0.1314A - 4.20 0.1022A 85.9597mA 0.1322A - 4.30 0.1063A 93.0914mA 0.1344A - 4.40 0.1126A 0.1004A 0.1384A - 4.50 0.1206A 0.1078A 0.1435A - 4.60 0.1294A 0.1153A 0.1489A - 4.70 0.1385A 0.1229A 0.1551A - 4.80 0.1479A 0.1307A 0.1648A - 4.90 0.1573A 0.1386A 0.1760A - 5.00 0.1669A 0.1467A 0.1878A - 5.10 0.1765A 0.1550A 0.1999A - 5.20 0.1863A 0.1634A 0.2120A - 5.30 0.1961A 0.1719A 0.2241A - 5.40 0.2062A 0.1805A 0.2362A - 5.50 0.2163A 0.1892A 0.2482A - 5.60 0.2265A 0.1980A 0.2603A - 5.70 0.2369A 0.2068A 0.2726A - 5.80 0.2473A 0.2158A 0.2851A - 5.90 0.2579A 0.2248A 0.2978A - 6.00 0.2687A 0.2339A 0.3108A - 6.10 0.2796A 0.2431A 0.3240A - 6.20 0.2907A 0.2524A 0.3374A - 6.30 0.3021A 0.2618A 0.3511A - 6.40 0.3136A 0.2714A 0.3652A - 6.50 0.3254A 0.2811A 0.3794A - 6.60 0.3374A 0.2909A 0.3940A -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| - -3.30 0.3688A 0.3085A 0.4482A - -3.20 0.3595A 0.3039A 0.4356A - -3.10 0.3495A 0.2972A 0.4227A - -3.00 0.3390A 0.2892A 0.4094A - -2.90 0.3282A 0.2805A 0.3959A - -2.80 0.3171A 0.2712A 0.3822A - -2.70 0.3056A 0.2615A 0.3683A - -2.60 0.2939A 0.2514A 0.3543A - -2.50 0.2819A 0.2409A 0.3400A - -2.40 0.2697A 0.2303A 0.3256A - -2.30 0.2573A 0.2194A 0.3110A - -2.20 0.2447A 0.2084A 0.2962A - -2.10 0.2318A 0.1972A 0.2811A - -2.00 0.2189A 0.1859A 0.2659A - -1.90 0.2058A 0.1745A 0.2504A - -1.80 0.1927A 0.1631A 0.2346A - -1.70 0.1795A 0.1517A 0.2186A - -1.60 0.1662A 0.1402A 0.2025A - -1.50 0.1528A 0.1288A 0.1863A - -1.40 0.1394A 0.1175A 0.1702A - -1.30 0.1260A 0.1062A 0.1543A - -1.20 0.1126A 94.9202mA 0.1391A - -1.10 99.3436mA 83.7786mA 0.1252A - -1.00 86.4581mA 72.7899mA 0.1110A - -0.90 74.6466mA 62.0952mA 97.2911mA - -0.80 64.2979mA 52.0534mA 84.6162mA - -0.70 54.8762mA 43.3265mA 72.7261mA - -0.60 46.1133mA 35.9755mA 61.5078mA - -0.50 37.8734mA 29.3476mA 50.1553mA - -0.40 29.8849mA 23.1046mA 40.2866mA - -0.30 22.2622mA 17.0802mA 30.1199mA - -0.20 14.7337mA 11.2591mA 20.0045mA - -0.10 7.3149mA 5.5671mA 9.9673mA - 0.00 -27.6800nA -12.5600nA -0.2990uA - 0.10 -7.1350mA -5.3932mA -9.7862mA - 0.20 -14.0071mA -10.5601mA -19.2690mA - 0.30 -20.6131mA -15.4991mA -28.4448mA - 0.40 -26.9531mA -20.2101mA -37.3096mA - 0.50 -33.0231mA -24.6920mA -45.8605mA - 0.60 -38.8211mA -28.9440mA -54.0924mA - 0.70 -44.3460mA -32.9660mA -62.0013mA - 0.80 -49.5950mA -36.7560mA -69.5842mA - 0.90 -54.5660mA -40.3130mA -76.8361mA - 1.00 -59.2570mA -43.6380mA -83.7531mA - 1.10 -63.6650mA -46.7280mA -90.3311mA - 1.20 -67.7890mA -49.5840mA -96.5660mA - 1.30 -71.6270mA -52.2040mA -0.1025A - 1.40 -75.1760mA -54.5890mA -0.1080A - 1.50 -78.4330mA -56.7370mA -0.1132A - 1.60 -81.3980mA -58.6480mA -0.1180A - 1.70 -84.0680mA -60.3220mA -0.1224A - 1.80 -86.4420mA -61.7600mA -0.1265A - 1.90 -88.5180mA -62.9650mA -0.1302A - 2.00 -90.2990mA -63.9430mA -0.1335A - 2.10 -91.7860mA -64.7110mA -0.1365A - 2.20 -92.9940mA -65.3040mA -0.1391A - 2.30 -93.9530mA -65.7740mA -0.1412A - 2.40 -94.7160mA -66.1750mA -0.1431A - 2.50 -95.3540mA -66.5370mA -0.1446A - 2.60 -95.9200mA -66.8780mA -0.1458A - 2.70 -96.4460mA -67.2020mA -0.1469A - 2.80 -96.9450mA -67.5150mA -0.1478A - 2.90 -97.4230mA -67.8180mA -0.1487A - 3.00 -97.8850mA -68.1109mA -0.1495A - 3.10 -98.3320mA -68.3969mA -0.1504A - 3.20 -98.7659mA -68.6739mA -0.1511A - 3.30 -99.1879mA -68.9436mA -0.1519A - 3.40 -99.5979mA -69.2026mA -0.1526A - 3.50 -99.9963mA -69.3920mA -0.1533A - 3.60 -0.1004A -69.3920mA -0.1540A - 3.70 -0.1005A -69.3920mA -0.1547A - 3.80 -0.1005A -69.3920mA -0.1553A - 3.90 -0.1005A -69.3920mA -0.1554A - 4.00 -0.1005A -69.3920mA -0.1554A - 4.10 -0.1005A -69.3920mA -0.1554A - 4.20 -0.1005A -69.3920mA -0.1554A - 4.30 -0.1005A -69.3920mA -0.1554A - 4.40 -0.1005A -69.3920mA -0.1554A - 4.50 -0.1005A -69.3920mA -0.1554A - 4.60 -0.1005A -69.3920mA -0.1554A - 4.70 -0.1005A -69.3920mA -0.1554A - 4.80 -0.1005A -69.3920mA -0.1554A - 4.90 -0.1005A -69.3920mA -0.1554A - 5.00 -0.1005A -69.3920mA -0.1554A - 5.10 -0.1005A -69.3920mA -0.1554A - 5.20 -0.1005A -69.3920mA -0.1554A - 5.30 -0.1005A -69.3920mA -0.1554A - 5.40 -0.1005A -69.3920mA -0.1554A - 5.50 -0.1005A -69.3920mA -0.1554A - 5.60 -0.1005A -69.3920mA -0.1554A - 5.70 -0.1005A -69.3920mA -0.1554A - 5.80 -0.1005A -69.3920mA -0.1554A - 5.90 -0.1005A -69.3920mA -0.1554A - 6.00 -0.1005A -69.3920mA -0.1554A - 6.10 -0.1005A -69.3920mA -0.1554A - 6.20 -0.1005A -69.3920mA -0.1554A - 6.30 -0.1005A -69.3920mA -0.1554A - 6.40 -0.1005A -69.3920mA -0.1554A - 6.50 -0.1005A -69.3920mA -0.1554A - 6.55 -0.1005A -69.3920mA -0.1554A -| -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A -0.9287A - -3.15 -0.8816A -0.8571A -0.9041A - -3.10 -0.8571A -0.8328A -0.8794A - -3.05 -0.8326A -0.8084A -0.8548A - -3.00 -0.8081A -0.7841A -0.8302A - -2.95 -0.7837A -0.7598A -0.8056A - -2.90 -0.7592A -0.7356A -0.781A - -2.85 -0.7348A -0.7113A -0.7565A - -2.80 -0.7104A -0.6872A -0.7319A - -2.75 -0.686A -0.663A -0.7074A - -2.70 -0.6617A -0.6389A -0.6829A - -2.65 -0.6374A -0.6149A -0.6584A - -2.60 -0.6131A -0.5909A -0.634A - -2.55 -0.5889A -0.5669A -0.6096A - -2.50 -0.5647A -0.5431A -0.5852A - -2.45 -0.5406A -0.5193A -0.5609A - -2.40 -0.5166A -0.4956A -0.5366A - -2.35 -0.4926A -0.472A -0.5124A - -2.30 -0.4687A -0.4485A -0.4882A - -2.25 -0.4449A -0.4251A -0.4641A - -2.20 -0.4211A -0.4019A -0.44A - -2.15 -0.3976A -0.3789A -0.4161A - -2.10 -0.3741A -0.3562A -0.3923A - -2.05 -0.3509A -0.3337A -0.3686A - -2.00 -0.3279A -0.3116A -0.3451A - -1.95 -0.3052A -0.2899A -0.3218A - -1.90 -0.283A -0.2689A -0.2988A - -1.85 -0.2612A -0.2486A -0.2762A - -1.80 -0.2402A -0.2294A -0.2543A - -1.75 -0.2204A -0.2116A -0.2332A - -1.70 -0.202A -0.1954A -0.2135A - -1.65 -0.1857A -0.181A -0.1959A - -1.60 -0.1717A -0.1682A -0.181A - -1.55 -0.1594A -0.1563A -0.1685A - -1.50 -0.1481A -0.1452A -0.1571A - -1.45 -0.1372A -0.1343A -0.1462A - -1.40 -0.1266A -0.1237A -0.1355A - -1.35 -0.1162A -0.1132A -0.125A - -1.30 -0.106A -0.1029A -0.1146A - -1.25 -95.9599mA -92.8329mA -0.1046A - -1.20 -86.1849mA -82.9339mA -94.9069mA - -1.15 -76.7349mA -73.2869mA -85.7379mA - -1.10 -67.7089mA -63.9519mA -77.2789mA - -1.05 -59.2439mA -55.0099mA -69.7479mA - -1.00 -51.5159mA -46.5729mA -63.2139mA - -0.95 -44.7119mA -38.7979mA -57.3089mA - -0.90 -38.8659mA -31.8819mA -51.2599mA - -0.85 -33.5299mA -25.9129mA -44.7209mA - -0.80 -28.2499mA -20.5839mA -37.9699mA - -0.75 -23.0669mA -15.7839mA -31.2789mA - -0.70 -18.0989mA -11.6329mA -24.8089mA - -0.65 -13.4569mA -8.1389mA -18.6889mA - -0.60 -9.2667mA -5.2646mA -13.0589mA - -0.55 -5.6915mA -3.0244mA -8.1194mA - -0.50 -2.937mA -1.4709mA -4.1747mA - -0.45 -1.1814mA -0.5866mA -1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.6648mA 0.7494mA 0.5971mA - -3.15 0.5464mA 0.6392mA 0.4620mA - -3.05 0.4320mA 0.5325mA 0.3346mA - -2.95 0.3223mA 0.4288mA 0.2203mA - -2.85 0.2202mA 0.3288mA 0.1294mA - -2.75 0.1318mA 0.2341mA 72.8320uA - -2.65 67.1940uA 0.1484mA 47.8300uA - -2.55 33.3840uA 79.2130uA 38.1430uA - -2.45 21.1020uA 36.2270uA 33.4230uA - -2.35 16.7350uA 18.9540uA 30.1320uA - -2.25 14.6020uA 13.5630uA 27.2570uA - -2.15 13.0530uA 11.4700uA 24.5650uA - -2.05 11.6730uA 10.2220uA 22.0130uA - -1.95 10.3790uA 9.1903uA 19.5970uA - -1.85 9.1554uA 8.2406uA 17.3220uA - -1.75 8.0024uA 7.3472uA 15.1930uA - -1.65 6.9220uA 6.5055uA 13.2180uA - -1.55 5.9168uA 5.7151uA 11.4030uA - -1.45 4.9897uA 4.9762uA 9.7538uA - -1.35 4.1435uA 4.2896uA 8.2775uA - -1.25 3.3813uA 3.6558uA 6.9794uA - -1.15 2.7058uA 3.0755uA 5.8656uA - -1.05 2.1197uA 2.5496uA 4.9436uA - -0.95 1.6260uA 2.0788uA 4.2185uA - -0.85 1.2282uA 1.6639uA 3.6568uA - -0.75 0.9321uA 1.3059uA 3.6568uA - -0.65 0.7406uA 1.0064uA 3.6568uA - -0.55 0.6334uA 0.7687uA 3.6568uA - -0.45 0.5657uA 0.5976uA 1.9769uA - -0.35 0.5657uA 0.4934uA 1.5352uA - -0.25 0.5657uA 0.4388uA 1.2603uA - -0.15 0.5657uA 0.4063uA 1.0262uA - -0.05 0.2497uA 0.3931uA 0.8243uA - 0.00 0.1905uA 0.3931uA 0.7347uA - 0.05 0.1661uA 0.3931uA 0.6522uA - 0.15 0.1377uA 0.3931uA 0.5077uA - 0.25 0.1149uA 0.2673uA 0.3882uA - 0.35 95.5840nA 94.4790nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2000nA 17.4270nA -0.8025nA - 1.55 4.6215nA 13.7460nA -4.4469nA - 1.65 1.0974nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8986nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2566nA -22.2600nA - 2.15 -16.3730nA -7.8413nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -[Ramp] -| variable typ min max -dV/dt_r 1.4966/0.2592n 1.2936/0.4087n 1.7021/0.1678n -dV/dt_f 1.5290/0.2281n 1.3043/0.3741n 1.7112/0.1501n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 0.7516V 0.9661V 0.6180V -0.1010nS 0.7516V 0.9661V 0.6180V -0.2020nS 0.7516V 0.9661V 0.6180V -0.3030nS 0.7516V 0.9661V 0.6180V -0.4040nS 0.7516V 0.9661V 0.6171V -0.5051nS 0.7517V 0.9661V 0.7829V -0.6061nS 0.7505V 0.9661V 2.0255V -0.7071nS 0.7950V 0.9661V 2.8797V -0.8081nS 1.7861V 0.9664V 3.3462V -0.9091nS 2.4193V 0.9655V 3.4176V -1.0101nS 2.8512V 0.9681V 3.4439V -1.1111nS 3.1357V 1.3754V 3.4564V -1.2121nS 3.2249V 2.1421V 3.4627V -1.3131nS 3.2565V 2.5293V 3.4661V -1.4141nS 3.2737V 2.7345V 3.4678V -1.5152nS 3.2838V 2.8969V 3.4688V -1.6162nS 3.2896V 3.0120V 3.4693V -1.7172nS 3.2934V 3.0632V 3.4696V -1.8182nS 3.2957V 3.0894V 3.4697V -1.9192nS 3.2972V 3.1045V 3.4698V -2.0202nS 3.2981V 3.1151V 3.4699V -2.1212nS 3.2987V 3.1221V 3.4699V -2.2222nS 3.2991V 3.1274V 3.4699V -2.3232nS 3.2994V 3.1308V 3.4699V -2.4242nS 3.2996V 3.1334V 3.4700V -2.5253nS 3.2997V 3.1352V 3.4700V -2.6263nS 3.2998V 3.1365V 3.4700V -2.7273nS 3.2998V 3.1374V 3.4700V -2.8283nS 3.2999V 3.1380V 3.4700V -2.9293nS 3.2999V 3.1385V 3.4700V -3.0303nS 3.2999V 3.1389V 3.4700V -3.1313nS 3.2999V 3.1391V 3.4700V -3.2323nS 3.3000V 3.1393V 3.4700V -3.3333nS 3.3000V 3.1395V 3.4700V -3.4343nS 3.3000V 3.1396V 3.4700V -3.5354nS 3.3000V 3.1397V 3.4700V -3.6364nS 3.3000V 3.1398V 3.4700V -3.7374nS 3.3000V 3.1398V 3.4700V -3.8384nS 3.3000V 3.1398V 3.4700V -3.9394nS 3.3000V 3.1399V 3.4700V -4.0404nS 3.3000V 3.1399V 3.4700V -4.1414nS 3.3000V 3.1399V 3.4700V -4.2424nS 3.3000V 3.1399V 3.4700V -4.3434nS 3.3000V 3.1399V 3.4700V -4.4444nS 3.3000V 3.1399V 3.4700V -4.5455nS 3.3000V 3.1400V 3.4700V -4.6465nS 3.3000V 3.1400V 3.4700V -4.7475nS 3.3000V 3.1400V 3.4700V -4.8485nS 3.3000V 3.1400V 3.4700V -4.9495nS 3.3000V 3.1400V 3.4700V -5.0505nS 3.3000V 3.1400V 3.4700V -5.1515nS 3.3000V 3.1400V 3.4700V -5.2525nS 3.3000V 3.1400V 3.4700V -5.3535nS 3.3000V 3.1400V 3.4700V -5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4700V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4700V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4700V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4700V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4700V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 3.3000V 3.1400V 3.4700V -8.4848nS 3.3000V 3.1400V 3.4700V -8.5859nS 3.3000V 3.1400V 3.4700V -8.6869nS 3.3000V 3.1400V 3.4700V -8.7879nS 3.3000V 3.1400V 3.4700V -8.8889nS 3.3000V 3.1400V 3.4700V -8.9899nS 3.3000V 3.1400V 3.4700V -9.0909nS 3.3000V 3.1400V 3.4700V -9.1919nS 3.3000V 3.1400V 3.4700V -9.2929nS 3.3000V 3.1400V 3.4700V -9.3939nS 3.3000V 3.1400V 3.4700V -9.4949nS 3.3000V 3.1400V 3.4700V -9.5960nS 3.3000V 3.1400V 3.4700V -9.6970nS 3.3000V 3.1400V 3.4700V -9.7980nS 3.3000V 3.1400V 3.4700V -9.8990nS 3.3000V 3.1400V 3.4700V -10.0000nS 3.3000V 3.1400V 3.4700V -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 0.4849uV 0.6538uV 0.4584uV -0.1010nS -91.8400nV 63.2160nV -25.7920nV -0.2020nS -2.6993uV -0.4530uV -0.2185uV -0.3030nS -0.1263uV -1.9171uV 9.8177uV -0.4040nS 2.2148uV 0.3884uV -0.7508mV -0.5051nS 17.9080uV 0.4320uV -54.9180mV -0.6061nS -0.9283mV 2.0154uV -38.8140mV -0.7071nS -36.0310mV 19.4020uV 0.5590V -0.8081nS -59.6090mV 49.7370uV 1.7463V -0.9091nS -7.5013mV -0.5918mV 2.5098V -1.0101nS 0.3035V -13.7970mV 2.7118V -1.1111nS 0.8765V -46.7140mV 2.7764V -1.2121nS 1.5353V -51.2590mV 2.8047V -1.3131nS 2.0287V -34.8250mV 2.8192V -1.4141nS 2.2720V 25.7290mV 2.8271V -1.5152nS 2.3732V 0.1849V 2.8315V -1.6162nS 2.4197V 0.4573V 2.8339V -1.7172nS 2.4473V 0.8065V 2.8353V -1.8182nS 2.4633V 1.1645V 2.8360V -1.9192nS 2.4738V 1.4818V 2.8364V -2.0202nS 2.4810V 1.7269V 2.8366V -2.1212nS 2.4853V 1.8846V 2.8368V -2.2222nS 2.4883V 1.9770V 2.8368V -2.3232nS 2.4902V 2.0335V 2.8369V -2.4242nS 2.4916V 2.0698V 2.8369V -2.5253nS 2.4924V 2.0942V 2.8369V -2.6263nS 2.4930V 2.1112V 2.8369V -2.7273nS 2.4934V 2.1231V 2.8370V -2.8283nS 2.4937V 2.1316V 2.8369V -2.9293nS 2.4938V 2.1374V 2.8370V -3.0303nS 2.4940V 2.1420V 2.8369V -3.1313nS 2.4940V 2.1455V 2.8370V -3.2323nS 2.4942V 2.1480V 2.8369V -3.3333nS 2.4941V 2.1499V 2.8370V -3.4343nS 2.4942V 2.1514V 2.8369V -3.5354nS 2.4942V 2.1525V 2.8370V -3.6364nS 2.4943V 2.1533V 2.8369V -3.7374nS 2.4942V 2.1539V 2.8370V -3.8384nS 2.4943V 2.1544V 2.8369V -3.9394nS 2.4942V 2.1548V 2.8370V -4.0404nS 2.4943V 2.1551V 2.8369V -4.1414nS 2.4942V 2.1553V 2.8370V -4.2424nS 2.4943V 2.1554V 2.8369V -4.3434nS 2.4942V 2.1556V 2.8370V -4.4444nS 2.4943V 2.1557V 2.8369V -4.5455nS 2.4942V 2.1557V 2.8370V -4.6465nS 2.4943V 2.1558V 2.8369V -4.7475nS 2.4942V 2.1558V 2.8370V -4.8485nS 2.4943V 2.1559V 2.8369V -4.9495nS 2.4942V 2.1559V 2.8370V -5.0505nS 2.4942V 2.1559V 2.8369V -5.1515nS 2.4943V 2.1560V 2.8369V -5.2525nS 2.4943V 2.1560V 2.8370V -5.3535nS 2.4943V 2.1560V 2.8369V -5.4545nS 2.4943V 2.1560V 2.8370V -5.5556nS 2.4943V 2.1560V 2.8369V -5.6566nS 2.4943V 2.1560V 2.8370V -5.7576nS 2.4943V 2.1560V 2.8370V -5.8586nS 2.4943V 2.1560V 2.8370V -5.9596nS 2.4943V 2.1560V 2.8370V -6.0606nS 2.4943V 2.1560V 2.8370V -6.1616nS 2.4943V 2.1560V 2.8370V -6.2626nS 2.4943V 2.1560V 2.8370V -6.3636nS 2.4943V 2.1560V 2.8370V -6.4646nS 2.4943V 2.1560V 2.8370V -6.5657nS 2.4943V 2.1560V 2.8370V -6.6667nS 2.4943V 2.1560V 2.8370V -6.7677nS 2.4943V 2.1560V 2.8370V -6.8687nS 2.4943V 2.1560V 2.8370V -6.9697nS 2.4943V 2.1560V 2.8370V -7.0707nS 2.4943V 2.1560V 2.8370V -7.1717nS 2.4943V 2.1560V 2.8370V -7.2727nS 2.4943V 2.1560V 2.8370V -7.3737nS 2.4943V 2.1560V 2.8370V -7.4747nS 2.4943V 2.1560V 2.8370V -7.5758nS 2.4943V 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1.1411uV -8.0808nS 6.6183uV 14.1310uV 1.9398uV -8.1818nS 4.3304uV 7.8499uV 7.3706uV -8.2828nS 0.9901uV 15.2460uV 4.3539uV -8.3838nS 7.4534uV 11.2570uV -1.5751uV -8.4848nS 6.0071uV 10.9100uV -4.0515uV -8.5859nS 3.9708uV 6.6233uV 6.1371uV -8.6869nS 0.8938uV 12.1060uV 5.2581uV -8.7879nS 7.0344uV 11.9130uV 1.0700uV -8.8889nS 5.6379uV 18.0050uV -3.9073uV -8.9899nS 2.9239uV 9.1095uV 0.1500uV -9.0909nS 2.8023uV 6.8319uV 7.0838uV -9.1919nS 8.4026uV 3.9617uV 5.4861uV -9.2929nS 4.3812uV 7.2141uV -1.7852uV -9.3939nS 2.8463uV -53.3950nV -0.4309uV -9.4949nS 0.5257uV 12.7920uV -1.2755uV -9.5960nS 6.2361uV 11.5200uV 6.5424uV -9.6970nS 8.1020uV 10.1450uV 2.3600uV -9.7980nS 11.5310uV 9.4795uV 0.8669uV -9.8990nS 9.9990uV 13.4000uV 1.3956uV -10.0000nS 9.1292uV 5.3100uV 7.4741uV -| -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 3.3000V 3.1400V 3.4700V -0.1010nS 3.3000V 3.1400V 3.4700V -0.2020nS 3.3000V 3.1400V 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0.7517V 0.9661V 0.6180V -6.2626nS 0.7516V 0.9661V 0.6180V -6.3636nS 0.7517V 0.9661V 0.6180V -6.4646nS 0.7517V 0.9661V 0.6180V -6.5657nS 0.7516V 0.9661V 0.6180V -6.6667nS 0.7516V 0.9661V 0.6180V -6.7677nS 0.7516V 0.9661V 0.6180V -6.8687nS 0.7516V 0.9661V 0.6180V -6.9697nS 0.7517V 0.9661V 0.6180V -7.0707nS 0.7516V 0.9661V 0.6180V -7.1717nS 0.7516V 0.9661V 0.6180V -7.2727nS 0.7516V 0.9661V 0.6180V -7.3737nS 0.7516V 0.9661V 0.6180V -7.4747nS 0.7516V 0.9661V 0.6180V -7.5758nS 0.7516V 0.9661V 0.6180V -7.6768nS 0.7516V 0.9661V 0.6180V -7.7778nS 0.7516V 0.9661V 0.6180V -7.8788nS 0.7516V 0.9661V 0.6180V -7.9798nS 0.7516V 0.9661V 0.6180V -8.0808nS 0.7516V 0.9661V 0.6180V -8.1818nS 0.7516V 0.9661V 0.6180V -8.2828nS 0.7516V 0.9661V 0.6180V -8.3838nS 0.7516V 0.9661V 0.6180V -8.4848nS 0.7516V 0.9661V 0.6180V -8.5859nS 0.7516V 0.9661V 0.6180V -8.6869nS 0.7516V 0.9661V 0.6180V -8.7879nS 0.7516V 0.9661V 0.6180V -8.8889nS 0.7516V 0.9661V 0.6180V -8.9899nS 0.7517V 0.9661V 0.6180V -9.0909nS 0.7516V 0.9661V 0.6180V -9.1919nS 0.7517V 0.9661V 0.6180V -9.2929nS 0.7516V 0.9661V 0.6180V -9.3939nS 0.7517V 0.9661V 0.6180V -9.4949nS 0.7516V 0.9661V 0.6180V -9.5960nS 0.7516V 0.9661V 0.6180V -9.6970nS 0.7516V 0.9661V 0.6180V -9.7980nS 0.7516V 0.9661V 0.6180V -9.8990nS 0.7516V 0.9661V 0.6180V -10.0000nS 0.7517V 0.9661V 0.6180V -| -| End [Model] lvt330s160aaaaaaaaou -|************************************************************************ -| End [Component] -[End] diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep deleted file mode 100644 index e5894f8..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep +++ /dev/null @@ -1,22 +0,0 @@ ----------------------------------------------------------------------- -Report for cell RAM2GS.TECH -Register bits: 119 of 877 (13.569%) -I/O cells: 63 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 10 100.0 - EFB 1 100.0 - FD1P3AX 30 100.0 - FD1P3AY 4 100.0 - FD1P3IX 3 100.0 - FD1S3AX 64 100.0 - FD1S3IX 14 100.0 - FD1S3JX 4 100.0 - GSR 1 100.0 - IB 25 100.0 - INV 3 100.0 - LUT4 236 100.0 - OB 30 100.0 - PFUMX 16 100.0 - TOTAL 449 diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn deleted file mode 100644 index 86c3161..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn +++ /dev/null @@ -1,86 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 17 06:21:07 2021 - - -Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf - -Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 191 Pages (128*191 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). -Initialized UFM Pages: 0 Page. - -Total CPU Time: 1 secs -Total REAL Time: 2 secs -Peak Memory Usage: 245 MB diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bit deleted file mode 100644 index cdb167c..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bit and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd deleted file mode 100644 index 20354b0..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad deleted file mode 100644 index 98c36e1..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad +++ /dev/null @@ -1,273 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-640HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.39 - -Sat Oct 09 01:19:20 2021 - -Pinout by Port Name: -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ -| CROW[0] | 10/3 | LVTTL33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVTTL33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVTTL33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVTTL33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVTTL33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVTTL33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVTTL33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVTTL33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVTTL33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVTTL33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVTTL33_OUT | PT11D | | | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 86/0 | LVTTL33_OUT | PT9C | | | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 87/0 | LVTTL33_OUT | PT9B | | | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 85/0 | LVTTL33_OUT | PT9D | | | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 83/0 | LVTTL33_OUT | PT10B | | | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 84/0 | LVTTL33_OUT | PT10A | | | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 78/0 | LVTTL33_OUT | PT11A | | | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 82/0 | LVTTL33_OUT | PT10C | | | DRIVE:4mA SLEW:SLOW | -| LED | 34/2 | LVTTL33_OUT | PB6C | | | DRIVE:16mA SLEW:SLOW | -| MAin[0] | 14/3 | LVTTL33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVTTL33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVTTL33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVTTL33_IN | PL7B | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVTTL33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVTTL33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVTTL33_IN | PL7C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVTTL33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVTTL33_IN | PL7D | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVTTL33_IN | PB6B | | | CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVTTL33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVTTL33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW | -| RA[10] | 64/1 | LVTTL33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | -| RA[11] | 59/1 | LVTTL33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW | -| RA[1] | 67/1 | LVTTL33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW | -| RA[2] | 69/1 | LVTTL33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | -| RA[3] | 71/1 | LVTTL33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW | -| RA[4] | 74/1 | LVTTL33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | -| RA[5] | 70/1 | LVTTL33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW | -| RA[6] | 68/1 | LVTTL33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | -| RA[7] | 75/1 | LVTTL33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | -| RA[8] | 65/1 | LVTTL33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RA[9] | 62/1 | LVTTL33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | -| RBA[0] | 58/1 | LVTTL33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVTTL33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | -| RCKE | 53/1 | LVTTL33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | -| RCLK | 63/1 | LVTTL33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVTTL33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | -| RDQML | 48/2 | LVTTL33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | -| RD[0] | 36/2 | LVTTL33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVTTL33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVTTL33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVTTL33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVTTL33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVTTL33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVTTL33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVTTL33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| nCCAS | 9/3 | LVTTL33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVTTL33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 15/3 | LVTTL33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVTTL33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW | -| nRCS | 57/1 | LVTTL33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW | -| nRRAS | 54/1 | LVTTL33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW | -| nRWE | 49/2 | LVTTL33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW | -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVTTL33_IN | PL2A | | | | -| 2/3 | Din[6] | LOCATED | LVTTL33_IN | PL2B | | | | -| 3/3 | Din[0] | LOCATED | LVTTL33_IN | PL2C | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3A | | | | -| 8/3 | PHI2 | LOCATED | LVTTL33_IN | PL3B | | | | -| 9/3 | nCCAS | LOCATED | LVTTL33_IN | PL3C | | | | -| 10/3 | CROW[0] | LOCATED | LVTTL33_IN | PL3D | | | | -| 12/3 | MAin[1] | LOCATED | LVTTL33_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVTTL33_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVTTL33_IN | PL5C | | | | -| 15/3 | nFWE | LOCATED | LVTTL33_IN | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVTTL33_IN | PL6A | | | | -| 17/3 | nCRAS | LOCATED | LVTTL33_IN | PL6B | | | | -| 18/3 | MAin[7] | LOCATED | LVTTL33_IN | PL6C | | | | -| 19/3 | MAin[5] | LOCATED | LVTTL33_IN | PL6D | | | | -| 20/3 | MAin[4] | LOCATED | LVTTL33_IN | PL7A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVTTL33_IN | PL7B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVTTL33_IN | PL7C | | | | -| 25/3 | MAin[8] | LOCATED | LVTTL33_IN | PL7D | | | | -| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | -| 28/2 | unused, PULL:DOWN | | | PB4B | | | | -| 29/2 | unused, PULL:DOWN | | | PB4C | | | | -| 30/2 | unused, PULL:DOWN | | | PB4D | | | | -| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVTTL33_IN | PB6B | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVTTL33_OUT | PB6C | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVTTL33_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVTTL33_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVTTL33_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVTTL33_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVTTL33_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVTTL33_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVTTL33_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVTTL33_BIDI | PB12D | | | | -| 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | RDQML | LOCATED | LVTTL33_OUT | PB14C | SN | | | -| 49/2 | nRWE | LOCATED | LVTTL33_OUT | PB14D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVTTL33_OUT | PR7D | | | | -| 52/1 | nRCAS | LOCATED | LVTTL33_OUT | PR7C | | | | -| 53/1 | RCKE | LOCATED | LVTTL33_OUT | PR7B | | | | -| 54/1 | nRRAS | LOCATED | LVTTL33_OUT | PR7A | | | | -| 57/1 | nRCS | LOCATED | LVTTL33_OUT | PR6D | | | | -| 58/1 | RBA[0] | LOCATED | LVTTL33_OUT | PR6C | | | | -| 59/1 | RA[11] | LOCATED | LVTTL33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVTTL33_OUT | PR6A | | | | -| 62/1 | RA[9] | LOCATED | LVTTL33_OUT | PR5D | PCLKC1_0 | | | -| 63/1 | RCLK | LOCATED | LVTTL33_IN | PR5C | PCLKT1_0 | | | -| 64/1 | RA[10] | LOCATED | LVTTL33_OUT | PR5B | | | | -| 65/1 | RA[8] | LOCATED | LVTTL33_OUT | PR5A | | | | -| 66/1 | RA[0] | LOCATED | LVTTL33_OUT | PR3D | | | | -| 67/1 | RA[1] | LOCATED | LVTTL33_OUT | PR3C | | | | -| 68/1 | RA[6] | LOCATED | LVTTL33_OUT | PR3B | | | | -| 69/1 | RA[2] | LOCATED | LVTTL33_OUT | PR3A | | | | -| 70/1 | RA[5] | LOCATED | LVTTL33_OUT | PR2D | | | | -| 71/1 | RA[3] | LOCATED | LVTTL33_OUT | PR2C | | | | -| 74/1 | RA[4] | LOCATED | LVTTL33_OUT | PR2B | | | | -| 75/1 | RA[7] | LOCATED | LVTTL33_OUT | PR2A | | | | -| 76/0 | Dout[0] | LOCATED | LVTTL33_OUT | PT11D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVTTL33_OUT | PT11A | | | | -| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVTTL33_OUT | PT10C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVTTL33_OUT | PT10B | | | | -| 84/0 | Dout[5] | LOCATED | LVTTL33_OUT | PT10A | | | | -| 85/0 | Dout[3] | LOCATED | LVTTL33_OUT | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVTTL33_OUT | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVTTL33_OUT | PT9B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVTTL33_IN | PT9A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[1] | LOCATED | LVTTL33_IN | PT6D | | | | -| 97/0 | Din[3] | LOCATED | LVTTL33_IN | PT6C | | | | -| 98/0 | Din[5] | LOCATED | LVTTL33_IN | PT6B | | | | -| 99/0 | Din[4] | LOCATED | LVTTL33_IN | PT6A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "62"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "63"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "15"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Sat Oct 09 01:19:22 2021 - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd deleted file mode 100644 index c0f7313..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd +++ /dev/null @@ -1,41 +0,0 @@ -[ActiveSupport PAR] -; Global primary clocks -GLOBAL_PRIMARY_USED = 4; -; Global primary clock #0 -GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; -GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; -GLOBAL_PRIMARY_0_LOADNUM = 52; -; Global primary clock #1 -GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; -GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_1_LOADNUM = 13; -; Global primary clock #2 -GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c; -GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_2_LOADNUM = 7; -; Global primary clock #3 -GLOBAL_PRIMARY_3_SIGNALNAME = nCCAS_c; -GLOBAL_PRIMARY_3_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_3_LOADNUM = 4; -; # of global secondary clocks -GLOBAL_SECONDARY_USED = 0; -; I/O Bank 0 Usage -BANK_0_USED = 13; -BANK_0_AVAIL = 19; -BANK_0_VCCIO = 3.3V; -BANK_0_VREF1 = NA; -; I/O Bank 1 Usage -BANK_1_USED = 20; -BANK_1_AVAIL = 20; -BANK_1_VCCIO = 3.3V; -BANK_1_VREF1 = NA; -; I/O Bank 2 Usage -BANK_2_USED = 12; -BANK_2_AVAIL = 20; -BANK_2_VCCIO = 3.3V; -BANK_2_VREF1 = NA; -; I/O Bank 3 Usage -BANK_3_USED = 18; -BANK_3_AVAIL = 20; -BANK_3_VCCIO = 3.3V; -BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.jed deleted file mode 100644 index 3343732..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.jed +++ /dev/null @@ -1,1431 +0,0 @@ -* -NOTE Diamond (64-bit) 3.12.0.240.2 JEDEC Compatible Fuse File.* -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* -NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Aug 17 06:21:07 2021* -NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd* -NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* -NOTE JEDEC FILE STATUS: Final Version 1.95* -NOTE PIN ASSIGNMENTS* -NOTE PINS RCLK : 63 : in* -NOTE PINS nFWE : 15 : in* -NOTE PINS nCRAS : 17 : in* -NOTE PINS nCCAS : 9 : in* -NOTE PINS Din[0] : 3 : in* -NOTE PINS Din[1] : 96 : in* -NOTE PINS Din[2] : 88 : in* -NOTE PINS Din[3] : 97 : in* -NOTE PINS Din[4] : 99 : in* -NOTE PINS Din[5] : 98 : in* -NOTE PINS Din[6] : 2 : in* -NOTE PINS Din[7] : 1 : in* -NOTE PINS CROW[0] : 10 : in* -NOTE PINS CROW[1] : 16 : in* -NOTE PINS MAin[0] : 14 : in* -NOTE PINS MAin[1] : 12 : in* -NOTE PINS MAin[2] : 13 : in* -NOTE PINS MAin[3] : 21 : in* -NOTE PINS MAin[4] : 20 : in* -NOTE PINS MAin[5] : 19 : in* -NOTE PINS MAin[6] : 24 : in* -NOTE PINS MAin[7] : 18 : in* -NOTE PINS MAin[8] : 25 : in* -NOTE PINS MAin[9] : 32 : in* -NOTE PINS PHI2 : 8 : in* -NOTE PINS RDQML : 48 : out* -NOTE PINS RDQMH : 51 : out* -NOTE PINS nRCAS : 52 : out* -NOTE PINS nRRAS : 54 : out* -NOTE PINS nRWE : 49 : out* -NOTE PINS RCKE : 53 : out* -NOTE PINS nRCS : 57 : out* -NOTE PINS RA[0] : 66 : out* -NOTE PINS RA[1] : 67 : out* -NOTE PINS RA[2] : 69 : out* -NOTE PINS RA[3] : 71 : out* -NOTE PINS RA[4] : 74 : out* -NOTE PINS RA[5] : 70 : out* -NOTE PINS RA[6] : 68 : out* -NOTE PINS RA[7] : 75 : out* -NOTE PINS RA[8] : 65 : out* -NOTE PINS RA[9] : 62 : out* -NOTE PINS RA[10] : 64 : out* -NOTE PINS RA[11] : 59 : out* -NOTE PINS RBA[0] : 58 : out* -NOTE PINS RBA[1] : 60 : out* -NOTE PINS LED : 34 : out* -NOTE PINS Dout[0] : 76 : out* -NOTE PINS Dout[1] : 86 : out* -NOTE PINS Dout[2] : 87 : out* -NOTE PINS Dout[3] : 85 : out* -NOTE PINS Dout[4] : 83 : out* -NOTE PINS Dout[5] : 84 : out* -NOTE PINS Dout[6] : 78 : out* -NOTE PINS Dout[7] : 82 : out* -NOTE PINS RD[0] : 36 : inout* -NOTE PINS RD[1] : 37 : inout* -NOTE PINS RD[2] : 38 : inout* -NOTE PINS RD[3] : 39 : inout* -NOTE PINS RD[4] : 40 : inout* -NOTE PINS RD[5] : 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp deleted file mode 100644 index aa483f5..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp +++ /dev/null @@ -1,402 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2GS' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr - RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use - rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX - O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/ - LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -Target Vendor: LATTICE -Target Device: LCMXO2-640HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2 -Mapped on: 10/09/21 01:19:14 - -Design Summary --------------- - - Number of registers: 119 out of 877 (14%) - PFU registers: 119 out of 640 (19%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 131 out of 320 (41%) - SLICEs as Logic/ROM: 131 out of 320 (41%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 255 out of 640 (40%) - Number used as logic LUTs: 235 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 5 - Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_20: 4 loads, 4 LSLICEs - - Page 1 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -Design Summary (cont) ---------------------- - Net RCLK_c_enable_29: 2 loads, 2 LSLICEs - Net RCLK_c_enable_25: 2 loads, 2 LSLICEs - Net InitReady: 1 loads, 1 LSLICEs - Net RCLK_c_enable_24: 2 loads, 2 LSLICEs - Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs - Net RCLK_c_enable_26: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs - Net Ready_N_280: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs - Number of LSRs: 8 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Net wb_rst: 1 loads, 0 LSLICEs - Net nRWE_N_210: 1 loads, 1 LSLICEs - Net C1Submitted_N_232: 2 loads, 2 LSLICEs - Net wb_adr_7__N_92: 2 loads, 2 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 36 loads - Net FS_10: 32 loads - Net FS_11: 32 loads - Net FS_9: 26 loads - Net FS_7: 25 loads - Net FS_8: 23 loads - Net FS_5: 21 loads - Net FS_6: 21 loads - Net FS_12: 20 loads - Net Ready: 18 loads - - - - - Number of warnings: 0 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - - No errors or warnings present. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVTTL33 | | - - Page 2 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[3] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[2] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RDQMH | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVTTL33 | | - - Page 3 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[3] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVTTL33 | | - - Page 4 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block i2 undriven or does not drive anything - clipped. -Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_151 was merged into signal PHI2_c -Signal nRWE_N_209 was merged into signal nRWE_N_210 -Signal RCLK_c_enable_22 was merged into signal InitReady -Signal n2557 was merged into signal nRowColSel_N_34 -Signal n4935 was merged into signal Ready -Signal n4933 was merged into signal nRowColSel_N_35 -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped. -Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped. -Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped. -Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped. -Block i4008 was optimized away. -Block nRWE_I_53_1_lut was optimized away. -Block InitReady_I_0_586_1_lut_rep_73 was optimized away. -Block i1683_1_lut was optimized away. -Block i1044_1_lut_rep_86 was optimized away. -Block i1684_1_lut_rep_84 was optimized away. -Block i1 was optimized away. - - - -Embedded Functional Block Connection Summary --------------------------------------------- - - Desired WISHBONE clock frequency: 50.0 MHz - Clock source: wb_clk - Reset source: wb_rst - Functions mode: - I2C #1 (Primary) Function: DISABLED - I2C #2 (Secondary) Function: DISABLED - SPI Function: DISABLED - Timer/Counter Function: DISABLED - Timer/Counter Mode: NO_WB - UFM Connection: DISABLED - PLL0 Connection: DISABLED - PLL1 Connection: DISABLED - I2C Function Summary: - -------------------- - - Page 5 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - None - SPI Function Summary: - -------------------- - None - Timer/Counter Function Summary: - ------------------------------ - None - UFM Function Summary: - -------------------- - UFM Utilization: General Purpose Flash Memory - Available General - Purpose Flash Memory: 191 Pages (191*128 Bits) - - EBR Blocks with Unique - Initialization Data: 0 - - WID EBR Instance - --- ------------ - - -ASIC Components ---------------- - -Instance Name: ufmefb - Type: EFB - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 37 MB - - - - - - - - - - - - - - - - - - - - - - - - - - Page 6 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights - reserved. diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mt deleted file mode 100644 index 2d70ad1..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mt +++ /dev/null @@ -1,9 +0,0 @@ --v -1 - - --gt - - --mapchkpnt 0 --sethld diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd deleted file mode 100644 index 20354b0..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd deleted file mode 100644 index 3bffa8c..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t deleted file mode 100644 index 6ff5632..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "RAM2GS_LCMXO2_640HC_impl1.log" --o "RAM2GS_LCMXO2_640HC_impl1.csv" --pr "RAM2GS_LCMXO2_640HC_impl1.prf" diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.pad deleted file mode 100644 index 98c36e1..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.pad +++ /dev/null @@ -1,273 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-640HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.39 - -Sat Oct 09 01:19:20 2021 - -Pinout by Port Name: -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ -| CROW[0] | 10/3 | LVTTL33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL | -| CROW[1] | 16/3 | LVTTL33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[0] | 3/3 | LVTTL33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 96/0 | LVTTL33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 88/0 | LVTTL33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 97/0 | LVTTL33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 99/0 | LVTTL33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 98/0 | LVTTL33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 2/3 | LVTTL33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 1/3 | LVTTL33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 76/0 | LVTTL33_OUT | PT11D | | | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 86/0 | LVTTL33_OUT | PT9C | | | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 87/0 | LVTTL33_OUT | PT9B | | | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 85/0 | LVTTL33_OUT | PT9D | | | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 83/0 | LVTTL33_OUT | PT10B | | | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 84/0 | LVTTL33_OUT | PT10A | | | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 78/0 | LVTTL33_OUT | PT11A | | | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 82/0 | LVTTL33_OUT | PT10C | | | DRIVE:4mA SLEW:SLOW | -| LED | 34/2 | LVTTL33_OUT | PB6C | | | DRIVE:16mA SLEW:SLOW | -| MAin[0] | 14/3 | LVTTL33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[1] | 12/3 | LVTTL33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[2] | 13/3 | LVTTL33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[3] | 21/3 | LVTTL33_IN | PL7B | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[4] | 20/3 | LVTTL33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[5] | 19/3 | LVTTL33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[6] | 24/3 | LVTTL33_IN | PL7C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[7] | 18/3 | LVTTL33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[8] | 25/3 | LVTTL33_IN | PL7D | | | CLAMP:ON HYSTERESIS:SMALL | -| MAin[9] | 32/2 | LVTTL33_IN | PB6B | | | CLAMP:ON HYSTERESIS:SMALL | -| PHI2 | 8/3 | LVTTL33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL | -| RA[0] | 66/1 | LVTTL33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW | -| RA[10] | 64/1 | LVTTL33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | -| RA[11] | 59/1 | LVTTL33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW | -| RA[1] | 67/1 | LVTTL33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW | -| RA[2] | 69/1 | LVTTL33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | -| RA[3] | 71/1 | LVTTL33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW | -| RA[4] | 74/1 | LVTTL33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | -| RA[5] | 70/1 | LVTTL33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW | -| RA[6] | 68/1 | LVTTL33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | -| RA[7] | 75/1 | LVTTL33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | -| RA[8] | 65/1 | LVTTL33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RA[9] | 62/1 | LVTTL33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW | -| RBA[0] | 58/1 | LVTTL33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 60/1 | LVTTL33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | -| RCKE | 53/1 | LVTTL33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | -| RCLK | 63/1 | LVTTL33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL | -| RDQMH | 51/1 | LVTTL33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | -| RDQML | 48/2 | LVTTL33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | -| RD[0] | 36/2 | LVTTL33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVTTL33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVTTL33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVTTL33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVTTL33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVTTL33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVTTL33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVTTL33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| nCCAS | 9/3 | LVTTL33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL | -| nCRAS | 17/3 | LVTTL33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL | -| nFWE | 15/3 | LVTTL33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL | -| nRCAS | 52/1 | LVTTL33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW | -| nRCS | 57/1 | LVTTL33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW | -| nRRAS | 54/1 | LVTTL33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW | -| nRWE | 49/2 | LVTTL33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW | -+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[7] | LOCATED | LVTTL33_IN | PL2A | | | | -| 2/3 | Din[6] | LOCATED | LVTTL33_IN | PL2B | | | | -| 3/3 | Din[0] | LOCATED | LVTTL33_IN | PL2C | PCLKT3_2 | | | -| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | -| 7/3 | unused, PULL:DOWN | | | PL3A | | | | -| 8/3 | PHI2 | LOCATED | LVTTL33_IN | PL3B | | | | -| 9/3 | nCCAS | LOCATED | LVTTL33_IN | PL3C | | | | -| 10/3 | CROW[0] | LOCATED | LVTTL33_IN | PL3D | | | | -| 12/3 | MAin[1] | LOCATED | LVTTL33_IN | PL5A | PCLKT3_1 | | | -| 13/3 | MAin[2] | LOCATED | LVTTL33_IN | PL5B | PCLKC3_1 | | | -| 14/3 | MAin[0] | LOCATED | LVTTL33_IN | PL5C | | | | -| 15/3 | nFWE | LOCATED | LVTTL33_IN | PL5D | | | | -| 16/3 | CROW[1] | LOCATED | LVTTL33_IN | PL6A | | | | -| 17/3 | nCRAS | LOCATED | LVTTL33_IN | PL6B | | | | -| 18/3 | MAin[7] | LOCATED | LVTTL33_IN | PL6C | | | | -| 19/3 | MAin[5] | LOCATED | LVTTL33_IN | PL6D | | | | -| 20/3 | MAin[4] | LOCATED | LVTTL33_IN | PL7A | PCLKT3_0 | | | -| 21/3 | MAin[3] | LOCATED | LVTTL33_IN | PL7B | PCLKC3_0 | | | -| 24/3 | MAin[6] | LOCATED | LVTTL33_IN | PL7C | | | | -| 25/3 | MAin[8] | LOCATED | LVTTL33_IN | PL7D | | | | -| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | -| 28/2 | unused, PULL:DOWN | | | PB4B | | | | -| 29/2 | unused, PULL:DOWN | | | PB4C | | | | -| 30/2 | unused, PULL:DOWN | | | PB4D | | | | -| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | -| 32/2 | MAin[9] | LOCATED | LVTTL33_IN | PB6B | SO/SPISO | | | -| 34/2 | LED | LOCATED | LVTTL33_OUT | PB6C | PCLKT2_0 | | | -| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVTTL33_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVTTL33_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVTTL33_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVTTL33_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVTTL33_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVTTL33_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVTTL33_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVTTL33_BIDI | PB12D | | | | -| 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | RDQML | LOCATED | LVTTL33_OUT | PB14C | SN | | | -| 49/2 | nRWE | LOCATED | LVTTL33_OUT | PB14D | SI/SISPI | | | -| 51/1 | RDQMH | LOCATED | LVTTL33_OUT | PR7D | | | | -| 52/1 | nRCAS | LOCATED | LVTTL33_OUT | PR7C | | | | -| 53/1 | RCKE | LOCATED | LVTTL33_OUT | PR7B | | | | -| 54/1 | nRRAS | LOCATED | LVTTL33_OUT | PR7A | | | | -| 57/1 | nRCS | LOCATED | LVTTL33_OUT | PR6D | | | | -| 58/1 | RBA[0] | LOCATED | LVTTL33_OUT | PR6C | | | | -| 59/1 | RA[11] | LOCATED | LVTTL33_OUT | PR6B | | | | -| 60/1 | RBA[1] | LOCATED | LVTTL33_OUT | PR6A | | | | -| 62/1 | RA[9] | LOCATED | LVTTL33_OUT | PR5D | PCLKC1_0 | | | -| 63/1 | RCLK | LOCATED | LVTTL33_IN | PR5C | PCLKT1_0 | | | -| 64/1 | RA[10] | LOCATED | LVTTL33_OUT | PR5B | | | | -| 65/1 | RA[8] | LOCATED | LVTTL33_OUT | PR5A | | | | -| 66/1 | RA[0] | LOCATED | LVTTL33_OUT | PR3D | | | | -| 67/1 | RA[1] | LOCATED | LVTTL33_OUT | PR3C | | | | -| 68/1 | RA[6] | LOCATED | LVTTL33_OUT | PR3B | | | | -| 69/1 | RA[2] | LOCATED | LVTTL33_OUT | PR3A | | | | -| 70/1 | RA[5] | LOCATED | LVTTL33_OUT | PR2D | | | | -| 71/1 | RA[3] | LOCATED | LVTTL33_OUT | PR2C | | | | -| 74/1 | RA[4] | LOCATED | LVTTL33_OUT | PR2B | | | | -| 75/1 | RA[7] | LOCATED | LVTTL33_OUT | PR2A | | | | -| 76/0 | Dout[0] | LOCATED | LVTTL33_OUT | PT11D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | -| 78/0 | Dout[6] | LOCATED | LVTTL33_OUT | PT11A | | | | -| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | Dout[7] | LOCATED | LVTTL33_OUT | PT10C | JTAGENB | | | -| 83/0 | Dout[4] | LOCATED | LVTTL33_OUT | PT10B | | | | -| 84/0 | Dout[5] | LOCATED | LVTTL33_OUT | PT10A | | | | -| 85/0 | Dout[3] | LOCATED | LVTTL33_OUT | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Dout[1] | LOCATED | LVTTL33_OUT | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Dout[2] | LOCATED | LVTTL33_OUT | PT9B | PCLKC0_1 | | | -| 88/0 | Din[2] | LOCATED | LVTTL33_IN | PT9A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[1] | LOCATED | LVTTL33_IN | PT6D | | | | -| 97/0 | Din[3] | LOCATED | LVTTL33_IN | PT6C | | | | -| 98/0 | Din[5] | LOCATED | LVTTL33_IN | PT6B | | | | -| 99/0 | Din[4] | LOCATED | LVTTL33_IN | PT6A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "10"; -LOCATE COMP "CROW[1]" SITE "16"; -LOCATE COMP "Din[0]" SITE "3"; -LOCATE COMP "Din[1]" SITE "96"; -LOCATE COMP "Din[2]" SITE "88"; -LOCATE COMP "Din[3]" SITE "97"; -LOCATE COMP "Din[4]" SITE "99"; -LOCATE COMP "Din[5]" SITE "98"; -LOCATE COMP "Din[6]" SITE "2"; -LOCATE COMP "Din[7]" SITE "1"; -LOCATE COMP "Dout[0]" SITE "76"; -LOCATE COMP "Dout[1]" SITE "86"; -LOCATE COMP "Dout[2]" SITE "87"; -LOCATE COMP "Dout[3]" SITE "85"; -LOCATE COMP "Dout[4]" SITE "83"; -LOCATE COMP "Dout[5]" SITE "84"; -LOCATE COMP "Dout[6]" SITE "78"; -LOCATE COMP "Dout[7]" SITE "82"; -LOCATE COMP "LED" SITE "34"; -LOCATE COMP "MAin[0]" SITE "14"; -LOCATE COMP "MAin[1]" SITE "12"; -LOCATE COMP "MAin[2]" SITE "13"; -LOCATE COMP "MAin[3]" SITE "21"; -LOCATE COMP "MAin[4]" SITE "20"; -LOCATE COMP "MAin[5]" SITE "19"; -LOCATE COMP "MAin[6]" SITE "24"; -LOCATE COMP "MAin[7]" SITE "18"; -LOCATE COMP "MAin[8]" SITE "25"; -LOCATE COMP "MAin[9]" SITE "32"; -LOCATE COMP "PHI2" SITE "8"; -LOCATE COMP "RA[0]" SITE "66"; -LOCATE COMP "RA[10]" SITE "64"; -LOCATE COMP "RA[11]" SITE "59"; -LOCATE COMP "RA[1]" SITE "67"; -LOCATE COMP "RA[2]" SITE "69"; -LOCATE COMP "RA[3]" SITE "71"; -LOCATE COMP "RA[4]" SITE "74"; -LOCATE COMP "RA[5]" SITE "70"; -LOCATE COMP "RA[6]" SITE "68"; -LOCATE COMP "RA[7]" SITE "75"; -LOCATE COMP "RA[8]" SITE "65"; -LOCATE COMP "RA[9]" SITE "62"; -LOCATE COMP "RBA[0]" SITE "58"; -LOCATE COMP "RBA[1]" SITE "60"; -LOCATE COMP "RCKE" SITE "53"; -LOCATE COMP "RCLK" SITE "63"; -LOCATE COMP "RDQMH" SITE "51"; -LOCATE COMP "RDQML" SITE "48"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "nCCAS" SITE "9"; -LOCATE COMP "nCRAS" SITE "17"; -LOCATE COMP "nFWE" SITE "15"; -LOCATE COMP "nRCAS" SITE "52"; -LOCATE COMP "nRCS" SITE "57"; -LOCATE COMP "nRRAS" SITE "54"; -LOCATE COMP "nRWE" SITE "49"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Sat Oct 09 01:19:22 2021 - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.prf deleted file mode 100644 index a5d46c6..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.prf +++ /dev/null @@ -1,158 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "62" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; -PERIOD NET "PHI2_c" 350.000000 ns ; -USE PRIMARY NET "RCLK_c" ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -USE PRIMARY NET "PHI2_c" ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -USE PRIMARY NET "nCRAS_c" ; -PERIOD NET "RCLK_c" 16.000000 ns ; -USE PRIMARY NET "nCCAS_c" ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -COMMERCIAL ; diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b deleted file mode 100644 index 2579ff8..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b +++ /dev/null @@ -1,5 +0,0 @@ - - --g RamCfg:Reset - --path "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC" diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 deleted file mode 100644 index e130e52..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 +++ /dev/null @@ -1,2547 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:15 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 121 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i5 (from PHI2_c +) - Destination: FF Data in CmdEnable_541 (to PHI2_c -) - - Delay: 13.035ns (30.0% logic, 70.0% route), 8 logic levels. - - Constraint Details: - - 13.035ns physical path delay SLICE_111 to SLICE_19 meets - 175.000ns delay constraint less - 0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_111.CLK to SLICE_111.Q1 SLICE_111 (from PHI2_c) -ROUTE 1 e 1.234 SLICE_111.Q1 to SLICE_158.B0 Bank_5 -CTOF_DEL --- 0.495 SLICE_158.B0 to SLICE_158.F0 SLICE_158 -ROUTE 1 e 1.234 SLICE_158.F0 to SLICE_139.B0 n4610 -CTOF_DEL --- 0.495 SLICE_139.B0 to SLICE_139.F0 SLICE_139 -ROUTE 2 e 1.234 SLICE_139.F0 to SLICE_114.B1 n4628 -CTOF_DEL --- 0.495 SLICE_114.B1 to SLICE_114.F1 SLICE_114 -ROUTE 4 e 1.234 SLICE_114.F1 to SLICE_116.B1 n2384 -CTOF_DEL --- 0.495 SLICE_116.B1 to SLICE_116.F1 SLICE_116 -ROUTE 2 e 0.480 SLICE_116.F1 to SLICE_116.D0 n4888 -CTOF_DEL --- 0.495 SLICE_116.D0 to SLICE_116.F0 SLICE_116 -ROUTE 1 e 1.234 SLICE_116.F0 to SLICE_19.B1 n4624 -CTOF_DEL --- 0.495 SLICE_19.B1 to SLICE_19.F1 SLICE_19 -ROUTE 4 e 1.234 SLICE_19.F1 to SLICE_130.C0 C1Submitted_N_232 -CTOF_DEL --- 0.495 SLICE_130.C0 to SLICE_130.F0 SLICE_130 -ROUTE 1 e 1.234 SLICE_130.F0 to SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c) - -------- - 13.035 (30.0% logic, 70.0% route), 8 logic levels. - -Report: 26.684ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 347.500ns - The internal maximum frequency of the following component is 400.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK SLICE_122 - - Delay: 2.500ns -- based on Minimum Pulse Width - -Report: 2.500ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 347.500ns - The internal maximum frequency of the following component is 400.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK SLICE_25 - - Delay: 2.500ns -- based on Minimum Pulse Width - -Report: 2.500ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 1409 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.077ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i8 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 13.757ns (33.7% logic, 66.3% route), 9 logic levels. - - Constraint Details: - - 13.757ns physical path delay SLICE_5 to SLICE_70 meets - 16.000ns delay constraint less - 0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_5.CLK to SLICE_5.Q1 SLICE_5 (from RCLK_c) -ROUTE 23 e 1.234 SLICE_5.Q1 to SLICE_98.B1 FS_8 -CTOF_DEL --- 0.495 SLICE_98.B1 to SLICE_98.F1 SLICE_98 -ROUTE 4 e 1.234 SLICE_98.F1 to SLICE_93.B1 n4924 -CTOF_DEL --- 0.495 SLICE_93.B1 to SLICE_93.F1 SLICE_93 -ROUTE 1 e 1.234 SLICE_93.F1 to SLICE_133.D0 n98 -CTOF_DEL --- 0.495 SLICE_133.D0 to SLICE_133.F0 SLICE_133 -ROUTE 2 e 0.480 SLICE_133.F0 to SLICE_133.B1 n2199 -CTOF_DEL --- 0.495 SLICE_133.B1 to SLICE_133.F1 SLICE_133 -ROUTE 1 e 1.234 SLICE_133.F1 to *9/SLICE_84.C1 n53 -CTOOFX_DEL --- 0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84 -ROUTE 1 e 1.234 *SLICE_84.OFX0 to SLICE_148.C1 n14_adj_3 -CTOF_DEL --- 0.495 SLICE_148.C1 to SLICE_148.F1 SLICE_148 -ROUTE 2 e 1.234 SLICE_148.F1 to SLICE_135.C0 n12_adj_8 -CTOF_DEL --- 0.495 SLICE_135.C0 to SLICE_135.F0 SLICE_135 -ROUTE 2 e 1.234 SLICE_135.F0 to SLICE_70.A1 n14_adj_7 -CTOF_DEL --- 0.495 SLICE_70.A1 to SLICE_70.F1 SLICE_70 -ROUTE 1 e 0.001 SLICE_70.F1 to SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 13.757 (33.7% logic, 66.3% route), 9 logic levels. - -Report: 13.923ns is the minimum period for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_536 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_54 and - 5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets - 12.500ns offset RCLK to RA[10] by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_54.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_54 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_54.CLK to SLICE_54.Q0 SLICE_54 (from RCLK_c) -ROUTE 1 e 1.234 SLICE_54.Q0 to 64.PADDO n1975 -DOPAD_DEL --- 4.105 64.PADDO to 64.PAD RA[10] - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[9] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_151.C0 nRowColSel -CTOF_DEL --- 0.495 SLICE_151.C0 to SLICE_151.F0 SLICE_151 -ROUTE 1 e 1.234 SLICE_151.F0 to 62.PADDO RA_c_9 -DOPAD_DEL --- 4.105 62.PADDO to 62.PAD RA[9] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[8] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_163.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_163.C1 to SLICE_163.F1 SLICE_163 -ROUTE 1 e 1.234 SLICE_163.F1 to 65.PADDO RA_c_8 -DOPAD_DEL --- 4.105 65.PADDO to 65.PAD RA[8] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[7] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_155.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_155.C1 to SLICE_155.F1 SLICE_155 -ROUTE 1 e 1.234 SLICE_155.F1 to 75.PADDO RA_c_7 -DOPAD_DEL --- 4.105 75.PADDO to 75.PAD RA[7] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[6] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_163.C0 nRowColSel -CTOF_DEL --- 0.495 SLICE_163.C0 to SLICE_163.F0 SLICE_163 -ROUTE 1 e 1.234 SLICE_163.F0 to 68.PADDO RA_c_6 -DOPAD_DEL --- 4.105 68.PADDO to 68.PAD RA[6] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[5] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_157.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_157.C1 to SLICE_157.F1 SLICE_157 -ROUTE 1 e 1.234 SLICE_157.F1 to 70.PADDO RA_c_5 -DOPAD_DEL --- 4.105 70.PADDO to 70.PAD RA[5] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[4] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_158.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_158.C1 to SLICE_158.F1 SLICE_158 -ROUTE 1 e 1.234 SLICE_158.F1 to 74.PADDO RA_c_4 -DOPAD_DEL --- 4.105 74.PADDO to 74.PAD RA[4] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[3] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_162.C0 nRowColSel -CTOF_DEL --- 0.495 SLICE_162.C0 to SLICE_162.F0 SLICE_162 -ROUTE 1 e 1.234 SLICE_162.F0 to 71.PADDO RA_c_3 -DOPAD_DEL --- 4.105 71.PADDO to 71.PAD RA[3] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[2] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_161.C0 nRowColSel -CTOF_DEL --- 0.495 SLICE_161.C0 to SLICE_161.F0 SLICE_161 -ROUTE 1 e 1.234 SLICE_161.F0 to 69.PADDO RA_c_2 -DOPAD_DEL --- 4.105 69.PADDO to 69.PAD RA[2] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[1] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_162.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_162.C1 to SLICE_162.F1 SLICE_162 -ROUTE 1 e 1.234 SLICE_162.F1 to 67.PADDO RA_c_1 -DOPAD_DEL --- 4.105 67.PADDO to 67.PAD RA[1] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets - 12.500ns offset RCLK to RA[0] by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_159.C1 nRowColSel -CTOF_DEL --- 0.495 SLICE_159.C1 to SLICE_159.F1 SLICE_159 -ROUTE 1 e 1.234 SLICE_159.F1 to 66.PADDO RA_c_0 -DOPAD_DEL --- 4.105 66.PADDO to 66.PAD RA[0] - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_532 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_59 and - 5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets - 12.500ns offset RCLK to nRCS by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_59: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_59.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_59 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_59.CLK to SLICE_59.Q0 SLICE_59 (from RCLK_c) -ROUTE 1 e 1.234 SLICE_59.Q0 to 57.PADDO nRCS_c -DOPAD_DEL --- 4.105 57.PADDO to 57.PAD nRCS - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_531 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_35 and - 5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets - 12.500ns offset RCLK to RCKE by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_35: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_35.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_35 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_35.CLK to SLICE_35.Q0 SLICE_35 (from RCLK_c) -ROUTE 4 e 1.234 SLICE_35.Q0 to 53.PADDO RCKE_c -DOPAD_DEL --- 4.105 53.PADDO to 53.PAD RCKE - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_535 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_62 and - 5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets - 12.500ns offset RCLK to nRWE by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_62: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_62.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_62 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_62.CLK to SLICE_62.Q0 SLICE_62 (from RCLK_c) -ROUTE 1 e 1.234 SLICE_62.Q0 to 49.PADDO nRWE_c -DOPAD_DEL --- 4.105 49.PADDO to 49.PAD nRWE - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_533 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_60 and - 5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets - 12.500ns offset RCLK to nRRAS by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_60.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_60 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 e 1.234 SLICE_60.Q0 to 54.PADDO nRRAS_c -DOPAD_DEL --- 4.105 54.PADDO to 54.PAD nRRAS - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.343ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_534 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_57 and - 5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets - 12.500ns offset RCLK to nRCAS by 4.343ns - - Physical Path Details: - - Clock path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_57.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_57 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_57.CLK to SLICE_57.Q0 SLICE_57 (from RCLK_c) -ROUTE 1 e 1.234 SLICE_57.Q0 to 52.PADDO nRCAS_c -DOPAD_DEL --- 4.105 52.PADDO to 52.PAD nRCAS - -------- - 5.791 (78.7% logic, 21.3% route), 2 logic levels. - -Report: 8.157ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets - 12.500ns offset RCLK to RDQMH by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_151.B1 nRowColSel -CTOF_DEL --- 0.495 SLICE_151.B1 to SLICE_151.F1 SLICE_151 -ROUTE 1 e 1.234 SLICE_151.F1 to 51.PADDO RDQMH_c -DOPAD_DEL --- 4.105 51.PADDO to 51.PAD RDQMH - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.614ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. - - Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. - - Constraint Details: - 2.366ns delay RCLK to SLICE_63 and - 7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets - 12.500ns offset RCLK to RDQML by 2.614ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.366 (47.8% logic, 52.2% route), 1 logic levels. - - Data path SLICE_63 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_161.B1 nRowColSel -CTOF_DEL --- 0.495 SLICE_161.B1 to SLICE_161.F1 SLICE_161 -ROUTE 1 e 1.234 SLICE_161.F1 to 48.PADDO RDQML_c -DOPAD_DEL --- 4.105 48.PADDO to 48.PAD RDQML - -------- - 7.520 (67.2% logic, 32.8% route), 3 logic levels. - -Report: 9.886ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.684 ns| 8 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 13.923 ns| 9 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 5 clocks: - -Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 - No transfer within this clock domain is found - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: wb_clk Source: SLICE_73.Q0 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 - - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:15 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 121 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.447ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_542 (from PHI2_c -) - Destination: FF Data in C1Submitted_542 (to PHI2_c -) - - Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. - - Constraint Details: - - 0.434ns physical path delay SLICE_15 to SLICE_15 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.D0 C1Submitted -CTOF_DEL --- 0.101 SLICE_15.D0 to SLICE_15.F0 SLICE_15 -ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n2549 (to PHI2_c) - -------- - 0.434 (53.9% logic, 46.1% route), 2 logic levels. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 1409 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.351ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i2 (from RCLK_c +) - Destination: FF Data in IS_FSM__i3 (to RCLK_c +) - - Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. - - Constraint Details: - - 0.332ns physical path delay SLICE_118 to SLICE_118 meets - -0.019ns M_HLD and - 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns - - Physical Path Details: - - Data path SLICE_118 to SLICE_118: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_118.CLK to SLICE_118.Q0 SLICE_118 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_118.Q0 to SLICE_118.M1 n1197 (to RCLK_c) - -------- - 0.332 (40.1% logic, 59.9% route), 1 logic levels. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_536 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_54 and - 2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets - 0.000ns hold offset RCLK to RA[10] by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_54.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_54 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_54.CLK to SLICE_54.Q0 SLICE_54 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_54.Q0 to 64.PADDO n1975 -DOPAD_DEL --- 1.673 64.PADDO to 64.PAD RA[10] - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[9] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_151.C0 nRowColSel -CTOF_DEL --- 0.101 SLICE_151.C0 to SLICE_151.F0 SLICE_151 -ROUTE 1 e 0.515 SLICE_151.F0 to 62.PADDO RA_c_9 -DOPAD_DEL --- 1.673 62.PADDO to 62.PAD RA[9] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[8] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_163.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_163.C1 to SLICE_163.F1 SLICE_163 -ROUTE 1 e 0.515 SLICE_163.F1 to 65.PADDO RA_c_8 -DOPAD_DEL --- 1.673 65.PADDO to 65.PAD RA[8] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[7] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_155.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_155.C1 to SLICE_155.F1 SLICE_155 -ROUTE 1 e 0.515 SLICE_155.F1 to 75.PADDO RA_c_7 -DOPAD_DEL --- 1.673 75.PADDO to 75.PAD RA[7] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[6] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_163.C0 nRowColSel -CTOF_DEL --- 0.101 SLICE_163.C0 to SLICE_163.F0 SLICE_163 -ROUTE 1 e 0.515 SLICE_163.F0 to 68.PADDO RA_c_6 -DOPAD_DEL --- 1.673 68.PADDO to 68.PAD RA[6] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[5] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_157.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_157.C1 to SLICE_157.F1 SLICE_157 -ROUTE 1 e 0.515 SLICE_157.F1 to 70.PADDO RA_c_5 -DOPAD_DEL --- 1.673 70.PADDO to 70.PAD RA[5] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[4] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_158.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_158.C1 to SLICE_158.F1 SLICE_158 -ROUTE 1 e 0.515 SLICE_158.F1 to 74.PADDO RA_c_4 -DOPAD_DEL --- 1.673 74.PADDO to 74.PAD RA[4] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[3] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_162.C0 nRowColSel -CTOF_DEL --- 0.101 SLICE_162.C0 to SLICE_162.F0 SLICE_162 -ROUTE 1 e 0.515 SLICE_162.F0 to 71.PADDO RA_c_3 -DOPAD_DEL --- 1.673 71.PADDO to 71.PAD RA[3] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[2] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_161.C0 nRowColSel -CTOF_DEL --- 0.101 SLICE_161.C0 to SLICE_161.F0 SLICE_161 -ROUTE 1 e 0.515 SLICE_161.F0 to 69.PADDO RA_c_2 -DOPAD_DEL --- 1.673 69.PADDO to 69.PAD RA[2] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[1] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_162.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_162.C1 to SLICE_162.F1 SLICE_162 -ROUTE 1 e 0.515 SLICE_162.F1 to 67.PADDO RA_c_1 -DOPAD_DEL --- 1.673 67.PADDO to 67.PAD RA[1] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RA[0] by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_159.C1 nRowColSel -CTOF_DEL --- 0.101 SLICE_159.C1 to SLICE_159.F1 SLICE_159 -ROUTE 1 e 0.515 SLICE_159.F1 to 66.PADDO RA_c_0 -DOPAD_DEL --- 1.673 66.PADDO to 66.PAD RA[0] - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_532 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_59 and - 2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets - 0.000ns hold offset RCLK to nRCS by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_59: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_59.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_59 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_59.CLK to SLICE_59.Q0 SLICE_59 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_59.Q0 to 57.PADDO nRCS_c -DOPAD_DEL --- 1.673 57.PADDO to 57.PAD nRCS - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_531 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_35 and - 2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets - 0.000ns hold offset RCLK to RCKE by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_35: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_35.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_35 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_35.CLK to SLICE_35.Q0 SLICE_35 (from RCLK_c) -ROUTE 4 e 0.515 SLICE_35.Q0 to 53.PADDO RCKE_c -DOPAD_DEL --- 1.673 53.PADDO to 53.PAD RCKE - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_535 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_62 and - 2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets - 0.000ns hold offset RCLK to nRWE by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_62: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_62.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_62 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_62.CLK to SLICE_62.Q0 SLICE_62 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_62.Q0 to 49.PADDO nRWE_c -DOPAD_DEL --- 1.673 49.PADDO to 49.PAD nRWE - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_533 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_60 and - 2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets - 0.000ns hold offset RCLK to nRRAS by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_60.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_60 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_60.Q0 to 54.PADDO nRRAS_c -DOPAD_DEL --- 1.673 54.PADDO to 54.PAD nRRAS - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_534 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_57 and - 2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets - 0.000ns hold offset RCLK to nRCAS by 3.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_57.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_57 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_57.CLK to SLICE_57.Q0 SLICE_57 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_57.Q0 to 52.PADDO nRCAS_c -DOPAD_DEL --- 1.673 52.PADDO to 52.PAD nRCAS - -------- - 2.321 (77.8% logic, 22.2% route), 2 logic levels. - -Report: 3.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RDQMH by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_151.B1 nRowColSel -CTOF_DEL --- 0.101 SLICE_151.B1 to SLICE_151.F1 SLICE_151 -ROUTE 1 e 0.515 SLICE_151.F1 to 51.PADDO RDQMH_c -DOPAD_DEL --- 1.673 51.PADDO to 51.PAD RDQMH - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.900ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. - - Constraint Details: - 0.963ns delay RCLK to SLICE_63 and - 2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets - 0.000ns hold offset RCLK to RDQML by 3.900ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.963 (46.5% logic, 53.5% route), 1 logic levels. - - Data path SLICE_63 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_161.B1 nRowColSel -CTOF_DEL --- 0.101 SLICE_161.B1 to SLICE_161.F1 SLICE_161 -ROUTE 1 e 0.515 SLICE_161.F1 to 48.PADDO RDQML_c -DOPAD_DEL --- 1.673 48.PADDO to 48.PAD RDQML - -------- - 2.937 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 3.900ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 5 clocks: - -Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 - No transfer within this clock domain is found - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: wb_clk Source: SLICE_73.Q0 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 - - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.twr deleted file mode 100644 index 1af0820..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.twr +++ /dev/null @@ -1,4466 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:23 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 121 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdLEDEN_545 (to PHI2_c -) - - Delay: 12.593ns (31.1% logic, 68.9% route), 8 logic levels. - - Constraint Details: - - 12.593ns physical path delay SLICE_151 to SLICE_20 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns - - Physical Path Details: - - Data path SLICE_151 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c) -ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6 -CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.593 (31.1% logic, 68.9% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_151: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 12.593ns (31.1% logic, 68.9% route), 8 logic levels. - - Constraint Details: - - 12.593ns physical path delay SLICE_151 to SLICE_24 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns - - Physical Path Details: - - Data path SLICE_151 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c) -ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6 -CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.593 (31.1% logic, 68.9% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_151: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in CmdLEDEN_545 (to PHI2_c -) - - Delay: 12.319ns (31.8% logic, 68.2% route), 8 logic levels. - - Constraint Details: - - 12.319ns physical path delay SLICE_111 to SLICE_20 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c) -ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4 -CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.319 (31.8% logic, 68.2% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_111: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 12.319ns (31.8% logic, 68.2% route), 8 logic levels. - - Constraint Details: - - 12.319ns physical path delay SLICE_111 to SLICE_24 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c) -ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4 -CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.319 (31.8% logic, 68.2% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_111: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i5 (from PHI2_c +) - Destination: FF Data in CmdLEDEN_545 (to PHI2_c -) - - Delay: 12.282ns (31.9% logic, 68.1% route), 8 logic levels. - - Constraint Details: - - 12.282ns physical path delay SLICE_111 to SLICE_20 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_111 (from PHI2_c) -ROUTE 1 0.967 R2C8C.Q1 to R2C8B.A0 Bank_5 -CTOF_DEL --- 0.495 R2C8B.A0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.282 (31.9% logic, 68.1% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_111: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i5 (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 12.282ns (31.9% logic, 68.1% route), 8 logic levels. - - Constraint Details: - - 12.282ns physical path delay SLICE_111 to SLICE_24 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_111 (from PHI2_c) -ROUTE 1 0.967 R2C8C.Q1 to R2C8B.A0 Bank_5 -CTOF_DEL --- 0.495 R2C8B.A0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 12.282 (31.9% logic, 68.1% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_111: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdEnable_541 (to PHI2_c -) - - Delay: 11.357ns (34.5% logic, 65.5% route), 8 logic levels. - - Constraint Details: - - 11.357ns physical path delay SLICE_151 to SLICE_19 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns - - Physical Path Details: - - Data path SLICE_151 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q0 SLICE_151 (from PHI2_c) -ROUTE 1 1.278 R5C9B.Q0 to R2C8B.C0 Bank_6 -CTOF_DEL --- 0.495 R2C8B.C0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.756 R2C9D.F1 to R2C9B.C1 n2384 -CTOF_DEL --- 0.495 R2C9B.C1 to R2C9B.F1 SLICE_116 -ROUTE 2 0.445 R2C9B.F1 to R2C9B.C0 n4888 -CTOF_DEL --- 0.495 R2C9B.C0 to R2C9B.F0 SLICE_116 -ROUTE 1 0.645 R2C9B.F0 to R3C9A.D1 n4624 -CTOF_DEL --- 0.495 R3C9A.D1 to R3C9A.F1 SLICE_19 -ROUTE 4 1.042 R3C9A.F1 to R3C9D.B0 C1Submitted_N_232 -CTOF_DEL --- 0.495 R3C9D.B0 to R3C9D.F0 SLICE_130 -ROUTE 1 0.653 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c) - -------- - 11.357 (34.5% logic, 65.5% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_151: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C9A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdLEDEN_545 (to PHI2_c -) - - Delay: 11.183ns (35.0% logic, 65.0% route), 8 logic levels. - - Constraint Details: - - 11.183ns physical path delay SLICE_151 to SLICE_20 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns - - Physical Path Details: - - Data path SLICE_151 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_151 (from PHI2_c) -ROUTE 1 0.967 R5C9B.Q1 to R5C9D.A1 Bank_7 -CTOF_DEL --- 0.495 R5C9D.A1 to R5C9D.F1 SLICE_139 -ROUTE 1 0.436 R5C9D.F1 to R5C9D.C0 n4574 -CTOF_DEL --- 0.495 R5C9D.C0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 11.183 (35.0% logic, 65.0% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_151: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 11.183ns (35.0% logic, 65.0% route), 8 logic levels. - - Constraint Details: - - 11.183ns physical path delay SLICE_151 to SLICE_24 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns - - Physical Path Details: - - Data path SLICE_151 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_151 (from PHI2_c) -ROUTE 1 0.967 R5C9B.Q1 to R5C9D.A1 Bank_7 -CTOF_DEL --- 0.495 R5C9D.A1 to R5C9D.F1 SLICE_139 -ROUTE 1 0.436 R5C9D.F1 to R5C9D.C0 n4574 -CTOF_DEL --- 0.495 R5C9D.C0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.788 R2C9D.F1 to R3C9D.C1 n2384 -CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 SLICE_130 -ROUTE 2 0.995 R3C9D.F1 to R4C9B.A0 n4889 -CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_21 -ROUTE 4 1.474 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.495 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.436 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 1.084 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 11.183 (35.0% logic, 65.0% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_151: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R5C6B.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i4 (from PHI2_c +) - Destination: FF Data in CmdEnable_541 (to PHI2_c -) - - Delay: 11.083ns (35.3% logic, 64.7% route), 8 logic levels. - - Constraint Details: - - 11.083ns physical path delay SLICE_111 to SLICE_19 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns - - Physical Path Details: - - Data path SLICE_111 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_111 (from PHI2_c) -ROUTE 1 1.004 R2C8C.Q0 to R2C8B.B0 Bank_4 -CTOF_DEL --- 0.495 R2C8B.B0 to R2C8B.F0 SLICE_158 -ROUTE 1 1.535 R2C8B.F0 to R5C9D.B0 n4610 -CTOF_DEL --- 0.495 R5C9D.B0 to R5C9D.F0 SLICE_139 -ROUTE 2 1.086 R5C9D.F0 to R2C9D.C1 n4628 -CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_114 -ROUTE 4 0.756 R2C9D.F1 to R2C9B.C1 n2384 -CTOF_DEL --- 0.495 R2C9B.C1 to R2C9B.F1 SLICE_116 -ROUTE 2 0.445 R2C9B.F1 to R2C9B.C0 n4888 -CTOF_DEL --- 0.495 R2C9B.C0 to R2C9B.F0 SLICE_116 -ROUTE 1 0.645 R2C9B.F0 to R3C9A.D1 n4624 -CTOF_DEL --- 0.495 R3C9A.D1 to R3C9A.F1 SLICE_19 -ROUTE 4 1.042 R3C9A.F1 to R3C9D.B0 C1Submitted_N_232 -CTOF_DEL --- 0.495 R3C9D.B0 to R3C9D.F0 SLICE_130 -ROUTE 1 0.653 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c) - -------- - 11.083 (35.3% logic, 64.7% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_111: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R2C8C.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.539 8.PADDI to R3C9A.CLK PHI2_c - -------- - 3.539 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 25.800ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 347.500ns - The internal maximum frequency of the following component is 400.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK SLICE_122 - - Delay: 2.500ns -- based on Minimum Pulse Width - -Report: 2.500ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 347.500ns - The internal maximum frequency of the following component is 400.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK SLICE_25 - - Delay: 2.500ns -- based on Minimum Pulse Width - -Report: 2.500ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 1409 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.573ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i6 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 12.261ns (37.8% logic, 62.2% route), 9 logic levels. - - Constraint Details: - - 12.261ns physical path delay SLICE_6 to SLICE_70 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c) -ROUTE 21 1.808 R6C6D.Q1 to R3C7A.B1 FS_6 -CTOF_DEL --- 0.495 R3C7A.B1 to R3C7A.F1 SLICE_98 -ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924 -CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7 -CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70 -ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 12.261 (37.8% logic, 62.2% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 3.573ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i6 (from RCLK_c +) - Destination: FF Data in wb_adr_i6 (to RCLK_c +) - - Delay: 12.261ns (37.8% logic, 62.2% route), 9 logic levels. - - Constraint Details: - - 12.261ns physical path delay SLICE_6 to SLICE_72 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c) -ROUTE 21 1.808 R6C6D.Q1 to R3C7A.B1 FS_6 -CTOF_DEL --- 0.495 R3C7A.B1 to R3C7A.F1 SLICE_98 -ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924 -CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7 -CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72 -ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c) - -------- - 12.261 (37.8% logic, 62.2% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.370ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i7 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 11.464ns (36.1% logic, 63.9% route), 8 logic levels. - - Constraint Details: - - 11.464ns physical path delay SLICE_5 to SLICE_70 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) -ROUTE 25 2.442 R6C7A.Q0 to R2C8D.C1 FS_7 -CTOF_DEL --- 0.495 R2C8D.C1 to R2C8D.F1 SLICE_143 -ROUTE 2 1.427 R2C8D.F1 to R2C6A.B1 n4915 -CTOF_DEL --- 0.495 R2C6A.B1 to R2C6A.F1 SLICE_113 -ROUTE 5 0.672 R2C6A.F1 to R2C7D.D1 n4890 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7 -CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70 -ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 11.464 (36.1% logic, 63.9% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.370ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i7 (from RCLK_c +) - Destination: FF Data in wb_adr_i6 (to RCLK_c +) - - Delay: 11.464ns (36.1% logic, 63.9% route), 8 logic levels. - - Constraint Details: - - 11.464ns physical path delay SLICE_5 to SLICE_72 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) -ROUTE 25 2.442 R6C7A.Q0 to R2C8D.C1 FS_7 -CTOF_DEL --- 0.495 R2C8D.C1 to R2C8D.F1 SLICE_143 -ROUTE 2 1.427 R2C8D.F1 to R2C6A.B1 n4915 -CTOF_DEL --- 0.495 R2C6A.B1 to R2C6A.F1 SLICE_113 -ROUTE 5 0.672 R2C6A.F1 to R2C7D.D1 n4890 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7 -CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72 -ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c) - -------- - 11.464 (36.1% logic, 63.9% route), 8 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.376ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i8 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 11.458ns (40.5% logic, 59.5% route), 9 logic levels. - - Constraint Details: - - 11.458ns physical path delay SLICE_5 to SLICE_70 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_5 (from RCLK_c) -ROUTE 23 1.005 R6C7A.Q1 to R3C7A.D1 FS_8 -CTOF_DEL --- 0.495 R3C7A.D1 to R3C7A.F1 SLICE_98 -ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924 -CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7 -CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70 -ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 11.458 (40.5% logic, 59.5% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.376ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i8 (from RCLK_c +) - Destination: FF Data in wb_adr_i6 (to RCLK_c +) - - Delay: 11.458ns (40.5% logic, 59.5% route), 9 logic levels. - - Constraint Details: - - 11.458ns physical path delay SLICE_5 to SLICE_72 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 SLICE_5 (from RCLK_c) -ROUTE 23 1.005 R6C7A.Q1 to R3C7A.D1 FS_8 -CTOF_DEL --- 0.495 R3C7A.D1 to R3C7A.F1 SLICE_98 -ROUTE 4 1.021 R3C7A.F1 to R3C7D.B1 n4924 -CTOF_DEL --- 0.495 R3C7D.B1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7 -CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72 -ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c) - -------- - 11.458 (40.5% logic, 59.5% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C7A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.398ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i6 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 11.436ns (40.6% logic, 59.4% route), 9 logic levels. - - Constraint Details: - - 11.436ns physical path delay SLICE_6 to SLICE_70 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c) -ROUTE 21 1.551 R6C6D.Q1 to R3C7D.C0 FS_6 -CTOF_DEL --- 0.495 R3C7D.C0 to R3C7D.F0 SLICE_93 -ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9 -CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7 -CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70 -ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 11.436 (40.6% logic, 59.4% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.398ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i6 (from RCLK_c +) - Destination: FF Data in wb_adr_i6 (to RCLK_c +) - - Delay: 11.436ns (40.6% logic, 59.4% route), 9 logic levels. - - Constraint Details: - - 11.436ns physical path delay SLICE_6 to SLICE_72 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q1 SLICE_6 (from RCLK_c) -ROUTE 21 1.551 R6C6D.Q1 to R3C7D.C0 FS_6 -CTOF_DEL --- 0.495 R3C7D.C0 to R3C7D.F0 SLICE_93 -ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9 -CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7 -CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72 -ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c) - -------- - 11.436 (40.6% logic, 59.4% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.449ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i5 (from RCLK_c +) - Destination: FF Data in wb_adr_i4 (to RCLK_c +) - - Delay: 11.385ns (40.7% logic, 59.3% route), 9 logic levels. - - Constraint Details: - - 11.385ns physical path delay SLICE_6 to SLICE_70 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_70: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q0 SLICE_6 (from RCLK_c) -ROUTE 21 1.500 R6C6D.Q0 to R3C7D.D0 FS_5 -CTOF_DEL --- 0.495 R3C7D.D0 to R3C7D.F0 SLICE_93 -ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9 -CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3A.D1 n14_adj_7 -CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_70 -ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c) - -------- - 11.385 (40.7% logic, 59.3% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_70: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3A.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 4.449ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i5 (from RCLK_c +) - Destination: FF Data in wb_adr_i6 (to RCLK_c +) - - Delay: 11.385ns (40.7% logic, 59.3% route), 9 logic levels. - - Constraint Details: - - 11.385ns physical path delay SLICE_6 to SLICE_72 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C6D.CLK to R6C6D.Q0 SLICE_6 (from RCLK_c) -ROUTE 21 1.500 R6C6D.Q0 to R3C7D.D0 FS_5 -CTOF_DEL --- 0.495 R3C7D.D0 to R3C7D.F0 SLICE_93 -ROUTE 3 0.453 R3C7D.F0 to R3C7D.C1 n53_adj_9 -CTOF_DEL --- 0.495 R3C7D.C1 to R3C7D.F1 SLICE_93 -ROUTE 1 1.001 R3C7D.F1 to R2C7D.B0 n98 -CTOF_DEL --- 0.495 R2C7D.B0 to R2C7D.F0 SLICE_133 -ROUTE 2 1.013 R2C7D.F0 to R2C7D.B1 n2199 -CTOF_DEL --- 0.495 R2C7D.B1 to R2C7D.F1 SLICE_133 -ROUTE 1 0.747 R2C7D.F1 to R2C7A.C1 n53 -CTOOFX_DEL --- 0.721 R2C7A.C1 to R2C7A.OFX0 i29/SLICE_84 -ROUTE 1 0.744 R2C7A.OFX0 to R2C6C.C1 n14_adj_3 -CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_148 -ROUTE 2 0.637 R2C6C.F1 to R2C5D.D0 n12_adj_8 -CTOF_DEL --- 0.495 R2C5D.D0 to R2C5D.F0 SLICE_135 -ROUTE 2 0.652 R2C5D.F0 to R2C3D.D0 n14_adj_7 -CTOF_DEL --- 0.495 R2C3D.D0 to R2C3D.F0 SLICE_72 -ROUTE 1 0.000 R2C3D.F0 to R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c) - -------- - 11.385 (40.7% logic, 59.3% route), 9 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R6C6D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 2.019 63.PADDI to R2C3D.CLK RCLK_c - -------- - 2.019 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 12.427ns is the minimum period for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.015ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_536 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 6.334ns (71.9% logic, 28.1% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_54 and - 6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets - 12.500ns offset RCLK to RA[10] by 3.015ns - - Physical Path Details: - - Clock path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R4C11D.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_54 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C11D.CLK to R4C11D.Q0 SLICE_54 (from RCLK_c) -ROUTE 1 1.777 R4C11D.Q0 to 64.PADDO n1975 -DOPAD_DEL --- 4.105 64.PADDO to 64.PAD RA[10] - -------- - 6.334 (71.9% logic, 28.1% route), 2 logic levels. - -Report: 9.485ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.495ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 7.854ns (64.3% logic, 35.7% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets - 12.500ns offset RCLK to RA[9] by 1.495ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.016 R5C10A.Q0 to R5C9B.A0 nRowColSel -CTOF_DEL --- 0.495 R5C9B.A0 to R5C9B.F0 SLICE_151 -ROUTE 1 1.786 R5C9B.F0 to 62.PADDO RA_c_9 -DOPAD_DEL --- 4.105 62.PADDO to 62.PAD RA[9] - -------- - 7.854 (64.3% logic, 35.7% route), 3 logic levels. - -Report: 11.005ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.386ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 7.963ns (63.4% logic, 36.6% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets - 12.500ns offset RCLK to RA[8] by 1.386ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.053 R5C10A.Q0 to R4C10D.B1 nRowColSel -CTOF_DEL --- 0.495 R4C10D.B1 to R4C10D.F1 SLICE_163 -ROUTE 1 1.858 R4C10D.F1 to 65.PADDO RA_c_8 -DOPAD_DEL --- 4.105 65.PADDO to 65.PAD RA[8] - -------- - 7.963 (63.4% logic, 36.6% route), 3 logic levels. - -Report: 11.114ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.552ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 7.797ns (64.8% logic, 35.2% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets - 12.500ns offset RCLK to RA[7] by 1.552ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.017 R5C10A.Q0 to R2C10D.D1 nRowColSel -CTOF_DEL --- 0.495 R2C10D.D1 to R2C10D.F1 SLICE_155 -ROUTE 1 1.728 R2C10D.F1 to 75.PADDO RA_c_7 -DOPAD_DEL --- 4.105 75.PADDO to 75.PAD RA[7] - -------- - 7.797 (64.8% logic, 35.2% route), 3 logic levels. - -Report: 10.948ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.401ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 7.948ns (63.6% logic, 36.4% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets - 12.500ns offset RCLK to RA[6] by 1.401ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.053 R5C10A.Q0 to R4C10D.B0 nRowColSel -CTOF_DEL --- 0.495 R4C10D.B0 to R4C10D.F0 SLICE_163 -ROUTE 1 1.843 R4C10D.F0 to 68.PADDO RA_c_6 -DOPAD_DEL --- 4.105 68.PADDO to 68.PAD RA[6] - -------- - 7.948 (63.6% logic, 36.4% route), 3 logic levels. - -Report: 11.099ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.135ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 8.214ns (61.5% logic, 38.5% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets - 12.500ns offset RCLK to RA[5] by 1.135ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.310 R5C10A.Q0 to R2C9A.C1 nRowColSel -CTOF_DEL --- 0.495 R2C9A.C1 to R2C9A.F1 SLICE_157 -ROUTE 1 1.852 R2C9A.F1 to 70.PADDO RA_c_5 -DOPAD_DEL --- 4.105 70.PADDO to 70.PAD RA[5] - -------- - 8.214 (61.5% logic, 38.5% route), 3 logic levels. - -Report: 11.365ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.135ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 8.214ns (61.5% logic, 38.5% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets - 12.500ns offset RCLK to RA[4] by 1.135ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.310 R5C10A.Q0 to R2C8B.C1 nRowColSel -CTOF_DEL --- 0.495 R2C8B.C1 to R2C8B.F1 SLICE_158 -ROUTE 1 1.852 R2C8B.F1 to 74.PADDO RA_c_4 -DOPAD_DEL --- 4.105 74.PADDO to 74.PAD RA[4] - -------- - 8.214 (61.5% logic, 38.5% route), 3 logic levels. - -Report: 11.365ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.322ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 8.027ns (62.9% logic, 37.1% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets - 12.500ns offset RCLK to RA[3] by 1.322ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.990 R5C10A.Q0 to R3C10C.D0 nRowColSel -CTOF_DEL --- 0.495 R3C10C.D0 to R3C10C.F0 SLICE_162 -ROUTE 1 1.985 R3C10C.F0 to 71.PADDO RA_c_3 -DOPAD_DEL --- 4.105 71.PADDO to 71.PAD RA[3] - -------- - 8.027 (62.9% logic, 37.1% route), 3 logic levels. - -Report: 11.178ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.577ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 7.772ns (65.0% logic, 35.0% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets - 12.500ns offset RCLK to RA[2] by 1.577ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.796 R5C10A.Q0 to R5C9C.C0 nRowColSel -CTOF_DEL --- 0.495 R5C9C.C0 to R5C9C.F0 SLICE_161 -ROUTE 1 1.924 R5C9C.F0 to 69.PADDO RA_c_2 -DOPAD_DEL --- 4.105 69.PADDO to 69.PAD RA[2] - -------- - 7.772 (65.0% logic, 35.0% route), 3 logic levels. - -Report: 10.923ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.579ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 7.770ns (65.0% logic, 35.0% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets - 12.500ns offset RCLK to RA[1] by 1.579ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.990 R5C10A.Q0 to R3C10C.D1 nRowColSel -CTOF_DEL --- 0.495 R3C10C.D1 to R3C10C.F1 SLICE_162 -ROUTE 1 1.728 R3C10C.F1 to 67.PADDO RA_c_1 -DOPAD_DEL --- 4.105 67.PADDO to 67.PAD RA[1] - -------- - 7.770 (65.0% logic, 35.0% route), 3 logic levels. - -Report: 10.921ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.855ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 7.494ns (67.4% logic, 32.6% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets - 12.500ns offset RCLK to RA[0] by 1.855ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 1.017 R5C10A.Q0 to R3C10D.D1 nRowColSel -CTOF_DEL --- 0.495 R3C10D.D1 to R3C10D.F1 SLICE_159 -ROUTE 1 1.425 R3C10D.F1 to 66.PADDO RA_c_0 -DOPAD_DEL --- 4.105 66.PADDO to 66.PAD RA[0] - -------- - 7.494 (67.4% logic, 32.6% route), 3 logic levels. - -Report: 10.645ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.826ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_532 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 6.523ns (69.9% logic, 30.1% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_59 and - 6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets - 12.500ns offset RCLK to nRCS by 2.826ns - - Physical Path Details: - - Clock path RCLK to SLICE_59: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R4C11B.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_59 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C11B.CLK to R4C11B.Q0 SLICE_59 (from RCLK_c) -ROUTE 1 1.966 R4C11B.Q0 to 57.PADDO nRCS_c -DOPAD_DEL --- 4.105 57.PADDO to 57.PAD nRCS - -------- - 6.523 (69.9% logic, 30.1% route), 2 logic levels. - -Report: 9.674ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.616ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_531 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 6.733ns (67.7% logic, 32.3% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_35 and - 6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets - 12.500ns offset RCLK to RCKE by 2.616ns - - Physical Path Details: - - Clock path RCLK to SLICE_35: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R4C7B.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_35 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_35 (from RCLK_c) -ROUTE 4 2.176 R4C7B.Q0 to 53.PADDO RCKE_c -DOPAD_DEL --- 4.105 53.PADDO to 53.PAD RCKE - -------- - 6.733 (67.7% logic, 32.3% route), 2 logic levels. - -Report: 9.884ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.225ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_535 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 6.124ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_62 and - 6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets - 12.500ns offset RCLK to nRWE by 3.225ns - - Physical Path Details: - - Clock path RCLK to SLICE_62: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C11A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_62 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C11A.CLK to R5C11A.Q0 SLICE_62 (from RCLK_c) -ROUTE 1 1.567 R5C11A.Q0 to 49.PADDO nRWE_c -DOPAD_DEL --- 4.105 49.PADDO to 49.PAD nRWE - -------- - 6.124 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 9.275ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.703ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_533 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 6.646ns (68.6% logic, 31.4% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_60 and - 6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets - 12.500ns offset RCLK to nRRAS by 2.703ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R4C11A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_60 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R4C11A.CLK to R4C11A.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 2.089 R4C11A.Q0 to 54.PADDO nRRAS_c -DOPAD_DEL --- 4.105 54.PADDO to 54.PAD nRRAS - -------- - 6.646 (68.6% logic, 31.4% route), 2 logic levels. - -Report: 9.797ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.826ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_534 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 6.523ns (69.9% logic, 30.1% route), 2 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_57 and - 6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets - 12.500ns offset RCLK to nRCAS by 2.826ns - - Physical Path Details: - - Clock path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C11B.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_57 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C11B.CLK to R5C11B.Q0 SLICE_57 (from RCLK_c) -ROUTE 1 1.966 R5C11B.Q0 to 52.PADDO nRCAS_c -DOPAD_DEL --- 4.105 52.PADDO to 52.PAD nRCAS - -------- - 6.523 (69.9% logic, 30.1% route), 2 logic levels. - -Report: 9.674ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 7.790ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets - 12.500ns offset RCLK to RDQMH by 1.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.648 R5C10A.Q0 to R5C9B.D1 nRowColSel -CTOF_DEL --- 0.495 R5C9B.D1 to R5C9B.F1 SLICE_151 -ROUTE 1 2.090 R5C9B.F1 to 51.PADDO RDQMH_c -DOPAD_DEL --- 4.105 51.PADDO to 51.PAD RDQMH - -------- - 7.790 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 10.941ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.859ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 7.490ns (67.4% logic, 32.6% route), 3 logic levels. - - Clock Path Delay: 3.151ns (35.9% logic, 64.1% route), 1 logic levels. - - Constraint Details: - 3.151ns delay RCLK to SLICE_63 and - 7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets - 12.500ns offset RCLK to RDQML by 1.859ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK -ROUTE 52 2.019 63.PADDI to R5C10A.CLK RCLK_c - -------- - 3.151 (35.9% logic, 64.1% route), 1 logic levels. - - Data path SLICE_63 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.796 R5C10A.Q0 to R5C9C.C1 nRowColSel -CTOF_DEL --- 0.495 R5C9C.C1 to R5C9C.F1 SLICE_161 -ROUTE 1 1.642 R5C9C.F1 to 48.PADDO RDQML_c -DOPAD_DEL --- 4.105 48.PADDO to 48.PAD RDQML - -------- - 7.490 (67.4% logic, 32.6% route), 3 logic levels. - -Report: 10.641ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 25.800 ns| 8 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 12.427 ns| 9 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.485 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.005 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.114 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.948 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.099 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.365 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.365 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 11.178 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.923 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.921 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.645 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.884 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.275 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.797 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.941 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.641 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 5 clocks: - -Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 - No transfer within this clock domain is found - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: wb_clk Source: SLICE_73.Q0 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 - - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:24 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 121 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_542 (from PHI2_c -) - Destination: FF Data in C1Submitted_542 (to PHI2_c -) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_15 to SLICE_15 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.132 R3C9C.Q0 to R3C9C.A0 C1Submitted -CTOF_DEL --- 0.101 R3C9C.A0 to R3C9C.F0 SLICE_15 -ROUTE 1 0.000 R3C9C.F0 to R3C9C.DI0 n2549 (to PHI2_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.474ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_541 (from PHI2_c -) - Destination: FF Data in CmdSubmitted_549 (to PHI2_c -) - - Delay: 0.461ns (50.8% logic, 49.2% route), 2 logic levels. - - Constraint Details: - - 0.461ns physical path delay SLICE_19 to SLICE_21 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.474ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c) -ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable -CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21 -ROUTE 4 0.003 R4C9B.F0 to R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c) - -------- - 0.461 (50.8% logic, 49.2% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_21: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R4C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.538ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_543 (from PHI2_c -) - Destination: FF Data in CmdEnable_541 (to PHI2_c -) - - Delay: 0.510ns (45.9% logic, 54.1% route), 2 logic levels. - - Constraint Details: - - 0.510ns physical path delay SLICE_10 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.538ns - - Physical Path Details: - - Data path SLICE_10 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9B.CLK to R3C9B.Q0 SLICE_10 (from PHI2_c) -ROUTE 1 0.133 R3C9B.Q0 to R3C9D.D0 ADSubmitted -CTOF_DEL --- 0.101 R3C9D.D0 to R3C9D.F0 SLICE_130 -ROUTE 1 0.143 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c) - -------- - 0.510 (45.9% logic, 54.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.860ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_542 (from PHI2_c -) - Destination: FF Data in CmdEnable_541 (to PHI2_c -) - - Delay: 0.832ns (40.3% logic, 59.7% route), 3 logic levels. - - Constraint Details: - - 0.832ns physical path delay SLICE_15 to SLICE_19 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.860ns - - Physical Path Details: - - Data path SLICE_15 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9C.CLK to R3C9C.Q0 SLICE_15 (from PHI2_c) -ROUTE 2 0.224 R3C9C.Q0 to R3C9C.B1 C1Submitted -CTOF_DEL --- 0.101 R3C9C.B1 to R3C9C.F1 SLICE_15 -ROUTE 1 0.130 R3C9C.F1 to R3C9D.A0 n7 -CTOF_DEL --- 0.101 R3C9D.A0 to R3C9D.F0 SLICE_130 -ROUTE 1 0.143 R3C9D.F0 to R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c) - -------- - 0.832 (40.3% logic, 59.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_15: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.873ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_541 (from PHI2_c -) - Destination: FF Data in XOR8MEG_544 (to PHI2_c -) - - Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. - - Constraint Details: - - 0.845ns physical path delay SLICE_19 to SLICE_145 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 0.873ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_145: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c) -ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable -CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21 -ROUTE 4 0.141 R4C9B.F0 to R5C9A.D1 XOR8MEG_N_149 -CTOF_DEL --- 0.101 R5C9A.D1 to R5C9A.F1 SLICE_110 -ROUTE 1 0.145 R5C9A.F1 to R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c) - -------- - 0.845 (39.6% logic, 60.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_145: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.009ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_541 (from PHI2_c -) - Destination: FF Data in CmdUFMShift_547 (to PHI2_c -) - FF CmdUFMData_548 - - Delay: 0.981ns (34.1% logic, 65.9% route), 3 logic levels. - - Constraint Details: - - 0.981ns physical path delay SLICE_19 to SLICE_161 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.009ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_161: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c) -ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable -CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21 -ROUTE 4 0.059 R4C9B.F0 to R4C9B.C1 XOR8MEG_N_149 -CTOF_DEL --- 0.101 R4C9B.C1 to R4C9B.F1 SLICE_21 -ROUTE 1 0.363 R4C9B.F1 to R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c) - -------- - 0.981 (34.1% logic, 65.9% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_161: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C9C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.341ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_541 (from PHI2_c -) - Destination: FF Data in CmdLEDEN_545 (to PHI2_c -) - - Delay: 1.313ns (33.2% logic, 66.8% route), 4 logic levels. - - Constraint Details: - - 1.313ns physical path delay SLICE_19 to SLICE_20 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.341ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c) -ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable -CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21 -ROUTE 4 0.335 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.056 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.101 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 0.262 R5C8D.F1 to R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 1.313 (33.2% logic, 66.8% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_20: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C6A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.341ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_541 (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 1.313ns (33.2% logic, 66.8% route), 4 logic levels. - - Constraint Details: - - 1.313ns physical path delay SLICE_19 to SLICE_24 meets - -0.028ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.028ns) by 1.341ns - - Physical Path Details: - - Data path SLICE_19 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_19 (from PHI2_c) -ROUTE 1 0.224 R3C9A.Q0 to R4C9B.B0 CmdEnable -CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_21 -ROUTE 4 0.335 R4C9B.F0 to R5C8D.B0 XOR8MEG_N_149 -CTOF_DEL --- 0.101 R5C8D.B0 to R5C8D.F0 SLICE_112 -ROUTE 1 0.056 R5C8D.F0 to R5C8D.C1 n4882 -CTOF_DEL --- 0.101 R5C8D.C1 to R5C8D.F1 SLICE_112 -ROUTE 2 0.262 R5C8D.F1 to R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c) - -------- - 1.313 (33.2% logic, 66.8% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C6B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q XOR8MEG_544 (from PHI2_c -) - Destination: FF Data in RA11_521 (to PHI2_c +) - - Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels. - - Constraint Details: - - 0.444ns physical path delay SLICE_145 to SLICE_32 meets - -0.013ns DIN_HLD and - -175.000ns delay constraint less - 0.000ns skew requirement (totaling -175.013ns) by 175.457ns - - Physical Path Details: - - Data path SLICE_145 to SLICE_32: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C8A.CLK to R5C8A.Q0 SLICE_145 (from PHI2_c) -ROUTE 1 0.210 R5C8A.Q0 to R5C8C.A0 XOR8MEG -CTOF_DEL --- 0.101 R5C8C.A0 to R5C8C.F0 SLICE_32 -ROUTE 1 0.000 R5C8C.F0 to R5C8C.DI0 RA11_N_217 (to PHI2_c) - -------- - 0.444 (52.7% logic, 47.3% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_145: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8A.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_32: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i2 (from PHI2_c +) - Destination: FF Data in ADSubmitted_543 (to PHI2_c -) - - Delay: 0.787ns (42.6% logic, 57.4% route), 3 logic levels. - - Constraint Details: - - 0.787ns physical path delay SLICE_143 to SLICE_10 meets - -0.028ns CE_HLD and - -175.000ns delay constraint less - 0.000ns skew requirement (totaling -175.028ns) by 175.815ns - - Physical Path Details: - - Data path SLICE_143 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C8D.CLK to R2C8D.Q0 SLICE_143 (from PHI2_c) -ROUTE 2 0.139 R2C8D.Q0 to R2C9C.C1 Bank_2 -CTOF_DEL --- 0.101 R2C9C.C1 to R2C9C.F1 SLICE_132 -ROUTE 1 0.056 R2C9C.F1 to R2C9C.C0 n4782 -CTOF_DEL --- 0.101 R2C9C.C0 to R2C9C.F0 SLICE_132 -ROUTE 1 0.257 R2C9C.F0 to R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c) - -------- - 0.787 (42.6% logic, 57.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_143: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R2C8D.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_10: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.240 8.PADDI to R3C9B.CLK PHI2_c - -------- - 1.240 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 1409 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i2 (from RCLK_c +) - Destination: FF Data in IS_FSM__i3 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_118 to SLICE_118 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_118 to SLICE_118: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C9C.CLK to R4C9C.Q0 SLICE_118 (from RCLK_c) -ROUTE 1 0.152 R4C9C.Q0 to R4C9C.M1 n1197 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_118: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C9C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_118: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C9C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i4 (from RCLK_c +) - Destination: FF Data in IS_FSM__i5 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_127 to SLICE_127 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_127 to SLICE_127: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10B.CLK to R4C10B.Q0 SLICE_127 (from RCLK_c) -ROUTE 1 0.152 R4C10B.Q0 to R4C10B.M1 n1195 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_127: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C10B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_127: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C10B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CASr_518 (from RCLK_c +) - Destination: FF Data in CASr2_519 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_16 to SLICE_16 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_16 to SLICE_16: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C10C.CLK to R6C10C.Q0 SLICE_16 (from RCLK_c) -ROUTE 1 0.152 R6C10C.Q0 to R6C10C.M1 CASr (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R6C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_16: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R6C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i10 (from RCLK_c +) - Destination: FF Data in IS_FSM__i11 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_163 to SLICE_163 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_163 to SLICE_163: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C10D.CLK to R4C10D.Q0 SLICE_163 (from RCLK_c) -ROUTE 1 0.152 R4C10D.Q0 to R4C10D.M1 n1189 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_163: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C10D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_163: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C10D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i14 (from RCLK_c +) - Destination: FF Data in IS_FSM__i15 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_91 to SLICE_91 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_91 to SLICE_91: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C8D.CLK to R4C8D.Q0 SLICE_91 (from RCLK_c) -ROUTE 1 0.152 R4C8D.Q0 to R4C8D.M1 n1185 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_91: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C8D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_91: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C8D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i12 (from RCLK_c +) - Destination: FF Data in IS_FSM__i13 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_94 to SLICE_94 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C7D.CLK to R4C7D.Q0 SLICE_94 (from RCLK_c) -ROUTE 1 0.152 R4C7D.Q0 to R4C7D.M1 n1187 (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C7D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C7D.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.304ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q PHI2r_512 (from RCLK_c +) - Destination: FF Data in PHI2r2_513 (to RCLK_c +) - - Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. - - Constraint Details: - - 0.285ns physical path delay SLICE_95 to SLICE_35 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.304ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_35: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C7A.CLK to R4C7A.Q0 SLICE_95 (from RCLK_c) -ROUTE 1 0.152 R4C7A.Q0 to R4C7B.M1 PHI2r (to RCLK_c) - -------- - 0.285 (46.7% logic, 53.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_95: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_35: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R4C7B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.306ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RASr_515 (from RCLK_c +) - Destination: FF Data in RASr2_516 (to RCLK_c +) - - Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. - - Constraint Details: - - 0.287ns physical path delay SLICE_30 to SLICE_30 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.306ns - - Physical Path Details: - - Data path SLICE_30 to SLICE_30: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C7A.CLK to R5C7A.Q0 SLICE_30 (from RCLK_c) -ROUTE 2 0.154 R5C7A.Q0 to R5C7A.M1 RASr (to RCLK_c) - -------- - 0.287 (46.3% logic, 53.7% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R5C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_30: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R5C7A.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.307ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i0 (from RCLK_c +) - Destination: FF Data in IS_FSM__i1 (to RCLK_c +) - - Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. - - Constraint Details: - - 0.288ns physical path delay SLICE_162 to SLICE_162 meets - -0.019ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.019ns) by 0.307ns - - Physical Path Details: - - Data path SLICE_162 to SLICE_162: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C10C.CLK to R3C10C.Q0 SLICE_162 (from RCLK_c) -ROUTE 4 0.155 R3C10C.Q0 to R3C10C.M1 nRCS_N_172 (to RCLK_c) - -------- - 0.288 (46.2% logic, 53.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_162: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R3C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_162: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R3C10C.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_972__i2 (from RCLK_c +) - Destination: FF Data in FS_972__i2 (to RCLK_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_0 to SLICE_0 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R6C6B.CLK to R6C6B.Q1 SLICE_0 (from RCLK_c) -ROUTE 3 0.132 R6C6B.Q1 to R6C6B.A1 FS_2 -CTOF_DEL --- 0.101 R6C6B.A1 to R6C6B.F1 SLICE_0 -ROUTE 1 0.000 R6C6B.F1 to R6C6B.DI1 n93 (to RCLK_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R6C6B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 52 0.651 63.PADDI to R6C6B.CLK RCLK_c - -------- - 0.651 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.236ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_536 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 2.217ns (81.5% logic, 18.5% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_54 and - 2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets - 0.000ns hold offset RCLK to RA[10] by 3.236ns - - Physical Path Details: - - Clock path RCLK to SLICE_54: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R4C11D.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_54 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11D.CLK to R4C11D.Q0 SLICE_54 (from RCLK_c) -ROUTE 1 0.411 R4C11D.Q0 to 64.PADDO n1975 -DOPAD_DEL --- 1.673 64.PADDO to 64.PAD RA[10] - -------- - 2.217 (81.5% logic, 18.5% route), 2 logic levels. - -Report: 3.236ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.561ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 2.542ns (75.0% logic, 25.0% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets - 0.000ns hold offset RCLK to RA[9] by 3.561ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.219 R5C10A.Q0 to R5C9B.A0 nRowColSel -CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_151 -ROUTE 1 0.416 R5C9B.F0 to 62.PADDO RA_c_9 -DOPAD_DEL --- 1.673 62.PADDO to 62.PAD RA[9] - -------- - 2.542 (75.0% logic, 25.0% route), 3 logic levels. - -Report: 3.561ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.608ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 2.589ns (73.7% logic, 26.3% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets - 0.000ns hold offset RCLK to RA[8] by 3.608ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.231 R5C10A.Q0 to R4C10D.B1 nRowColSel -CTOF_DEL --- 0.101 R4C10D.B1 to R4C10D.F1 SLICE_163 -ROUTE 1 0.451 R4C10D.F1 to 65.PADDO RA_c_8 -DOPAD_DEL --- 1.673 65.PADDO to 65.PAD RA[8] - -------- - 2.589 (73.7% logic, 26.3% route), 3 logic levels. - -Report: 3.608ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.552ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 2.533ns (75.3% logic, 24.7% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets - 0.000ns hold offset RCLK to RA[7] by 3.552ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.229 R5C10A.Q0 to R2C10D.D1 nRowColSel -CTOF_DEL --- 0.101 R2C10D.D1 to R2C10D.F1 SLICE_155 -ROUTE 1 0.397 R2C10D.F1 to 75.PADDO RA_c_7 -DOPAD_DEL --- 1.673 75.PADDO to 75.PAD RA[7] - -------- - 2.533 (75.3% logic, 24.7% route), 3 logic levels. - -Report: 3.552ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.573ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 2.554ns (74.7% logic, 25.3% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets - 0.000ns hold offset RCLK to RA[6] by 3.573ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.231 R5C10A.Q0 to R4C10D.B0 nRowColSel -CTOF_DEL --- 0.101 R4C10D.B0 to R4C10D.F0 SLICE_163 -ROUTE 1 0.416 R4C10D.F0 to 68.PADDO RA_c_6 -DOPAD_DEL --- 1.673 68.PADDO to 68.PAD RA[6] - -------- - 2.554 (74.7% logic, 25.3% route), 3 logic levels. - -Report: 3.573ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.630ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 2.611ns (73.0% logic, 27.0% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets - 0.000ns hold offset RCLK to RA[5] by 3.630ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.283 R5C10A.Q0 to R2C9A.C1 nRowColSel -CTOF_DEL --- 0.101 R2C9A.C1 to R2C9A.F1 SLICE_157 -ROUTE 1 0.421 R2C9A.F1 to 70.PADDO RA_c_5 -DOPAD_DEL --- 1.673 70.PADDO to 70.PAD RA[5] - -------- - 2.611 (73.0% logic, 27.0% route), 3 logic levels. - -Report: 3.630ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.630ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 2.611ns (73.0% logic, 27.0% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets - 0.000ns hold offset RCLK to RA[4] by 3.630ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.283 R5C10A.Q0 to R2C8B.C1 nRowColSel -CTOF_DEL --- 0.101 R2C8B.C1 to R2C8B.F1 SLICE_158 -ROUTE 1 0.421 R2C8B.F1 to 74.PADDO RA_c_4 -DOPAD_DEL --- 1.673 74.PADDO to 74.PAD RA[4] - -------- - 2.611 (73.0% logic, 27.0% route), 3 logic levels. - -Report: 3.630ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.615ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 2.596ns (73.5% logic, 26.5% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets - 0.000ns hold offset RCLK to RA[3] by 3.615ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.226 R5C10A.Q0 to R3C10C.D0 nRowColSel -CTOF_DEL --- 0.101 R3C10C.D0 to R3C10C.F0 SLICE_162 -ROUTE 1 0.463 R3C10C.F0 to 71.PADDO RA_c_3 -DOPAD_DEL --- 1.673 71.PADDO to 71.PAD RA[3] - -------- - 2.596 (73.5% logic, 26.5% route), 3 logic levels. - -Report: 3.615ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.527ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 2.508ns (76.0% logic, 24.0% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets - 0.000ns hold offset RCLK to RA[2] by 3.527ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.145 R5C10A.Q0 to R5C9C.C0 nRowColSel -CTOF_DEL --- 0.101 R5C9C.C0 to R5C9C.F0 SLICE_161 -ROUTE 1 0.456 R5C9C.F0 to 69.PADDO RA_c_2 -DOPAD_DEL --- 1.673 69.PADDO to 69.PAD RA[2] - -------- - 2.508 (76.0% logic, 24.0% route), 3 logic levels. - -Report: 3.527ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.549ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 2.530ns (75.4% logic, 24.6% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets - 0.000ns hold offset RCLK to RA[1] by 3.549ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.226 R5C10A.Q0 to R3C10C.D1 nRowColSel -CTOF_DEL --- 0.101 R3C10C.D1 to R3C10C.F1 SLICE_162 -ROUTE 1 0.397 R3C10C.F1 to 67.PADDO RA_c_1 -DOPAD_DEL --- 1.673 67.PADDO to 67.PAD RA[1] - -------- - 2.530 (75.4% logic, 24.6% route), 3 logic levels. - -Report: 3.549ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.471ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 2.452ns (77.8% logic, 22.2% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets - 0.000ns hold offset RCLK to RA[0] by 3.471ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.229 R5C10A.Q0 to R3C10D.D1 nRowColSel -CTOF_DEL --- 0.101 R3C10D.D1 to R3C10D.F1 SLICE_159 -ROUTE 1 0.316 R3C10D.F1 to 66.PADDO RA_c_0 -DOPAD_DEL --- 1.673 66.PADDO to 66.PAD RA[0] - -------- - 2.452 (77.8% logic, 22.2% route), 3 logic levels. - -Report: 3.471ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.300ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_532 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 2.281ns (79.2% logic, 20.8% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_59 and - 2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets - 0.000ns hold offset RCLK to nRCS by 3.300ns - - Physical Path Details: - - Clock path RCLK to SLICE_59: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R4C11B.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_59 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11B.CLK to R4C11B.Q0 SLICE_59 (from RCLK_c) -ROUTE 1 0.475 R4C11B.Q0 to 57.PADDO nRCS_c -DOPAD_DEL --- 1.673 57.PADDO to 57.PAD nRCS - -------- - 2.281 (79.2% logic, 20.8% route), 2 logic levels. - -Report: 3.300ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.362ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_531 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 2.343ns (77.1% logic, 22.9% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_35 and - 2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets - 0.000ns hold offset RCLK to RCKE by 3.362ns - - Physical Path Details: - - Clock path RCLK to SLICE_35: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R4C7B.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_35 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C7B.CLK to R4C7B.Q0 SLICE_35 (from RCLK_c) -ROUTE 4 0.537 R4C7B.Q0 to 53.PADDO RCKE_c -DOPAD_DEL --- 1.673 53.PADDO to 53.PAD RCKE - -------- - 2.343 (77.1% logic, 22.9% route), 2 logic levels. - -Report: 3.362ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.194ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_535 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 2.175ns (83.0% logic, 17.0% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_62 and - 2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets - 0.000ns hold offset RCLK to nRWE by 3.194ns - - Physical Path Details: - - Clock path RCLK to SLICE_62: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C11A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_62 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q0 SLICE_62 (from RCLK_c) -ROUTE 1 0.369 R5C11A.Q0 to 49.PADDO nRWE_c -DOPAD_DEL --- 1.673 49.PADDO to 49.PAD nRWE - -------- - 2.175 (83.0% logic, 17.0% route), 2 logic levels. - -Report: 3.194ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.322ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_533 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 2.303ns (78.4% logic, 21.6% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_60 and - 2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets - 0.000ns hold offset RCLK to nRRAS by 3.322ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R4C11A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_60 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C11A.CLK to R4C11A.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 0.497 R4C11A.Q0 to 54.PADDO nRRAS_c -DOPAD_DEL --- 1.673 54.PADDO to 54.PAD nRRAS - -------- - 2.303 (78.4% logic, 21.6% route), 2 logic levels. - -Report: 3.322ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.300ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_534 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 2.281ns (79.2% logic, 20.8% route), 2 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_57 and - 2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets - 0.000ns hold offset RCLK to nRCAS by 3.300ns - - Physical Path Details: - - Clock path RCLK to SLICE_57: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C11B.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_57 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11B.CLK to R5C11B.Q0 SLICE_57 (from RCLK_c) -ROUTE 1 0.475 R5C11B.Q0 to 52.PADDO nRCAS_c -DOPAD_DEL --- 1.673 52.PADDO to 52.PAD nRCAS - -------- - 2.281 (79.2% logic, 20.8% route), 2 logic levels. - -Report: 3.300ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 2.540ns (75.1% logic, 24.9% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets - 0.000ns hold offset RCLK to RDQMH by 3.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.139 R5C10A.Q0 to R5C9B.D1 nRowColSel -CTOF_DEL --- 0.101 R5C9B.D1 to R5C9B.F1 SLICE_151 -ROUTE 1 0.494 R5C9B.F1 to 51.PADDO RDQMH_c -DOPAD_DEL --- 1.673 51.PADDO to 51.PAD RDQMH - -------- - 2.540 (75.1% logic, 24.9% route), 3 logic levels. - -Report: 3.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.470ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_538 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 2.451ns (77.8% logic, 22.2% route), 3 logic levels. - - Clock Path Delay: 1.019ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 1.019ns delay RCLK to SLICE_63 and - 2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets - 0.000ns hold offset RCLK to RDQML by 3.470ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK -ROUTE 52 0.571 63.PADDI to R5C10A.CLK RCLK_c - -------- - 1.019 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10A.CLK to R5C10A.Q0 SLICE_63 (from RCLK_c) -ROUTE 12 0.145 R5C10A.Q0 to R5C9C.C1 nRowColSel -CTOF_DEL --- 0.101 R5C9C.C1 to R5C9C.F1 SLICE_161 -ROUTE 1 0.399 R5C9C.F1 to 48.PADDO RDQML_c -DOPAD_DEL --- 1.673 48.PADDO to 48.PAD RDQML - -------- - 2.451 (77.8% logic, 22.2% route), 3 logic levels. - -Report: 3.470ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.236 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.561 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.608 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.552 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.573 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.630 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.630 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.615 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.527 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.549 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.471 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.300 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.362 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.194 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.322 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.300 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.559 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.470 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 5 clocks: - -Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 - No transfer within this clock domain is found - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: wb_clk Source: SLICE_73.Q0 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 - - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html deleted file mode 100644 index 7a7fffc..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html +++ /dev/null @@ -1,152 +0,0 @@ - -Bitgen Report - - -
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 17 06:21:07 2021
-
-
-Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                         2.08**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                      JTAG_PORT  |                       ENABLE**  |
-+---------------------------------+---------------------------------+
-|                       SDM_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                       I2C_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  CONFIGURATION  |                          CFG**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                        MY_ASSP  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|               ONE_TIME_PROGRAM  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                 ENABLE_TRANSFR  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  SHAREDEBRINIT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 1.95.
- 
-Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
- 
-===========
-UFM Summary.
-===========
-UFM Size:        191 Pages (128*191 Bits).
-UFM Utilization: General Purpose Flash Memory.
- 
-Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     0 Page.
- 
-Total CPU Time: 1 secs 
-Total REAL Time: 2 secs 
-Peak Memory Usage: 245 MB
-
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html deleted file mode 100644 index 2e5e5a5..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html +++ /dev/null @@ -1,198 +0,0 @@ - -I/O Timing Report - - -
I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Sat Oct 09 01:19:25 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F    -0.195      M       1.729     4
-CROW[1] nCRAS F    -0.218      M       1.801     4
-Din[0]  PHI2  F     6.339      4       1.186     4
-Din[0]  nCCAS F     1.641      4       0.107     M
-Din[1]  PHI2  F     6.084      4       1.570     4
-Din[1]  nCCAS F     0.198      4       1.314     4
-Din[2]  PHI2  F     3.778      4       1.771     4
-Din[2]  nCCAS F     0.075      4       1.431     4
-Din[3]  PHI2  F     4.331      4       1.705     4
-Din[3]  nCCAS F    -0.116      M       1.722     4
-Din[4]  PHI2  F     6.176      4       1.711     4
-Din[4]  nCCAS F     1.065      4       0.575     4
-Din[5]  PHI2  F     4.684      4       1.261     4
-Din[5]  nCCAS F    -0.081      M       1.625     4
-Din[6]  PHI2  F     5.243      4       0.356     4
-Din[6]  nCCAS F     1.414      4       0.309     4
-Din[7]  PHI2  F     6.602      4       1.175     4
-Din[7]  nCCAS F    -0.286      M       2.137     4
-MAin[0] PHI2  F     5.034      4       0.629     4
-MAin[0] nCRAS F     1.094      4       0.380     4
-MAin[1] PHI2  F     6.081      4       1.157     4
-MAin[1] nCRAS F     0.544      4       0.877     4
-MAin[2] PHI2  F     9.979      4      -0.319     M
-MAin[2] nCRAS F    -0.050      M       1.401     4
-MAin[3] PHI2  F     9.162      4      -0.219     M
-MAin[3] nCRAS F     1.032      4       0.440     4
-MAin[4] PHI2  F    11.678      4      -0.770     M
-MAin[4] nCRAS F    -0.150      M       1.620     4
-MAin[5] PHI2  F     8.668      4      -0.081     M
-MAin[5] nCRAS F    -0.050      M       1.401     4
-MAin[6] PHI2  F     8.516      4      -0.025     M
-MAin[6] nCRAS F     1.003      4       0.478     4
-MAin[7] PHI2  F     9.320      4      -0.061     M
-MAin[7] nCRAS F     1.001      4       0.478     4
-MAin[8] nCRAS F    -0.146      M       1.657     4
-MAin[9] nCRAS F    -0.360      M       2.140     4
-PHI2    RCLK  R     3.079      4      -0.602     M
-nCCAS   RCLK  R     3.574      4      -0.705     M
-nCCAS   nCRAS F     3.232      4      -0.351     M
-nCRAS   RCLK  R     2.757      4      -0.470     M
-nFWE    PHI2  F     5.913      4       0.723     4
-nFWE    nCRAS F     0.547      4       0.890     4
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    10.062         4        3.164          M
-RA[0]  RCLK  R    10.645         4        3.471          M
-RA[0]  nCRAS F    11.744         4        3.770          M
-RA[10] RCLK  R     9.485         4        3.236          M
-RA[11] PHI2  R    11.513         4        3.824          M
-RA[1]  RCLK  R    10.921         4        3.549          M
-RA[1]  nCRAS F    12.664         4        4.036          M
-RA[2]  RCLK  R    10.923         4        3.527          M
-RA[2]  nCRAS F    12.463         4        3.984          M
-RA[3]  RCLK  R    11.178         4        3.615          M
-RA[3]  nCRAS F    12.304         4        3.917          M
-RA[4]  RCLK  R    11.365         4        3.630          M
-RA[4]  nCRAS F    13.243         4        4.179          M
-RA[5]  RCLK  R    11.365         4        3.630          M
-RA[5]  nCRAS F    12.940         4        4.098          M
-RA[6]  RCLK  R    11.099         4        3.573          M
-RA[6]  nCRAS F    12.162         4        3.870          M
-RA[7]  RCLK  R    10.948         4        3.552          M
-RA[7]  nCRAS F    12.282         4        3.936          M
-RA[8]  RCLK  R    11.114         4        3.608          M
-RA[8]  nCRAS F    12.909         4        4.116          M
-RA[9]  RCLK  R    11.005         4        3.561          M
-RA[9]  nCRAS F    12.959         4        4.081          M
-RBA[0] nCRAS F    11.842         4        3.911          M
-RBA[1] nCRAS F    11.343         4        3.771          M
-RCKE   RCLK  R     9.884         4        3.362          M
-RDQMH  RCLK  R    10.941         4        3.559          M
-RDQML  RCLK  R    10.641         4        3.470          M
-RD[0]  nCCAS F    12.628         4        4.413          M
-RD[1]  nCCAS F    12.231         4        4.302          M
-RD[2]  nCCAS F    12.231         4        4.302          M
-RD[3]  nCCAS F    11.928         4        4.221          M
-RD[4]  nCCAS F    12.427         4        4.361          M
-RD[5]  nCCAS F    12.697         4        4.400          M
-RD[6]  nCCAS F    12.427         4        4.361          M
-RD[7]  nCCAS F    12.427         4        4.361          M
-nRCAS  RCLK  R     9.674         4        3.300          M
-nRCS   RCLK  R     9.674         4        3.300          M
-nRRAS  RCLK  R     9.797         4        3.322          M
-nRWE   RCLK  R     9.275         4        3.194          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: M
-
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj deleted file mode 100644 index 7540ad6..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj +++ /dev/null @@ -1,41 +0,0 @@ --a "MachXO2" --d LCMXO2-640HC --t TQFP100 --s 4 --frequency 200 --optimization_goal Balanced --bram_utilization 100 --ramstyle Auto --romstyle auto --dsp_utilization 100 --use_dsp 1 --use_carry_chain 1 --carry_chain_length 0 --force_gsr Auto --resource_sharing 1 --propagate_constants 1 --remove_duplicate_regs 1 --mux_style Auto --max_fanout 1000 --fsm_encoding_style Auto --twr_paths 3 --fix_gated_clocks 1 --loop_limit 1950 - - - --use_io_insertion 1 --resolve_mixed_drivers 0 --use_io_reg auto - - --lpf 1 --p "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC" --ver "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v" --top RAM2GS - - --p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC" - --ngd "RAM2GS_LCMXO2_640HC_impl1.ngd" - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam deleted file mode 100644 index 1db8fb1..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam +++ /dev/null @@ -1,94 +0,0 @@ -[ START MERGED ] -n4935 Ready -n4933 nRowColSel_N_35 -n2557 nRowColSel_N_34 -nRWE_N_209 nRWE_N_210 -PHI2_N_151 PHI2_c -RCLK_c_enable_22 InitReady -[ END MERGED ] -[ START CLIPPED ] -GND_net -VCC_net -FS_972_add_4_1/S0 -FS_972_add_4_1/CI -FS_972_add_4_19/S1 -FS_972_add_4_19/CO -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "62" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; -PERIOD NET "PHI2_c" 350.000000 ns ; -USE PRIMARY NET "RCLK_c" ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -USE PRIMARY NET "PHI2_c" ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -USE PRIMARY NET "nCRAS_c" ; -PERIOD NET "RCLK_c" 16.000000 ns ; -USE PRIMARY NET "nCCAS_c" ; -SCHEMATIC END ; -[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr deleted file mode 100644 index 1264102..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr +++ /dev/null @@ -1,10 +0,0 @@ ---------------------------------------------------- -Report for cell RAM2GS - Instance path: RAM2GS - Cell usage: - cell count Res Usage(%) - SLIC 131.00 100.0 - LUT4 235.00 100.0 - IOBUF 63 100.0 - PFUREG 119 100.0 - RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd deleted file mode 100644 index 5f6f396..0000000 Binary files a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd and /dev/null differ diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html deleted file mode 100644 index 1f33ab9..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html +++ /dev/null @@ -1,428 +0,0 @@ - -Project Summary - - -

-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-
-Design Information
-
-Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
-     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
-     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
-     rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
-     O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
-     LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui 
-Target Vendor:  LATTICE
-Target Device:  LCMXO2-640HCTQFP100
-Target Performance:   4
-Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
-Mapped on:  10/09/21  01:19:14
-
-
-Design Summary
-   Number of registers:    119 out of   877 (14%)
-      PFU registers:          119 out of   640 (19%)
-      PIO registers:            0 out of   237 (0%)
-   Number of SLICEs:       131 out of   320 (41%)
-      SLICEs as Logic/ROM:    131 out of   320 (41%)
-      SLICEs as RAM:            0 out of   240 (0%)
-      SLICEs as Carry:         10 out of   320 (3%)
-   Number of LUT4s:        255 out of   640 (40%)
-      Number used as logic LUTs:        235
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       20
-      Number used as shift registers:     0
-   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
-   Number of block RAMs:  0 out of 2 (0%)
-   Number of GSRs:        0 out of 1 (0%)
-   EFB used :        Yes
-   JTAG used :       No
-   Readback used :   No
-   Oscillator used : No
-   Startup used :    No
-   POR :             On
-   Bandgap :         On
-   Number of Power Controller:  0 out of 1 (0%)
-   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
-   Number of DCCA:  0 out of 8 (0%)
-   Number of DCMA:  0 out of 2 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  5
-     Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
-     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
-     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
-     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  14
-     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
-     Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
-
-     Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
-     Net InitReady: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
-     Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
-     Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
-     Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
-     Net Ready_N_280: 1 loads, 1 LSLICEs
-     Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
-     Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
-   Number of LSRs:  8
-     Net RASr2: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
-     Net wb_rst: 1 loads, 0 LSLICEs
-     Net nRWE_N_210: 1 loads, 1 LSLICEs
-     Net C1Submitted_N_232: 2 loads, 2 LSLICEs
-     Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
-     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
-     Net Ready: 7 loads, 7 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net InitReady: 36 loads
-     Net FS_10: 32 loads
-     Net FS_11: 32 loads
-     Net FS_9: 26 loads
-     Net FS_7: 25 loads
-     Net FS_8: 23 loads
-     Net FS_5: 21 loads
-     Net FS_6: 21 loads
-     Net FS_12: 20 loads
-     Net Ready: 18 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-   No errors or warnings present.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+
-| IO Name             | Direction | Levelmode | IO         |
-|                     |           |  IO_TYPE  | Register   |
-+---------------------+-----------+-----------+------------+
-| RCLK                | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nFWE                | INPUT     | LVTTL33   |            |
-
-+---------------------+-----------+-----------+------------+
-| nCRAS               | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nCCAS               | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[0]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[1]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[2]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[3]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[4]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[5]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[6]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Din[7]              | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| CROW[0]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| CROW[1]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[0]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[1]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[2]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[3]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[4]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[5]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[6]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[7]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[8]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| MAin[9]             | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| PHI2                | INPUT     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RDQML               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RDQMH               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nRCAS               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nRRAS               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVTTL33   |            |
-
-+---------------------+-----------+-----------+------------+
-| RCKE                | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| nRCS                | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[3]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RBA[0]              | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RBA[1]              | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| LED                 | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[0]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[1]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[2]               | BIDIR     | LVTTL33   |            |
-
-+---------------------+-----------+-----------+------------+
-| RD[3]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[4]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[5]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[6]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-| RD[7]               | BIDIR     | LVTTL33   |            |
-+---------------------+-----------+-----------+------------+
-
-
-
-Removed logic
-
-Block i2 undriven or does not drive anything - clipped.
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal PHI2_N_151 was merged into signal PHI2_c
-Signal nRWE_N_209 was merged into signal nRWE_N_210
-Signal RCLK_c_enable_22 was merged into signal InitReady
-Signal n2557 was merged into signal nRowColSel_N_34
-Signal n4935 was merged into signal Ready
-Signal n4933 was merged into signal nRowColSel_N_35
-Signal GND_net undriven or does not drive anything - clipped.
-Signal VCC_net undriven or does not drive anything - clipped.
-Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
-Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
-Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
-Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
-Block i4008 was optimized away.
-Block nRWE_I_53_1_lut was optimized away.
-Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
-Block i1683_1_lut was optimized away.
-Block i1044_1_lut_rep_86 was optimized away.
-Block i1684_1_lut_rep_84 was optimized away.
-Block i1 was optimized away.
-
-     
-
-
-
-Embedded Functional Block Connection Summary
-
-   Desired WISHBONE clock frequency: 50.0 MHz
-   Clock source:                     wb_clk
-   Reset source:                     wb_rst
-   Functions mode:
-      I2C #1 (Primary) Function:     DISABLED
-      I2C #2 (Secondary) Function:   DISABLED
-      SPI Function:                  DISABLED
-      Timer/Counter Function:        DISABLED
-      Timer/Counter Mode:            NO_WB
-      UFM Connection:                DISABLED
-      PLL0 Connection:               DISABLED
-      PLL1 Connection:               DISABLED
-   I2C Function Summary:
-   --------------------
-
-      None
-   SPI Function Summary:
-   --------------------
-      None
-   Timer/Counter Function Summary:
-   ------------------------------
-      None
-   UFM Function Summary:
-   --------------------
-      UFM Utilization:        General Purpose Flash Memory
-      Available General
-      Purpose Flash Memory:   191 Pages (191*128 Bits)
-
-           EBR Blocks with Unique
-      Initialization Data:    0
-
-           WID		EBR Instance
-      ---		------------
-
-
-
-
-ASIC Components
----------------
-
-Instance Name: ufmefb
-         Type: EFB
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 37 MB
-        
-
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-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html deleted file mode 100644 index 7f7a4dc..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html +++ /dev/null @@ -1,338 +0,0 @@ - -PAD Specification File - - -
PAD Specification File
-***************************
-
-PART TYPE:        LCMXO2-640HC
-Performance Grade:      4
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.39
-
-Sat Oct 09 01:19:20 2021
-
-Pinout by Port Name:
-+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
-| Port Name | Pin/Bank | Buffer Type  | Site  | PG Enable | BC Enable | Properties                                                 |
-+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
-| CROW[0]   | 10/3     | LVTTL33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CROW[1]   | 16/3     | LVTTL33_IN   | PL6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[0]    | 3/3      | LVTTL33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[1]    | 96/0     | LVTTL33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[2]    | 88/0     | LVTTL33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[3]    | 97/0     | LVTTL33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[4]    | 99/0     | LVTTL33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[5]    | 98/0     | LVTTL33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[6]    | 2/3      | LVTTL33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[7]    | 1/3      | LVTTL33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 76/0     | LVTTL33_OUT  | PT11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[1]   | 86/0     | LVTTL33_OUT  | PT9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[2]   | 87/0     | LVTTL33_OUT  | PT9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[3]   | 85/0     | LVTTL33_OUT  | PT9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[4]   | 83/0     | LVTTL33_OUT  | PT10B |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[5]   | 84/0     | LVTTL33_OUT  | PT10A |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[6]   | 78/0     | LVTTL33_OUT  | PT11A |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[7]   | 82/0     | LVTTL33_OUT  | PT10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| LED       | 34/2     | LVTTL33_OUT  | PB6C  |           |           | DRIVE:16mA SLEW:SLOW                                       |
-| MAin[0]   | 14/3     | LVTTL33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[1]   | 12/3     | LVTTL33_IN   | PL5A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[2]   | 13/3     | LVTTL33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[3]   | 21/3     | LVTTL33_IN   | PL7B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[4]   | 20/3     | LVTTL33_IN   | PL7A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[5]   | 19/3     | LVTTL33_IN   | PL6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[6]   | 24/3     | LVTTL33_IN   | PL7C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[7]   | 18/3     | LVTTL33_IN   | PL6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[8]   | 25/3     | LVTTL33_IN   | PL7D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| MAin[9]   | 32/2     | LVTTL33_IN   | PB6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| PHI2      | 8/3      | LVTTL33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RA[0]     | 66/1     | LVTTL33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[10]    | 64/1     | LVTTL33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[11]    | 59/1     | LVTTL33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[1]     | 67/1     | LVTTL33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[2]     | 69/1     | LVTTL33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[3]     | 71/1     | LVTTL33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[4]     | 74/1     | LVTTL33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[5]     | 70/1     | LVTTL33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[6]     | 68/1     | LVTTL33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[7]     | 75/1     | LVTTL33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[8]     | 65/1     | LVTTL33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[9]     | 62/1     | LVTTL33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RBA[0]    | 58/1     | LVTTL33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RBA[1]    | 60/1     | LVTTL33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RCKE      | 53/1     | LVTTL33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RCLK      | 63/1     | LVTTL33_IN   | PR5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RDQMH     | 51/1     | LVTTL33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RDQML     | 48/2     | LVTTL33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RD[0]     | 36/2     | LVTTL33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[1]     | 37/2     | LVTTL33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[2]     | 38/2     | LVTTL33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[3]     | 39/2     | LVTTL33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[4]     | 40/2     | LVTTL33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[5]     | 41/2     | LVTTL33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[6]     | 42/2     | LVTTL33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[7]     | 43/2     | LVTTL33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| nCCAS     | 9/3      | LVTTL33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCRAS     | 17/3     | LVTTL33_IN   | PL6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nFWE      | 15/3     | LVTTL33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRCAS     | 52/1     | LVTTL33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRCS      | 57/1     | LVTTL33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRRAS     | 54/1     | LVTTL33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWE      | 49/2     | LVTTL33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    | 3.3V  |
-| 3    | 3.3V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
-| Pin/Bank | Pin Info              | Preference | Buffer Type  | Site  | Dual Function | PG Enable | BC Enable |
-+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
-| 1/3      | Din[7]                | LOCATED    | LVTTL33_IN   | PL2A  |               |           |           |
-| 2/3      | Din[6]                | LOCATED    | LVTTL33_IN   | PL2B  |               |           |           |
-| 3/3      | Din[0]                | LOCATED    | LVTTL33_IN   | PL2C  | PCLKT3_2      |           |           |
-| 4/3      |     unused, PULL:DOWN |            |              | PL2D  | PCLKC3_2      |           |           |
-| 7/3      |     unused, PULL:DOWN |            |              | PL3A  |               |           |           |
-| 8/3      | PHI2                  | LOCATED    | LVTTL33_IN   | PL3B  |               |           |           |
-| 9/3      | nCCAS                 | LOCATED    | LVTTL33_IN   | PL3C  |               |           |           |
-| 10/3     | CROW[0]               | LOCATED    | LVTTL33_IN   | PL3D  |               |           |           |
-| 12/3     | MAin[1]               | LOCATED    | LVTTL33_IN   | PL5A  | PCLKT3_1      |           |           |
-| 13/3     | MAin[2]               | LOCATED    | LVTTL33_IN   | PL5B  | PCLKC3_1      |           |           |
-| 14/3     | MAin[0]               | LOCATED    | LVTTL33_IN   | PL5C  |               |           |           |
-| 15/3     | nFWE                  | LOCATED    | LVTTL33_IN   | PL5D  |               |           |           |
-| 16/3     | CROW[1]               | LOCATED    | LVTTL33_IN   | PL6A  |               |           |           |
-| 17/3     | nCRAS                 | LOCATED    | LVTTL33_IN   | PL6B  |               |           |           |
-| 18/3     | MAin[7]               | LOCATED    | LVTTL33_IN   | PL6C  |               |           |           |
-| 19/3     | MAin[5]               | LOCATED    | LVTTL33_IN   | PL6D  |               |           |           |
-| 20/3     | MAin[4]               | LOCATED    | LVTTL33_IN   | PL7A  | PCLKT3_0      |           |           |
-| 21/3     | MAin[3]               | LOCATED    | LVTTL33_IN   | PL7B  | PCLKC3_0      |           |           |
-| 24/3     | MAin[6]               | LOCATED    | LVTTL33_IN   | PL7C  |               |           |           |
-| 25/3     | MAin[8]               | LOCATED    | LVTTL33_IN   | PL7D  |               |           |           |
-| 27/2     |     unused, PULL:DOWN |            |              | PB4A  | CSSPIN        |           |           |
-| 28/2     |     unused, PULL:DOWN |            |              | PB4B  |               |           |           |
-| 29/2     |     unused, PULL:DOWN |            |              | PB4C  |               |           |           |
-| 30/2     |     unused, PULL:DOWN |            |              | PB4D  |               |           |           |
-| 31/2     |     unused, PULL:DOWN |            |              | PB6A  | MCLK/CCLK     |           |           |
-| 32/2     | MAin[9]               | LOCATED    | LVTTL33_IN   | PB6B  | SO/SPISO      |           |           |
-| 34/2     | LED                   | LOCATED    | LVTTL33_OUT  | PB6C  | PCLKT2_0      |           |           |
-| 35/2     |     unused, PULL:DOWN |            |              | PB6D  | PCLKC2_0      |           |           |
-| 36/2     | RD[0]                 | LOCATED    | LVTTL33_BIDI | PB10A |               |           |           |
-| 37/2     | RD[1]                 | LOCATED    | LVTTL33_BIDI | PB10B |               |           |           |
-| 38/2     | RD[2]                 | LOCATED    | LVTTL33_BIDI | PB10C | PCLKT2_1      |           |           |
-| 39/2     | RD[3]                 | LOCATED    | LVTTL33_BIDI | PB10D | PCLKC2_1      |           |           |
-| 40/2     | RD[4]                 | LOCATED    | LVTTL33_BIDI | PB12A |               |           |           |
-| 41/2     | RD[5]                 | LOCATED    | LVTTL33_BIDI | PB12B |               |           |           |
-| 42/2     | RD[6]                 | LOCATED    | LVTTL33_BIDI | PB12C |               |           |           |
-| 43/2     | RD[7]                 | LOCATED    | LVTTL33_BIDI | PB12D |               |           |           |
-| 45/2     |     unused, PULL:DOWN |            |              | PB14A |               |           |           |
-| 47/2     |     unused, PULL:DOWN |            |              | PB14B |               |           |           |
-| 48/2     | RDQML                 | LOCATED    | LVTTL33_OUT  | PB14C | SN            |           |           |
-| 49/2     | nRWE                  | LOCATED    | LVTTL33_OUT  | PB14D | SI/SISPI      |           |           |
-| 51/1     | RDQMH                 | LOCATED    | LVTTL33_OUT  | PR7D  |               |           |           |
-| 52/1     | nRCAS                 | LOCATED    | LVTTL33_OUT  | PR7C  |               |           |           |
-| 53/1     | RCKE                  | LOCATED    | LVTTL33_OUT  | PR7B  |               |           |           |
-| 54/1     | nRRAS                 | LOCATED    | LVTTL33_OUT  | PR7A  |               |           |           |
-| 57/1     | nRCS                  | LOCATED    | LVTTL33_OUT  | PR6D  |               |           |           |
-| 58/1     | RBA[0]                | LOCATED    | LVTTL33_OUT  | PR6C  |               |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVTTL33_OUT  | PR6B  |               |           |           |
-| 60/1     | RBA[1]                | LOCATED    | LVTTL33_OUT  | PR6A  |               |           |           |
-| 62/1     | RA[9]                 | LOCATED    | LVTTL33_OUT  | PR5D  | PCLKC1_0      |           |           |
-| 63/1     | RCLK                  | LOCATED    | LVTTL33_IN   | PR5C  | PCLKT1_0      |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVTTL33_OUT  | PR5B  |               |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVTTL33_OUT  | PR5A  |               |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVTTL33_OUT  | PR3D  |               |           |           |
-| 67/1     | RA[1]                 | LOCATED    | LVTTL33_OUT  | PR3C  |               |           |           |
-| 68/1     | RA[6]                 | LOCATED    | LVTTL33_OUT  | PR3B  |               |           |           |
-| 69/1     | RA[2]                 | LOCATED    | LVTTL33_OUT  | PR3A  |               |           |           |
-| 70/1     | RA[5]                 | LOCATED    | LVTTL33_OUT  | PR2D  |               |           |           |
-| 71/1     | RA[3]                 | LOCATED    | LVTTL33_OUT  | PR2C  |               |           |           |
-| 74/1     | RA[4]                 | LOCATED    | LVTTL33_OUT  | PR2B  |               |           |           |
-| 75/1     | RA[7]                 | LOCATED    | LVTTL33_OUT  | PR2A  |               |           |           |
-| 76/0     | Dout[0]               | LOCATED    | LVTTL33_OUT  | PT11D | DONE          |           |           |
-| 77/0     |     unused, PULL:DOWN |            |              | PT11C | INITN         |           |           |
-| 78/0     | Dout[6]               | LOCATED    | LVTTL33_OUT  | PT11A |               |           |           |
-| 81/0     |     unused, PULL:DOWN |            |              | PT10D | PROGRAMN      |           |           |
-| 82/0     | Dout[7]               | LOCATED    | LVTTL33_OUT  | PT10C | JTAGENB       |           |           |
-| 83/0     | Dout[4]               | LOCATED    | LVTTL33_OUT  | PT10B |               |           |           |
-| 84/0     | Dout[5]               | LOCATED    | LVTTL33_OUT  | PT10A |               |           |           |
-| 85/0     | Dout[3]               | LOCATED    | LVTTL33_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
-| 86/0     | Dout[1]               | LOCATED    | LVTTL33_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
-| 87/0     | Dout[2]               | LOCATED    | LVTTL33_OUT  | PT9B  | PCLKC0_1      |           |           |
-| 88/0     | Din[2]                | LOCATED    | LVTTL33_IN   | PT9A  | PCLKT0_1      |           |           |
-| 90/0     | Reserved: sysCONFIG   |            |              | PT7D  | TMS           |           |           |
-| 91/0     | Reserved: sysCONFIG   |            |              | PT7C  | TCK           |           |           |
-| 94/0     | Reserved: sysCONFIG   |            |              | PT7B  | TDI           |           |           |
-| 95/0     | Reserved: sysCONFIG   |            |              | PT7A  | TDO           |           |           |
-| 96/0     | Din[1]                | LOCATED    | LVTTL33_IN   | PT6D  |               |           |           |
-| 97/0     | Din[3]                | LOCATED    | LVTTL33_IN   | PT6C  |               |           |           |
-| 98/0     | Din[5]                | LOCATED    | LVTTL33_IN   | PT6B  |               |           |           |
-| 99/0     | Din[4]                | LOCATED    | LVTTL33_IN   | PT6A  |               |           |           |
-| PT11B/0  |     unused, PULL:DOWN |            |              | PT11B |               |           |           |
-+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
-
-sysCONFIG Pins:
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
-| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
-| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
-| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-
-Dedicated sysCONFIG Pins:
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "10";
-LOCATE  COMP  "CROW[1]"  SITE  "16";
-LOCATE  COMP  "Din[0]"  SITE  "3";
-LOCATE  COMP  "Din[1]"  SITE  "96";
-LOCATE  COMP  "Din[2]"  SITE  "88";
-LOCATE  COMP  "Din[3]"  SITE  "97";
-LOCATE  COMP  "Din[4]"  SITE  "99";
-LOCATE  COMP  "Din[5]"  SITE  "98";
-LOCATE  COMP  "Din[6]"  SITE  "2";
-LOCATE  COMP  "Din[7]"  SITE  "1";
-LOCATE  COMP  "Dout[0]"  SITE  "76";
-LOCATE  COMP  "Dout[1]"  SITE  "86";
-LOCATE  COMP  "Dout[2]"  SITE  "87";
-LOCATE  COMP  "Dout[3]"  SITE  "85";
-LOCATE  COMP  "Dout[4]"  SITE  "83";
-LOCATE  COMP  "Dout[5]"  SITE  "84";
-LOCATE  COMP  "Dout[6]"  SITE  "78";
-LOCATE  COMP  "Dout[7]"  SITE  "82";
-LOCATE  COMP  "LED"  SITE  "34";
-LOCATE  COMP  "MAin[0]"  SITE  "14";
-LOCATE  COMP  "MAin[1]"  SITE  "12";
-LOCATE  COMP  "MAin[2]"  SITE  "13";
-LOCATE  COMP  "MAin[3]"  SITE  "21";
-LOCATE  COMP  "MAin[4]"  SITE  "20";
-LOCATE  COMP  "MAin[5]"  SITE  "19";
-LOCATE  COMP  "MAin[6]"  SITE  "24";
-LOCATE  COMP  "MAin[7]"  SITE  "18";
-LOCATE  COMP  "MAin[8]"  SITE  "25";
-LOCATE  COMP  "MAin[9]"  SITE  "32";
-LOCATE  COMP  "PHI2"  SITE  "8";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "67";
-LOCATE  COMP  "RA[2]"  SITE  "69";
-LOCATE  COMP  "RA[3]"  SITE  "71";
-LOCATE  COMP  "RA[4]"  SITE  "74";
-LOCATE  COMP  "RA[5]"  SITE  "70";
-LOCATE  COMP  "RA[6]"  SITE  "68";
-LOCATE  COMP  "RA[7]"  SITE  "75";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "62";
-LOCATE  COMP  "RBA[0]"  SITE  "58";
-LOCATE  COMP  "RBA[1]"  SITE  "60";
-LOCATE  COMP  "RCKE"  SITE  "53";
-LOCATE  COMP  "RCLK"  SITE  "63";
-LOCATE  COMP  "RDQMH"  SITE  "51";
-LOCATE  COMP  "RDQML"  SITE  "48";
-LOCATE  COMP  "RD[0]"  SITE  "36";
-LOCATE  COMP  "RD[1]"  SITE  "37";
-LOCATE  COMP  "RD[2]"  SITE  "38";
-LOCATE  COMP  "RD[3]"  SITE  "39";
-LOCATE  COMP  "RD[4]"  SITE  "40";
-LOCATE  COMP  "RD[5]"  SITE  "41";
-LOCATE  COMP  "RD[6]"  SITE  "42";
-LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "nCCAS"  SITE  "9";
-LOCATE  COMP  "nCRAS"  SITE  "17";
-LOCATE  COMP  "nFWE"  SITE  "15";
-LOCATE  COMP  "nRCAS"  SITE  "52";
-LOCATE  COMP  "nRCS"  SITE  "57";
-LOCATE  COMP  "nRRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "49";
-
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-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Sat Oct 09 01:19:22 2021
-
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html deleted file mode 100644 index 087b477..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -

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RAM2GS_LCMXO2_640HC project summary
Module Name:RAM2GS_LCMXO2_640HCSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:I/O Timing Analysis State:Passed
Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-640HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2GS_LCMXO2_640HC.lpf
Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prf
Product Version:3.12.0.240.2Patch Version:
Updated:2021/10/09 01:19:25
Implementation Location:C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1
Project File:C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf

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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html deleted file mode 100644 index e259dcf..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html +++ /dev/null @@ -1,2780 +0,0 @@ - -Lattice Map TRACE Report - - -
Map TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Sat Oct 09 01:19:15 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-VCCIO Voltage:
-                   3.135 V (Bank 0)
-                   3.135 V (Bank 1)
-                   3.135 V (Bank 2)
-                   3.135 V (Bank 3)
-                   2.375 V (Bank 4)
-                   2.375 V (Bank 5)
-                   2.375 V (Bank 6)
-                   2.375 V (Bank 7)
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            121 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
-
-   Delay:              13.035ns  (30.0% logic, 70.0% route), 8 logic levels.
-
- Constraint Details:
-
-     13.035ns physical path delay SLICE_111 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452  SLICE_111.CLK to   SLICE_111.Q1 SLICE_111 (from PHI2_c)
-ROUTE         1   e 1.234   SLICE_111.Q1 to   SLICE_158.B0 Bank_5
-CTOF_DEL    ---     0.495   SLICE_158.B0 to   SLICE_158.F0 SLICE_158
-ROUTE         1   e 1.234   SLICE_158.F0 to   SLICE_139.B0 n4610
-CTOF_DEL    ---     0.495   SLICE_139.B0 to   SLICE_139.F0 SLICE_139
-ROUTE         2   e 1.234   SLICE_139.F0 to   SLICE_114.B1 n4628
-CTOF_DEL    ---     0.495   SLICE_114.B1 to   SLICE_114.F1 SLICE_114
-ROUTE         4   e 1.234   SLICE_114.F1 to   SLICE_116.B1 n2384
-CTOF_DEL    ---     0.495   SLICE_116.B1 to   SLICE_116.F1 SLICE_116
-ROUTE         2   e 0.480   SLICE_116.F1 to   SLICE_116.D0 n4888
-CTOF_DEL    ---     0.495   SLICE_116.D0 to   SLICE_116.F0 SLICE_116
-ROUTE         1   e 1.234   SLICE_116.F0 to    SLICE_19.B1 n4624
-CTOF_DEL    ---     0.495    SLICE_19.B1 to    SLICE_19.F1 SLICE_19
-ROUTE         4   e 1.234    SLICE_19.F1 to   SLICE_130.C0 C1Submitted_N_232
-CTOF_DEL    ---     0.495   SLICE_130.C0 to   SLICE_130.F0 SLICE_130
-ROUTE         1   e 1.234   SLICE_130.F0 to    SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c)
-                  --------
-                   13.035   (30.0% logic, 70.0% route), 8 logic levels.
-
-Report:   26.684ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 347.500ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            SLICE_122
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:    2.500ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 347.500ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            SLICE_25
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:    2.500ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            1409 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 2.077ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              13.757ns  (33.7% logic, 66.3% route), 9 logic levels.
-
- Constraint Details:
-
-     13.757ns physical path delay SLICE_5 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_5.CLK to     SLICE_5.Q1 SLICE_5 (from RCLK_c)
-ROUTE        23   e 1.234     SLICE_5.Q1 to    SLICE_98.B1 FS_8
-CTOF_DEL    ---     0.495    SLICE_98.B1 to    SLICE_98.F1 SLICE_98
-ROUTE         4   e 1.234    SLICE_98.F1 to    SLICE_93.B1 n4924
-CTOF_DEL    ---     0.495    SLICE_93.B1 to    SLICE_93.F1 SLICE_93
-ROUTE         1   e 1.234    SLICE_93.F1 to   SLICE_133.D0 n98
-CTOF_DEL    ---     0.495   SLICE_133.D0 to   SLICE_133.F0 SLICE_133
-ROUTE         2   e 0.480   SLICE_133.F0 to   SLICE_133.B1 n2199
-CTOF_DEL    ---     0.495   SLICE_133.B1 to   SLICE_133.F1 SLICE_133
-ROUTE         1   e 1.234   SLICE_133.F1 to *9/SLICE_84.C1 n53
-CTOOFX_DEL  ---     0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84
-ROUTE         1   e 1.234 *SLICE_84.OFX0 to   SLICE_148.C1 n14_adj_3
-CTOF_DEL    ---     0.495   SLICE_148.C1 to   SLICE_148.F1 SLICE_148
-ROUTE         2   e 1.234   SLICE_148.F1 to   SLICE_135.C0 n12_adj_8
-CTOF_DEL    ---     0.495   SLICE_135.C0 to   SLICE_135.F0 SLICE_135
-ROUTE         2   e 1.234   SLICE_135.F0 to    SLICE_70.A1 n14_adj_7
-CTOF_DEL    ---     0.495    SLICE_70.A1 to    SLICE_70.F1 SLICE_70
-ROUTE         1   e 0.001    SLICE_70.F1 to   SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   13.757   (33.7% logic, 66.3% route), 9 logic levels.
-
-Report:   13.923ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_536  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_54 and
-      5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets
-     12.500ns offset RCLK to RA[10] by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_54.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_54 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
-ROUTE         1   e 1.234    SLICE_54.Q0 to       64.PADDO n1975
-DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[9] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
-ROUTE         1   e 1.234   SLICE_151.F0 to       62.PADDO RA_c_9
-DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[8] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
-ROUTE         1   e 1.234   SLICE_163.F1 to       65.PADDO RA_c_8
-DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[7] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
-ROUTE         1   e 1.234   SLICE_155.F1 to       75.PADDO RA_c_7
-DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[6] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
-ROUTE         1   e 1.234   SLICE_163.F0 to       68.PADDO RA_c_6
-DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[5] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
-ROUTE         1   e 1.234   SLICE_157.F1 to       70.PADDO RA_c_5
-DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[4] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
-ROUTE         1   e 1.234   SLICE_158.F1 to       74.PADDO RA_c_4
-DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[3] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
-ROUTE         1   e 1.234   SLICE_162.F0 to       71.PADDO RA_c_3
-DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[2] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
-ROUTE         1   e 1.234   SLICE_161.F0 to       69.PADDO RA_c_2
-DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[1] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
-ROUTE         1   e 1.234   SLICE_162.F1 to       67.PADDO RA_c_1
-DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets
-     12.500ns offset RCLK to RA[0] by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
-ROUTE         1   e 1.234   SLICE_159.F1 to       66.PADDO RA_c_0
-DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_532  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_59 and
-      5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets
-     12.500ns offset RCLK to nRCS by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_59:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_59.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_59 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
-ROUTE         1   e 1.234    SLICE_59.Q0 to       57.PADDO nRCS_c
-DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_531  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_35 and
-      5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets
-     12.500ns offset RCLK to RCKE by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_35.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_35 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
-ROUTE         4   e 1.234    SLICE_35.Q0 to       53.PADDO RCKE_c
-DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_535  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_62 and
-      5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets
-     12.500ns offset RCLK to nRWE by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_62:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_62.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_62 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
-ROUTE         1   e 1.234    SLICE_62.Q0 to       49.PADDO nRWE_c
-DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_60 and
-      5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets
-     12.500ns offset RCLK to nRRAS by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_60 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 1.234    SLICE_60.Q0 to       54.PADDO nRRAS_c
-DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.343ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.791ns  (78.7% logic, 21.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_57 and
-      5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets
-     12.500ns offset RCLK to nRCAS by 4.343ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_57.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_57 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
-ROUTE         1   e 1.234    SLICE_57.Q0 to       52.PADDO nRCAS_c
-DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
-                  --------
-                    5.791   (78.7% logic, 21.3% route), 2 logic levels.
-
-Report:    8.157ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets
-     12.500ns offset RCLK to RDQMH by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
-ROUTE         1   e 1.234   SLICE_151.F1 to       51.PADDO RDQMH_c
-DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.614ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.520ns  (67.2% logic, 32.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.366ns  (47.8% logic, 52.2% route), 1 logic levels.
-
- Constraint Details:
-      2.366ns delay RCLK to SLICE_63 and
-      7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets
-     12.500ns offset RCLK to RDQML by 2.614ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 1.234       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.366   (47.8% logic, 52.2% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 1.234    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
-CTOF_DEL    ---     0.495   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
-ROUTE         1   e 1.234   SLICE_161.F1 to       48.PADDO RDQML_c
-DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
-                  --------
-                    7.520   (67.2% logic, 32.8% route), 3 logic levels.
-
-Report:    9.886ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.684 ns|   8  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    13.923 ns|   9  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.157 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.886 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 5 clocks:
-
-Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
-   No transfer within this clock domain is found
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: wb_clk   Source: SLICE_73.Q0
-      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
-
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Sat Oct 09 01:19:15 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-VCCIO Voltage:
-                   3.135 V (Bank 0)
-                   3.135 V (Bank 1)
-                   3.135 V (Bank 2)
-                   3.135 V (Bank 3)
-                   2.375 V (Bank 4)
-                   2.375 V (Bank 5)
-                   2.375 V (Bank 6)
-                   2.375 V (Bank 7)
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            121 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.D0 C1Submitted
-CTOF_DEL    ---     0.101    SLICE_15.D0 to    SLICE_15.F0 SLICE_15
-ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n2549 (to PHI2_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            1409 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.332ns physical path delay SLICE_118 to SLICE_118 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
-
- Physical Path Details:
-
-      Data path SLICE_118 to SLICE_118:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133  SLICE_118.CLK to   SLICE_118.Q0 SLICE_118 (from RCLK_c)
-ROUTE         1   e 0.199   SLICE_118.Q0 to   SLICE_118.M1 n1197 (to RCLK_c)
-                  --------
-                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_536  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_54 and
-      2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to RA[10] by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_54.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_54 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_54.CLK to    SLICE_54.Q0 SLICE_54 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_54.Q0 to       64.PADDO n1975
-DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[9] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.C0 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_151.C0 to   SLICE_151.F0 SLICE_151
-ROUTE         1   e 0.515   SLICE_151.F0 to       62.PADDO RA_c_9
-DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[8] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_163.C1 to   SLICE_163.F1 SLICE_163
-ROUTE         1   e 0.515   SLICE_163.F1 to       65.PADDO RA_c_8
-DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[7] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_155.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_155.C1 to   SLICE_155.F1 SLICE_155
-ROUTE         1   e 0.515   SLICE_155.F1 to       75.PADDO RA_c_7
-DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[6] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_163.C0 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_163.C0 to   SLICE_163.F0 SLICE_163
-ROUTE         1   e 0.515   SLICE_163.F0 to       68.PADDO RA_c_6
-DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[5] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_157.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_157.C1 to   SLICE_157.F1 SLICE_157
-ROUTE         1   e 0.515   SLICE_157.F1 to       70.PADDO RA_c_5
-DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[4] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_158.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_158.C1 to   SLICE_158.F1 SLICE_158
-ROUTE         1   e 0.515   SLICE_158.F1 to       74.PADDO RA_c_4
-DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[3] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C0 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_162.C0 to   SLICE_162.F0 SLICE_162
-ROUTE         1   e 0.515   SLICE_162.F0 to       71.PADDO RA_c_3
-DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[2] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.C0 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_161.C0 to   SLICE_161.F0 SLICE_161
-ROUTE         1   e 0.515   SLICE_161.F0 to       69.PADDO RA_c_2
-DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[1] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_162.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_162.C1 to   SLICE_162.F1 SLICE_162
-ROUTE         1   e 0.515   SLICE_162.F1 to       67.PADDO RA_c_1
-DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RA[0] by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_159.C1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_159.C1 to   SLICE_159.F1 SLICE_159
-ROUTE         1   e 0.515   SLICE_159.F1 to       66.PADDO RA_c_0
-DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_532  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_59 and
-      2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to nRCS by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_59:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_59.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_59 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_59.CLK to    SLICE_59.Q0 SLICE_59 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_59.Q0 to       57.PADDO nRCS_c
-DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_531  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_35 and
-      2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to RCKE by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_35.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_35 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_35.CLK to    SLICE_35.Q0 SLICE_35 (from RCLK_c)
-ROUTE         4   e 0.515    SLICE_35.Q0 to       53.PADDO RCKE_c
-DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_535  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_62 and
-      2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to nRWE by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_62:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_62.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_62 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_62.CLK to    SLICE_62.Q0 SLICE_62 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_62.Q0 to       49.PADDO nRWE_c
-DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_60 and
-      2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to nRRAS by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_60 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_60.Q0 to       54.PADDO nRRAS_c
-DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     2.321ns  (77.8% logic, 22.2% route), 2 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_57 and
-      2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets
-      0.000ns hold offset RCLK to nRCAS by 3.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_57.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_57 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_57.CLK to    SLICE_57.Q0 SLICE_57 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_57.Q0 to       52.PADDO nRCAS_c
-DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
-                  --------
-                    2.321   (77.8% logic, 22.2% route), 2 logic levels.
-
-Report:    3.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RDQMH by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_151.B1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_151.B1 to   SLICE_151.F1 SLICE_151
-ROUTE         1   e 0.515   SLICE_151.F1 to       51.PADDO RDQMH_c
-DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.900ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.937ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.963ns  (46.5% logic, 53.5% route), 1 logic levels.
-
- Constraint Details:
-      0.963ns delay RCLK to SLICE_63 and
-      2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets
-      0.000ns hold offset RCLK to RDQML by 3.900ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52   e 0.515       63.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.963   (46.5% logic, 53.5% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12   e 0.515    SLICE_63.Q0 to   SLICE_161.B1 nRowColSel
-CTOF_DEL    ---     0.101   SLICE_161.B1 to   SLICE_161.F1 SLICE_161
-ROUTE         1   e 0.515   SLICE_161.F1 to       48.PADDO RDQML_c
-DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
-                  --------
-                    2.937   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    3.900ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.284 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.900 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 5 clocks:
-
-Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
-   No transfer within this clock domain is found
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: wb_clk   Source: SLICE_73.Q0
-      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
-
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
-
-
-
    
-
    
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-
    
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-
    
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-
    
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-
    
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-
    
-
    - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html deleted file mode 100644 index 22dc62a..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html +++ /dev/null @@ -1,4699 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Sat Oct 09 01:19:23 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-VCCIO Voltage:
-                   3.135 V (Bank 0)
-                   3.135 V (Bank 1)
-                   3.135 V (Bank 2)
-                   3.135 V (Bank 3)
-                   2.375 V (Bank 4)
-                   2.375 V (Bank 5)
-                   2.375 V (Bank 6)
-                   2.375 V (Bank 7)
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            121 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
-
- Constraint Details:
-
-     12.593ns physical path delay SLICE_151 to SLICE_20 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
-
- Physical Path Details:
-
-      Data path SLICE_151 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
-ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
-CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_151:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.100ns (weighted slack = 324.200ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:              12.593ns  (31.1% logic, 68.9% route), 8 logic levels.
-
- Constraint Details:
-
-     12.593ns physical path delay SLICE_151 to SLICE_24 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.100ns
-
- Physical Path Details:
-
-      Data path SLICE_151 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
-ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
-CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.593   (31.1% logic, 68.9% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_151:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
-
- Constraint Details:
-
-     12.319ns physical path delay SLICE_111 to SLICE_20 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
-ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
-CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_111:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.374ns (weighted slack = 324.748ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:              12.319ns  (31.8% logic, 68.2% route), 8 logic levels.
-
- Constraint Details:
-
-     12.319ns physical path delay SLICE_111 to SLICE_24 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.374ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
-ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
-CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.319   (31.8% logic, 68.2% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_111:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
-
- Constraint Details:
-
-     12.282ns physical path delay SLICE_111 to SLICE_20 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
-ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
-CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_111:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.411ns (weighted slack = 324.822ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:              12.282ns  (31.9% logic, 68.1% route), 8 logic levels.
-
- Constraint Details:
-
-     12.282ns physical path delay SLICE_111 to SLICE_24 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 162.411ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_111 (from PHI2_c)
-ROUTE         1     0.967       R2C8C.Q1 to       R2C8B.A0 Bank_5
-CTOF_DEL    ---     0.495       R2C8B.A0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   12.282   (31.9% logic, 68.1% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_111:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.336ns (weighted slack = 326.672ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
-
-   Delay:              11.357ns  (34.5% logic, 65.5% route), 8 logic levels.
-
- Constraint Details:
-
-     11.357ns physical path delay SLICE_151 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 163.336ns
-
- Physical Path Details:
-
-      Data path SLICE_151 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_151 (from PHI2_c)
-ROUTE         1     1.278       R5C9B.Q0 to       R2C8B.C0 Bank_6
-CTOF_DEL    ---     0.495       R2C8B.C0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
-CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
-ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
-CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
-ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
-CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
-ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
-CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
-ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
-                  --------
-                   11.357   (34.5% logic, 65.5% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_151:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
-
- Constraint Details:
-
-     11.183ns physical path delay SLICE_151 to SLICE_20 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
-
- Physical Path Details:
-
-      Data path SLICE_151 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
-ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
-CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
-ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
-CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_151:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.510ns (weighted slack = 327.020ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:              11.183ns  (35.0% logic, 65.0% route), 8 logic levels.
-
- Constraint Details:
-
-     11.183ns physical path delay SLICE_151 to SLICE_24 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 163.510ns
-
- Physical Path Details:
-
-      Data path SLICE_151 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_151 (from PHI2_c)
-ROUTE         1     0.967       R5C9B.Q1 to       R5C9D.A1 Bank_7
-CTOF_DEL    ---     0.495       R5C9D.A1 to       R5C9D.F1 SLICE_139
-ROUTE         1     0.436       R5C9D.F1 to       R5C9D.C0 n4574
-CTOF_DEL    ---     0.495       R5C9D.C0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.788       R2C9D.F1 to       R3C9D.C1 n2384
-CTOF_DEL    ---     0.495       R3C9D.C1 to       R3C9D.F1 SLICE_130
-ROUTE         2     0.995       R3C9D.F1 to       R4C9B.A0 n4889
-CTOF_DEL    ---     0.495       R4C9B.A0 to       R4C9B.F0 SLICE_21
-ROUTE         4     1.474       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.495       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.436       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     1.084       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                   11.183   (35.0% logic, 65.0% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_151:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R5C6B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.610ns (weighted slack = 327.220ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
-
-   Delay:              11.083ns  (35.3% logic, 64.7% route), 8 logic levels.
-
- Constraint Details:
-
-     11.083ns physical path delay SLICE_111 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.307ns CE_SET requirement (totaling 174.693ns) by 163.610ns
-
- Physical Path Details:
-
-      Data path SLICE_111 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_111 (from PHI2_c)
-ROUTE         1     1.004       R2C8C.Q0 to       R2C8B.B0 Bank_4
-CTOF_DEL    ---     0.495       R2C8B.B0 to       R2C8B.F0 SLICE_158
-ROUTE         1     1.535       R2C8B.F0 to       R5C9D.B0 n4610
-CTOF_DEL    ---     0.495       R5C9D.B0 to       R5C9D.F0 SLICE_139
-ROUTE         2     1.086       R5C9D.F0 to       R2C9D.C1 n4628
-CTOF_DEL    ---     0.495       R2C9D.C1 to       R2C9D.F1 SLICE_114
-ROUTE         4     0.756       R2C9D.F1 to       R2C9B.C1 n2384
-CTOF_DEL    ---     0.495       R2C9B.C1 to       R2C9B.F1 SLICE_116
-ROUTE         2     0.445       R2C9B.F1 to       R2C9B.C0 n4888
-CTOF_DEL    ---     0.495       R2C9B.C0 to       R2C9B.F0 SLICE_116
-ROUTE         1     0.645       R2C9B.F0 to       R3C9A.D1 n4624
-CTOF_DEL    ---     0.495       R3C9A.D1 to       R3C9A.F1 SLICE_19
-ROUTE         4     1.042       R3C9A.F1 to       R3C9D.B0 C1Submitted_N_232
-CTOF_DEL    ---     0.495       R3C9D.B0 to       R3C9D.F0 SLICE_130
-ROUTE         1     0.653       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
-                  --------
-                   11.083   (35.3% logic, 64.7% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_111:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R2C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.539        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   25.800ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 347.500ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            SLICE_122
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:    2.500ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 347.500ns
-         The internal maximum frequency of the following component is 400.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            SLICE_25
-
-   Delay:               2.500ns -- based on Minimum Pulse Width
-
-Report:    2.500ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            1409 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 3.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
-
- Constraint Details:
-
-     12.261ns physical path delay SLICE_6 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
-ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
-CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
-ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
-CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
-ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 3.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
-
-   Delay:              12.261ns  (37.8% logic, 62.2% route), 9 logic levels.
-
- Constraint Details:
-
-     12.261ns physical path delay SLICE_6 to SLICE_72 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 3.573ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
-ROUTE        21     1.808       R6C6D.Q1 to       R3C7A.B1 FS_6
-CTOF_DEL    ---     0.495       R3C7A.B1 to       R3C7A.F1 SLICE_98
-ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
-CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
-ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
-                  --------
-                   12.261   (37.8% logic, 62.2% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.370ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
-
- Constraint Details:
-
-     11.464ns physical path delay SLICE_5 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
-ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
-CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
-ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
-CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
-ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
-ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.370ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i7  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
-
-   Delay:              11.464ns  (36.1% logic, 63.9% route), 8 logic levels.
-
- Constraint Details:
-
-     11.464ns physical path delay SLICE_5 to SLICE_72 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.370ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
-ROUTE        25     2.442       R6C7A.Q0 to       R2C8D.C1 FS_7
-CTOF_DEL    ---     0.495       R2C8D.C1 to       R2C8D.F1 SLICE_143
-ROUTE         2     1.427       R2C8D.F1 to       R2C6A.B1 n4915
-CTOF_DEL    ---     0.495       R2C6A.B1 to       R2C6A.F1 SLICE_113
-ROUTE         5     0.672       R2C6A.F1 to       R2C7D.D1 n4890
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
-ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
-                  --------
-                   11.464   (36.1% logic, 63.9% route), 8 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.376ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
-
- Constraint Details:
-
-     11.458ns physical path delay SLICE_5 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
-ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
-CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
-ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
-CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
-ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.376ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i8  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
-
-   Delay:              11.458ns  (40.5% logic, 59.5% route), 9 logic levels.
-
- Constraint Details:
-
-     11.458ns physical path delay SLICE_5 to SLICE_72 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.376ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q1 SLICE_5 (from RCLK_c)
-ROUTE        23     1.005       R6C7A.Q1 to       R3C7A.D1 FS_8
-CTOF_DEL    ---     0.495       R3C7A.D1 to       R3C7A.F1 SLICE_98
-ROUTE         4     1.021       R3C7A.F1 to       R3C7D.B1 n4924
-CTOF_DEL    ---     0.495       R3C7D.B1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
-ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
-                  --------
-                   11.458   (40.5% logic, 59.5% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C7A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.398ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
-
- Constraint Details:
-
-     11.436ns physical path delay SLICE_6 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
-ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
-CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
-ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
-CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
-ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.398ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i6  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
-
-   Delay:              11.436ns  (40.6% logic, 59.4% route), 9 logic levels.
-
- Constraint Details:
-
-     11.436ns physical path delay SLICE_6 to SLICE_72 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.398ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q1 SLICE_6 (from RCLK_c)
-ROUTE        21     1.551       R6C6D.Q1 to       R3C7D.C0 FS_6
-CTOF_DEL    ---     0.495       R3C7D.C0 to       R3C7D.F0 SLICE_93
-ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
-CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
-ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
-                  --------
-                   11.436   (40.6% logic, 59.4% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.449ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i4  (to RCLK_c +)
-
-   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
-
- Constraint Details:
-
-     11.385ns physical path delay SLICE_6 to SLICE_70 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
-ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
-CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
-ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
-CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3A.D1 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3A.D1 to       R2C3A.F1 SLICE_70
-ROUTE         1     0.000       R2C3A.F1 to      R2C3A.DI1 wb_adr_7_N_60_4 (to RCLK_c)
-                  --------
-                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_70:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3A.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 4.449ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i5  (from RCLK_c +)
-   Destination:    FF         Data in        wb_adr_i6  (to RCLK_c +)
-
-   Delay:              11.385ns  (40.7% logic, 59.3% route), 9 logic levels.
-
- Constraint Details:
-
-     11.385ns physical path delay SLICE_6 to SLICE_72 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 15.834ns) by 4.449ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C6D.CLK to       R6C6D.Q0 SLICE_6 (from RCLK_c)
-ROUTE        21     1.500       R6C6D.Q0 to       R3C7D.D0 FS_5
-CTOF_DEL    ---     0.495       R3C7D.D0 to       R3C7D.F0 SLICE_93
-ROUTE         3     0.453       R3C7D.F0 to       R3C7D.C1 n53_adj_9
-CTOF_DEL    ---     0.495       R3C7D.C1 to       R3C7D.F1 SLICE_93
-ROUTE         1     1.001       R3C7D.F1 to       R2C7D.B0 n98
-CTOF_DEL    ---     0.495       R2C7D.B0 to       R2C7D.F0 SLICE_133
-ROUTE         2     1.013       R2C7D.F0 to       R2C7D.B1 n2199
-CTOF_DEL    ---     0.495       R2C7D.B1 to       R2C7D.F1 SLICE_133
-ROUTE         1     0.747       R2C7D.F1 to       R2C7A.C1 n53
-CTOOFX_DEL  ---     0.721       R2C7A.C1 to     R2C7A.OFX0 i29/SLICE_84
-ROUTE         1     0.744     R2C7A.OFX0 to       R2C6C.C1 n14_adj_3
-CTOF_DEL    ---     0.495       R2C6C.C1 to       R2C6C.F1 SLICE_148
-ROUTE         2     0.637       R2C6C.F1 to       R2C5D.D0 n12_adj_8
-CTOF_DEL    ---     0.495       R2C5D.D0 to       R2C5D.F0 SLICE_135
-ROUTE         2     0.652       R2C5D.F0 to       R2C3D.D0 n14_adj_7
-CTOF_DEL    ---     0.495       R2C3D.D0 to       R2C3D.F0 SLICE_72
-ROUTE         1     0.000       R2C3D.F0 to      R2C3D.DI0 wb_adr_7_N_60_6 (to RCLK_c)
-                  --------
-                   11.385   (40.7% logic, 59.3% route), 9 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R6C6D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     2.019       63.PADDI to      R2C3D.CLK RCLK_c
-                  --------
-                    2.019   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   12.427ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.015ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_536  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     6.334ns  (71.9% logic, 28.1% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_54 and
-      6.334ns delay SLICE_54 to RA[10] (totaling 9.485ns) meets
-     12.500ns offset RCLK to RA[10] by 3.015ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R4C11D.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_54 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
-ROUTE         1     1.777      R4C11D.Q0 to       64.PADDO n1975
-DOPAD_DEL   ---     4.105       64.PADDO to         64.PAD RA[10]
-                  --------
-                    6.334   (71.9% logic, 28.1% route), 2 logic levels.
-
-Report:    9.485ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.495ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.854ns  (64.3% logic, 35.7% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.854ns delay SLICE_63 to RA[9] (totaling 11.005ns) meets
-     12.500ns offset RCLK to RA[9] by 1.495ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.016      R5C10A.Q0 to       R5C9B.A0 nRowColSel
-CTOF_DEL    ---     0.495       R5C9B.A0 to       R5C9B.F0 SLICE_151
-ROUTE         1     1.786       R5C9B.F0 to       62.PADDO RA_c_9
-DOPAD_DEL   ---     4.105       62.PADDO to         62.PAD RA[9]
-                  --------
-                    7.854   (64.3% logic, 35.7% route), 3 logic levels.
-
-Report:   11.005ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.386ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.963ns  (63.4% logic, 36.6% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.963ns delay SLICE_63 to RA[8] (totaling 11.114ns) meets
-     12.500ns offset RCLK to RA[8] by 1.386ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B1 nRowColSel
-CTOF_DEL    ---     0.495      R4C10D.B1 to      R4C10D.F1 SLICE_163
-ROUTE         1     1.858      R4C10D.F1 to       65.PADDO RA_c_8
-DOPAD_DEL   ---     4.105       65.PADDO to         65.PAD RA[8]
-                  --------
-                    7.963   (63.4% logic, 36.6% route), 3 logic levels.
-
-Report:   11.114ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.552ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.797ns  (64.8% logic, 35.2% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.797ns delay SLICE_63 to RA[7] (totaling 10.948ns) meets
-     12.500ns offset RCLK to RA[7] by 1.552ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.017      R5C10A.Q0 to      R2C10D.D1 nRowColSel
-CTOF_DEL    ---     0.495      R2C10D.D1 to      R2C10D.F1 SLICE_155
-ROUTE         1     1.728      R2C10D.F1 to       75.PADDO RA_c_7
-DOPAD_DEL   ---     4.105       75.PADDO to         75.PAD RA[7]
-                  --------
-                    7.797   (64.8% logic, 35.2% route), 3 logic levels.
-
-Report:   10.948ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.401ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.948ns  (63.6% logic, 36.4% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.948ns delay SLICE_63 to RA[6] (totaling 11.099ns) meets
-     12.500ns offset RCLK to RA[6] by 1.401ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.053      R5C10A.Q0 to      R4C10D.B0 nRowColSel
-CTOF_DEL    ---     0.495      R4C10D.B0 to      R4C10D.F0 SLICE_163
-ROUTE         1     1.843      R4C10D.F0 to       68.PADDO RA_c_6
-DOPAD_DEL   ---     4.105       68.PADDO to         68.PAD RA[6]
-                  --------
-                    7.948   (63.6% logic, 36.4% route), 3 logic levels.
-
-Report:   11.099ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.135ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      8.214ns delay SLICE_63 to RA[5] (totaling 11.365ns) meets
-     12.500ns offset RCLK to RA[5] by 1.135ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.310      R5C10A.Q0 to       R2C9A.C1 nRowColSel
-CTOF_DEL    ---     0.495       R2C9A.C1 to       R2C9A.F1 SLICE_157
-ROUTE         1     1.852       R2C9A.F1 to       70.PADDO RA_c_5
-DOPAD_DEL   ---     4.105       70.PADDO to         70.PAD RA[5]
-                  --------
-                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
-
-Report:   11.365ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.135ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     8.214ns  (61.5% logic, 38.5% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      8.214ns delay SLICE_63 to RA[4] (totaling 11.365ns) meets
-     12.500ns offset RCLK to RA[4] by 1.135ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.310      R5C10A.Q0 to       R2C8B.C1 nRowColSel
-CTOF_DEL    ---     0.495       R2C8B.C1 to       R2C8B.F1 SLICE_158
-ROUTE         1     1.852       R2C8B.F1 to       74.PADDO RA_c_4
-DOPAD_DEL   ---     4.105       74.PADDO to         74.PAD RA[4]
-                  --------
-                    8.214   (61.5% logic, 38.5% route), 3 logic levels.
-
-Report:   11.365ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.322ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     8.027ns  (62.9% logic, 37.1% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      8.027ns delay SLICE_63 to RA[3] (totaling 11.178ns) meets
-     12.500ns offset RCLK to RA[3] by 1.322ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D0 nRowColSel
-CTOF_DEL    ---     0.495      R3C10C.D0 to      R3C10C.F0 SLICE_162
-ROUTE         1     1.985      R3C10C.F0 to       71.PADDO RA_c_3
-DOPAD_DEL   ---     4.105       71.PADDO to         71.PAD RA[3]
-                  --------
-                    8.027   (62.9% logic, 37.1% route), 3 logic levels.
-
-Report:   11.178ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.577ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.772ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.772ns delay SLICE_63 to RA[2] (totaling 10.923ns) meets
-     12.500ns offset RCLK to RA[2] by 1.577ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C0 nRowColSel
-CTOF_DEL    ---     0.495       R5C9C.C0 to       R5C9C.F0 SLICE_161
-ROUTE         1     1.924       R5C9C.F0 to       69.PADDO RA_c_2
-DOPAD_DEL   ---     4.105       69.PADDO to         69.PAD RA[2]
-                  --------
-                    7.772   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:   10.923ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.579ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.770ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.770ns delay SLICE_63 to RA[1] (totaling 10.921ns) meets
-     12.500ns offset RCLK to RA[1] by 1.579ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.990      R5C10A.Q0 to      R3C10C.D1 nRowColSel
-CTOF_DEL    ---     0.495      R3C10C.D1 to      R3C10C.F1 SLICE_162
-ROUTE         1     1.728      R3C10C.F1 to       67.PADDO RA_c_1
-DOPAD_DEL   ---     4.105       67.PADDO to         67.PAD RA[1]
-                  --------
-                    7.770   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:   10.921ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.855ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.494ns  (67.4% logic, 32.6% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.494ns delay SLICE_63 to RA[0] (totaling 10.645ns) meets
-     12.500ns offset RCLK to RA[0] by 1.855ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     1.017      R5C10A.Q0 to      R3C10D.D1 nRowColSel
-CTOF_DEL    ---     0.495      R3C10D.D1 to      R3C10D.F1 SLICE_159
-ROUTE         1     1.425      R3C10D.F1 to       66.PADDO RA_c_0
-DOPAD_DEL   ---     4.105       66.PADDO to         66.PAD RA[0]
-                  --------
-                    7.494   (67.4% logic, 32.6% route), 3 logic levels.
-
-Report:   10.645ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.826ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_532  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_59 and
-      6.523ns delay SLICE_59 to nRCS (totaling 9.674ns) meets
-     12.500ns offset RCLK to nRCS by 2.826ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_59:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R4C11B.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_59 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
-ROUTE         1     1.966      R4C11B.Q0 to       57.PADDO nRCS_c
-DOPAD_DEL   ---     4.105       57.PADDO to         57.PAD nRCS
-                  --------
-                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
-
-Report:    9.674ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.616ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_531  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     6.733ns  (67.7% logic, 32.3% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_35 and
-      6.733ns delay SLICE_35 to RCKE (totaling 9.884ns) meets
-     12.500ns offset RCLK to RCKE by 2.616ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to      R4C7B.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_35 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
-ROUTE         4     2.176       R4C7B.Q0 to       53.PADDO RCKE_c
-DOPAD_DEL   ---     4.105       53.PADDO to         53.PAD RCKE
-                  --------
-                    6.733   (67.7% logic, 32.3% route), 2 logic levels.
-
-Report:    9.884ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.225ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_535  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     6.124ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_62 and
-      6.124ns delay SLICE_62 to nRWE (totaling 9.275ns) meets
-     12.500ns offset RCLK to nRWE by 3.225ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_62:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C11A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_62 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
-ROUTE         1     1.567      R5C11A.Q0 to       49.PADDO nRWE_c
-DOPAD_DEL   ---     4.105       49.PADDO to         49.PAD nRWE
-                  --------
-                    6.124   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    9.275ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.703ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     6.646ns  (68.6% logic, 31.4% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_60 and
-      6.646ns delay SLICE_60 to nRRAS (totaling 9.797ns) meets
-     12.500ns offset RCLK to nRRAS by 2.703ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R4C11A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_60 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     2.089      R4C11A.Q0 to       54.PADDO nRRAS_c
-DOPAD_DEL   ---     4.105       54.PADDO to         54.PAD nRRAS
-                  --------
-                    6.646   (68.6% logic, 31.4% route), 2 logic levels.
-
-Report:    9.797ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.826ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     6.523ns  (69.9% logic, 30.1% route), 2 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_57 and
-      6.523ns delay SLICE_57 to nRCAS (totaling 9.674ns) meets
-     12.500ns offset RCLK to nRCAS by 2.826ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C11B.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_57 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
-ROUTE         1     1.966      R5C11B.Q0 to       52.PADDO nRCAS_c
-DOPAD_DEL   ---     4.105       52.PADDO to         52.PAD nRCAS
-                  --------
-                    6.523   (69.9% logic, 30.1% route), 2 logic levels.
-
-Report:    9.674ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.790ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.790ns delay SLICE_63 to RDQMH (totaling 10.941ns) meets
-     12.500ns offset RCLK to RDQMH by 1.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.648      R5C10A.Q0 to       R5C9B.D1 nRowColSel
-CTOF_DEL    ---     0.495       R5C9B.D1 to       R5C9B.F1 SLICE_151
-ROUTE         1     2.090       R5C9B.F1 to       51.PADDO RDQMH_c
-DOPAD_DEL   ---     4.105       51.PADDO to         51.PAD RDQMH
-                  --------
-                    7.790   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:   10.941ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.859ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.490ns  (67.4% logic, 32.6% route), 3 logic levels.
-
-   Clock Path Delay:    3.151ns  (35.9% logic, 64.1% route), 1 logic levels.
-
- Constraint Details:
-      3.151ns delay RCLK to SLICE_63 and
-      7.490ns delay SLICE_63 to RDQML (totaling 10.641ns) meets
-     12.500ns offset RCLK to RDQML by 1.859ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.132         63.PAD to       63.PADDI RCLK
-ROUTE        52     2.019       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    3.151   (35.9% logic, 64.1% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.796      R5C10A.Q0 to       R5C9C.C1 nRowColSel
-CTOF_DEL    ---     0.495       R5C9C.C1 to       R5C9C.F1 SLICE_161
-ROUTE         1     1.642       R5C9C.F1 to       48.PADDO RDQML_c
-DOPAD_DEL   ---     4.105       48.PADDO to         48.PAD RDQML
-                  --------
-                    7.490   (67.4% logic, 32.6% route), 3 logic levels.
-
-Report:   10.641ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    25.800 ns|   8  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.500 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    12.427 ns|   9  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.485 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.005 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.114 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.948 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.099 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.365 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.178 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.923 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.921 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.645 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.884 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.275 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.797 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.941 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.641 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 5 clocks:
-
-Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
-   No transfer within this clock domain is found
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: wb_clk   Source: SLICE_73.Q0
-      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
-
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Sat Oct 09 01:19:24 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             121 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             1409 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-VCCIO Voltage:
-                   3.135 V (Bank 0)
-                   3.135 V (Bank 1)
-                   3.135 V (Bank 2)
-                   3.135 V (Bank 3)
-                   2.375 V (Bank 4)
-                   2.375 V (Bank 5)
-                   2.375 V (Bank 6)
-                   2.375 V (Bank 7)
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            121 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted_542  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2     0.132       R3C9C.Q0 to       R3C9C.A0 C1Submitted
-CTOF_DEL    ---     0.101       R3C9C.A0 to       R3C9C.F0 SLICE_15
-ROUTE         1     0.000       R3C9C.F0 to      R3C9C.DI0 n2549 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.474ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_549  (to PHI2_c -)
-
-   Delay:               0.461ns  (50.8% logic, 49.2% route), 2 logic levels.
-
- Constraint Details:
-
-      0.461ns physical path delay SLICE_19 to SLICE_21 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.474ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
-ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
-CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
-ROUTE         4     0.003       R4C9B.F0 to      R4C9B.DI0 XOR8MEG_N_149 (to PHI2_c)
-                  --------
-                    0.461   (50.8% logic, 49.2% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R4C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.538ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_543  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
-
-   Delay:               0.510ns  (45.9% logic, 54.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.510ns physical path delay SLICE_10 to SLICE_19 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.538ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9B.CLK to       R3C9B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         1     0.133       R3C9B.Q0 to       R3C9D.D0 ADSubmitted
-CTOF_DEL    ---     0.101       R3C9D.D0 to       R3C9D.F0 SLICE_130
-ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
-                  --------
-                    0.510   (45.9% logic, 54.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.860ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_542  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_541  (to PHI2_c -)
-
-   Delay:               0.832ns  (40.3% logic, 59.7% route), 3 logic levels.
-
- Constraint Details:
-
-      0.832ns physical path delay SLICE_15 to SLICE_19 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.860ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9C.CLK to       R3C9C.Q0 SLICE_15 (from PHI2_c)
-ROUTE         2     0.224       R3C9C.Q0 to       R3C9C.B1 C1Submitted
-CTOF_DEL    ---     0.101       R3C9C.B1 to       R3C9C.F1 SLICE_15
-ROUTE         1     0.130       R3C9C.F1 to       R3C9D.A0 n7
-CTOF_DEL    ---     0.101       R3C9D.A0 to       R3C9D.F0 SLICE_130
-ROUTE         1     0.143       R3C9D.F0 to       R3C9A.CE PHI2_N_151_enable_1 (to PHI2_c)
-                  --------
-                    0.832   (40.3% logic, 59.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.873ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_544  (to PHI2_c -)
-
-   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.845ns physical path delay SLICE_19 to SLICE_145 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_145:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
-ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
-CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
-ROUTE         4     0.141       R4C9B.F0 to       R5C9A.D1 XOR8MEG_N_149
-CTOF_DEL    ---     0.101       R5C9A.D1 to       R5C9A.F1 SLICE_110
-ROUTE         1     0.145       R5C9A.F1 to       R5C8A.CE PHI2_N_151_enable_6 (to PHI2_c)
-                  --------
-                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_145:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.009ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMShift_547  (to PHI2_c -)
-                   FF                        CmdUFMData_548
-
-   Delay:               0.981ns  (34.1% logic, 65.9% route), 3 logic levels.
-
- Constraint Details:
-
-      0.981ns physical path delay SLICE_19 to SLICE_161 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.009ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_161:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
-ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
-CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
-ROUTE         4     0.059       R4C9B.F0 to       R4C9B.C1 XOR8MEG_N_149
-CTOF_DEL    ---     0.101       R4C9B.C1 to       R4C9B.F1 SLICE_21
-ROUTE         1     0.363       R4C9B.F1 to       R5C9C.CE PHI2_N_151_enable_3 (to PHI2_c)
-                  --------
-                    0.981   (34.1% logic, 65.9% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_161:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C9C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.341ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
-   Destination:    FF         Data in        CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
-
- Constraint Details:
-
-      1.313ns physical path delay SLICE_19 to SLICE_20 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
-ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
-CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
-ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     0.262       R5C8D.F1 to       R5C6A.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C6A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.341ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_541  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:               1.313ns  (33.2% logic, 66.8% route), 4 logic levels.
-
- Constraint Details:
-
-      1.313ns physical path delay SLICE_19 to SLICE_24 meets
-     -0.028ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.028ns) by 1.341ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_19 (from PHI2_c)
-ROUTE         1     0.224       R3C9A.Q0 to       R4C9B.B0 CmdEnable
-CTOF_DEL    ---     0.101       R4C9B.B0 to       R4C9B.F0 SLICE_21
-ROUTE         4     0.335       R4C9B.F0 to       R5C8D.B0 XOR8MEG_N_149
-CTOF_DEL    ---     0.101       R5C8D.B0 to       R5C8D.F0 SLICE_112
-ROUTE         1     0.056       R5C8D.F0 to       R5C8D.C1 n4882
-CTOF_DEL    ---     0.101       R5C8D.C1 to       R5C8D.F1 SLICE_112
-ROUTE         2     0.262       R5C8D.F1 to       R5C6B.CE PHI2_N_151_enable_5 (to PHI2_c)
-                  --------
-                    1.313   (33.2% logic, 66.8% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C6B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 175.457ns (weighted slack = 350.914ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_544  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_521  (to PHI2_c +)
-
-   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.444ns physical path delay SLICE_145 to SLICE_32 meets
-     -0.013ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.013ns) by 175.457ns
-
- Physical Path Details:
-
-      Data path SLICE_145 to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C8A.CLK to       R5C8A.Q0 SLICE_145 (from PHI2_c)
-ROUTE         1     0.210       R5C8A.Q0 to       R5C8C.A0 XOR8MEG
-CTOF_DEL    ---     0.101       R5C8C.A0 to       R5C8C.F0 SLICE_32
-ROUTE         1     0.000       R5C8C.F0 to      R5C8C.DI0 RA11_N_217 (to PHI2_c)
-                  --------
-                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_145:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 175.815ns (weighted slack = 351.630ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i2  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted_543  (to PHI2_c -)
-
-   Delay:               0.787ns  (42.6% logic, 57.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.787ns physical path delay SLICE_143 to SLICE_10 meets
-     -0.028ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.028ns) by 175.815ns
-
- Physical Path Details:
-
-      Data path SLICE_143 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C8D.CLK to       R2C8D.Q0 SLICE_143 (from PHI2_c)
-ROUTE         2     0.139       R2C8D.Q0 to       R2C9C.C1 Bank_2
-CTOF_DEL    ---     0.101       R2C9C.C1 to       R2C9C.F1 SLICE_132
-ROUTE         1     0.056       R2C9C.F1 to       R2C9C.C0 n4782
-CTOF_DEL    ---     0.101       R2C9C.C0 to       R2C9C.F0 SLICE_132
-ROUTE         1     0.257       R2C9C.F0 to       R3C9B.CE PHI2_N_151_enable_7 (to PHI2_c)
-                  --------
-                    0.787   (42.6% logic, 57.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_143:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R2C8D.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.240        8.PADDI to      R3C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            1409 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_118 to SLICE_118 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_118 to SLICE_118:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C9C.CLK to       R4C9C.Q0 SLICE_118 (from RCLK_c)
-ROUTE         1     0.152       R4C9C.Q0 to       R4C9C.M1 n1197 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_118:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_118:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C9C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_127 to SLICE_127 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_127 to SLICE_127:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_127 (from RCLK_c)
-ROUTE         1     0.152      R4C10B.Q0 to      R4C10B.M1 n1195 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_127:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_127:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R4C10B.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr_518  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2_519  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R6C10C.CLK to      R6C10C.Q0 SLICE_16 (from RCLK_c)
-ROUTE         1     0.152      R6C10C.Q0 to      R6C10C.M1 CASr (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R6C10C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_163 to SLICE_163 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_163 to SLICE_163:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_163 (from RCLK_c)
-ROUTE         1     0.152      R4C10D.Q0 to      R4C10D.M1 n1189 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_163:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_163:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R4C10D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_91 to SLICE_91 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_91 to SLICE_91:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C8D.CLK to       R4C8D.Q0 SLICE_91 (from RCLK_c)
-ROUTE         1     0.152       R4C8D.Q0 to       R4C8D.M1 n1185 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_91:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_91:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C8D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_94 to SLICE_94 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_94 (from RCLK_c)
-ROUTE         1     0.152       R4C7D.Q0 to       R4C7D.M1 n1187 (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C7D.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r_512  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r2_513  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_95 to SLICE_35 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_95 (from RCLK_c)
-ROUTE         1     0.152       R4C7A.Q0 to       R4C7B.M1 PHI2r (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C7A.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R4C7B.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.306ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr_515  (from RCLK_c +)
-   Destination:    FF         Data in        RASr2_516  (to RCLK_c +)
-
-   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.287ns physical path delay SLICE_30 to SLICE_30 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
-
- Physical Path Details:
-
-      Data path SLICE_30 to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_30 (from RCLK_c)
-ROUTE         2     0.154       R5C7A.Q0 to       R5C7A.M1 RASr (to RCLK_c)
-                  --------
-                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_30:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.307ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
-
-   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.288ns physical path delay SLICE_162 to SLICE_162 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
-
- Physical Path Details:
-
-      Data path SLICE_162 to SLICE_162:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_162 (from RCLK_c)
-ROUTE         4     0.155      R3C10C.Q0 to      R3C10C.M1 nRCS_N_172 (to RCLK_c)
-                  --------
-                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_162:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_162:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to     R3C10C.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_972__i2  (from RCLK_c +)
-   Destination:    FF         Data in        FS_972__i2  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C6B.CLK to       R6C6B.Q1 SLICE_0 (from RCLK_c)
-ROUTE         3     0.132       R6C6B.Q1 to       R6C6B.A1 FS_2
-CTOF_DEL    ---     0.101       R6C6B.A1 to       R6C6B.F1 SLICE_0
-ROUTE         1     0.000       R6C6B.F1 to      R6C6B.DI1 n93 (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        52     0.651       63.PADDI to      R6C6B.CLK RCLK_c
-                  --------
-                    0.651   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.236ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_536  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     2.217ns  (81.5% logic, 18.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_54 and
-      2.217ns delay SLICE_54 to RA[10] (totaling 3.236ns) meets
-      0.000ns hold offset RCLK to RA[10] by 3.236ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R4C11D.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_54 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C11D.CLK to      R4C11D.Q0 SLICE_54 (from RCLK_c)
-ROUTE         1     0.411      R4C11D.Q0 to       64.PADDO n1975
-DOPAD_DEL   ---     1.673       64.PADDO to         64.PAD RA[10]
-                  --------
-                    2.217   (81.5% logic, 18.5% route), 2 logic levels.
-
-Report:    3.236ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.561ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.542ns  (75.0% logic, 25.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.542ns delay SLICE_63 to RA[9] (totaling 3.561ns) meets
-      0.000ns hold offset RCLK to RA[9] by 3.561ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.219      R5C10A.Q0 to       R5C9B.A0 nRowColSel
-CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_151
-ROUTE         1     0.416       R5C9B.F0 to       62.PADDO RA_c_9
-DOPAD_DEL   ---     1.673       62.PADDO to         62.PAD RA[9]
-                  --------
-                    2.542   (75.0% logic, 25.0% route), 3 logic levels.
-
-Report:    3.561ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.608ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.589ns  (73.7% logic, 26.3% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.589ns delay SLICE_63 to RA[8] (totaling 3.608ns) meets
-      0.000ns hold offset RCLK to RA[8] by 3.608ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B1 nRowColSel
-CTOF_DEL    ---     0.101      R4C10D.B1 to      R4C10D.F1 SLICE_163
-ROUTE         1     0.451      R4C10D.F1 to       65.PADDO RA_c_8
-DOPAD_DEL   ---     1.673       65.PADDO to         65.PAD RA[8]
-                  --------
-                    2.589   (73.7% logic, 26.3% route), 3 logic levels.
-
-Report:    3.608ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.552ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.533ns  (75.3% logic, 24.7% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.533ns delay SLICE_63 to RA[7] (totaling 3.552ns) meets
-      0.000ns hold offset RCLK to RA[7] by 3.552ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.229      R5C10A.Q0 to      R2C10D.D1 nRowColSel
-CTOF_DEL    ---     0.101      R2C10D.D1 to      R2C10D.F1 SLICE_155
-ROUTE         1     0.397      R2C10D.F1 to       75.PADDO RA_c_7
-DOPAD_DEL   ---     1.673       75.PADDO to         75.PAD RA[7]
-                  --------
-                    2.533   (75.3% logic, 24.7% route), 3 logic levels.
-
-Report:    3.552ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.554ns  (74.7% logic, 25.3% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.554ns delay SLICE_63 to RA[6] (totaling 3.573ns) meets
-      0.000ns hold offset RCLK to RA[6] by 3.573ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.231      R5C10A.Q0 to      R4C10D.B0 nRowColSel
-CTOF_DEL    ---     0.101      R4C10D.B0 to      R4C10D.F0 SLICE_163
-ROUTE         1     0.416      R4C10D.F0 to       68.PADDO RA_c_6
-DOPAD_DEL   ---     1.673       68.PADDO to         68.PAD RA[6]
-                  --------
-                    2.554   (74.7% logic, 25.3% route), 3 logic levels.
-
-Report:    3.573ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.630ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.611ns delay SLICE_63 to RA[5] (totaling 3.630ns) meets
-      0.000ns hold offset RCLK to RA[5] by 3.630ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.283      R5C10A.Q0 to       R2C9A.C1 nRowColSel
-CTOF_DEL    ---     0.101       R2C9A.C1 to       R2C9A.F1 SLICE_157
-ROUTE         1     0.421       R2C9A.F1 to       70.PADDO RA_c_5
-DOPAD_DEL   ---     1.673       70.PADDO to         70.PAD RA[5]
-                  --------
-                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
-
-Report:    3.630ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.630ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.611ns  (73.0% logic, 27.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.611ns delay SLICE_63 to RA[4] (totaling 3.630ns) meets
-      0.000ns hold offset RCLK to RA[4] by 3.630ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.283      R5C10A.Q0 to       R2C8B.C1 nRowColSel
-CTOF_DEL    ---     0.101       R2C8B.C1 to       R2C8B.F1 SLICE_158
-ROUTE         1     0.421       R2C8B.F1 to       74.PADDO RA_c_4
-DOPAD_DEL   ---     1.673       74.PADDO to         74.PAD RA[4]
-                  --------
-                    2.611   (73.0% logic, 27.0% route), 3 logic levels.
-
-Report:    3.630ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.615ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.596ns  (73.5% logic, 26.5% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.596ns delay SLICE_63 to RA[3] (totaling 3.615ns) meets
-      0.000ns hold offset RCLK to RA[3] by 3.615ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D0 nRowColSel
-CTOF_DEL    ---     0.101      R3C10C.D0 to      R3C10C.F0 SLICE_162
-ROUTE         1     0.463      R3C10C.F0 to       71.PADDO RA_c_3
-DOPAD_DEL   ---     1.673       71.PADDO to         71.PAD RA[3]
-                  --------
-                    2.596   (73.5% logic, 26.5% route), 3 logic levels.
-
-Report:    3.615ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.527ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.508ns  (76.0% logic, 24.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.508ns delay SLICE_63 to RA[2] (totaling 3.527ns) meets
-      0.000ns hold offset RCLK to RA[2] by 3.527ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C0 nRowColSel
-CTOF_DEL    ---     0.101       R5C9C.C0 to       R5C9C.F0 SLICE_161
-ROUTE         1     0.456       R5C9C.F0 to       69.PADDO RA_c_2
-DOPAD_DEL   ---     1.673       69.PADDO to         69.PAD RA[2]
-                  --------
-                    2.508   (76.0% logic, 24.0% route), 3 logic levels.
-
-Report:    3.527ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.549ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.530ns  (75.4% logic, 24.6% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.530ns delay SLICE_63 to RA[1] (totaling 3.549ns) meets
-      0.000ns hold offset RCLK to RA[1] by 3.549ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.226      R5C10A.Q0 to      R3C10C.D1 nRowColSel
-CTOF_DEL    ---     0.101      R3C10C.D1 to      R3C10C.F1 SLICE_162
-ROUTE         1     0.397      R3C10C.F1 to       67.PADDO RA_c_1
-DOPAD_DEL   ---     1.673       67.PADDO to         67.PAD RA[1]
-                  --------
-                    2.530   (75.4% logic, 24.6% route), 3 logic levels.
-
-Report:    3.549ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.471ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.452ns  (77.8% logic, 22.2% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.452ns delay SLICE_63 to RA[0] (totaling 3.471ns) meets
-      0.000ns hold offset RCLK to RA[0] by 3.471ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.229      R5C10A.Q0 to      R3C10D.D1 nRowColSel
-CTOF_DEL    ---     0.101      R3C10D.D1 to      R3C10D.F1 SLICE_159
-ROUTE         1     0.316      R3C10D.F1 to       66.PADDO RA_c_0
-DOPAD_DEL   ---     1.673       66.PADDO to         66.PAD RA[0]
-                  --------
-                    2.452   (77.8% logic, 22.2% route), 3 logic levels.
-
-Report:    3.471ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.300ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_532  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_59 and
-      2.281ns delay SLICE_59 to nRCS (totaling 3.300ns) meets
-      0.000ns hold offset RCLK to nRCS by 3.300ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_59:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R4C11B.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_59 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C11B.CLK to      R4C11B.Q0 SLICE_59 (from RCLK_c)
-ROUTE         1     0.475      R4C11B.Q0 to       57.PADDO nRCS_c
-DOPAD_DEL   ---     1.673       57.PADDO to         57.PAD nRCS
-                  --------
-                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
-
-Report:    3.300ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.362ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_531  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     2.343ns  (77.1% logic, 22.9% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_35 and
-      2.343ns delay SLICE_35 to RCKE (totaling 3.362ns) meets
-      0.000ns hold offset RCLK to RCKE by 3.362ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_35:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to      R4C7B.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_35 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7B.CLK to       R4C7B.Q0 SLICE_35 (from RCLK_c)
-ROUTE         4     0.537       R4C7B.Q0 to       53.PADDO RCKE_c
-DOPAD_DEL   ---     1.673       53.PADDO to         53.PAD RCKE
-                  --------
-                    2.343   (77.1% logic, 22.9% route), 2 logic levels.
-
-Report:    3.362ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.194ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_535  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     2.175ns  (83.0% logic, 17.0% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_62 and
-      2.175ns delay SLICE_62 to nRWE (totaling 3.194ns) meets
-      0.000ns hold offset RCLK to nRWE by 3.194ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_62:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C11A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_62 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q0 SLICE_62 (from RCLK_c)
-ROUTE         1     0.369      R5C11A.Q0 to       49.PADDO nRWE_c
-DOPAD_DEL   ---     1.673       49.PADDO to         49.PAD nRWE
-                  --------
-                    2.175   (83.0% logic, 17.0% route), 2 logic levels.
-
-Report:    3.194ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.322ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_533  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     2.303ns  (78.4% logic, 21.6% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_60 and
-      2.303ns delay SLICE_60 to nRRAS (totaling 3.322ns) meets
-      0.000ns hold offset RCLK to nRRAS by 3.322ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R4C11A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_60 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C11A.CLK to      R4C11A.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.497      R4C11A.Q0 to       54.PADDO nRRAS_c
-DOPAD_DEL   ---     1.673       54.PADDO to         54.PAD nRRAS
-                  --------
-                    2.303   (78.4% logic, 21.6% route), 2 logic levels.
-
-Report:    3.322ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.300ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_534  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     2.281ns  (79.2% logic, 20.8% route), 2 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_57 and
-      2.281ns delay SLICE_57 to nRCAS (totaling 3.300ns) meets
-      0.000ns hold offset RCLK to nRCAS by 3.300ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_57:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C11B.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_57 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_57 (from RCLK_c)
-ROUTE         1     0.475      R5C11B.Q0 to       52.PADDO nRCAS_c
-DOPAD_DEL   ---     1.673       52.PADDO to         52.PAD nRCAS
-                  --------
-                    2.281   (79.2% logic, 20.8% route), 2 logic levels.
-
-Report:    3.300ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.540ns  (75.1% logic, 24.9% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.540ns delay SLICE_63 to RDQMH (totaling 3.559ns) meets
-      0.000ns hold offset RCLK to RDQMH by 3.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.139      R5C10A.Q0 to       R5C9B.D1 nRowColSel
-CTOF_DEL    ---     0.101       R5C9B.D1 to       R5C9B.F1 SLICE_151
-ROUTE         1     0.494       R5C9B.F1 to       51.PADDO RDQMH_c
-DOPAD_DEL   ---     1.673       51.PADDO to         51.PAD RDQMH
-                  --------
-                    2.540   (75.1% logic, 24.9% route), 3 logic levels.
-
-Report:    3.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.470ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_538  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.451ns  (77.8% logic, 22.2% route), 3 logic levels.
-
-   Clock Path Delay:    1.019ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      1.019ns delay RCLK to SLICE_63 and
-      2.451ns delay SLICE_63 to RDQML (totaling 3.470ns) meets
-      0.000ns hold offset RCLK to RDQML by 3.470ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.448         63.PAD to       63.PADDI RCLK
-ROUTE        52     0.571       63.PADDI to     R5C10A.CLK RCLK_c
-                  --------
-                    1.019   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10A.CLK to      R5C10A.Q0 SLICE_63 (from RCLK_c)
-ROUTE        12     0.145      R5C10A.Q0 to       R5C9C.C1 nRowColSel
-CTOF_DEL    ---     0.101       R5C9C.C1 to       R5C9C.F1 SLICE_161
-ROUTE         1     0.399       R5C9C.F1 to       48.PADDO RDQML_c
-DOPAD_DEL   ---     1.673       48.PADDO to         48.PAD RDQML
-                  --------
-                    2.451   (77.8% logic, 22.2% route), 3 logic levels.
-
-Report:    3.470ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.236 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.561 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.608 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.552 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.573 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.630 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.615 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.527 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.549 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.471 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.362 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.194 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.322 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.300 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.559 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.470 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 5 clocks:
-
-Clock Domain: wb_clk   Source: SLICE_73.Q0   Loads: 1
-   No transfer within this clock domain is found
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 52
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: wb_clk   Source: SLICE_73.Q0
-      Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;   Transfers: 2
-
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
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    - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_drc.log deleted file mode 100644 index 0265ac7..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_drc.log +++ /dev/null @@ -1,15 +0,0 @@ -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 452 blocks expanded -completed the first expansion -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse.twr deleted file mode 100644 index 6f3d23b..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse.twr +++ /dev/null @@ -1,335 +0,0 @@ --------------------------------------------------------------------------------- -Lattice Synthesis Timing Report, Version -Sat Oct 09 01:19:14 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Design: RAM2GS -Constraint file: -Report level: verbose report, limited to 3 items per constraint --------------------------------------------------------------------------------- - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c] - 130 items scored, 125 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 10.606ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i4 (from PHI2_c +) - Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -) - - Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels. - - Constraint Details: - - 12.821ns data_path Bank_i4 to CmdLEDEN_545 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns - - Path Details: Bank_i4 to CmdLEDEN_545 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) -Route 1 e 0.941 Bank[4] -LUT4 --- 0.493 C to Z i3734_4_lut -Route 1 e 0.941 n4610 -LUT4 --- 0.493 B to Z i3751_4_lut -Route 2 e 1.141 n4628 -LUT4 --- 0.493 B to Z i13_4_lut_adj_13 -Route 4 e 1.340 n2384 -LUT4 --- 0.493 B to Z i3712_2_lut_rep_40 -Route 2 e 1.141 n4889 -LUT4 --- 0.493 D to Z i3_4_lut_adj_23 -Route 4 e 1.340 XOR8MEG_N_149 -LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut -Route 1 e 0.941 n4882 -LUT4 --- 0.493 A to Z i1_3_lut_adj_21 -Route 2 e 1.141 PHI2_N_151_enable_5 - -------- - 12.821 (30.4% logic, 69.6% route), 8 logic levels. - - -Error: The following path violates requirements by 10.606ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i4 (from PHI2_c +) - Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -) - - Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels. - - Constraint Details: - - 12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns - - Path Details: Bank_i4 to Cmdn8MEGEN_546 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) -Route 1 e 0.941 Bank[4] -LUT4 --- 0.493 C to Z i3734_4_lut -Route 1 e 0.941 n4610 -LUT4 --- 0.493 B to Z i3751_4_lut -Route 2 e 1.141 n4628 -LUT4 --- 0.493 B to Z i13_4_lut_adj_13 -Route 4 e 1.340 n2384 -LUT4 --- 0.493 B to Z i3712_2_lut_rep_40 -Route 2 e 1.141 n4889 -LUT4 --- 0.493 D to Z i3_4_lut_adj_23 -Route 4 e 1.340 XOR8MEG_N_149 -LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut -Route 1 e 0.941 n4882 -LUT4 --- 0.493 A to Z i1_3_lut_adj_21 -Route 2 e 1.141 PHI2_N_151_enable_5 - -------- - 12.821 (30.4% logic, 69.6% route), 8 logic levels. - - -Error: The following path violates requirements by 10.606ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i5 (from PHI2_c +) - Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -) - - Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels. - - Constraint Details: - - 12.821ns data_path Bank_i5 to CmdLEDEN_545 violates - 2.500ns delay constraint less - 0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns - - Path Details: Bank_i5 to CmdLEDEN_545 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c) -Route 1 e 0.941 Bank[5] -LUT4 --- 0.493 B to Z i3734_4_lut -Route 1 e 0.941 n4610 -LUT4 --- 0.493 B to Z i3751_4_lut -Route 2 e 1.141 n4628 -LUT4 --- 0.493 B to Z i13_4_lut_adj_13 -Route 4 e 1.340 n2384 -LUT4 --- 0.493 B to Z i3712_2_lut_rep_40 -Route 2 e 1.141 n4889 -LUT4 --- 0.493 D to Z i3_4_lut_adj_23 -Route 4 e 1.340 XOR8MEG_N_149 -LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut -Route 1 e 0.941 n4882 -LUT4 --- 0.493 A to Z i1_3_lut_adj_21 -Route 2 e 1.141 PHI2_N_151_enable_5 - -------- - 12.821 (30.4% logic, 69.6% route), 8 logic levels. - -Warning: 13.106 ns is the maximum delay for this constraint. - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] - 1392 items scored, 1147 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 10.222ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_972__i8 (from RCLK_c +) - Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +) - - Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels. - - Constraint Details: - - 15.062ns data_path FS_972__i8 to wb_adr_i4 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 10.222ns - - Path Details: FS_972__i8 to wb_adr_i4 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c) -Route 23 e 1.894 FS[8] -LUT4 --- 0.493 B to Z i1_2_lut_rep_75 -Route 4 e 1.340 n4924 -LUT4 --- 0.493 B to Z i2387_3_lut_4_lut -Route 1 e 0.941 n98 -LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9 -Route 2 e 1.141 n2199 -LUT4 --- 0.493 B to Z i92_4_lut -Route 1 e 0.941 n53 -LUT4 --- 0.493 C to Z i3106_3_lut_3_lut -Route 1 e 0.020 n1_adj_6 -MUXL5 --- 0.233 ALUT to Z i29 -Route 1 e 0.941 n14_adj_3 -LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut -Route 2 e 1.141 n12_adj_8 -LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11 -Route 2 e 1.141 n14_adj_7 -LUT4 --- 0.493 A to Z i28_3_lut -Route 1 e 0.941 wb_adr_7__N_60[4] - -------- - 15.062 (30.7% logic, 69.3% route), 10 logic levels. - - -Error: The following path violates requirements by 10.222ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_972__i8 (from RCLK_c +) - Destination: FD1S3AX D wb_adr_i6 (to RCLK_c +) - - Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels. - - Constraint Details: - - 15.062ns data_path FS_972__i8 to wb_adr_i6 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 10.222ns - - Path Details: FS_972__i8 to wb_adr_i6 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c) -Route 23 e 1.894 FS[8] -LUT4 --- 0.493 B to Z i1_2_lut_rep_75 -Route 4 e 1.340 n4924 -LUT4 --- 0.493 B to Z i2387_3_lut_4_lut -Route 1 e 0.941 n98 -LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9 -Route 2 e 1.141 n2199 -LUT4 --- 0.493 B to Z i92_4_lut -Route 1 e 0.941 n53 -LUT4 --- 0.493 C to Z i3106_3_lut_3_lut -Route 1 e 0.020 n1_adj_6 -MUXL5 --- 0.233 ALUT to Z i29 -Route 1 e 0.941 n14_adj_3 -LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut -Route 2 e 1.141 n12_adj_8 -LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11 -Route 2 e 1.141 n14_adj_7 -LUT4 --- 0.493 A to Z i29_3_lut -Route 1 e 0.941 wb_adr_7__N_60[6] - -------- - 15.062 (30.7% logic, 69.3% route), 10 logic levels. - - -Error: The following path violates requirements by 10.216ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_972__i6 (from RCLK_c +) - Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +) - - Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels. - - Constraint Details: - - 15.056ns data_path FS_972__i6 to wb_adr_i4 violates - 5.000ns delay constraint less - 0.160ns L_S requirement (totaling 4.840ns) by 10.216ns - - Path Details: FS_972__i6 to wb_adr_i4 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.444 CK to Q FS_972__i6 (from RCLK_c) -Route 21 e 1.888 FS[6] -LUT4 --- 0.493 A to Z i1_2_lut_rep_75 -Route 4 e 1.340 n4924 -LUT4 --- 0.493 B to Z i2387_3_lut_4_lut -Route 1 e 0.941 n98 -LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9 -Route 2 e 1.141 n2199 -LUT4 --- 0.493 B to Z i92_4_lut -Route 1 e 0.941 n53 -LUT4 --- 0.493 C to Z i3106_3_lut_3_lut -Route 1 e 0.020 n1_adj_6 -MUXL5 --- 0.233 ALUT to Z i29 -Route 1 e 0.941 n14_adj_3 -LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut -Route 2 e 1.141 n12_adj_8 -LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11 -Route 2 e 1.141 n14_adj_7 -LUT4 --- 0.493 A to Z i28_3_lut -Route 1 e 0.941 wb_adr_7__N_60[4] - -------- - 15.056 (30.7% logic, 69.3% route), 10 logic levels. - -Warning: 15.222 ns is the maximum delay for this constraint. - - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets PHI2_c] | 5.000 ns| 26.212 ns| 8 * - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 5.000 ns| 15.222 ns| 10 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - --------------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total --------------------------------------------------------------------------------- -n14 | 16| 200| 15.72% - | | | -n12_adj_8 | 2| 198| 15.57% - | | | -n14_adj_3 | 1| 183| 14.39% - | | | -n14_adj_7 | 2| 176| 13.84% - | | | --------------------------------------------------------------------------------- - - -Timing summary: ---------------- - -Timing errors: 1272 Score: 5951146 - -Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage) - - -Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes -CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse_lsetwr.html deleted file mode 100644 index 15ef8ae..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse_lsetwr.html +++ /dev/null @@ -1,400 +0,0 @@ - -Lattice Synthesis Timing Report - - -
    Lattice Synthesis Timing Report
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Sat Oct 09 01:19:14 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
-            130 items scored, 125 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 10.606ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
-
- Constraint Details:
-
-     12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
-
- Path Details: Bank_i4 to CmdLEDEN_545
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
-Route         1   e 0.941                                  Bank[4]
-LUT4        ---     0.493              C to Z              i3734_4_lut
-Route         1   e 0.941                                  n4610
-LUT4        ---     0.493              B to Z              i3751_4_lut
-Route         2   e 1.141                                  n4628
-LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
-Route         4   e 1.340                                  n2384
-LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
-Route         2   e 1.141                                  n4889
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
-Route         4   e 1.340                                  XOR8MEG_N_149
-LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
-Route         1   e 0.941                                  n4882
-LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
-Route         2   e 1.141                                  PHI2_N_151_enable_5
-                  --------
-                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
-
-
-Error:  The following path violates requirements by 10.606ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             Cmdn8MEGEN_546  (to PHI2_c -)
-
-   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
-
- Constraint Details:
-
-     12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
-
- Path Details: Bank_i4 to Cmdn8MEGEN_546
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
-Route         1   e 0.941                                  Bank[4]
-LUT4        ---     0.493              C to Z              i3734_4_lut
-Route         1   e 0.941                                  n4610
-LUT4        ---     0.493              B to Z              i3751_4_lut
-Route         2   e 1.141                                  n4628
-LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
-Route         4   e 1.340                                  n2384
-LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
-Route         2   e 1.141                                  n4889
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
-Route         4   e 1.340                                  XOR8MEG_N_149
-LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
-Route         1   e 0.941                                  n4882
-LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
-Route         2   e 1.141                                  PHI2_N_151_enable_5
-                  --------
-                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
-
-
-Error:  The following path violates requirements by 10.606ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdLEDEN_545  (to PHI2_c -)
-
-   Delay:                  12.821ns  (30.4% logic, 69.6% route), 8 logic levels.
-
- Constraint Details:
-
-     12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
-
- Path Details: Bank_i5 to CmdLEDEN_545
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 0.941                                  Bank[5]
-LUT4        ---     0.493              B to Z              i3734_4_lut
-Route         1   e 0.941                                  n4610
-LUT4        ---     0.493              B to Z              i3751_4_lut
-Route         2   e 1.141                                  n4628
-LUT4        ---     0.493              B to Z              i13_4_lut_adj_13
-Route         4   e 1.340                                  n2384
-LUT4        ---     0.493              B to Z              i3712_2_lut_rep_40
-Route         2   e 1.141                                  n4889
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_23
-Route         4   e 1.340                                  XOR8MEG_N_149
-LUT4        ---     0.493              D to Z              i2_3_lut_rep_33_4_lut
-Route         1   e 0.941                                  n4882
-LUT4        ---     0.493              A to Z              i1_3_lut_adj_21
-Route         2   e 1.141                                  PHI2_N_151_enable_5
-                  --------
-                   12.821  (30.4% logic, 69.6% route), 8 logic levels.
-
-Warning: 13.106 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            1392 items scored, 1147 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 10.222ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
-   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
-
-   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
-
- Constraint Details:
-
-     15.062ns data_path FS_972__i8 to wb_adr_i4 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
-
- Path Details: FS_972__i8 to wb_adr_i4
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
-Route        23   e 1.894                                  FS[8]
-LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
-Route         4   e 1.340                                  n4924
-LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
-Route         1   e 0.941                                  n98
-LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
-Route         2   e 1.141                                  n2199
-LUT4        ---     0.493              B to Z              i92_4_lut
-Route         1   e 0.941                                  n53
-LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
-Route         1   e 0.020                                  n1_adj_6
-MUXL5       ---     0.233           ALUT to Z              i29
-Route         1   e 0.941                                  n14_adj_3
-LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
-Route         2   e 1.141                                  n12_adj_8
-LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
-Route         2   e 1.141                                  n14_adj_7
-LUT4        ---     0.493              A to Z              i28_3_lut
-Route         1   e 0.941                                  wb_adr_7__N_60[4]
-                  --------
-                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
-
-
-Error:  The following path violates requirements by 10.222ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_972__i8  (from RCLK_c +)
-   Destination:    FD1S3AX    D              wb_adr_i6  (to RCLK_c +)
-
-   Delay:                  15.062ns  (30.7% logic, 69.3% route), 10 logic levels.
-
- Constraint Details:
-
-     15.062ns data_path FS_972__i8 to wb_adr_i6 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
-
- Path Details: FS_972__i8 to wb_adr_i6
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_972__i8 (from RCLK_c)
-Route        23   e 1.894                                  FS[8]
-LUT4        ---     0.493              B to Z              i1_2_lut_rep_75
-Route         4   e 1.340                                  n4924
-LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
-Route         1   e 0.941                                  n98
-LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
-Route         2   e 1.141                                  n2199
-LUT4        ---     0.493              B to Z              i92_4_lut
-Route         1   e 0.941                                  n53
-LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
-Route         1   e 0.020                                  n1_adj_6
-MUXL5       ---     0.233           ALUT to Z              i29
-Route         1   e 0.941                                  n14_adj_3
-LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
-Route         2   e 1.141                                  n12_adj_8
-LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
-Route         2   e 1.141                                  n14_adj_7
-LUT4        ---     0.493              A to Z              i29_3_lut
-Route         1   e 0.941                                  wb_adr_7__N_60[6]
-                  --------
-                   15.062  (30.7% logic, 69.3% route), 10 logic levels.
-
-
-Error:  The following path violates requirements by 10.216ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_972__i6  (from RCLK_c +)
-   Destination:    FD1S3AX    D              wb_adr_i4  (to RCLK_c +)
-
-   Delay:                  15.056ns  (30.7% logic, 69.3% route), 10 logic levels.
-
- Constraint Details:
-
-     15.056ns data_path FS_972__i6 to wb_adr_i4 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
-
- Path Details: FS_972__i6 to wb_adr_i4
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_972__i6 (from RCLK_c)
-Route        21   e 1.888                                  FS[6]
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_75
-Route         4   e 1.340                                  n4924
-LUT4        ---     0.493              B to Z              i2387_3_lut_4_lut
-Route         1   e 0.941                                  n98
-LUT4        ---     0.493              D to Z              i1_3_lut_4_lut_adj_9
-Route         2   e 1.141                                  n2199
-LUT4        ---     0.493              B to Z              i92_4_lut
-Route         1   e 0.941                                  n53
-LUT4        ---     0.493              C to Z              i3106_3_lut_3_lut
-Route         1   e 0.020                                  n1_adj_6
-MUXL5       ---     0.233           ALUT to Z              i29
-Route         1   e 0.941                                  n14_adj_3
-LUT4        ---     0.493              C to Z              i1_2_lut_2_lut_3_lut
-Route         2   e 1.141                                  n12_adj_8
-LUT4        ---     0.493              C to Z              i1_3_lut_4_lut_adj_11
-Route         2   e 1.141                                  n14_adj_7
-LUT4        ---     0.493              A to Z              i28_3_lut
-Route         1   e 0.941                                  wb_adr_7__N_60[4]
-                  --------
-                   15.056  (30.7% logic, 69.3% route), 10 logic levels.
-
-Warning: 15.222 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets PHI2_c]                  |     5.000 ns|    26.212 ns|     8 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|    15.222 ns|    10 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n14                                     |      16|     200|     15.72%
-                                        |        |        |
-n12_adj_8                               |       2|     198|     15.57%
-                                        |        |        |
-n14_adj_3                               |       1|     183|     14.39%
-                                        |        |        |
-n14_adj_7                               |       2|     176|     13.84%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 1272  Score: 5951146
-
-Constraints cover  1577 paths, 335 nets, and 954 connections (77.9% coverage)
-
-
-Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
-CPU_TIME_REPORT: 0 secs 
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    - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_prim.v deleted file mode 100644 index dc1901b..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_prim.v +++ /dev/null @@ -1,1243 +0,0 @@ -// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.0.240.2 -// Netlist written on Sat Oct 09 01:19:14 2021 -// -// Verilog Description of module RAM2GS -// - -module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, - LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, - nRCAS, RDQMH, RDQML) /* synthesis syn_module_defined=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1[8:14]) - input PHI2; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12]) - input [9:0]MAin; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - input [1:0]CROW; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18]) - input [7:0]Din; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - output [7:0]Dout; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - input nCCAS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13]) - input nCRAS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20]) - input nFWE; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12]) - output LED; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12]) - output [1:0]RBA; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22]) - output [11:0]RA; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - inout [7:0]RD; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - output nRCS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17]) - input RCLK; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12]) - output RCKE; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17]) - output nRWE; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49]) - output nRRAS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28]) - output nRCAS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39]) - output RDQMH; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21]) - output RDQML; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14]) - - wire PHI2_c /* synthesis is_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12]) - wire nCCAS_c /* synthesis is_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13]) - wire nCRAS_c /* synthesis is_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20]) - wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12]) - wire wb_clk /* synthesis is_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(317[6:12]) - wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22]) - wire PHI2_N_151 /* synthesis is_inv_clock=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(37[6:13]) - - wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, - RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, - Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0; - wire [7:0]Bank; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(30[12:16]) - - wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, - MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, - nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, - nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n1975; - wire [9:0]RowA; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(50[12:16]) - - wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, - RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c; - wire [7:0]WRD; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(58[12:15]) - - wire C1Submitted, ADSubmitted, CmdEnable, CmdSubmitted, CmdLEDEN, - Cmdn8MEGEN, CmdUFMData, CmdUFMShift, n4097, InitReady, Ready, - n10; - wire [17:0]FS; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - - wire wb_rst, wb_cyc_stb, wb_we; - wire [7:0]wb_adr; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(321[12:18]) - wire [7:0]wb_dati; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(322[12:19]) - wire [1:0]wb_dato; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(323[13:20]) - - wire LED_N_134, RA11_N_217, n1197, n3, RCKE_N_165, nRowColSel_N_35, - nRWE_N_215, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, - nRCS_N_179, n2557, nRCS_N_175, n2556, n4883, nRCS_N_174, - nRCAS_N_199, nRWE_N_211, RCKEEN_N_153, nRCS_N_172, nRCAS_N_198, - nRWE_N_210, nRWE_N_209, n1196, n1195, n1194, n1193, n3622, - Ready_N_284, nRCS_N_170, Ready_N_280, nRCS_N_169, nRRAS_N_189, - nRCAS_N_194, nRWE_N_204, RCKEEN_N_152, n3989, n1, CmdEnable_N_243, - C1Submitted_N_232, XOR8MEG_N_149, CmdLEDEN_N_251, Cmdn8MEGEN_N_260, - n4901, n2199, wb_adr_7__N_92, RCLK_c_enable_27, n4149, n17, - wb_we_N_354, n2426, n5144, n4539, n93, n38, n4900, n87, - wb_we_N_351, n638, n646, n4893, wb_cyc_stb_N_350, n4888, - n5142, n4087, wb_cyc_stb_N_348, n89, n4880, n80, n4899, - n2238, n746, n747, n748, n751, n752, n754, n755, n756, - n757, n758, n759, n760, n761, n4094, n4093, n4882, n4628, - n23, n4624, n4892, n4092, n4622, n3609, n4091, LEDEN_N_110, - n8MEGEN_N_139, PHI2_N_151_enable_3, n4610, RCLK_c_enable_25, - RCLK_c_enable_28, n4887, n4548, n84, wb_we_N_338, n2549, - n83, n1969, n1971, wb_cyc_stb_N_307, n4517; - wire [7:0]wb_adr_7__N_60; - wire [7:0]wb_dati_7__N_68; - - wire n1192, n1191, n1189, n1188, n1187, n1186, n1185, n6, - n3_adj_1, n4519, n2308, n14, n86, n39, PHI2_N_151_enable_1, - n12, n2040, n2104, n1286, n4869, PHI2_N_151_enable_5, RCLK_c_enable_24, - n4165, n1972, Dout_c, n1965, n1974, n10_adj_2, n78, n2262, - n2252, n2258, n1973, n14_adj_3, n4884, n2244, n1885, n56, - n4859, n4858, n1889, RCLK_c_enable_20, RCLK_c_enable_29, n4898, - n45, n53, n85, n92, RCLK_c_enable_26, n4526, n4090, n1970, - n4939, n4938, n95, n4937, n4089, n2384, n4850, n42, - n3_adj_4, n4936, n1968, n91, n94, n90, n88, n79, n4935, - n42_adj_5, n81, n82, n1_adj_6, n14_adj_7, n4574, n4504, - n4088, n4086, n12_adj_8, n4934, PHI2_N_151_enable_6, n4933, - n4585, n4932, n4733, n98, n4732, n3671, n4931, n4930, - n4125, n4929, n4928, n4731, n4927, n4926, n4925, n4924, - n4730, n4897, n4923, RCLK_c_enable_22, n4729, n53_adj_9, - n175, n4921, n4920, n4919, n4164, n4918, n4917, n4916, - n4915, n12_adj_10, n4914, n4913, n4896, n4807, n4806, - n4582, n15, n4129, n3969, n4911, n3711, n4910, n4527, - n4909, n4530, n4891, n6_adj_11, n4718, n4908, n6_adj_12, - n4895, n4890, n4886, n4, n4907, n4_adj_13, PHI2_N_151_enable_7, - n4782, n4889, n4894, n14_adj_14, n4885, n4777, n4776, - n6_adj_15, n4906, n4905, n4941, n4632, n4513, n3_adj_16, - n20, n4904, n4775, n4618, n4774, n4634, n22, n4903, - n4902, n4940, n7; - - VHI i2 (.Z(VCC_net)); - INV i4006 (.A(nCCAS_c), .Z(nCCAS_N_3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13]) - FD1P3AX IS_FSM__i15 (.D(n1185), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(Ready_N_284)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i15.GSR = "ENABLED"; - FD1P3AX IS_FSM__i14 (.D(n1186), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1185)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i14.GSR = "ENABLED"; - FD1S3AX PHI2r2_513 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam PHI2r2_513.GSR = "ENABLED"; - FD1S3AX PHI2r3_514 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam PHI2r3_514.GSR = "ENABLED"; - FD1S3AX RASr_515 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam RASr_515.GSR = "ENABLED"; - FD1S3AX RASr2_516 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam RASr2_516.GSR = "ENABLED"; - FD1S3AX RASr3_517 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam RASr3_517.GSR = "ENABLED"; - FD1S3AX CASr_518 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam CASr_518.GSR = "ENABLED"; - FD1S3AX CASr2_519 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam CASr2_519.GSR = "ENABLED"; - FD1S3AX CASr3_520 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam CASr3_520.GSR = "ENABLED"; - FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i0.GSR = "ENABLED"; - FD1S3IX S_FSM_i2 (.D(n2556), .CK(RCLK_c), .CD(n4933), .Q(nRowColSel_N_34)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam S_FSM_i2.GSR = "ENABLED"; - FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i0.GSR = "ENABLED"; - FD1S3AX FWEr_525 (.D(n4932), .CK(nCRAS_N_9), .Q(FWEr)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam FWEr_525.GSR = "ENABLED"; - FD1S3AX CBR_526 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam CBR_526.GSR = "ENABLED"; - FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_0)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RBA__i1.GSR = "ENABLED"; - FD1P3AX IS_FSM__i13 (.D(n1187), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1186)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i13.GSR = "ENABLED"; - FD1P3AX IS_FSM__i12 (.D(n1188), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1187)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i12.GSR = "ENABLED"; - EFB ufmefb (.WBCLKI(wb_clk), .WBRSTI(wb_rst), .WBCYCI(wb_cyc_stb), - .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), .WBADRI0(wb_adr[0]), .WBADRI1(wb_adr[1]), - .WBADRI2(wb_adr[2]), .WBADRI3(wb_adr[3]), .WBADRI4(wb_adr[4]), - .WBADRI5(wb_adr[5]), .WBADRI6(wb_adr[6]), .WBADRI7(wb_adr[7]), - .WBDATI0(wb_dati[0]), .WBDATI1(wb_dati[1]), .WBDATI2(wb_dati[2]), - .WBDATI3(wb_dati[3]), .WBDATI4(wb_dati[4]), .WBDATI5(wb_dati[5]), - .WBDATI6(wb_dati[6]), .WBDATI7(wb_dati[7]), .I2C1SCLI(GND_net), - .I2C1SDAI(GND_net), .I2C2SCLI(GND_net), .I2C2SDAI(GND_net), .SPISCKI(GND_net), - .SPIMISOI(GND_net), .SPIMOSII(GND_net), .SPISCSN(GND_net), .TCCLKI(GND_net), - .TCRSTN(GND_net), .TCIC(GND_net), .PLL0DATI0(GND_net), .PLL0DATI1(GND_net), - .PLL0DATI2(GND_net), .PLL0DATI3(GND_net), .PLL0DATI4(GND_net), - .PLL0DATI5(GND_net), .PLL0DATI6(GND_net), .PLL0DATI7(GND_net), - .PLL0ACKI(GND_net), .PLL1DATI0(GND_net), .PLL1DATI1(GND_net), - .PLL1DATI2(GND_net), .PLL1DATI3(GND_net), .PLL1DATI4(GND_net), - .PLL1DATI5(GND_net), .PLL1DATI6(GND_net), .PLL1DATI7(GND_net), - .PLL1ACKI(GND_net), .WBDATO0(wb_dato[0]), .WBDATO1(wb_dato[1])) /* synthesis syn_instantiated=1 */ ; - defparam ufmefb.EFB_I2C1 = "DISABLED"; - defparam ufmefb.EFB_I2C2 = "DISABLED"; - defparam ufmefb.EFB_SPI = "DISABLED"; - defparam ufmefb.EFB_TC = "DISABLED"; - defparam ufmefb.EFB_TC_PORTMODE = "NO_WB"; - defparam ufmefb.EFB_UFM = "DISABLED"; - defparam ufmefb.EFB_WB_CLK_FREQ = "50.0"; - defparam ufmefb.DEV_DENSITY = "1200L"; - defparam ufmefb.UFM_INIT_PAGES = 0; - defparam ufmefb.UFM_INIT_START_PAGE = 0; - defparam ufmefb.UFM_INIT_ALL_ZEROS = "ENABLED"; - defparam ufmefb.UFM_INIT_FILE_NAME = "NONE"; - defparam ufmefb.UFM_INIT_FILE_FORMAT = "HEX"; - defparam ufmefb.I2C1_ADDRESSING = "7BIT"; - defparam ufmefb.I2C2_ADDRESSING = "7BIT"; - defparam ufmefb.I2C1_SLAVE_ADDR = "0b1000001"; - defparam ufmefb.I2C2_SLAVE_ADDR = "0b1000010"; - defparam ufmefb.I2C1_BUS_PERF = "100kHz"; - defparam ufmefb.I2C2_BUS_PERF = "100kHz"; - defparam ufmefb.I2C1_CLK_DIVIDER = 1; - defparam ufmefb.I2C2_CLK_DIVIDER = 1; - defparam ufmefb.I2C1_GEN_CALL = "DISABLED"; - defparam ufmefb.I2C2_GEN_CALL = "DISABLED"; - defparam ufmefb.I2C1_WAKEUP = "DISABLED"; - defparam ufmefb.I2C2_WAKEUP = "DISABLED"; - defparam ufmefb.SPI_MODE = "SLAVE"; - defparam ufmefb.SPI_CLK_DIVIDER = 1; - defparam ufmefb.SPI_LSB_FIRST = "DISABLED"; - defparam ufmefb.SPI_CLK_INV = "DISABLED"; - defparam ufmefb.SPI_PHASE_ADJ = "DISABLED"; - defparam ufmefb.SPI_SLAVE_HANDSHAKE = "DISABLED"; - defparam ufmefb.SPI_INTR_TXRDY = "DISABLED"; - defparam ufmefb.SPI_INTR_RXRDY = "DISABLED"; - defparam ufmefb.SPI_INTR_TXOVR = "DISABLED"; - defparam ufmefb.SPI_INTR_RXOVR = "DISABLED"; - defparam ufmefb.SPI_WAKEUP = "DISABLED"; - defparam ufmefb.TC_MODE = "CTCM"; - defparam ufmefb.TC_SCLK_SEL = "PCLOCK"; - defparam ufmefb.TC_CCLK_SEL = 1; - defparam ufmefb.GSR = "ENABLED"; - defparam ufmefb.TC_TOP_SET = 65535; - defparam ufmefb.TC_OCR_SET = 32767; - defparam ufmefb.TC_OC_MODE = "TOGGLE"; - defparam ufmefb.TC_RESETN = "ENABLED"; - defparam ufmefb.TC_TOP_SEL = "ON"; - defparam ufmefb.TC_OV_INT = "OFF"; - defparam ufmefb.TC_OCR_INT = "OFF"; - defparam ufmefb.TC_ICR_INT = "OFF"; - defparam ufmefb.TC_OVERFLOW = "ENABLED"; - defparam ufmefb.TC_ICAPTURE = "DISABLED"; - FD1P3AX IS_FSM__i11 (.D(n1189), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1188)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i11.GSR = "ENABLED"; - FD1P3AX IS_FSM__i10 (.D(nRWE_N_210), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1189)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i10.GSR = "ENABLED"; - FD1P3AX IS_FSM__i9 (.D(n1191), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRWE_N_210)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i9.GSR = "ENABLED"; - FD1P3AX IS_FSM__i8 (.D(n1192), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1191)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i8.GSR = "ENABLED"; - FD1S3AX RCKE_531 (.D(RCKE_N_165), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(133[9] 136[5]) - defparam RCKE_531.GSR = "ENABLED"; - FD1P3AY nRCS_532 (.D(nRCS_N_169), .SP(RCLK_c_enable_20), .CK(RCLK_c), - .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam nRCS_532.GSR = "ENABLED"; - FD1P3AX IS_FSM__i7 (.D(n1193), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1192)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i7.GSR = "ENABLED"; - FD1P3AX IS_FSM__i6 (.D(n1194), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1193)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i6.GSR = "ENABLED"; - FD1S3IX S_FSM_i3 (.D(n2556), .CK(RCLK_c), .CD(n2557), .Q(nRowColSel_N_33)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam S_FSM_i3.GSR = "ENABLED"; - FD1P3AX IS_FSM__i5 (.D(n1195), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1194)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i5.GSR = "ENABLED"; - FD1P3AX IS_FSM__i4 (.D(n1196), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1195)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i4.GSR = "ENABLED"; - FD1P3AX IS_FSM__i3 (.D(n1197), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1196)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i3.GSR = "ENABLED"; - FD1P3AX IS_FSM__i2 (.D(nRCAS_N_198), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(n1197)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i2.GSR = "ENABLED"; - FD1P3AX IS_FSM__i1 (.D(nRCS_N_172), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRCAS_N_198)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i1.GSR = "ENABLED"; - FD1P3AY nRRAS_533 (.D(nRRAS_N_189), .SP(RCLK_c_enable_20), .CK(RCLK_c), - .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam nRRAS_533.GSR = "ENABLED"; - LUT4 m1_lut (.Z(n5144)) /* synthesis lut_function=1, syn_instantiated=1 */ ; - defparam m1_lut.init = 16'hffff; - FD1P3AY nRCAS_534 (.D(nRCAS_N_194), .SP(RCLK_c_enable_20), .CK(RCLK_c), - .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam nRCAS_534.GSR = "ENABLED"; - FD1P3AY nRWE_535 (.D(nRWE_N_204), .SP(RCLK_c_enable_29), .CK(RCLK_c), - .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam nRWE_535.GSR = "ENABLED"; - FD1S3JX RA10_536 (.D(n4129), .CK(RCLK_c), .PD(nRWE_N_209), .Q(n1975)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam RA10_536.GSR = "ENABLED"; - FD1P3AX RCKEEN_537 (.D(RCKEEN_N_152), .SP(RCLK_c_enable_20), .CK(RCLK_c), - .Q(RCKEEN)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam RCKEEN_537.GSR = "ENABLED"; - FD1S3JX C1Submitted_542 (.D(n2549), .CK(PHI2_N_151), .PD(C1Submitted_N_232), - .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam C1Submitted_542.GSR = "ENABLED"; - FD1P3IX wb_we_553 (.D(wb_we_N_338), .SP(RCLK_c_enable_25), .CD(wb_adr_7__N_92), - .CK(RCLK_c), .Q(wb_we)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_we_553.GSR = "ENABLED"; - LUT4 nRCS_I_34_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), - .D(nRCS_N_175), .Z(nRCS_N_174)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; - defparam nRCS_I_34_3_lut_4_lut.init = 16'h1f10; - FD1S3AX CmdSubmitted_549 (.D(XOR8MEG_N_149), .CK(PHI2_N_151), .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam CmdSubmitted_549.GSR = "ENABLED"; - FD1S3AX FS_972__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i17.GSR = "ENABLED"; - PFUMX i12 (.BLUT(n3), .ALUT(n758), .C0(InitReady), .Z(wb_dati_7__N_68[3])); - FD1S3AX FS_972__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i16.GSR = "ENABLED"; - FD1S3AX FS_972__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i15.GSR = "ENABLED"; - FD1S3AX FS_972__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i14.GSR = "ENABLED"; - FD1S3AX FS_972__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i13.GSR = "ENABLED"; - FD1S3AX FS_972__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i12.GSR = "ENABLED"; - FD1S3AX FS_972__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i11.GSR = "ENABLED"; - FD1S3AX FS_972__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i10.GSR = "ENABLED"; - FD1S3AX FS_972__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i9.GSR = "ENABLED"; - FD1S3AX FS_972__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i8.GSR = "ENABLED"; - FD1S3AX FS_972__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i7.GSR = "ENABLED"; - FD1S3AX FS_972__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i6.GSR = "ENABLED"; - FD1S3AX wb_adr_i0 (.D(wb_adr_7__N_60[0]), .CK(RCLK_c), .Q(wb_adr[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i0.GSR = "ENABLED"; - FD1S3AX FS_972__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i5.GSR = "ENABLED"; - FD1S3AX FS_972__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i4.GSR = "ENABLED"; - FD1S3AX FS_972__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i3.GSR = "ENABLED"; - FD1S3AX FS_972__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i2.GSR = "ENABLED"; - FD1S3AX FS_972__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i1.GSR = "ENABLED"; - FD1P3AX wb_rst_551 (.D(n3671), .SP(RCLK_c_enable_22), .CK(RCLK_c), - .Q(wb_rst)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_rst_551.GSR = "ENABLED"; - FD1S3AX wb_dati_i0 (.D(wb_dati_7__N_68[0]), .CK(RCLK_c), .Q(wb_dati[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i0.GSR = "ENABLED"; - FD1S3AX S_FSM_i1 (.D(n4921), .CK(RCLK_c), .Q(nRowColSel_N_35)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam S_FSM_i1.GSR = "ENABLED"; - FD1P3AX LEDEN_556 (.D(LEDEN_N_110), .SP(RCLK_c_enable_24), .CK(RCLK_c), - .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam LEDEN_556.GSR = "ENABLED"; - FD1P3AX n8MEGEN_557 (.D(n8MEGEN_N_139), .SP(RCLK_c_enable_24), .CK(RCLK_c), - .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam n8MEGEN_557.GSR = "ENABLED"; - FD1S3AX PHI2r_512 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam PHI2r_512.GSR = "ENABLED"; - FD1S3IX S_FSM_i4 (.D(n1286), .CK(RCLK_c), .CD(n4921), .Q(nRowColSel_N_32)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam S_FSM_i4.GSR = "ENABLED"; - IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(40[8:12]) - IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(35[8:12]) - IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20]) - IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[8:13]) - IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(25[14:17]) - IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18]) - IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(33[14:18]) - IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(34[14:18]) - IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12]) - OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[9:14]) - OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(55[16:21]) - OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[34:39]) - OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[23:28]) - OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[45:49]) - OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(44[13:17]) - OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(45[13:17]) - OB RA_pad_0 (.I(RA_c_0), .O(RA[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_1 (.I(RA_c_1), .O(RA[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_2 (.I(RA_c_2), .O(RA[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_3 (.I(RA_c_3), .O(RA[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_4 (.I(RA_c_4), .O(RA[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_5 (.I(RA_c_5), .O(RA[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_6 (.I(RA_c_6), .O(RA[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_7 (.I(RA_c_7), .O(RA[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_8 (.I(RA_c_8), .O(RA[8])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_9 (.I(RA_c_9), .O(RA[9])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_10 (.I(n1975), .O(RA[10])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RA_pad_11 (.I(RA_c), .O(RA[11])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(51[16:18]) - OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22]) - OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(46[19:22]) - OB LED_pad (.I(LED_N_134), .O(LED)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(11[9:12]) - OB Dout_pad_0 (.I(Dout_c), .O(Dout[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_1 (.I(n1974), .O(Dout[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_2 (.I(n1973), .O(Dout[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_3 (.I(n1972), .O(Dout[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_4 (.I(n1971), .O(Dout[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_5 (.I(n1970), .O(Dout[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_6 (.I(n1969), .O(Dout[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - OB Dout_pad_7 (.I(n1968), .O(Dout[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(26[15:19]) - BB Dout_pad_0__1130 (.I(WRD[0]), .T(n1965), .B(RD[0]), .O(Dout_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_1__1129 (.I(WRD[1]), .T(n1965), .B(RD[1]), .O(n1974)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_2__1128 (.I(WRD[2]), .T(n1965), .B(RD[2]), .O(n1973)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_3__1127 (.I(WRD[3]), .T(n1965), .B(RD[3]), .O(n1972)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_4__1126 (.I(WRD[4]), .T(n1965), .B(RD[4]), .O(n1971)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_5__1125 (.I(WRD[5]), .T(n1965), .B(RD[5]), .O(n1970)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - BB Dout_pad_6__1124 (.I(WRD[6]), .T(n1965), .B(RD[6]), .O(n1969)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - FD1S3AX wb_dati_i7 (.D(wb_dati_7__N_68[7]), .CK(RCLK_c), .Q(wb_dati[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i7.GSR = "ENABLED"; - FD1S3AX wb_dati_i6 (.D(wb_dati_7__N_68[6]), .CK(RCLK_c), .Q(wb_dati[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i6.GSR = "ENABLED"; - FD1S3AX wb_dati_i5 (.D(wb_dati_7__N_68[5]), .CK(RCLK_c), .Q(wb_dati[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i5.GSR = "ENABLED"; - FD1S3AX wb_dati_i4 (.D(wb_dati_7__N_68[4]), .CK(RCLK_c), .Q(wb_dati[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i4.GSR = "ENABLED"; - FD1S3AX wb_dati_i3 (.D(wb_dati_7__N_68[3]), .CK(RCLK_c), .Q(wb_dati[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i3.GSR = "ENABLED"; - FD1S3AX wb_dati_i2 (.D(wb_dati_7__N_68[2]), .CK(RCLK_c), .Q(wb_dati[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i2.GSR = "ENABLED"; - FD1S3AX wb_dati_i1 (.D(wb_dati_7__N_68[1]), .CK(RCLK_c), .Q(wb_dati[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_dati_i1.GSR = "ENABLED"; - CCU2D FS_972_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4086), - .COUT(n4087), .S0(n94), .S1(n93)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_3.INIT0 = 16'hfaaa; - defparam FS_972_add_4_3.INIT1 = 16'hfaaa; - defparam FS_972_add_4_3.INJECT1_0 = "NO"; - defparam FS_972_add_4_3.INJECT1_1 = "NO"; - PFUMX i1369 (.BLUT(wb_we_N_351), .ALUT(n2104), .C0(n4886), .Z(n2238)); - FD1P3IX wb_cyc_stb_552 (.D(wb_cyc_stb_N_307), .SP(RCLK_c_enable_25), - .CD(wb_adr_7__N_92), .CK(RCLK_c), .Q(wb_cyc_stb)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_cyc_stb_552.GSR = "ENABLED"; - FD1S3AX wb_adr_i7 (.D(wb_adr_7__N_60[7]), .CK(RCLK_c), .Q(wb_adr[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i7.GSR = "ENABLED"; - FD1S3AX wb_adr_i6 (.D(wb_adr_7__N_60[6]), .CK(RCLK_c), .Q(wb_adr[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i6.GSR = "ENABLED"; - FD1S3AX wb_adr_i5 (.D(wb_adr_7__N_60[5]), .CK(RCLK_c), .Q(wb_adr[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i5.GSR = "ENABLED"; - FD1S3AX wb_adr_i4 (.D(wb_adr_7__N_60[4]), .CK(RCLK_c), .Q(wb_adr[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i4.GSR = "ENABLED"; - FD1S3AX wb_adr_i3 (.D(wb_adr_7__N_60[3]), .CK(RCLK_c), .Q(wb_adr[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i3.GSR = "ENABLED"; - FD1S3AX wb_adr_i2 (.D(wb_adr_7__N_60[2]), .CK(RCLK_c), .Q(wb_adr[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i2.GSR = "ENABLED"; - FD1S3AX wb_adr_i1 (.D(wb_adr_7__N_60[1]), .CK(RCLK_c), .Q(wb_adr[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_adr_i1.GSR = "ENABLED"; - FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RBA_c_1)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RBA__i2.GSR = "ENABLED"; - CCU2D FS_972_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4093), - .COUT(n4094), .S0(n80), .S1(n79)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_17.INIT0 = 16'hfaaa; - defparam FS_972_add_4_17.INIT1 = 16'hfaaa; - defparam FS_972_add_4_17.INJECT1_0 = "NO"; - defparam FS_972_add_4_17.INJECT1_1 = "NO"; - CCU2D FS_972_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4092), - .COUT(n4093), .S0(n82), .S1(n81)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_15.INIT0 = 16'hfaaa; - defparam FS_972_add_4_15.INIT1 = 16'hfaaa; - defparam FS_972_add_4_15.INJECT1_0 = "NO"; - defparam FS_972_add_4_15.INJECT1_1 = "NO"; - FD1P3AX CmdEnable_541 (.D(CmdEnable_N_243), .SP(PHI2_N_151_enable_1), - .CK(PHI2_N_151), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam CmdEnable_541.GSR = "ENABLED"; - FD1P3AX InitReady_530 (.D(n5144), .SP(RCLK_c_enable_26), .CK(RCLK_c), - .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(126[9] 130[5]) - defparam InitReady_530.GSR = "ENABLED"; - PFUMX i12_adj_1 (.BLUT(n3_adj_4), .ALUT(n755), .C0(InitReady), .Z(wb_dati_7__N_68[6])); - LUT4 i1_3_lut_4_lut_then_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), - .Z(n4941)) /* synthesis lut_function=(A (B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_3_lut_4_lut_then_4_lut.init = 16'h8000; - LUT4 i1_3_lut_4_lut_else_4_lut (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), - .Z(n4940)) /* synthesis lut_function=(!(A (B+(D))+!A (B+(C (D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_3_lut_4_lut_else_4_lut.init = 16'h0133; - LUT4 i2692_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_215)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(160[14] 176[8]) - defparam i2692_2_lut.init = 16'hdddd; - LUT4 i217_2_lut_rep_70 (.A(FS[9]), .B(FS[5]), .Z(n4919)) /* synthesis lut_function=(A+(B)) */ ; - defparam i217_2_lut_rep_70.init = 16'heeee; - LUT4 i1_2_lut (.A(n3989), .B(n3969), .Z(wb_dati_7__N_68[1])) /* synthesis lut_function=(A+(B)) */ ; - defparam i1_2_lut.init = 16'heeee; - LUT4 n4542_bdd_4_lut (.A(FS[10]), .B(FS[11]), .C(FS[7]), .D(n4924), - .Z(n4806)) /* synthesis lut_function=(!((B ((D)+!C)+!B (C+(D)))+!A)) */ ; - defparam n4542_bdd_4_lut.init = 16'h0082; - LUT4 i1_2_lut_4_lut (.A(n4929), .B(XOR8MEG_N_149), .C(Din_c_4), .D(n4931), - .Z(PHI2_N_151_enable_3)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; - defparam i1_2_lut_4_lut.init = 16'h4000; - PFUMX i3861 (.BLUT(n4777), .ALUT(n761), .C0(InitReady), .Z(wb_dati_7__N_68[0])); - FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i0.GSR = "ENABLED"; - LUT4 i1_4_lut_4_lut (.A(CBR), .B(FWEr), .C(n4618), .D(nRowColSel_N_34), - .Z(n20)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(206[26:30]) - defparam i1_4_lut_4_lut.init = 16'h5540; - LUT4 n10_bdd_4_lut_3959 (.A(n10_adj_2), .B(FS[10]), .C(FS[11]), .D(n14), - .Z(n4517)) /* synthesis lut_function=(A+(B (D)+!B ((D)+!C))) */ ; - defparam n10_bdd_4_lut_3959.init = 16'hffab; - LUT4 i3141_4_lut_4_lut (.A(n4895), .B(n3609), .C(FS[10]), .D(FS[11]), - .Z(n38)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A !(B (C)+!B (C+(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i3141_4_lut_4_lut.init = 16'h5350; - FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i7.GSR = "ENABLED"; - FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i6.GSR = "ENABLED"; - LUT4 i2_3_lut_rep_77 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .Z(n4926)) /* synthesis lut_function=(A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20]) - defparam i2_3_lut_rep_77.init = 16'h8080; - FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i5.GSR = "ENABLED"; - CCU2D FS_972_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4091), - .COUT(n4092), .S0(n84), .S1(n83)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_13.INIT0 = 16'hfaaa; - defparam FS_972_add_4_13.INIT1 = 16'hfaaa; - defparam FS_972_add_4_13.INJECT1_0 = "NO"; - defparam FS_972_add_4_13.INJECT1_1 = "NO"; - FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i4.GSR = "ENABLED"; - LUT4 i1_2_lut_rep_57_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .D(nRCS_N_172), .Z(n4906)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20]) - defparam i1_2_lut_rep_57_4_lut.init = 16'hff7f; - FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i3.GSR = "ENABLED"; - FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i2.GSR = "ENABLED"; - FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(115[9] 117[5]) - defparam WRD_i1.GSR = "ENABLED"; - FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[9])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i9.GSR = "ENABLED"; - FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[8])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i8.GSR = "ENABLED"; - LUT4 n2426_bdd_4_lut (.A(n2426), .B(n4165), .C(FS[11]), .D(FS[10]), - .Z(n5142)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ; - defparam n2426_bdd_4_lut.init = 16'hca00; - FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i7.GSR = "ENABLED"; - FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i6.GSR = "ENABLED"; - BB Dout_pad_7__1123 (.I(WRD[7]), .T(n1965), .B(RD[7]), .O(n1968)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(59[14:16]) - FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n4935), .Q(RowA[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i5.GSR = "ENABLED"; - FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i4.GSR = "ENABLED"; - FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i3.GSR = "ENABLED"; - FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i2.GSR = "ENABLED"; - LUT4 i3798_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), - .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(225[8:20]) - defparam i3798_2_lut_4_lut.init = 16'h0080; - LUT4 i3_4_lut (.A(Din_c_6), .B(n4624), .C(Din_c_5), .D(n4548), .Z(C1Submitted_N_232)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; - defparam i3_4_lut.init = 16'h0200; - FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n4935), .Q(RowA[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(97[9] 112[5]) - defparam RowA_i1.GSR = "ENABLED"; - GSR GSR_INST (.GSR(VCC_net)); - FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i7.GSR = "ENABLED"; - LUT4 i1392_4_lut (.A(wb_we_N_354), .B(n2258), .C(n10_adj_2), .D(n4), - .Z(n2262)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i1392_4_lut.init = 16'hccca; - LUT4 i1388_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4891), - .Z(n2258)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i1388_4_lut.init = 16'hccca; - CCU2D FS_972_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4090), - .COUT(n4091), .S0(n86), .S1(n85)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_11.INIT0 = 16'hfaaa; - defparam FS_972_add_4_11.INIT1 = 16'hfaaa; - defparam FS_972_add_4_11.INJECT1_0 = "NO"; - defparam FS_972_add_4_11.INJECT1_1 = "NO"; - LUT4 i1_2_lut_rep_35_3_lut_4_lut_4_lut (.A(n4920), .B(n4902), .C(n4899), - .D(FS[10]), .Z(n4884)) /* synthesis lut_function=(A+(B (C)+!B !((D)+!C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46]) - defparam i1_2_lut_rep_35_3_lut_4_lut_4_lut.init = 16'heafa; - LUT4 i1_2_lut_rep_78 (.A(FS[7]), .B(FS[6]), .Z(n4927)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_2_lut_rep_78.init = 16'heeee; - LUT4 i2_2_lut_rep_51_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), - .D(FS[9]), .Z(n4900)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i2_2_lut_rep_51_3_lut_4_lut.init = 16'hfffe; - LUT4 i1_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(FS[8]), .D(FS[5]), - .Z(n53_adj_9)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_3_lut_4_lut.init = 16'hf0e0; - LUT4 i1_2_lut_rep_79 (.A(FS[5]), .B(FS[9]), .Z(n4928)) /* synthesis lut_function=(!((B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_rep_79.init = 16'h2222; - LUT4 n34_bdd_2_lut_3877_3_lut (.A(FS[5]), .B(FS[9]), .C(n4806), .Z(n4807)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam n34_bdd_2_lut_3877_3_lut.init = 16'h2020; - LUT4 n61_bdd_4_lut_3912 (.A(n4923), .B(n12_adj_8), .C(n45), .D(FS[10]), - .Z(n4850)) /* synthesis lut_function=(A (B+!((D)+!C))+!A (B)) */ ; - defparam n61_bdd_4_lut_3912.init = 16'hccec; - FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i6.GSR = "ENABLED"; - LUT4 i3122_3_lut_3_lut_4_lut (.A(n4927), .B(n4905), .C(n646), .D(FS[10]), - .Z(n23)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i3122_3_lut_3_lut_4_lut.init = 16'h11f0; - FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i5.GSR = "ENABLED"; - FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i4.GSR = "ENABLED"; - LUT4 i1_4_lut_4_lut_4_lut (.A(FS[10]), .B(n3_adj_16), .C(FS[11]), - .D(n4895), .Z(n42_adj_5)) /* synthesis lut_function=(!(A+(B (C (D))+!B ((D)+!C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_4_lut_4_lut.init = 16'h0454; - LUT4 n1097_bdd_2_lut_3927 (.A(n4858), .B(FS[9]), .Z(n4859)) /* synthesis lut_function=(A+!(B)) */ ; - defparam n1097_bdd_2_lut_3927.init = 16'hbbbb; - FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i3.GSR = "ENABLED"; - FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i2.GSR = "ENABLED"; - FD1S3AX FS_972__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972__i0.GSR = "ENABLED"; - LUT4 i7_4_lut_4_lut (.A(FS[4]), .B(n4517), .C(n10), .D(n14_adj_14), - .Z(n4539)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(692[20:26]) - defparam i7_4_lut_4_lut.init = 16'h4000; - LUT4 FS_5__bdd_4_lut_3949 (.A(FS[5]), .B(FS[8]), .C(FS[6]), .D(FS[7]), - .Z(n4858)) /* synthesis lut_function=(A (B (C (D))+!B !(D))+!A !(B+(C (D)))) */ ; - defparam FS_5__bdd_4_lut_3949.init = 16'h8133; - FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam Bank_i1.GSR = "ENABLED"; - LUT4 n9_bdd_2_lut_3908_4_lut (.A(n4910), .B(n4919), .C(FS[10]), .D(FS[12]), - .Z(n4775)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam n9_bdd_2_lut_3908_4_lut.init = 16'h0200; - FD1P3AX CmdUFMData_548 (.D(Din_c_0), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), - .Q(CmdUFMData)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam CmdUFMData_548.GSR = "ENABLED"; - LUT4 i3106_3_lut_3_lut (.A(FS[12]), .B(FS[11]), .C(n53), .Z(n1_adj_6)) /* synthesis lut_function=(!(A (B+!(C))+!A !(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam i3106_3_lut_3_lut.init = 16'h7070; - LUT4 nRCAS_I_0_594_3_lut_4_lut (.A(nRCAS_N_198), .B(n4906), .C(Ready), - .D(nRCAS_N_199), .Z(nRCAS_N_194)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6]) - defparam nRCAS_I_0_594_3_lut_4_lut.init = 16'hfe0e; - LUT4 i5_4_lut_4_lut (.A(FS[12]), .B(n4895), .C(n4519), .D(n2308), - .Z(n12_adj_10)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam i5_4_lut_4_lut.init = 16'h4000; - LUT4 Din_7__I_0_i6_2_lut_rep_80 (.A(Din_c_6), .B(Din_c_7), .Z(n4929)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam Din_7__I_0_i6_2_lut_rep_80.init = 16'heeee; - LUT4 i1_4_lut_4_lut_adj_2 (.A(n4907), .B(FS[12]), .C(n42), .D(n4807), - .Z(n3_adj_4)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_4_lut_adj_2.init = 16'h5140; - LUT4 FS_7__bdd_4_lut_3948 (.A(FS[7]), .B(FS[9]), .C(FS[8]), .D(n4939), - .Z(n638)) /* synthesis lut_function=(!(A (B (C+(D)))+!A (B (C)+!B !(C+(D))))) */ ; - defparam FS_7__bdd_4_lut_3948.init = 16'h373e; - PFUMX i29 (.BLUT(n56), .ALUT(n1_adj_6), .C0(n4632), .Z(n14_adj_3)); - LUT4 i2_3_lut_rep_33_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), - .D(XOR8MEG_N_149), .Z(n4882)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam i2_3_lut_rep_33_4_lut.init = 16'h1000; - LUT4 i1_2_lut_rep_59_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), - .Z(n4908)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam i1_2_lut_rep_59_3_lut.init = 16'hfefe; - LUT4 i21_3_lut_4_lut_4_lut (.A(n4907), .B(n759), .C(InitReady), .D(n4880), - .Z(wb_dati_7__N_68[2])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i21_3_lut_4_lut_4_lut.init = 16'hc5c0; - PFUMX i13 (.BLUT(n4539), .ALUT(n4513), .C0(InitReady), .Z(RCLK_c_enable_24)); - LUT4 i1_4_lut_4_lut_adj_3 (.A(n4907), .B(n4900), .C(n4890), .D(FS[5]), - .Z(n45)) /* synthesis lut_function=(!(A+(B (C)+!B !((D)+!C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_4_lut_adj_3.init = 16'h1505; - LUT4 FS_6__bdd_4_lut_3962 (.A(FS[6]), .B(FS[5]), .C(FS[8]), .D(FS[7]), - .Z(n4869)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+(D)))+!A !(B (C+(D))+!B (C)))) */ ; - defparam FS_6__bdd_4_lut_3962.init = 16'h7ef0; - LUT4 i3707_2_lut_rep_81 (.A(MAin_c_3), .B(MAin_c_6), .Z(n4930)) /* synthesis lut_function=(A (B)) */ ; - defparam i3707_2_lut_rep_81.init = 16'h8888; - LUT4 i1_2_lut_rep_82 (.A(Din_c_3), .B(Din_c_5), .Z(n4931)) /* synthesis lut_function=(A (B)) */ ; - defparam i1_2_lut_rep_82.init = 16'h8888; - PFUMX i3859 (.BLUT(n4775), .ALUT(n4774), .C0(FS[11]), .Z(n4776)); - LUT4 i21_3_lut_4_lut_4_lut_adj_4 (.A(n4907), .B(n756), .C(InitReady), - .D(n4880), .Z(wb_dati_7__N_68[5])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i21_3_lut_4_lut_4_lut_adj_4.init = 16'hc5c0; - LUT4 i1_4_lut_4_lut_adj_5 (.A(n4907), .B(FS[12]), .C(n42), .D(n39), - .Z(n3)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_4_lut_adj_5.init = 16'h5140; - FD1P3AX CmdUFMShift_547 (.D(Din_c_1), .SP(PHI2_N_151_enable_3), .CK(PHI2_N_151), - .Q(CmdUFMShift)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam CmdUFMShift_547.GSR = "ENABLED"; - FD1P3AX Cmdn8MEGEN_546 (.D(Cmdn8MEGEN_N_260), .SP(PHI2_N_151_enable_5), - .CK(PHI2_N_151), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam Cmdn8MEGEN_546.GSR = "ENABLED"; - FD1P3AX CmdLEDEN_545 (.D(CmdLEDEN_N_251), .SP(PHI2_N_151_enable_5), - .CK(PHI2_N_151), .Q(CmdLEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam CmdLEDEN_545.GSR = "ENABLED"; - LUT4 i1_2_lut_4_lut_4_lut (.A(n4907), .B(FS[12]), .C(n42_adj_5), .D(n38), - .Z(n3_adj_1)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_2_lut_4_lut_4_lut.init = 16'h5140; - FD1P3AX Ready_540 (.D(n5144), .SP(Ready_N_280), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam Ready_540.GSR = "ENABLED"; - FD1P3AX XOR8MEG_544 (.D(Din_c_0), .SP(PHI2_N_151_enable_6), .CK(PHI2_N_151), - .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam XOR8MEG_544.GSR = "ENABLED"; - LUT4 i3748_4_lut (.A(Din_c_3), .B(MAin_c_0), .C(Din_c_2), .D(n4888), - .Z(n4624)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i3748_4_lut.init = 16'hfffe; - FD1S3IX RA11_521 (.D(RA11_N_217), .CK(PHI2_c), .CD(n4935), .Q(RA_c)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(90[9] 94[5]) - defparam RA11_521.GSR = "ENABLED"; - FD1P3AX IS_FSM__i0 (.D(Ready_N_284), .SP(RCLK_c_enable_27), .CK(RCLK_c), - .Q(nRCS_N_172)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255[11:15]) - defparam IS_FSM__i0.GSR = "ENABLED"; - FD1P3AX wb_clk_550 (.D(n1889), .SP(RCLK_c_enable_28), .CK(RCLK_c), - .Q(wb_clk)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(351[9] 730[5]) - defparam wb_clk_550.GSR = "ENABLED"; - LUT4 i1_4_lut_4_lut_adj_6 (.A(n4907), .B(FS[11]), .C(n3711), .D(n175), - .Z(n17)) /* synthesis lut_function=(!(A+(B (C)+!B !(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_4_lut_adj_6.init = 16'h1504; - FD1P3AX nRowColSel_538 (.D(n1885), .SP(RCLK_c_enable_29), .CK(RCLK_c), - .Q(nRowColSel)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam nRowColSel_538.GSR = "ENABLED"; - LUT4 i2_3_lut_rep_62_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_2), - .D(Din_c_6), .Z(n4911)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; - defparam i2_3_lut_rep_62_4_lut.init = 16'h0080; - LUT4 i2_1_lut_rep_83 (.A(nFWE_c), .Z(n4932)) /* synthesis lut_function=(!(A)) */ ; - defparam i2_1_lut_rep_83.init = 16'h5555; - LUT4 i1_2_lut_2_lut (.A(nFWE_c), .B(n4504), .Z(n4548)) /* synthesis lut_function=(!(A+!(B))) */ ; - defparam i1_2_lut_2_lut.init = 16'h4444; - LUT4 i1684_1_lut_rep_84 (.A(nRowColSel_N_35), .Z(n4933)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam i1684_1_lut_rep_84.init = 16'h5555; - LUT4 i2736_4_lut (.A(wb_adr[7]), .B(InitReady), .C(wb_adr[6]), .D(n4901), - .Z(wb_adr_7__N_60[7])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6]) - defparam i2736_4_lut.init = 16'hc088; - LUT4 i29_3_lut (.A(n14_adj_7), .B(n746), .C(InitReady), .Z(wb_adr_7__N_60[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i29_3_lut.init = 16'hcaca; - LUT4 i3_4_lut_4_lut (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), - .D(nRCS_N_172), .Z(nRCS_N_170)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam i3_4_lut_4_lut.init = 16'hff7f; - LUT4 i2787_2_lut_rep_85 (.A(FS[10]), .B(FS[11]), .Z(n4934)) /* synthesis lut_function=(A (B)) */ ; - defparam i2787_2_lut_rep_85.init = 16'h8888; - LUT4 i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut (.A(FS[11]), .B(n14), - .Z(n4891)) /* synthesis lut_function=((B)+!A) */ ; - defparam i2791_2_lut_rep_42_3_lut_4_lut_4_lut_2_lut.init = 16'hdddd; - LUT4 i3_4_lut_4_lut_adj_7 (.A(n4907), .B(n4904), .C(InitReady), .D(n4895), - .Z(n3969)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i3_4_lut_4_lut_adj_7.init = 16'h0004; - FD1P3IX ADSubmitted_543 (.D(n4883), .SP(PHI2_N_151_enable_7), .CD(C1Submitted_N_232), - .CK(PHI2_N_151), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(280[9] 315[5]) - defparam ADSubmitted_543.GSR = "ENABLED"; - LUT4 CmdLEDEN_I_69_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_1), - .D(LEDEN), .Z(CmdLEDEN_N_251)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam CmdLEDEN_I_69_3_lut_4_lut.init = 16'hdf02; - LUT4 Cmdn8MEGEN_I_72_3_lut_4_lut (.A(Din_c_4), .B(n4908), .C(Din_c_0), - .D(n8MEGEN), .Z(Cmdn8MEGEN_N_260)) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam Cmdn8MEGEN_I_72_3_lut_4_lut.init = 16'hdf02; - CCU2D FS_972_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4089), - .COUT(n4090), .S0(n88), .S1(n87)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_9.INIT0 = 16'hfaaa; - defparam FS_972_add_4_9.INIT1 = 16'hfaaa; - defparam FS_972_add_4_9.INJECT1_0 = "NO"; - defparam FS_972_add_4_9.INJECT1_1 = "NO"; - LUT4 i3804_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), - .Z(n3671)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46]) - defparam i3804_2_lut_4_lut.init = 16'h0001; - LUT4 i1_2_lut_rep_53 (.A(FS[11]), .B(n14), .Z(n4902)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46]) - defparam i1_2_lut_rep_53.init = 16'heeee; - LUT4 i3808_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(InitReady), - .Z(wb_adr_7__N_92)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46]) - defparam i3808_2_lut_4_lut.init = 16'h0001; - LUT4 i1_2_lut_rep_64_3_lut (.A(FS[10]), .B(FS[11]), .C(n14), .Z(n4913)) /* synthesis lut_function=(((C)+!B)+!A) */ ; - defparam i1_2_lut_rep_64_3_lut.init = 16'hf7f7; - LUT4 mux_427_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[3]), - .D(wb_adr[4]), .Z(n748)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_427_i5_3_lut_4_lut.init = 16'hf780; - LUT4 i1044_1_lut_rep_86 (.A(Ready), .Z(n4935)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam i1044_1_lut_rep_86.init = 16'h5555; - LUT4 n4729_bdd_2_lut_3976 (.A(n4729), .B(FS[11]), .Z(n4730)) /* synthesis lut_function=(!((B)+!A)) */ ; - defparam n4729_bdd_2_lut_3976.init = 16'h2222; - LUT4 i1_3_lut_rep_34_4_lut (.A(MAin_c_0), .B(n4888), .C(n4911), .D(n4548), - .Z(n4883)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31]) - defparam i1_3_lut_rep_34_4_lut.init = 16'h2000; - LUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n14), .C(FS[10]), .Z(n4)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46]) - defparam i1_2_lut_3_lut.init = 16'hefef; - LUT4 n3572_bdd_4_lut_3847 (.A(n4890), .B(wb_cyc_stb_N_350), .C(n638), - .D(FS[10]), .Z(n4729)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ; - defparam n3572_bdd_4_lut_3847.init = 16'h88f0; - LUT4 n4733_bdd_2_lut (.A(n4733), .B(n3969), .Z(wb_adr_7__N_60[0])) /* synthesis lut_function=(A+(B)) */ ; - defparam n4733_bdd_2_lut.init = 16'heeee; - LUT4 i28_3_lut (.A(n14_adj_7), .B(n748), .C(InitReady), .Z(wb_adr_7__N_60[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i28_3_lut.init = 16'hcaca; - LUT4 i1_2_lut_rep_44_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), - .D(n4920), .Z(n4893)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46]) - defparam i1_2_lut_rep_44_3_lut_4_lut.init = 16'hffef; - LUT4 i1_2_lut_2_lut_adj_8 (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam i1_2_lut_2_lut_adj_8.init = 16'hdddd; - LUT4 i1_2_lut_rep_37_3_lut_4_lut (.A(FS[11]), .B(n14), .C(FS[10]), - .D(n4920), .Z(n4886)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(648[30:46]) - defparam i1_2_lut_rep_37_3_lut_4_lut.init = 16'hfffe; - LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n2040), .C(nRowColSel_N_32), - .D(nRowColSel_N_35), .Z(RCLK_c_enable_29)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; - LUT4 i2742_4_lut (.A(wb_adr[3]), .B(InitReady), .C(wb_adr[2]), .D(n4901), - .Z(wb_adr_7__N_60[3])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6]) - defparam i2742_4_lut.init = 16'hc088; - LUT4 i2_2_lut_4_lut (.A(FS[11]), .B(n4909), .C(n10_adj_2), .D(FS[9]), - .Z(n10)) /* synthesis lut_function=(!(A (D)+!A (B (D)+!B ((D)+!C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(522[30:46]) - defparam i2_2_lut_4_lut.init = 16'h00fe; - LUT4 i2743_4_lut (.A(wb_adr[2]), .B(InitReady), .C(wb_adr[1]), .D(n4901), - .Z(wb_adr_7__N_60[2])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6]) - defparam i2743_4_lut.init = 16'hc088; - CCU2D FS_972_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4088), - .COUT(n4089), .S0(n90), .S1(n89)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_7.INIT0 = 16'hfaaa; - defparam FS_972_add_4_7.INIT1 = 16'hfaaa; - defparam FS_972_add_4_7.INJECT1_0 = "NO"; - defparam FS_972_add_4_7.INJECT1_1 = "NO"; - LUT4 i2_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[8]), .D(FS[6]), - .Z(n3_adj_16)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; - defparam i2_3_lut_4_lut.init = 16'h0100; - LUT4 nRCS_N_179_bdd_4_lut (.A(nRCS_N_179), .B(n2040), .C(nRWE_N_215), - .D(nRowColSel_N_35), .Z(nRWE_N_211)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; - defparam nRCS_N_179_bdd_4_lut.init = 16'hf0dd; - LUT4 i34_4_lut (.A(n7), .B(ADSubmitted), .C(C1Submitted_N_232), .D(n4889), - .Z(PHI2_N_151_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; - defparam i34_4_lut.init = 16'hc0c5; - LUT4 FS_8__bdd_3_lut_4_lut (.A(FS[7]), .B(n4919), .C(FS[6]), .D(FS[8]), - .Z(n4718)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; - defparam FS_8__bdd_3_lut_4_lut.init = 16'h0100; - LUT4 i13_4_lut (.A(MAin_c_0), .B(C1Submitted), .C(MAin_c_1), .D(n6_adj_11), - .Z(n7)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (C))) */ ; - defparam i13_4_lut.init = 16'h2505; - LUT4 i2_2_lut_rep_54_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n4903)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam i2_2_lut_rep_54_2_lut.init = 16'hdddd; - LUT4 i1_2_lut_rep_87 (.A(FS[7]), .B(FS[5]), .Z(n4936)) /* synthesis lut_function=(A (B)) */ ; - defparam i1_2_lut_rep_87.init = 16'h8888; - LUT4 n34_bdd_2_lut_3867_3_lut_4_lut (.A(n4782), .B(n4930), .C(n4628), - .D(n4582), .Z(PHI2_N_151_enable_7)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam n34_bdd_2_lut_3867_3_lut_4_lut.init = 16'h8000; - LUT4 i1_3_lut_4_lut_adj_9 (.A(n4938), .B(n4914), .C(FS[9]), .D(n98), - .Z(n2199)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_3_lut_4_lut_adj_9.init = 16'hc5cf; - LUT4 i3_4_lut_adj_10 (.A(FS[11]), .B(FS[12]), .C(n4907), .D(n23), - .Z(n4125)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i3_4_lut_adj_10.init = 16'h0400; - LUT4 i1_2_lut_rep_49_3_lut_4_lut (.A(FS[7]), .B(FS[5]), .C(FS[9]), - .D(n4937), .Z(n4898)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i1_2_lut_rep_49_3_lut_4_lut.init = 16'h8000; - LUT4 i1_3_lut_4_lut_adj_11 (.A(FS[10]), .B(n4923), .C(n12_adj_8), - .D(n45), .Z(n14_adj_7)) /* synthesis lut_function=(A (C)+!A (B (C+(D))+!B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_3_lut_4_lut_adj_11.init = 16'hf4f0; - LUT4 i1_2_lut_rep_88 (.A(FS[6]), .B(FS[8]), .Z(n4937)) /* synthesis lut_function=(A (B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_rep_88.init = 16'h8888; - LUT4 i1_2_lut_rep_65_3_lut_4_lut (.A(FS[6]), .B(FS[8]), .C(FS[5]), - .D(FS[7]), .Z(n4914)) /* synthesis lut_function=(A (B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_rep_65_3_lut_4_lut.init = 16'h8000; - LUT4 i3_4_lut_adj_12 (.A(Din_c_1), .B(Din_c_0), .C(Din_c_7), .D(Din_c_4), - .Z(n4504)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; - defparam i3_4_lut_adj_12.init = 16'h0040; - LUT4 i1_2_lut_rep_89 (.A(FS[7]), .B(FS[8]), .Z(n4938)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1_2_lut_rep_89.init = 16'heeee; - LUT4 i2_3_lut (.A(InitReady), .B(FS[12]), .C(n754), .Z(n4165)) /* synthesis lut_function=(A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[12] 729[6]) - defparam i2_3_lut.init = 16'h8080; - LUT4 i1_2_lut_rep_45_3_lut_4_lut (.A(FS[7]), .B(FS[8]), .C(FS[9]), - .D(n4939), .Z(n4894)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i1_2_lut_rep_45_3_lut_4_lut.init = 16'hfffe; - LUT4 n61_bdd_4_lut (.A(n4923), .B(n4895), .C(n4530), .D(FS[10]), - .Z(n4880)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B ((D)+!C)+!B !(C+(D))))) */ ; - defparam n61_bdd_4_lut.init = 16'h11f0; - LUT4 i1_2_lut_rep_90 (.A(FS[5]), .B(FS[6]), .Z(n4939)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i1_2_lut_rep_90.init = 16'heeee; - LUT4 i2_2_lut_rep_66_3_lut_4_lut (.A(FS[5]), .B(FS[6]), .C(FS[8]), - .D(FS[7]), .Z(n4915)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i2_2_lut_rep_66_3_lut_4_lut.init = 16'hfffe; - LUT4 i13_4_lut_adj_13 (.A(n4582), .B(n4628), .C(n15), .D(n4930), - .Z(n2384)) /* synthesis lut_function=(((C+!(D))+!B)+!A) */ ; - defparam i13_4_lut_adj_13.init = 16'hf7ff; - LUT4 i1_2_lut_adj_14 (.A(MAin_c_7), .B(Bank[2]), .Z(n15)) /* synthesis lut_function=((B)+!A) */ ; - defparam i1_2_lut_adj_14.init = 16'hdddd; - LUT4 i1_2_lut_rep_38_4_lut (.A(n53_adj_9), .B(n4914), .C(FS[9]), .D(FS[11]), - .Z(n4887)) /* synthesis lut_function=(A (B (C (D)))+!A (B (D)+!B !(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(464[4] 521[11]) - defparam i1_2_lut_rep_38_4_lut.init = 16'hc500; - LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_172), .B(n4926), .C(Ready), .D(nRCAS_N_198), - .Z(n4129)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(267[12] 276[6]) - defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; - LUT4 i1_3_lut_3_lut_4_lut (.A(FS[7]), .B(n4924), .C(n4914), .D(FS[9]), - .Z(wb_cyc_stb_N_348)) /* synthesis lut_function=(A (C (D))+!A (B (C (D))+!B (C+!(D)))) */ ; - defparam i1_3_lut_3_lut_4_lut.init = 16'hf011; - LUT4 i1_2_lut_rep_58 (.A(n14), .B(FS[13]), .Z(n4907)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_2_lut_rep_58.init = 16'heeee; - LUT4 i1_2_lut_adj_15 (.A(RASr2), .B(nRowColSel_N_32), .Z(n2556)) /* synthesis lut_function=(!((B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam i1_2_lut_adj_15.init = 16'h2222; - CCU2D FS_972_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4094), - .S0(n78)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_19.INIT0 = 16'hfaaa; - defparam FS_972_add_4_19.INIT1 = 16'h0000; - defparam FS_972_add_4_19.INJECT1_0 = "NO"; - defparam FS_972_add_4_19.INJECT1_1 = "NO"; - LUT4 i3746_2_lut_3_lut (.A(n14), .B(FS[13]), .C(FS[10]), .Z(n4622)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i3746_2_lut_3_lut.init = 16'hfefe; - LUT4 i3709_2_lut (.A(Bank[3]), .B(MAin_c_5), .Z(n4582)) /* synthesis lut_function=(A (B)) */ ; - defparam i3709_2_lut.init = 16'h8888; - LUT4 i3711_4_lut (.A(n4890), .B(n4887), .C(n2199), .D(FS[10]), .Z(n4585)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i3711_4_lut.init = 16'ha088; - PFUMX i12_adj_16 (.BLUT(n4526), .ALUT(n751), .C0(InitReady), .Z(wb_adr_7__N_60[1])); - LUT4 i3751_4_lut (.A(Bank[1]), .B(n4610), .C(n4574), .D(Bank[0]), - .Z(n4628)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i3751_4_lut.init = 16'h8000; - LUT4 i1_2_lut_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n14_adj_3), .Z(n12_adj_8)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_2_lut_2_lut_3_lut.init = 16'h1010; - LUT4 i3734_4_lut (.A(MAin_c_4), .B(Bank[5]), .C(Bank[4]), .D(Bank[6]), - .Z(n4610)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i3734_4_lut.init = 16'h8000; - PFUMX i1383 (.BLUT(n2244), .ALUT(n2252), .C0(n4634), .Z(wb_we_N_338)); - LUT4 i2856_2_lut_3_lut_4_lut (.A(n14), .B(FS[13]), .C(n4915), .D(FS[9]), - .Z(n2426)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i2856_2_lut_3_lut_4_lut.init = 16'h0001; - LUT4 i1669_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[0]), - .D(Cmdn8MEGEN), .Z(n8MEGEN_N_139)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ; - defparam i1669_3_lut_4_lut.init = 16'hfe10; - LUT4 i3701_2_lut (.A(Bank[7]), .B(MAin_c_2), .Z(n4574)) /* synthesis lut_function=(A (B)) */ ; - defparam i3701_2_lut.init = 16'h8888; - LUT4 n34_bdd_2_lut_3863_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4776), - .Z(n4777)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam n34_bdd_2_lut_3863_2_lut_3_lut.init = 16'h1010; - LUT4 i1382_3_lut (.A(wb_we_N_354), .B(wb_cyc_stb), .C(InitReady), - .Z(n2252)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i1382_3_lut.init = 16'hcaca; - PFUMX i12_adj_17 (.BLUT(n3_adj_1), .ALUT(n757), .C0(InitReady), .Z(wb_dati_7__N_68[4])); - LUT4 n34_bdd_2_lut_3841_2_lut_3_lut (.A(n14), .B(FS[13]), .C(n4731), - .Z(n4732)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam n34_bdd_2_lut_3841_2_lut_3_lut.init = 16'h1010; - LUT4 i1375_4_lut (.A(n4897), .B(n2238), .C(n10_adj_2), .D(n4913), - .Z(n2244)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i1375_4_lut.init = 16'hccca; - LUT4 i6_4_lut (.A(n4149), .B(n12_adj_10), .C(n4622), .D(n4164), - .Z(n4526)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i6_4_lut.init = 16'h0800; - LUT4 mux_427_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[7]), - .D(wb_adr[0]), .Z(n752)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_427_i1_3_lut_4_lut.init = 16'hf780; - LUT4 i6_4_lut_adj_18 (.A(FS[13]), .B(n12), .C(FS[17]), .D(FS[14]), - .Z(RCLK_c_enable_26)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i6_4_lut_adj_18.init = 16'h8000; - LUT4 i5_4_lut (.A(FS[12]), .B(FS[16]), .C(FS[15]), .D(n4934), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i5_4_lut.init = 16'h8000; - LUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_5), .B(n4929), .C(XOR8MEG_N_149), - .D(Din_c_4), .Z(PHI2_N_151_enable_6)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(304[17:31]) - defparam i2_3_lut_4_lut_adj_19.init = 16'h0010; - LUT4 i1_2_lut_rep_39 (.A(MAin_c_1), .B(n2384), .Z(n4888)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31]) - defparam i1_2_lut_rep_39.init = 16'hdddd; - PFUMX i3833 (.BLUT(n4732), .ALUT(n752), .C0(InitReady), .Z(n4733)); - LUT4 i1683_1_lut (.A(nRowColSel_N_34), .Z(n2557)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam i1683_1_lut.init = 16'h5555; - LUT4 i1_2_lut_rep_36_3_lut (.A(MAin_c_1), .B(n2384), .C(MAin_c_0), - .Z(n4885)) /* synthesis lut_function=((B+!(C))+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(72[15:31]) - defparam i1_2_lut_rep_36_3_lut.init = 16'hdfdf; - LUT4 i92_4_lut (.A(n4887), .B(n2199), .C(FS[10]), .D(n4890), .Z(n53)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i92_4_lut.init = 16'hcafa; - LUT4 i3812_2_lut (.A(FS[11]), .B(FS[12]), .Z(n4632)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i3812_2_lut.init = 16'hbbbb; - LUT4 i6_4_lut_adj_20 (.A(FS[10]), .B(n4527), .C(n4924), .D(n4936), - .Z(n14_adj_14)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; - defparam i6_4_lut_adj_20.init = 16'h0400; - LUT4 i4_4_lut (.A(FS[1]), .B(n4902), .C(n4920), .D(n6_adj_12), .Z(n4527)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; - defparam i4_4_lut.init = 16'h0100; - PFUMX i3123 (.BLUT(n4125), .ALUT(n760), .C0(InitReady), .Z(n3989)); - LUT4 i1_3_lut (.A(FS[0]), .B(FS[2]), .C(FS[3]), .Z(n6_adj_12)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; - defparam i1_3_lut.init = 16'h4040; - LUT4 i1_2_lut_rep_60 (.A(FS[10]), .B(n14), .Z(n4909)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam i1_2_lut_rep_60.init = 16'heeee; - LUT4 nRCS_N_170_I_0_4_lut (.A(nRCS_N_170), .B(n4918), .C(Ready), .D(nRowColSel_N_35), - .Z(nRRAS_N_189)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6]) - defparam nRCS_N_170_I_0_4_lut.init = 16'h3afa; - LUT4 i1_3_lut_adj_21 (.A(n4882), .B(Din_c_5), .C(Din_c_3), .Z(PHI2_N_151_enable_5)) /* synthesis lut_function=(A ((C)+!B)) */ ; - defparam i1_3_lut_adj_21.init = 16'ha2a2; - LUT4 FS_17__I_0_579_i10_2_lut (.A(FS[12]), .B(FS[13]), .Z(n10_adj_2)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(461[30:46]) - defparam FS_17__I_0_579_i10_2_lut.init = 16'heeee; - LUT4 i3_4_lut_adj_22 (.A(FS[15]), .B(FS[17]), .C(FS[16]), .D(FS[14]), - .Z(n14)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i3_4_lut_adj_22.init = 16'hfffe; - LUT4 i1_2_lut_rep_50_3_lut (.A(FS[10]), .B(n14), .C(FS[11]), .Z(n4899)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam i1_2_lut_rep_50_3_lut.init = 16'hefef; - LUT4 i1_2_lut_rep_43_3_lut_4_lut (.A(FS[10]), .B(n14), .C(n4920), - .D(FS[11]), .Z(n4892)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam i1_2_lut_rep_43_3_lut_4_lut.init = 16'hfeff; - LUT4 i3_4_lut_adj_23 (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n4889), - .Z(XOR8MEG_N_149)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; - defparam i3_4_lut_adj_23.init = 16'h0040; - LUT4 i3712_2_lut_rep_40 (.A(nFWE_c), .B(n2384), .Z(n4889)) /* synthesis lut_function=(A+(B)) */ ; - defparam i3712_2_lut_rep_40.init = 16'heeee; - LUT4 nRCAS_I_46_4_lut (.A(nRCS_N_175), .B(CBR), .C(nRowColSel_N_35), - .D(RASr2), .Z(nRCAS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7]) - defparam nRCAS_I_46_4_lut.init = 16'h3afa; - LUT4 i66_4_lut (.A(FS[10]), .B(n3609), .C(FS[11]), .D(n2308), .Z(n39)) /* synthesis lut_function=(!(A (C+(D))+!A (B+!(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i66_4_lut.init = 16'h101a; - LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_284), .Z(n6_adj_15)) /* synthesis lut_function=(A (B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(83[9] 87[5]) - defparam i2_2_lut.init = 16'h8888; - LUT4 i2_2_lut_4_lut_adj_24 (.A(n4931), .B(Din_c_6), .C(Din_c_2), .D(n4504), - .Z(n6_adj_11)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; - defparam i2_2_lut_4_lut_adj_24.init = 16'h2000; - LUT4 FS_17__I_0_572_i10_2_lut_rep_71 (.A(FS[12]), .B(FS[13]), .Z(n4920)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[30:46]) - defparam FS_17__I_0_572_i10_2_lut_rep_71.init = 16'hdddd; - LUT4 i1676_3_lut_4_lut (.A(nFWE_c), .B(n2384), .C(MAin_c_1), .D(C1Submitted), - .Z(n2549)) /* synthesis lut_function=(A (D)+!A (B (D)+!B !(C+!(D)))) */ ; - defparam i1676_3_lut_4_lut.init = 16'hef00; - LUT4 RA11_I_57_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_217)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(91[22:51]) - defparam RA11_I_57_3_lut.init = 16'hc6c6; - LUT4 i2387_3_lut_4_lut (.A(FS[5]), .B(n4924), .C(FS[11]), .D(n53_adj_9), - .Z(n98)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; - defparam i2387_3_lut_4_lut.init = 16'hfe0e; - LUT4 i1_4_lut (.A(FS[2]), .B(n4884), .C(n4886), .D(n4517), .Z(n1)) /* synthesis lut_function=(!((B (C (D)))+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_4_lut.init = 16'h2aaa; - LUT4 i2506_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_165)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(19[12:17]) - defparam i2506_4_lut.init = 16'hcfc8; - LUT4 i2801_4_lut (.A(FWEr), .B(n4903), .C(n2040), .D(n4_adj_13), - .Z(n1885)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(139[9] 277[5]) - defparam i2801_4_lut.init = 16'h3032; - LUT4 i1_2_lut_adj_25 (.A(CASr3), .B(CBR), .Z(n4_adj_13)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(222[16:37]) - defparam i1_2_lut_adj_25.init = 16'heeee; - LUT4 i2_2_lut_3_lut_4_lut_adj_26 (.A(n4898), .B(n4894), .C(n4897), - .D(FS[11]), .Z(n4519)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; - defparam i2_2_lut_3_lut_4_lut_adj_26.init = 16'h4000; - LUT4 n9_bdd_4_lut_3892 (.A(n4895), .B(n4718), .C(FS[10]), .D(FS[12]), - .Z(n4774)) /* synthesis lut_function=(!(A (((D)+!C)+!B)+!A (B (C (D)+!C !(D))+!B (C+!(D))))) */ ; - defparam n9_bdd_4_lut_3892.init = 16'h05c0; - LUT4 i1_4_lut_adj_27 (.A(FS[10]), .B(n646), .C(n4895), .D(FS[11]), - .Z(n42)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i1_4_lut_adj_27.init = 16'h0544; - LUT4 MAin_9__I_0_565_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), - .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i3_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_565_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), - .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i4_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_565_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), - .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i5_3_lut.init = 16'hcaca; - LUT4 i2319_3_lut_rep_47_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n4938), - .Z(n4896)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i2319_3_lut_rep_47_4_lut.init = 16'h808f; - LUT4 i24_3_lut_rep_48_4_lut (.A(n4937), .B(n4936), .C(FS[9]), .D(n53_adj_9), - .Z(n4897)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i24_3_lut_rep_48_4_lut.init = 16'h808f; - LUT4 i1_3_lut_4_lut_adj_28 (.A(n4927), .B(n4925), .C(FS[10]), .D(FS[12]), - .Z(n175)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; - defparam i1_3_lut_4_lut_adj_28.init = 16'h0100; - LUT4 i1_3_lut_3_lut_4_lut_adj_29 (.A(n4937), .B(n4936), .C(n4938), - .D(FS[9]), .Z(wb_cyc_stb_N_350)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_3_lut_3_lut_4_lut_adj_29.init = 16'h880f; - LUT4 i2708_2_lut_rep_41_3_lut_3_lut_4_lut (.A(n4937), .B(n4936), .C(n4915), - .D(FS[9]), .Z(n4890)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A !(C+(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i2708_2_lut_rep_41_3_lut_3_lut_4_lut.init = 16'h77f0; - LUT4 MAin_9__I_0_565_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), - .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i6_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_565_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), - .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i7_3_lut.init = 16'hcaca; - PFUMX i3831 (.BLUT(n4585), .ALUT(n4730), .C0(FS[12]), .Z(n4731)); - LUT4 MAin_9__I_0_565_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), - .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i8_3_lut.init = 16'hcaca; - CCU2D FS_972_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n4086), - .S1(n95)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_1.INIT0 = 16'hF000; - defparam FS_972_add_4_1.INIT1 = 16'h0555; - defparam FS_972_add_4_1.INJECT1_0 = "NO"; - defparam FS_972_add_4_1.INJECT1_1 = "NO"; - LUT4 MAin_9__I_0_565_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), - .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i9_3_lut.init = 16'hcaca; - LUT4 MAin_9__I_0_565_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), - .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i10_3_lut.init = 16'hcaca; - LUT4 i2_4_lut_4_lut (.A(FS[6]), .B(n4097), .C(FS[11]), .D(n4905), - .Z(n4530)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i2_4_lut_4_lut.init = 16'h0010; - CCU2D FS_972_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n4087), - .COUT(n4088), .S0(n92), .S1(n91)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam FS_972_add_4_5.INIT0 = 16'hfaaa; - defparam FS_972_add_4_5.INIT1 = 16'hfaaa; - defparam FS_972_add_4_5.INJECT1_0 = "NO"; - defparam FS_972_add_4_5.INJECT1_1 = "NO"; - LUT4 i1248_4_lut (.A(wb_cyc_stb_N_350), .B(wb_cyc_stb_N_348), .C(n4893), - .D(n4892), .Z(n2104)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(684[12] 729[6]) - defparam i1248_4_lut.init = 16'h0aca; - LUT4 i2812_2_lut_rep_69 (.A(RCKE_c), .B(RASr2), .Z(n4918)) /* synthesis lut_function=(A+(B)) */ ; - defparam i2812_2_lut_rep_69.init = 16'heeee; - LUT4 i1_2_lut_rep_52_4_lut (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), - .D(CmdUFMShift), .Z(n4901)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam i1_2_lut_rep_52_4_lut.init = 16'h0800; - LUT4 i3810_4_lut (.A(InitReady), .B(n10_adj_2), .C(n4899), .D(n4), - .Z(n4634)) /* synthesis lut_function=(A+!(B+(C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i3810_4_lut.init = 16'habbb; - LUT4 i3792_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_134)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(12[15:34]) - defparam i3792_2_lut.init = 16'hbbbb; - LUT4 i2694_2_lut_rep_67 (.A(FWEr), .B(CBR), .Z(n4916)) /* synthesis lut_function=(A+(B)) */ ; - defparam i2694_2_lut_rep_67.init = 16'heeee; - LUT4 RASr2_I_0_1_lut_rep_72 (.A(RASr2), .Z(n4921)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46]) - defparam RASr2_I_0_1_lut_rep_72.init = 16'h5555; - LUT4 i2_3_lut_rep_68 (.A(CmdSubmitted), .B(PHI2r3), .C(PHI2r2), .Z(n4917)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam i2_3_lut_rep_68.init = 16'h0808; - LUT4 i3742_2_lut (.A(nRowColSel_N_33), .B(CASr2), .Z(n4618)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(178[13] 223[7]) - defparam i3742_2_lut.init = 16'hbbbb; - LUT4 nRWE_I_0_596_4_lut (.A(n3622), .B(nRWE_N_211), .C(Ready), .D(n4906), - .Z(nRWE_N_204)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6]) - defparam nRWE_I_0_596_4_lut.init = 16'hcfc5; - LUT4 i1174_2_lut (.A(FS[9]), .B(n4869), .Z(wb_we_N_351)) /* synthesis lut_function=(!(A (B))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(525[4] 647[11]) - defparam i1174_2_lut.init = 16'h7777; - LUT4 i3224_2_lut (.A(FS[12]), .B(FS[7]), .Z(n4097)) /* synthesis lut_function=(A (B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i3224_2_lut.init = 16'h8888; - LUT4 i1662_2_lut_4_lut (.A(n4548), .B(n4885), .C(n4911), .D(C1Submitted_N_232), - .Z(CmdEnable_N_243)) /* synthesis lut_function=(A (B (D)+!B (C+(D)))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(301[7:24]) - defparam i1662_2_lut_4_lut.init = 16'hff20; - LUT4 i3754_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n22)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; - defparam i3754_2_lut_3_lut.init = 16'h1f1f; - LUT4 i4_4_lut_adj_30 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), - .D(n6), .Z(RCLK_c_enable_20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; - defparam i4_4_lut_adj_30.init = 16'hfffe; - LUT4 mux_427_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[4]), - .D(wb_adr[5]), .Z(n747)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_427_i6_3_lut_4_lut.init = 16'hf780; - LUT4 i1_4_lut_4_lut_adj_31 (.A(RASr2), .B(n6_adj_15), .C(nRowColSel_N_32), - .D(Ready), .Z(Ready_N_280)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(135[40:46]) - defparam i1_4_lut_4_lut_adj_31.init = 16'hff40; - LUT4 InitReady_I_0_586_1_lut_rep_73 (.A(InitReady), .Z(RCLK_c_enable_22)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26]) - defparam InitReady_I_0_586_1_lut_rep_73.init = 16'h5555; - LUT4 nRCS_I_0_590_3_lut (.A(nRCS_N_170), .B(nRCS_N_174), .C(Ready), - .Z(nRCS_N_169)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6]) - defparam nRCS_I_0_590_3_lut.init = 16'hcaca; - LUT4 i1390_4_lut_4_lut (.A(InitReady), .B(n2262), .C(FS[4]), .D(CmdUFMData), - .Z(wb_cyc_stb_N_307)) /* synthesis lut_function=(A (D)+!A !((C)+!B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26]) - defparam i1390_4_lut_4_lut.init = 16'hae04; - LUT4 i2758_2_lut (.A(nRWE_N_210), .B(nRCAS_N_198), .Z(n3622)) /* synthesis lut_function=(A+(B)) */ ; - defparam i2758_2_lut.init = 16'heeee; - LUT4 i1_2_lut_4_lut_4_lut_adj_32 (.A(InitReady), .B(PHI2r2), .C(PHI2r3), - .D(CmdSubmitted), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(!(A (B+!(C (D))))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26]) - defparam i1_2_lut_4_lut_4_lut_adj_32.init = 16'h7555; - LUT4 i1_2_lut_3_lut_adj_33 (.A(n4917), .B(CmdUFMShift), .C(InitReady), - .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B+!(C))+!A !(C)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam i1_2_lut_3_lut_adj_33.init = 16'h8f8f; - LUT4 mux_427_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[5]), - .D(wb_adr[6]), .Z(n746)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_427_i7_3_lut_4_lut.init = 16'hf780; - LUT4 i1_4_lut_4_lut_adj_34 (.A(InitReady), .B(n1), .C(CmdUFMShift), - .D(wb_adr_7__N_92), .Z(n1889)) /* synthesis lut_function=(!(A (C+(D))+!A ((D)+!B))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(710[16:26]) - defparam i1_4_lut_4_lut_adj_34.init = 16'h004e; - PFUMX i36 (.BLUT(n20), .ALUT(n22), .C0(nRowColSel_N_35), .Z(RCKEEN_N_153)); - LUT4 mux_428_i8_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[6]), - .D(wb_dati[7]), .Z(n754)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i8_3_lut_4_lut.init = 16'hf780; - LUT4 MAin_9__I_0_565_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), - .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i2_3_lut.init = 16'hcaca; - LUT4 i1_2_lut_rep_74 (.A(FS[11]), .B(FS[12]), .Z(n4923)) /* synthesis lut_function=(A (B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_rep_74.init = 16'h8888; - LUT4 i1185_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n2040)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7]) - defparam i1185_2_lut.init = 16'heeee; - PFUMX i3897 (.BLUT(n4850), .ALUT(n747), .C0(InitReady), .Z(wb_adr_7__N_60[5])); - LUT4 i2685_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n1965)) /* synthesis lut_function=(A+(B)) */ ; - defparam i2685_2_lut.init = 16'heeee; - LUT4 i1_2_lut_rep_55_3_lut (.A(FS[11]), .B(FS[12]), .C(FS[10]), .Z(n4904)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_rep_55_3_lut.init = 16'h0808; - LUT4 nRWE_I_53_1_lut (.A(nRWE_N_210), .Z(nRWE_N_209)) /* synthesis lut_function=(!(A)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(247[14] 254[8]) - defparam nRWE_I_53_1_lut.init = 16'h5555; - LUT4 i1_2_lut_3_lut_4_lut (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), - .Z(n4164)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i1_2_lut_3_lut_4_lut.init = 16'hfbff; - LUT4 i1_2_lut_rep_46_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(n4927), - .D(FS[5]), .Z(n4895)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; - defparam i1_2_lut_rep_46_3_lut_4_lut.init = 16'hfeff; - LUT4 i3789_3_lut_4_lut_4_lut (.A(n4890), .B(n4859), .C(FS[10]), .D(n4896), - .Z(n56)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (B+(C))) */ ; - defparam i3789_3_lut_4_lut_4_lut.init = 16'hfc5c; - LUT4 n4580_bdd_4_lut (.A(nFWE_c), .B(MAin_c_1), .C(MAin_c_7), .D(Bank[2]), - .Z(n4782)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; - defparam n4580_bdd_4_lut.init = 16'h0040; - LUT4 i2832_2_lut_3_lut_4_lut (.A(FS[9]), .B(FS[8]), .C(FS[6]), .D(FS[5]), - .Z(n3609)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; - defparam i2832_2_lut_3_lut_4_lut.init = 16'hfeff; - LUT4 i2_3_lut_4_lut_adj_35 (.A(FS[7]), .B(FS[6]), .C(n4925), .D(FS[5]), - .Z(n2308)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128[9:13]) - defparam i2_3_lut_4_lut_adj_35.init = 16'hfffb; - LUT4 i1_2_lut_rep_75 (.A(FS[6]), .B(FS[8]), .Z(n4924)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1_2_lut_rep_75.init = 16'heeee; - LUT4 i3_4_lut_adj_36 (.A(CASr2), .B(FWEr), .C(CBR), .D(CASr3), .Z(nRCS_N_179)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; - defparam i3_4_lut_adj_36.init = 16'h0008; - LUT4 i1_2_lut_3_lut_4_lut_adj_37 (.A(FS[6]), .B(FS[8]), .C(n4928), - .D(FS[7]), .Z(n646)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ; - defparam i1_2_lut_3_lut_4_lut_adj_37.init = 16'h0010; - PUR PUR_INST (.PUR(VCC_net)); - defparam PUR_INST.RST_PULSE = 1; - LUT4 i1_2_lut_rep_61_3_lut (.A(FS[6]), .B(FS[8]), .C(FS[7]), .Z(n4910)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; - defparam i1_2_lut_rep_61_3_lut.init = 16'h1010; - LUT4 mux_428_i6_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[4]), - .D(wb_dati[5]), .Z(n756)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i6_3_lut_4_lut.init = 16'hf780; - TSALL TSALL_INST (.TSALL(GND_net)); - LUT4 i1667_3_lut_4_lut (.A(InitReady), .B(n4886), .C(wb_dato[1]), - .D(CmdLEDEN), .Z(LEDEN_N_110)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C))) */ ; - defparam i1667_3_lut_4_lut.init = 16'hfe10; - LUT4 mux_428_i3_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[1]), - .D(wb_dati[2]), .Z(n759)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i3_3_lut_4_lut.init = 16'hf780; - LUT4 i1_2_lut_rep_76 (.A(FS[9]), .B(FS[8]), .Z(n4925)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1_2_lut_rep_76.init = 16'heeee; - LUT4 i1_3_lut_4_lut_adj_38 (.A(n4893), .B(n4892), .C(InitReady), .D(n4917), - .Z(n4513)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ; - defparam i1_3_lut_4_lut_adj_38.init = 16'hf800; - LUT4 i1_2_lut_rep_56_3_lut (.A(FS[9]), .B(FS[8]), .C(FS[5]), .Z(n4905)) /* synthesis lut_function=(A+(B+!(C))) */ ; - defparam i1_2_lut_rep_56_3_lut.init = 16'hefef; - LUT4 i36_4_lut (.A(n5142), .B(n754), .C(InitReady), .D(n17), .Z(wb_dati_7__N_68[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(359[12] 729[6]) - defparam i36_4_lut.init = 16'hcfca; - LUT4 mux_428_i4_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[2]), - .D(wb_dati[3]), .Z(n758)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i4_3_lut_4_lut.init = 16'hf780; - LUT4 i2696_4_lut (.A(nRCS_N_179), .B(nRowColSel_N_34), .C(n4916), - .D(nRowColSel_N_33), .Z(nRCS_N_175)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(187[13] 223[7]) - defparam i2696_4_lut.init = 16'hfcdd; - LUT4 InitReady_I_0_3_lut (.A(InitReady), .B(RCKEEN_N_153), .C(Ready), - .Z(RCKEEN_N_152)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(224[12] 276[6]) - defparam InitReady_I_0_3_lut.init = 16'hcaca; - LUT4 i2726_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n1286)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123[13:16]) - defparam i2726_2_lut.init = 16'heeee; - LUT4 i3795_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; - defparam i3795_2_lut.init = 16'h7777; - LUT4 i95_4_lut (.A(n4894), .B(FS[10]), .C(FS[12]), .D(n4900), .Z(n3711)) /* synthesis lut_function=(A (B (C+(D))+!B ((D)+!C))+!A (B (C+(D))+!B (C (D)))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(78[13:15]) - defparam i95_4_lut.init = 16'hfec2; - LUT4 i2684_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(57[17:46]) - defparam i2684_2_lut.init = 16'hbbbb; - LUT4 mux_428_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[0]), - .D(wb_dati[1]), .Z(n760)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i2_3_lut_4_lut.init = 16'hf780; - LUT4 i2_3_lut_4_lut_adj_39 (.A(FS[9]), .B(FS[8]), .C(FS[7]), .D(n4939), - .Z(n4149)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; - defparam i2_3_lut_4_lut_adj_39.init = 16'hffef; - LUT4 mux_428_i7_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[5]), - .D(wb_dati[6]), .Z(n755)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i7_3_lut_4_lut.init = 16'hf780; - LUT4 mux_428_i5_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_dati[3]), - .D(wb_dati[4]), .Z(n757)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i5_3_lut_4_lut.init = 16'hf780; - LUT4 mux_427_i2_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_adr[0]), - .D(wb_adr[1]), .Z(n751)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_427_i2_3_lut_4_lut.init = 16'hf780; - LUT4 MAin_9__I_0_565_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), - .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(54[19:54]) - defparam MAin_9__I_0_565_i1_3_lut.init = 16'hcaca; - LUT4 mux_428_i1_3_lut_4_lut (.A(n4917), .B(CmdUFMShift), .C(wb_we), - .D(wb_dati[0]), .Z(n761)) /* synthesis lut_function=(A (B (C)+!B (D))+!A (D)) */ ; // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(717[16:47]) - defparam mux_428_i1_3_lut_4_lut.init = 16'hf780; - INV i4008 (.A(PHI2_c), .Z(PHI2_N_151)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(7[8:12]) - INV i4007 (.A(nCRAS_c), .Z(nCRAS_N_9)); // c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(15[15:20]) - PFUMX i3913 (.BLUT(n4940), .ALUT(n4941), .C0(FS[9]), .Z(wb_we_N_354)); - VLO i1 (.Z(GND_net)); - -endmodule -// -// Verilog Description of module PUR -// module not written out since it is a black-box. -// - -// -// Verilog Description of module TSALL -// module not written out since it is a black-box. -// - diff --git a/CPLD/LCMXO2-640HC-old/impl1/automake.log b/CPLD/LCMXO2-640HC-old/impl1/automake.log deleted file mode 100644 index 992228a..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/automake.log +++ /dev/null @@ -1,982 +0,0 @@ - -synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj" -synthesis: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Sat Oct 09 01:19:13 2021 - - -Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui - - -Synthesis options: -The -a option is MachXO2. -The -s option is 4. -The -t option is TQFP100. -The -d option is LCMXO2-640HC. -Using package TQFP100. -Using performance grade 4. - - -########################################################## - -### Lattice Family : MachXO2 - -### Device : LCMXO2-640HC - -### Package : TQFP100 - -### Speed : 4 - -########################################################## - - - - -Optimization goal = Balanced -Top-level module name = RAM2GS. -Target frequency = 200.000000 MHz. -Maximum fanout = 1000. -Timing path count = 3 -BRAM utilization = 100.000000 % -DSP usage = true -DSP utilization = 100.000000 % -fsm_encoding_style = auto -resolve_mixed_drivers = 0 -fix_gated_clocks = 1 - -Mux style = Auto -Use Carry Chain = true -carry_chain_length = 0 -Loop Limit = 1950. -Use IO Insertion = TRUE -Use IO Reg = AUTO - -Resource Sharing = TRUE -Propagate Constants = TRUE -Remove Duplicate Registers = TRUE -force_gsr = auto -ROM style = auto -RAM style = auto -The -comp option is FALSE. -The -syn option is FALSE. --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added) --p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added) --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added) -Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v -NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd --sdc option: SDC file input not used. --lpf option: Output file option is ON. -Hardtimer checking is enabled (default). The -dt option is not used. -The -r option is OFF. [ Remove LOC Properties is OFF. ] -Technology check ok... - -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Compile design. -Compile Design Begin -Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482 -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Top module name (Verilog): RAM2GS - - - - - - -Last elaborated design is RAM2GS() -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Top-level module name = RAM2GS. -######## Missing driver on net n1128. Patching with GND. -######## Missing driver on net n1132. Patching with GND. -######## Missing driver on net n1133. Patching with GND. -######## Missing driver on net n1134. Patching with GND. -######## Missing driver on net n1135. Patching with GND. -######## Missing driver on net n1131. Patching with GND. -######## Missing driver on net n1130. Patching with GND. -######## Missing driver on net n1136. Patching with GND. -######## Missing driver on net n1137. Patching with GND. -######## Missing driver on net n1138. Patching with GND. -######## Missing driver on net n1139. Patching with GND. -######## Missing driver on net n1140. Patching with GND. -######## Missing driver on net n1141. Patching with GND. -######## Missing driver on net n1142. Patching with GND. -######## Missing driver on net n1143. Patching with GND. -######## Missing driver on net n1144. Patching with GND. -######## Missing driver on net n1145. Patching with GND. -######## Missing driver on net n1146. Patching with GND. -######## Missing driver on net n1147. Patching with GND. -######## Missing driver on net n1148. Patching with GND. -######## Missing driver on net n1129. Patching with GND. -######## Missing driver on net n1149. Patching with GND. -######## Missing driver on net n1150. Patching with GND. -######## Missing driver on net n1151. Patching with GND. -######## Missing driver on net n1152. Patching with GND. -######## Missing driver on net n1153. Patching with GND. -######## Missing driver on net n1154. Patching with GND. -######## Missing driver on net n1155. Patching with GND. -######## Missing driver on net n1156. Patching with GND. -######## Missing driver on net n1157. Patching with GND. - -original encoding -> new encoding (one-hot encoding) - - 0000 -> 0000000000000001 - - 0001 -> 0000000000000010 - - 0010 -> 0000000000000100 - - 0011 -> 0000000000001000 - - 0100 -> 0000000000010000 - - 0101 -> 0000000000100000 - - 0110 -> 0000000001000000 - - 0111 -> 0000000010000000 - - 1000 -> 0000000100000000 - - 1001 -> 0000001000000000 - - 1010 -> 0000010000000000 - - 1011 -> 0000100000000000 - - 1100 -> 0001000000000000 - - 1101 -> 0010000000000000 - - 1110 -> 0100000000000000 - - 1111 -> 1000000000000000 - - -original encoding -> new encoding (one-hot encoding) - - 00 -> 0001 - - 01 -> 0010 - - 10 -> 0100 - - 11 -> 1000 - - - - -GSR will not be inferred because no asynchronous signal was found in the netlist. - -Applying 200.000000 MHz constraint to all clocks - - -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 452 blocks expanded -completed the first expansion -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. - -################### Begin Area Report (RAM2GS)###################### -Number of register bits => 119 of 877 (13 % ) -BB => 8 -CCU2D => 10 -EFB => 1 -FD1P3AX => 30 -FD1P3AY => 4 -FD1P3IX => 3 -FD1S3AX => 64 -FD1S3IX => 14 -FD1S3JX => 4 -GSR => 1 -IB => 25 -INV => 3 -LUT4 => 236 -OB => 30 -PFUMX => 16 -################### End Area Report ################## - -################### Begin BlackBox Report ###################### -TSALL => 1 -################### End BlackBox Report ################## - -################### Begin Clock Report ###################### -Clock Nets -Number of Clocks: 5 - Net : RCLK_c, loads : 79 - Net : PHI2_c, loads : 11 - Net : nCRAS_c, loads : 2 - Net : nCCAS_c, loads : 2 - Net : wb_clk, loads : 1 -Clock Enable Nets -Number of Clock Enables: 14 -Top 10 highest fanout Clock Enables: - Net : RCLK_c_enable_27, loads : 16 - Net : RCLK_c_enable_20, loads : 4 - Net : RCLK_c_enable_25, loads : 2 - Net : RCLK_c_enable_24, loads : 2 - Net : RCLK_c_enable_29, loads : 2 - Net : PHI2_N_151_enable_5, loads : 2 - Net : PHI2_N_151_enable_3, loads : 2 - Net : PHI2_N_151_enable_1, loads : 1 - Net : Ready_N_280, loads : 1 - Net : PHI2_N_151_enable_6, loads : 1 -Highest fanout non-clock nets -Top 10 highest fanout non-clock nets: - Net : InitReady, loads : 36 - Net : FS_11, loads : 32 - Net : FS_10, loads : 32 - Net : FS_9, loads : 26 - Net : FS_7, loads : 25 - Net : FS_8, loads : 23 - Net : FS_6, loads : 21 - Net : FS_5, loads : 21 - Net : FS_12, loads : 20 - Net : CmdUFMShift, loads : 16 -################### End Clock Report ################## - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 * - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - - -Peak Memory Usage: 58.262 MB - --------------------------------------------------------------- -Elapsed CPU time for LSE flow : 0.813 secs --------------------------------------------------------------- - -map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0 -map: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd - Picdevice="LCMXO2-640HC" - - Pictype="TQFP100" - - Picspeed=4 - - Remove unused logic - - Do not produce over sized NCDs. - -Part used: LCMXO2-640HCTQFP100, Performance used: 4. - -Loading device for application baspr from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. - -Running general design DRC... - -Removing unused logic... - -Optimizing... - - - - -Design Summary: - Number of registers: 119 out of 877 (14%) - PFU registers: 119 out of 640 (19%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 131 out of 320 (41%) - SLICEs as Logic/ROM: 131 out of 320 (41%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 255 out of 640 (40%) - Number used as logic LUTs: 235 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. - Number of clocks: 5 - Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_20: 4 loads, 4 LSLICEs - Net RCLK_c_enable_29: 2 loads, 2 LSLICEs - Net RCLK_c_enable_25: 2 loads, 2 LSLICEs - Net InitReady: 1 loads, 1 LSLICEs - Net RCLK_c_enable_24: 2 loads, 2 LSLICEs - Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs - Net RCLK_c_enable_26: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs - Net Ready_N_280: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs - Number of LSRs: 8 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Net wb_rst: 1 loads, 0 LSLICEs - Net nRWE_N_210: 1 loads, 1 LSLICEs - Net C1Submitted_N_232: 2 loads, 2 LSLICEs - Net wb_adr_7__N_92: 2 loads, 2 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 36 loads - Net FS_10: 32 loads - Net FS_11: 32 loads - Net FS_9: 26 loads - Net FS_7: 25 loads - Net FS_8: 23 loads - Net FS_5: 21 loads - Net FS_6: 21 loads - Net FS_12: 20 loads - Net Ready: 18 loads - - - Number of warnings: 0 - Number of errors: 0 - - - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 37 MB - -Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd. - -ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" - -Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. - -trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:15 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:15 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 42 MB - - -mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd" - ----- MParTrce Tool ---- -Removing old design directory at request of -rem command line option to this program. -Running par. Please wait . . . - -Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -Sat Oct 09 01:19:16 2021 - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 63+4(JTAG)/80 84% used - 63+4(JTAG)/79 85% bonded - - SLICE 131/320 40% used - - EFB 1/1 100% used - - -Number of Signals: 401 -Number of Connections: 1131 - -Pin Constraint Summary: - 63 out of 63 pins locked (100% locked). - -The following 4 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 52) - PHI2_c (driver: PHI2, clk load #: 13) - nCRAS_c (driver: nCRAS, clk load #: 7) - nCCAS_c (driver: nCCAS, clk load #: 4) - - - - - -No signal is selected as secondary clock. - -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -............ -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -.................... -Placer score = 65362. -Finished Placer Phase 1. REAL time: 4 secs - -Starting Placer Phase 2. -. -Placer score = 65089 -Finished Placer Phase 2. REAL time: 4 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 8 (12%) - General PIO: 3 out of 80 (3%) - DCM : 0 out of 2 (0%) - DCC : 0 out of 8 (0%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7 - PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4 - - PRIMARY : 4 out of 8 (50%) - SECONDARY: 0 out of 8 (0%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. - 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. - Number of PIO comps: 63; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+-----------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref | -+----------+----------------+------------+-----------+ -| 0 | 13 / 19 ( 68%) | 3.3V | - | -| 1 | 20 / 20 (100%) | 3.3V | - | -| 2 | 12 / 20 ( 60%) | 3.3V | - | -| 3 | 18 / 20 ( 90%) | 3.3V | - | -+----------+----------------+------------+-----------+ - -Total placer CPU time: 4 secs - -Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. - -0 connections routed; 1131 unrouted. -Starting router resource preassignment - - - - - - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 01:19:22 10/09/21 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 01:19:22 10/09/21 - -Start NBR section for initial routing at 01:19:22 10/09/21 -Level 1, iteration 1 -0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 01:19:22 10/09/21 -Level 1, iteration 1 -1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs -Level 4, iteration 1 -12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs -Level 4, iteration 2 -5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs -Level 4, iteration 3 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21 - -Start NBR section for re-routing at 01:19:23 10/09/21 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs - -Start NBR section for post-routing at 01:19:23 10/09/21 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 1.135ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - - - -Total CPU time 7 secs -Total REAL time: 7 secs -Completely routed. -End of route. 1131 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 1.135 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.304 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 7 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Exiting par with exit code 0 -Exiting mpartrce with exit code 0 - -trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -trce: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:23 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Sat Oct 09 01:19:24 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -Design file: ram2gs_lcmxo2_640hc_impl1.ncd -Preference file: ram2gs_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - -VCCIO Voltage: - 3.135 V (Bank 0) - 3.135 V (Bank 1) - 3.135 V (Bank 2) - 3.135 V (Bank 3) - 2.375 V (Bank 4) - 2.375 V (Bank 5) - 2.375 V (Bank 6) - 2.375 V (Bank 7) - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 42 MB - - -iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" -I/O Timing Report: -: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 4 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 5 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: 6 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Running Performance Grade: M -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... -Done. diff --git a/CPLD/LCMXO2-640HC-old/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC-old/impl1/hdla_gen_hierarchy.html deleted file mode 100644 index 2d209a5..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/hdla_gen_hierarchy.html +++ /dev/null @@ -1,12 +0,0 @@ - 
    Setting log file to 'C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file 'C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v'
-INFO - C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(1,1-731,10) (VERI-9000) elaborating module 'RAM2GS'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
-WARNING - C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-2435) port 'PLL0DATI7' is not connected on this instance
-WARNING - C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v(325,2-348,25) (VERI-1927) port 'WBDATO7' remains unconnected for this instance
-Done: design load finished with (0) errors, and (2) warnings
-
-
    \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1.ior deleted file mode 100644 index ac9917c..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1.ior +++ /dev/null @@ -1,133 +0,0 @@ -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -// Design: RAM2GS -// Package: TQFP100 -// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd -// Version: Diamond (64-bit) 3.12.0.240.2 -// Written on Sat Oct 09 01:19:25 2021 -// M: Minimum Performance Grade -// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui - -I/O Timing Report (All units are in ns) - -Worst Case Results across Performance Grades (M, 6, 5, 4): - -// Input Setup and Hold Times - -Port Clock Edge Setup Performance_Grade Hold Performance_Grade ----------------------------------------------------------------------- -CROW[0] nCRAS F -0.195 M 1.729 4 -CROW[1] nCRAS F -0.218 M 1.801 4 -Din[0] PHI2 F 6.339 4 1.186 4 -Din[0] nCCAS F 1.641 4 0.107 M -Din[1] PHI2 F 6.084 4 1.570 4 -Din[1] nCCAS F 0.198 4 1.314 4 -Din[2] PHI2 F 3.778 4 1.771 4 -Din[2] nCCAS F 0.075 4 1.431 4 -Din[3] PHI2 F 4.331 4 1.705 4 -Din[3] nCCAS F -0.116 M 1.722 4 -Din[4] PHI2 F 6.176 4 1.711 4 -Din[4] nCCAS F 1.065 4 0.575 4 -Din[5] PHI2 F 4.684 4 1.261 4 -Din[5] nCCAS F -0.081 M 1.625 4 -Din[6] PHI2 F 5.243 4 0.356 4 -Din[6] nCCAS F 1.414 4 0.309 4 -Din[7] PHI2 F 6.602 4 1.175 4 -Din[7] nCCAS F -0.286 M 2.137 4 -MAin[0] PHI2 F 5.034 4 0.629 4 -MAin[0] nCRAS F 1.094 4 0.380 4 -MAin[1] PHI2 F 6.081 4 1.157 4 -MAin[1] nCRAS F 0.544 4 0.877 4 -MAin[2] PHI2 F 9.979 4 -0.319 M -MAin[2] nCRAS F -0.050 M 1.401 4 -MAin[3] PHI2 F 9.162 4 -0.219 M -MAin[3] nCRAS F 1.032 4 0.440 4 -MAin[4] PHI2 F 11.678 4 -0.770 M -MAin[4] nCRAS F -0.150 M 1.620 4 -MAin[5] PHI2 F 8.668 4 -0.081 M -MAin[5] nCRAS F -0.050 M 1.401 4 -MAin[6] PHI2 F 8.516 4 -0.025 M -MAin[6] nCRAS F 1.003 4 0.478 4 -MAin[7] PHI2 F 9.320 4 -0.061 M -MAin[7] nCRAS F 1.001 4 0.478 4 -MAin[8] nCRAS F -0.146 M 1.657 4 -MAin[9] nCRAS F -0.360 M 2.140 4 -PHI2 RCLK R 3.079 4 -0.602 M -nCCAS RCLK R 3.574 4 -0.705 M -nCCAS nCRAS F 3.232 4 -0.351 M -nCRAS RCLK R 2.757 4 -0.470 M -nFWE PHI2 F 5.913 4 0.723 4 -nFWE nCRAS F 0.547 4 0.890 4 - - -// Clock to Output Delay - -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------- -LED RCLK R 10.062 4 3.164 M -RA[0] RCLK R 10.645 4 3.471 M -RA[0] nCRAS F 11.744 4 3.770 M -RA[10] RCLK R 9.485 4 3.236 M -RA[11] PHI2 R 11.513 4 3.824 M -RA[1] RCLK R 10.921 4 3.549 M -RA[1] nCRAS F 12.664 4 4.036 M -RA[2] RCLK R 10.923 4 3.527 M -RA[2] nCRAS F 12.463 4 3.984 M -RA[3] RCLK R 11.178 4 3.615 M -RA[3] nCRAS F 12.304 4 3.917 M -RA[4] RCLK R 11.365 4 3.630 M -RA[4] nCRAS F 13.243 4 4.179 M -RA[5] RCLK R 11.365 4 3.630 M -RA[5] nCRAS F 12.940 4 4.098 M -RA[6] RCLK R 11.099 4 3.573 M -RA[6] nCRAS F 12.162 4 3.870 M -RA[7] RCLK R 10.948 4 3.552 M -RA[7] nCRAS F 12.282 4 3.936 M -RA[8] RCLK R 11.114 4 3.608 M -RA[8] nCRAS F 12.909 4 4.116 M -RA[9] RCLK R 11.005 4 3.561 M -RA[9] nCRAS F 12.959 4 4.081 M -RBA[0] nCRAS F 11.842 4 3.911 M -RBA[1] nCRAS F 11.343 4 3.771 M -RCKE RCLK R 9.884 4 3.362 M -RDQMH RCLK R 10.941 4 3.559 M -RDQML RCLK R 10.641 4 3.470 M -RD[0] nCCAS F 12.628 4 4.413 M -RD[1] nCCAS F 12.231 4 4.302 M -RD[2] nCCAS F 12.231 4 4.302 M -RD[3] nCCAS F 11.928 4 4.221 M -RD[4] nCCAS F 12.427 4 4.361 M -RD[5] nCCAS F 12.697 4 4.400 M -RD[6] nCCAS F 12.427 4 4.361 M -RD[7] nCCAS F 12.427 4 4.361 M -nRCAS RCLK R 9.674 4 3.300 M -nRCS RCLK R 9.674 4 3.300 M -nRRAS RCLK R 9.797 4 3.322 M -nRWE RCLK R 9.275 4 3.194 M -WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd deleted file mode 100644 index 0409f06..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd +++ /dev/null @@ -1,91 +0,0 @@ -[ActiveSupport TRCE] -; Setup Analysis -Period_0 = 25.800 ns (350.000 ns); -Period_1 = 2.500 ns (350.000 ns); -Period_2 = 2.500 ns (350.000 ns); -Period_3 = 12.427 ns (16.000 ns); -Tco_4 = - (-); -Tco_5 = - (-); -Tco_6 = - (-); -Tco_7 = - (-); -Tco_8 = - (-); -Tco_9 = - (-); -Tco_10 = - (-); -Tco_11 = - (-); -Tco_12 = - (-); -Tco_13 = - (-); -Tco_14 = - (-); -Tco_15 = - (-); -Tco_16 = 9.485 ns (12.500 ns); -Tco_17 = 11.005 ns (12.500 ns); -Tco_18 = 11.114 ns (12.500 ns); -Tco_19 = 10.948 ns (12.500 ns); -Tco_20 = 11.099 ns (12.500 ns); -Tco_21 = 11.365 ns (12.500 ns); -Tco_22 = 11.365 ns (12.500 ns); -Tco_23 = 11.178 ns (12.500 ns); -Tco_24 = 10.923 ns (12.500 ns); -Tco_25 = 10.921 ns (12.500 ns); -Tco_26 = 10.645 ns (12.500 ns); -Tco_27 = 9.674 ns (12.500 ns); -Tco_28 = 9.884 ns (12.500 ns); -Tco_29 = 9.275 ns (12.500 ns); -Tco_30 = 9.797 ns (12.500 ns); -Tco_31 = 9.674 ns (12.500 ns); -Tco_32 = 10.941 ns (12.500 ns); -Tco_33 = 10.641 ns (12.500 ns); -Tco_34 = - (-); -Tco_35 = - (-); -Tco_36 = - (-); -Tco_37 = - (-); -Tco_38 = - (-); -Tco_39 = - (-); -Tco_40 = - (-); -Failed = 0 (Total 41); -Clock_ports = 4; -Clock_nets = 5; -; Hold Analysis -Period_0 = - (-); -Period_1 = - (-); -Period_2 = - (-); -Period_3 = - (-); -Tco_4 = - (-); -Tco_5 = - (-); -Tco_6 = - (-); -Tco_7 = - (-); -Tco_8 = - (-); -Tco_9 = - (-); -Tco_10 = - (-); -Tco_11 = - (-); -Tco_12 = - (-); -Tco_13 = - (-); -Tco_14 = - (-); -Tco_15 = - (-); -Tco_16 = 3.236 ns (0.000 ns); -Tco_17 = 3.561 ns (0.000 ns); -Tco_18 = 3.608 ns (0.000 ns); -Tco_19 = 3.552 ns (0.000 ns); -Tco_20 = 3.573 ns (0.000 ns); -Tco_21 = 3.630 ns (0.000 ns); -Tco_22 = 3.630 ns (0.000 ns); -Tco_23 = 3.615 ns (0.000 ns); -Tco_24 = 3.527 ns (0.000 ns); -Tco_25 = 3.549 ns (0.000 ns); -Tco_26 = 3.471 ns (0.000 ns); -Tco_27 = 3.300 ns (0.000 ns); -Tco_28 = 3.362 ns (0.000 ns); -Tco_29 = 3.194 ns (0.000 ns); -Tco_30 = 3.322 ns (0.000 ns); -Tco_31 = 3.300 ns (0.000 ns); -Tco_32 = 3.559 ns (0.000 ns); -Tco_33 = 3.470 ns (0.000 ns); -Tco_34 = - (-); -Tco_35 = - (-); -Tco_36 = - (-); -Tco_37 = - (-); -Tco_38 = - (-); -Tco_39 = - (-); -Tco_40 = - (-); -Failed = 0 (Total 41); -Clock_ports = 4; -Clock_nets = 5; diff --git a/CPLD/LCMXO2-640HC-old/impl1/synthesis.log b/CPLD/LCMXO2-640HC-old/impl1/synthesis.log deleted file mode 100644 index 82a7043..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/synthesis.log +++ /dev/null @@ -1,271 +0,0 @@ -synthesis: version Diamond (64-bit) 3.12.0.240.2 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Sat Oct 09 01:19:13 2021 - - -Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui - -Synthesis options: -The -a option is MachXO2. -The -s option is 4. -The -t option is TQFP100. -The -d option is LCMXO2-640HC. -Using package TQFP100. -Using performance grade 4. - - -########################################################## - -### Lattice Family : MachXO2 - -### Device : LCMXO2-640HC - -### Package : TQFP100 - -### Speed : 4 - -########################################################## - - - -INFO - synthesis: User-Selected Strategy Settings -Optimization goal = Balanced -Top-level module name = RAM2GS. -Target frequency = 200.000000 MHz. -Maximum fanout = 1000. -Timing path count = 3 -BRAM utilization = 100.000000 % -DSP usage = true -DSP utilization = 100.000000 % -fsm_encoding_style = auto -resolve_mixed_drivers = 0 -fix_gated_clocks = 1 - -Mux style = Auto -Use Carry Chain = true -carry_chain_length = 0 -Loop Limit = 1950. -Use IO Insertion = TRUE -Use IO Reg = AUTO - -Resource Sharing = TRUE -Propagate Constants = TRUE -Remove Duplicate Registers = TRUE -force_gsr = auto -ROM style = auto -RAM style = auto -The -comp option is FALSE. -The -syn option is FALSE. --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added) --p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added) --p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added) -Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v -NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd --sdc option: SDC file input not used. --lpf option: Output file option is ON. -Hardtimer checking is enabled (default). The -dt option is not used. -The -r option is OFF. [ Remove LOC Properties is OFF. ] -Technology check ok... - -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Compile design. -Compile Design Begin -Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482 -Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 -Top module name (Verilog): RAM2GS -INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018 -WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209 -WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209 -WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209 -INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018 -WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013 -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Top-level module name = RAM2GS. -######## Missing driver on net n1128. Patching with GND. -######## Missing driver on net n1132. Patching with GND. -######## Missing driver on net n1133. Patching with GND. -######## Missing driver on net n1134. Patching with GND. -######## Missing driver on net n1135. Patching with GND. -######## Missing driver on net n1131. Patching with GND. -######## Missing driver on net n1130. Patching with GND. -######## Missing driver on net n1136. Patching with GND. -######## Missing driver on net n1137. Patching with GND. -######## Missing driver on net n1138. Patching with GND. -######## Missing driver on net n1139. Patching with GND. -######## Missing driver on net n1140. Patching with GND. -######## Missing driver on net n1141. Patching with GND. -######## Missing driver on net n1142. Patching with GND. -######## Missing driver on net n1143. Patching with GND. -######## Missing driver on net n1144. Patching with GND. -######## Missing driver on net n1145. Patching with GND. -######## Missing driver on net n1146. Patching with GND. -######## Missing driver on net n1147. Patching with GND. -######## Missing driver on net n1148. Patching with GND. -######## Missing driver on net n1129. Patching with GND. -######## Missing driver on net n1149. Patching with GND. -######## Missing driver on net n1150. Patching with GND. -######## Missing driver on net n1151. Patching with GND. -######## Missing driver on net n1152. Patching with GND. -######## Missing driver on net n1153. Patching with GND. -######## Missing driver on net n1154. Patching with GND. -######## Missing driver on net n1155. Patching with GND. -######## Missing driver on net n1156. Patching with GND. -######## Missing driver on net n1157. Patching with GND. -INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding -original encoding -> new encoding (one-hot encoding) - - 0000 -> 0000000000000001 - - 0001 -> 0000000000000010 - - 0010 -> 0000000000000100 - - 0011 -> 0000000000001000 - - 0100 -> 0000000000010000 - - 0101 -> 0000000000100000 - - 0110 -> 0000000001000000 - - 0111 -> 0000000010000000 - - 1000 -> 0000000100000000 - - 1001 -> 0000001000000000 - - 1010 -> 0000010000000000 - - 1011 -> 0000100000000000 - - 1100 -> 0001000000000000 - - 1101 -> 0010000000000000 - - 1110 -> 0100000000000000 - - 1111 -> 1000000000000000 - -INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding -original encoding -> new encoding (one-hot encoding) - - 00 -> 0001 - - 01 -> 0010 - - 10 -> 0100 - - 11 -> 1000 - - - - -GSR will not be inferred because no asynchronous signal was found in the netlist. -WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored. -Applying 200.000000 MHz constraint to all clocks - -WARNING - synthesis: No user .sdc file. -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. - -################### Begin Area Report (RAM2GS)###################### -Number of register bits => 119 of 877 (13 % ) -BB => 8 -CCU2D => 10 -EFB => 1 -FD1P3AX => 30 -FD1P3AY => 4 -FD1P3IX => 3 -FD1S3AX => 64 -FD1S3IX => 14 -FD1S3JX => 4 -GSR => 1 -IB => 25 -INV => 3 -LUT4 => 236 -OB => 30 -PFUMX => 16 -################### End Area Report ################## - -################### Begin BlackBox Report ###################### -TSALL => 1 -################### End BlackBox Report ################## - -################### Begin Clock Report ###################### -Clock Nets -Number of Clocks: 5 - Net : RCLK_c, loads : 79 - Net : PHI2_c, loads : 11 - Net : nCRAS_c, loads : 2 - Net : nCCAS_c, loads : 2 - Net : wb_clk, loads : 1 -Clock Enable Nets -Number of Clock Enables: 14 -Top 10 highest fanout Clock Enables: - Net : RCLK_c_enable_27, loads : 16 - Net : RCLK_c_enable_20, loads : 4 - Net : RCLK_c_enable_25, loads : 2 - Net : RCLK_c_enable_24, loads : 2 - Net : RCLK_c_enable_29, loads : 2 - Net : PHI2_N_151_enable_5, loads : 2 - Net : PHI2_N_151_enable_3, loads : 2 - Net : PHI2_N_151_enable_1, loads : 1 - Net : Ready_N_280, loads : 1 - Net : PHI2_N_151_enable_6, loads : 1 -Highest fanout non-clock nets -Top 10 highest fanout non-clock nets: - Net : InitReady, loads : 36 - Net : FS_11, loads : 32 - Net : FS_10, loads : 32 - Net : FS_9, loads : 26 - Net : FS_7, loads : 25 - Net : FS_8, loads : 23 - Net : FS_6, loads : 21 - Net : FS_5, loads : 21 - Net : FS_12, loads : 20 - Net : CmdUFMShift, loads : 16 -################### End Clock Report ################## - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 * - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - - -Peak Memory Usage: 58.262 MB - --------------------------------------------------------------- -Elapsed CPU time for LSE flow : 0.813 secs --------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC-old/impl1/synthesis_lse.html b/CPLD/LCMXO2-640HC-old/impl1/synthesis_lse.html deleted file mode 100644 index 09f48e2..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/synthesis_lse.html +++ /dev/null @@ -1,336 +0,0 @@ - -Synthesis and Ngdbuild Report - - -
    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.12.0.240.2
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Sat Oct 09 01:19:13 2021
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui 
-
-Synthesis options:
-The -a option is MachXO2.
-The -s option is 4.
-The -t option is TQFP100.
-The -d option is LCMXO2-640HC.
-Using package TQFP100.
-Using performance grade 4.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO2
-
-### Device  : LCMXO2-640HC
-
-### Package : TQFP100
-
-### Speed   : 4
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
--p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
--p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
-NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
-INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
-WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Top-level module name = RAM2GS.
-######## Missing driver on net n1128. Patching with GND.
-######## Missing driver on net n1132. Patching with GND.
-######## Missing driver on net n1133. Patching with GND.
-######## Missing driver on net n1134. Patching with GND.
-######## Missing driver on net n1135. Patching with GND.
-######## Missing driver on net n1131. Patching with GND.
-######## Missing driver on net n1130. Patching with GND.
-######## Missing driver on net n1136. Patching with GND.
-######## Missing driver on net n1137. Patching with GND.
-######## Missing driver on net n1138. Patching with GND.
-######## Missing driver on net n1139. Patching with GND.
-######## Missing driver on net n1140. Patching with GND.
-######## Missing driver on net n1141. Patching with GND.
-######## Missing driver on net n1142. Patching with GND.
-######## Missing driver on net n1143. Patching with GND.
-######## Missing driver on net n1144. Patching with GND.
-######## Missing driver on net n1145. Patching with GND.
-######## Missing driver on net n1146. Patching with GND.
-######## Missing driver on net n1147. Patching with GND.
-######## Missing driver on net n1148. Patching with GND.
-######## Missing driver on net n1129. Patching with GND.
-######## Missing driver on net n1149. Patching with GND.
-######## Missing driver on net n1150. Patching with GND.
-######## Missing driver on net n1151. Patching with GND.
-######## Missing driver on net n1152. Patching with GND.
-######## Missing driver on net n1153. Patching with GND.
-######## Missing driver on net n1154. Patching with GND.
-######## Missing driver on net n1155. Patching with GND.
-######## Missing driver on net n1156. Patching with GND.
-######## Missing driver on net n1157. Patching with GND.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 119 of 877 (13 % )
-BB => 8
-CCU2D => 10
-EFB => 1
-FD1P3AX => 30
-FD1P3AY => 4
-FD1P3IX => 3
-FD1S3AX => 64
-FD1S3IX => 14
-FD1S3JX => 4
-GSR => 1
-IB => 25
-INV => 3
-LUT4 => 236
-OB => 30
-PFUMX => 16
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 5
-  Net : RCLK_c, loads : 79
-  Net : PHI2_c, loads : 11
-  Net : nCRAS_c, loads : 2
-  Net : nCCAS_c, loads : 2
-  Net : wb_clk, loads : 1
-Clock Enable Nets
-Number of Clock Enables: 14
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : RCLK_c_enable_20, loads : 4
-  Net : RCLK_c_enable_25, loads : 2
-  Net : RCLK_c_enable_24, loads : 2
-  Net : RCLK_c_enable_29, loads : 2
-  Net : PHI2_N_151_enable_5, loads : 2
-  Net : PHI2_N_151_enable_3, loads : 2
-  Net : PHI2_N_151_enable_1, loads : 1
-  Net : Ready_N_280, loads : 1
-  Net : PHI2_N_151_enable_6, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 36
-  Net : FS_11, loads : 32
-  Net : FS_10, loads : 32
-  Net : FS_9, loads : 26
-  Net : FS_7, loads : 25
-  Net : FS_8, loads : 23
-  Net : FS_6, loads : 21
-  Net : FS_5, loads : 21
-  Net : FS_12, loads : 20
-  Net : CmdUFMShift, loads : 16
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets PHI2_c]                  |  200.000 MHz|   38.150 MHz|     8 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|   65.694 MHz|    10 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 58.262  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.813  secs
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    - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC-old/impl1/xxx_lse_cp_file_list deleted file mode 100644 index b0e606a..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/xxx_lse_cp_file_list +++ /dev/null @@ -1,350 +0,0 @@ -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v -3 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+sceneInViewRect=@Variant(\0\0\0\x14@3h.|\xba\x3\x42@\xbd\b\xdd\x8c\x9aJ\xe0@\xdf\x1e\x8e\x8b\0\x46\x39@\xc7\x15kK[@\xe0) diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini index 4c7a004..1546db3 100644 --- a/CPLD/LCMXO2-640HC/.setting.ini +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -1,4 +1,3 @@ [General] Export.auto_tasks=Jedecgen PAR.auto_tasks=@@empty() -Map.auto_tasks=@@empty() diff --git a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini index 0d0cdb7..f2afd63 100644 --- a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini +++ b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini @@ -6,7 +6,7 @@ sig_sort_ascending=true active_Sheet=Port Assignments [Port%20Assignments] -Name="154,0" +Name="160,0" Group%20By="84,1" Pin="50,2" BANK="62,3" diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf similarity index 54% rename from CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf rename to CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf index 5b8e620..4204338 100644 --- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf @@ -1,20 +1,20 @@ - + - + - + - + - + diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf new file mode 100644 index 0000000..325063a --- /dev/null +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf @@ -0,0 +1,2 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/LCMXO2_640HC1.sty similarity index 100% rename from CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC1.sty rename to CPLD/LCMXO2-640HC/LCMXO2_640HC1.sty diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html similarity index 63% rename from CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html rename to CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html index b1bb2c0..ff52e3e 100644 --- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html +++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html @@ -6,24 +6,14 @@ --> -
    pn230815045824
-#Start recording tcl command: 8/15/2023 04:58:13
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
-RAM2GS_LCMXO2_1200HC
-#Start recording tcl command: 8/15/2023 04:58:24
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
-prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
-#Stop recording: 8/15/2023 04:58:24
-
-
-
-pn230815050055
-#Start recording tcl command: 8/15/2023 05:00:44
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-#Stop recording: 8/15/2023 05:00:55
+
    pn230816203441
+#Start recording tcl command: 8/16/2023 20:34:10
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
+prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
+prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+prj_project save
+prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
+#Stop recording: 8/16/2023 20:34:41
 
 
 
diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816203441.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816203441.tcr
new file mode 100644
index 0000000..52a30f6
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816203441.tcr
@@ -0,0 +1,7 @@
+#Start recording tcl command: 8/16/2023 20:34:10
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
+prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
+prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+prj_project save
+prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
+#Stop recording: 8/16/2023 20:34:41
diff --git a/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816210353.tcr b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816210353.tcr
new file mode 100644
index 0000000..7cd8ca4
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230816210353.tcr
@@ -0,0 +1,24 @@
+#Start recording tcl command: 8/16/2023 20:34:55
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Synthesis -impl impl1
+prj_run Map -impl impl1
+prj_run Export -impl impl1
+prj_run PAR -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
+prj_run Export -impl impl1
+#Stop recording: 8/16/2023 21:03:53
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl b/CPLD/LCMXO2-640HC/RAM2GS-LCMXO2.ccl
similarity index 100%
rename from CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl
rename to CPLD/LCMXO2-640HC/RAM2GS-LCMXO2.ccl
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
deleted file mode 100644
index 39b91c8..0000000
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
+++ /dev/null
@@ -1,205 +0,0 @@
-
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diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr
deleted file mode 100644
index a9d6771..0000000
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr
+++ /dev/null
@@ -1,9 +0,0 @@
-#Start recording tcl command: 8/15/2023 04:58:13
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
-RAM2GS_LCMXO2_1200HC
-#Start recording tcl command: 8/15/2023 04:58:24
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
-prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
-#Stop recording: 8/15/2023 04:58:24
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr
deleted file mode 100644
index 4ca6762..0000000
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr
+++ /dev/null
@@ -1,4 +0,0 @@
-#Start recording tcl command: 8/15/2023 05:00:44
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-#Stop recording: 8/15/2023 05:00:55
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr
deleted file mode 100644
index 391d367..0000000
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230816015720.tcr
+++ /dev/null
@@ -1,79 +0,0 @@
-#Start recording tcl command: 8/15/2023 22:16:47
-#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1
-prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-prj_run Export -impl impl1
-pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1 -forceAll
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-prj_run Export -impl impl1 -forceAll
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-prj_run Export -impl impl1
-launch_synplify_prj impl1
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_strgy set_value -strategy Strategy1 syn_pipelining_retiming=None syn_frequency=70
-prj_strgy set_value -strategy Strategy1 map_io_reg=Both
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_project close
-pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_project close
-pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_project close
-pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_project close
-pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-prj_run Export -impl impl1
-pgr_program run
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-prj_run Export -impl impl1 -forceAll
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_program run
-prj_run Export -impl impl1
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-pgr_program run
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_program run
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1 -forceAll
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-prj_run Export -impl impl1
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-pgr_program run
-pgr_program run
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_run Export -impl impl1
-pgr_program run
-pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
-prj_project save
-prj_project close
-#Stop recording: 8/16/2023 01:57:20
diff --git a/CPLD/LCMXO2-640HC-old/EFB.edn b/CPLD/LCMXO2-640HC/REFB.edn
similarity index 98%
rename from CPLD/LCMXO2-640HC-old/EFB.edn
rename to CPLD/LCMXO2-640HC/REFB.edn
index 13d44b1..59d4276 100644
--- a/CPLD/LCMXO2-640HC-old/EFB.edn
+++ b/CPLD/LCMXO2-640HC/REFB.edn
@@ -1,12 +1,12 @@
-(edif EFB
+(edif REFB
   (edifVersion 2 0 0)
   (edifLevel 0)
   (keywordMap (keywordLevel 0))
   (status
     (written
-      (timestamp 2021 8 17 5 48 29)
-      (program "SCUBA" (version "Diamond (64-bit) 3.12.0.240.2"))))
-      (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
+      (timestamp 2023 8 16 20 52 2)
+      (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
+      (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
   (library ORCLIB
     (edifLevel 0)
     (technology
@@ -248,7 +248,7 @@
             (direction OUTPUT))
           (port CFGSTDBY
             (direction OUTPUT)))))
-    (cell EFB
+    (cell REFB
       (cellType GENERIC)
       (view view1
         (viewType NETLIST)
@@ -383,7 +383,7 @@
             (property EFB_I2C1
               (string "DISABLED"))
             (property EFB_WB_CLK_FREQ
-              (string "16.0")))
+              (string "62.5")))
           (net scuba_vhi
             (joined
               (portRef Z (instanceRef scuba_vhi_inst))
@@ -544,7 +544,7 @@
             (joined
               (portRef wb_clk_i)
               (portRef WBCLKI (instanceRef EFBInst_0))))))))
-  (design EFB
-    (cellRef EFB
+  (design REFB
+    (cellRef REFB
       (libraryRef ORCLIB)))
 )
diff --git a/CPLD/LCMXO2-640HC/REFB.ipx b/CPLD/LCMXO2-640HC/REFB.ipx
new file mode 100644
index 0000000..4d397ec
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/REFB.ipx
@@ -0,0 +1,8 @@
+
+
+  
+		
+		
+		
+  
+
diff --git a/CPLD/LCMXO2-640HC-old/EFB.lpc b/CPLD/LCMXO2-640HC/REFB.lpc
similarity index 89%
rename from CPLD/LCMXO2-640HC-old/EFB.lpc
rename to CPLD/LCMXO2-640HC/REFB.lpc
index ae74b18..7e8558b 100644
--- a/CPLD/LCMXO2-640HC-old/EFB.lpc
+++ b/CPLD/LCMXO2-640HC/REFB.lpc
@@ -13,11 +13,11 @@ CoreType=LPM
 CoreStatus=Demo
 CoreName=EFB
 CoreRevision=1.2
-ModuleName=EFB
+ModuleName=REFB
 SourceFormat=Verilog HDL
 ParameterFileVersion=1.0
-Date=08/17/2021
-Time=05:48:29
+Date=08/16/2023
+Time=20:52:02
 
 [Parameters]
 Verilog=1
@@ -81,7 +81,7 @@ ufm2=0
 ufm3=0
 ufm_cfg0=0
 ufm_cfg1=0
-wb_clk_freq=16
+wb_clk_freq=62.5
 ufm_usage=SHARED_EBR_TAG
 ufm_ebr=190
 ufm_remain=
@@ -138,4 +138,4 @@ t_wbport=0
 t_portlock=0
 
 [Command]
-cmd_line= -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
+cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
diff --git a/CPLD/LCMXO2-640HC-old/EFB.naf b/CPLD/LCMXO2-640HC/REFB.naf
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/EFB.naf
rename to CPLD/LCMXO2-640HC/REFB.naf
diff --git a/CPLD/LCMXO2-640HC/REFB.sort b/CPLD/LCMXO2-640HC/REFB.sort
new file mode 100644
index 0000000..794b751
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/REFB.sort
@@ -0,0 +1 @@
+REFB.v
diff --git a/CPLD/LCMXO2-640HC-old/EFB.srp b/CPLD/LCMXO2-640HC/REFB.srp
similarity index 68%
rename from CPLD/LCMXO2-640HC-old/EFB.srp
rename to CPLD/LCMXO2-640HC/REFB.srp
index 650b29b..7dc4bd4 100644
--- a/CPLD/LCMXO2-640HC-old/EFB.srp
+++ b/CPLD/LCMXO2-640HC/REFB.srp
@@ -1,5 +1,5 @@
-SCUBA, Version Diamond (64-bit) 3.12.0.240.2
-Tue Aug 17 05:48:29 2021
+SCUBA, Version Diamond (64-bit) 3.12.1.454
+Wed Aug 16 20:52:02 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -7,20 +7,20 @@ Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
-    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
-    Circuit name     : EFB
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : REFB
     Module type      : efb
     Module Version   : 1.2
     Ports            : 
 	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
 	Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
     I/O buffer       : not inserted
-    EDIF output      : EFB.edn
-    Verilog output   : EFB.v
-    Verilog template : EFB_tmpl.v
+    EDIF output      : REFB.edn
+    Verilog output   : REFB.v
+    Verilog template : REFB_tmpl.v
     Verilog purpose  : for synthesis and simulation
     Bus notation     : big endian
-    Report output    : EFB.srp
+    Report output    : REFB.srp
     Element Usage    :
             EFB : 1
     Estimated Resource Usage:
diff --git a/CPLD/LCMXO2-640HC/REFB.sym b/CPLD/LCMXO2-640HC/REFB.sym
new file mode 100644
index 0000000..6588d30
Binary files /dev/null and b/CPLD/LCMXO2-640HC/REFB.sym differ
diff --git a/CPLD/LCMXO2-640HC-old/EFB.v b/CPLD/LCMXO2-640HC/REFB.v
similarity index 92%
rename from CPLD/LCMXO2-640HC-old/EFB.v
rename to CPLD/LCMXO2-640HC/REFB.v
index 132b8b1..d9b5238 100644
--- a/CPLD/LCMXO2-640HC-old/EFB.v
+++ b/CPLD/LCMXO2-640HC/REFB.v
@@ -1,11 +1,11 @@
-/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
 /* Module Version: 1.2 */
-/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640  */
-/* Tue Aug 17 05:48:29 2021 */
+/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640  */
+/* Wed Aug 16 20:52:02 2023 */
 
 
 `timescale 1 ns / 1 ps
-module EFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, 
+module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, 
     wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
     input wire wb_clk_i;
     input wire wb_rst_i;
@@ -74,7 +74,7 @@ module EFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
     defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
     defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
     defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
-    defparam EFBInst_0.EFB_WB_CLK_FREQ = "16.0" ;
+    defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ;
     EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), 
         .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), 
         .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), 
diff --git a/CPLD/LCMXO2-640HC-old/EFB_generate.log b/CPLD/LCMXO2-640HC/REFB_generate.log
similarity index 70%
rename from CPLD/LCMXO2-640HC-old/EFB_generate.log
rename to CPLD/LCMXO2-640HC/REFB_generate.log
index 2296034..7291f66 100644
--- a/CPLD/LCMXO2-640HC-old/EFB_generate.log
+++ b/CPLD/LCMXO2-640HC/REFB_generate.log
@@ -2,8 +2,8 @@ Starting process: Module
 
 Starting process: 
 
-SCUBA, Version Diamond (64-bit) 3.12.0.240.2
-Tue Aug 17 05:48:29 2021
+SCUBA, Version Diamond (64-bit) 3.12.1.454
+Wed Aug 16 20:52:02 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -13,25 +13,25 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 BEGIN SCUBA Module Synthesis
 
-    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
-    Circuit name     : EFB
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : REFB
     Module type      : efb
     Module Version   : 1.2
     Ports            : 
 	Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
 	Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
     I/O buffer       : not inserted
-    EDIF output      : EFB.edn
-    Verilog output   : EFB.v
-    Verilog template : EFB_tmpl.v
+    EDIF output      : REFB.edn
+    Verilog output   : REFB.v
+    Verilog template : REFB_tmpl.v
     Verilog purpose  : for synthesis and simulation
     Bus notation     : big endian
-    Report output    : EFB.srp
+    Report output    : REFB.srp
     Estimated Resource Usage:
 
 END   SCUBA Module Synthesis
 
-File: EFB.lpc created.
+File: REFB.lpc created.
 
 
 End process: completed successfully.
diff --git a/CPLD/LCMXO2-640HC-old/EFB_tmpl.v b/CPLD/LCMXO2-640HC/REFB_tmpl.v
similarity index 64%
rename from CPLD/LCMXO2-640HC-old/EFB_tmpl.v
rename to CPLD/LCMXO2-640HC/REFB_tmpl.v
index 659ce82..ac4a91c 100644
--- a/CPLD/LCMXO2-640HC-old/EFB_tmpl.v
+++ b/CPLD/LCMXO2-640HC/REFB_tmpl.v
@@ -1,8 +1,8 @@
-/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
+/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
 /* Module Version: 1.2 */
-/* Tue Aug 17 05:48:29 2021 */
+/* Wed Aug 16 20:52:02 2023 */
 
 /* parameterized module instance */
-EFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), 
+REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), 
     .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), 
     .wbc_ufm_irq( ));
diff --git a/CPLD/LCMXO2-640HC-old/_math_real.vhd b/CPLD/LCMXO2-640HC/_math_real.vhd
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/_math_real.vhd
rename to CPLD/LCMXO2-640HC/_math_real.vhd
diff --git a/CPLD/LCMXO2-640HC-old/generate_core.tcl b/CPLD/LCMXO2-640HC/generate_core.tcl
similarity index 98%
rename from CPLD/LCMXO2-640HC-old/generate_core.tcl
rename to CPLD/LCMXO2-640HC/generate_core.tcl
index 264a94e..d562b73 100644
--- a/CPLD/LCMXO2-640HC-old/generate_core.tcl
+++ b/CPLD/LCMXO2-640HC/generate_core.tcl
@@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF)
 set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
 
 set scuba "$Para(FPGAPath)/scuba"
-set modulename "EFB"
+set modulename "REFB"
 set lang "verilog"
 set lpcfile "$Para(sbp_path)/$modulename.lpc"
 set arch "xo2c00"
diff --git a/CPLD/LCMXO2-640HC-old/generate_ngd.tcl b/CPLD/LCMXO2-640HC/generate_ngd.tcl
similarity index 50%
rename from CPLD/LCMXO2-640HC-old/generate_ngd.tcl
rename to CPLD/LCMXO2-640HC/generate_ngd.tcl
index ffa641e..239c19c 100644
--- a/CPLD/LCMXO2-640HC-old/generate_ngd.tcl
+++ b/CPLD/LCMXO2-640HC/generate_ngd.tcl
@@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF)
 set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
 set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
 
-set Para(ModuleName) "EFB"
+set Para(ModuleName) "REFB"
 set Para(Module) "EFB"
 set Para(libname) machxo2
 set Para(arch_name) xo2c00
@@ -63,59 +63,9 @@ set Para(SpeedGrade) "4"
 set Para(FMax) "100"
 set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
 
-#create LSE project file(*.synproj)
-proc CreateSynprojFile {} {
-	global Para
-
-	if [catch {open $Para(ModuleName).synproj w} synprojFile] {
-		puts "Cannot create LSE project file $Para(ModuleName).synproj."
-		exit -1
-	} else {
-		puts $synprojFile "-a \"$Para(tech_syn)\"
--d $Para(PartType)
--t $Para(Package)
--s $Para(SpeedGrade)
--frequency 200
--optimization_goal Balanced
--bram_utilization 100
--ramstyle auto
--romstyle auto
--use_carry_chain 1
--carry_chain_length 0
--force_gsr auto
--resource_sharing 1
--propagate_constants 1
--remove_duplicate_regs 1
--mux_style Auto
--max_fanout 1000
--fsm_encoding_style Auto
--twr_paths 3
--fix_gated_clocks 1
--use_io_insertion 0
--resolve_mixed_drivers 0
--use_io_reg 1
-
--lpf 1
--p $Para(sbp_path)
--ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
-\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
-\"$Para(sbp_path)/$Para(ModuleName).v\"
--top $Para(ModuleName)
--ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
-		"
-		close $synprojFile
-	}
-}
-
-#LSE
-CreateSynprojFile
-set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
-set synthesis "$Para(FPGAPath)/synthesis"
-if {[file exists $ldcfile] == 0} {
-	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
-} else {
-	set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
-}
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
 #puts $msg
 
 #ngdbuild
diff --git a/CPLD/LCMXO2-640HC/hdlparser.log b/CPLD/LCMXO2-640HC/hdlparser.log
deleted file mode 100644
index fa8401f..0000000
--- a/CPLD/LCMXO2-640HC/hdlparser.log
+++ /dev/null
@@ -1,3 +0,0 @@
--- all messages logged in file hdlparser.log
--- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo2.v' (VERI-1482)
--- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482)
diff --git a/CPLD/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2-640HC/impl1/.build_status
index c1e52c6..b4a92f0 100644
--- a/CPLD/LCMXO2-640HC/impl1/.build_status
+++ b/CPLD/LCMXO2-640HC/impl1/.build_status
@@ -6,46 +6,37 @@
             
             
             
-            
+            
         
-        
-            
-            
-            
-            
+        
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
+        
+            
         
         
-            
-            
+            
+            
             
             
             
         
-        
-            
+        
+            
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
     
 
diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
deleted file mode 100644
index 049dfbe..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
deleted file mode 100644
index 004500f..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb
deleted file mode 100644
index 936bc08..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
deleted file mode 100644
index 0a575a4..0000000
--- a/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
+++ /dev/null
@@ -1 +0,0 @@
-RAM2GS_rtl.vdb
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt
similarity index 95%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt
index 46f0e3d..8aac9df 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt
@@ -1,33 +1,11 @@
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Tue Aug 17 06:21:09 2021 *
+NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 *
 NOTE DESIGN NAME: RAM2GS *
 NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
 NOTE PIN ASSIGNMENTS *
-NOTE PINS RCLK : 63 : in *
-NOTE PINS nFWE : 15 : in *
-NOTE PINS nCRAS : 17 : in *
-NOTE PINS nCCAS : 9 : in *
-NOTE PINS Din[0] : 3 : in *
-NOTE PINS Din[1] : 96 : in *
-NOTE PINS Din[2] : 88 : in *
-NOTE PINS Din[3] : 97 : in *
-NOTE PINS Din[4] : 99 : in *
-NOTE PINS Din[5] : 98 : in *
-NOTE PINS Din[6] : 2 : in *
-NOTE PINS Din[7] : 1 : in *
-NOTE PINS CROW[0] : 10 : in *
-NOTE PINS CROW[1] : 16 : in *
-NOTE PINS MAin[0] : 14 : in *
-NOTE PINS MAin[1] : 12 : in *
-NOTE PINS MAin[2] : 13 : in *
-NOTE PINS MAin[3] : 21 : in *
-NOTE PINS MAin[4] : 20 : in *
-NOTE PINS MAin[5] : 19 : in *
-NOTE PINS MAin[6] : 24 : in *
-NOTE PINS MAin[7] : 18 : in *
-NOTE PINS MAin[8] : 25 : in *
-NOTE PINS MAin[9] : 32 : in *
+NOTE PINS RD[0] : 36 : inout *
+NOTE PINS Dout[0] : 76 : out *
 NOTE PINS PHI2 : 8 : in *
 NOTE PINS RDQML : 48 : out *
 NOTE PINS RDQMH : 51 : out *
@@ -35,37 +13,59 @@ NOTE PINS nRCAS : 52 : out *
 NOTE PINS nRRAS : 54 : out *
 NOTE PINS nRWE : 49 : out *
 NOTE PINS RCKE : 53 : out *
+NOTE PINS RCLK : 62 : in *
 NOTE PINS nRCS : 57 : out *
-NOTE PINS RA[0] : 66 : out *
-NOTE PINS RA[1] : 67 : out *
-NOTE PINS RA[2] : 69 : out *
-NOTE PINS RA[3] : 71 : out *
-NOTE PINS RA[4] : 74 : out *
-NOTE PINS RA[5] : 70 : out *
-NOTE PINS RA[6] : 68 : out *
-NOTE PINS RA[7] : 75 : out *
-NOTE PINS RA[8] : 65 : out *
-NOTE PINS RA[9] : 62 : out *
-NOTE PINS RA[10] : 64 : out *
-NOTE PINS RA[11] : 59 : out *
-NOTE PINS RBA[0] : 58 : out *
-NOTE PINS RBA[1] : 60 : out *
-NOTE PINS LED : 34 : out *
-NOTE PINS Dout[0] : 76 : out *
-NOTE PINS Dout[1] : 86 : out *
-NOTE PINS Dout[2] : 87 : out *
-NOTE PINS Dout[3] : 85 : out *
-NOTE PINS Dout[4] : 83 : out *
-NOTE PINS Dout[5] : 84 : out *
-NOTE PINS Dout[6] : 78 : out *
-NOTE PINS Dout[7] : 82 : out *
-NOTE PINS RD[0] : 36 : inout *
-NOTE PINS RD[1] : 37 : inout *
-NOTE PINS RD[2] : 38 : inout *
-NOTE PINS RD[3] : 39 : inout *
-NOTE PINS RD[4] : 40 : inout *
-NOTE PINS RD[5] : 41 : inout *
-NOTE PINS RD[6] : 42 : inout *
 NOTE PINS RD[7] : 43 : inout *
+NOTE PINS RD[6] : 42 : inout *
+NOTE PINS RD[5] : 41 : inout *
+NOTE PINS RD[4] : 40 : inout *
+NOTE PINS RD[3] : 39 : inout *
+NOTE PINS RD[2] : 38 : inout *
+NOTE PINS RD[1] : 37 : inout *
+NOTE PINS RA[11] : 59 : out *
+NOTE PINS RA[10] : 64 : out *
+NOTE PINS RA[9] : 63 : out *
+NOTE PINS RA[8] : 65 : out *
+NOTE PINS RA[7] : 75 : out *
+NOTE PINS RA[6] : 68 : out *
+NOTE PINS RA[5] : 70 : out *
+NOTE PINS RA[4] : 74 : out *
+NOTE PINS RA[3] : 71 : out *
+NOTE PINS RA[2] : 69 : out *
+NOTE PINS RA[1] : 67 : out *
+NOTE PINS RA[0] : 66 : out *
+NOTE PINS RBA[1] : 60 : out *
+NOTE PINS RBA[0] : 58 : out *
+NOTE PINS LED : 34 : out *
+NOTE PINS nFWE : 15 : in *
+NOTE PINS nCRAS : 17 : in *
+NOTE PINS nCCAS : 9 : in *
+NOTE PINS Dout[7] : 82 : out *
+NOTE PINS Dout[6] : 78 : out *
+NOTE PINS Dout[5] : 84 : out *
+NOTE PINS Dout[4] : 83 : out *
+NOTE PINS Dout[3] : 85 : out *
+NOTE PINS Dout[2] : 87 : out *
+NOTE PINS Dout[1] : 86 : out *
+NOTE PINS Din[7] : 1 : in *
+NOTE PINS Din[6] : 2 : in *
+NOTE PINS Din[5] : 98 : in *
+NOTE PINS Din[4] : 99 : in *
+NOTE PINS Din[3] : 97 : in *
+NOTE PINS Din[2] : 88 : in *
+NOTE PINS Din[1] : 96 : in *
+NOTE PINS Din[0] : 3 : in *
+NOTE PINS CROW[1] : 16 : in *
+NOTE PINS CROW[0] : 10 : in *
+NOTE PINS MAin[9] : 32 : in *
+NOTE PINS MAin[8] : 25 : in *
+NOTE PINS MAin[7] : 18 : in *
+NOTE PINS MAin[6] : 24 : in *
+NOTE PINS MAin[5] : 19 : in *
+NOTE PINS MAin[4] : 20 : in *
+NOTE PINS MAin[3] : 21 : in *
+NOTE PINS MAin[2] : 13 : in *
+NOTE PINS MAin[1] : 12 : in *
+NOTE PINS MAin[0] : 14 : in *
 NOTE CONFIGURATION MODE: NONE *
 NOTE COMPRESSION: on *
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr
new file mode 100644
index 0000000..69f71bd
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr
@@ -0,0 +1,42 @@
+----------------------------------------------------------------------
+Report for cell RAM2GS.verilog
+
+Register bits: 109 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                 BB        8       100.0
+                              CCU2D       10       100.0
+                                EFB        1       100.0
+                            FD1P3AX       27       100.0
+                            FD1P3IX        3       100.0
+                            FD1S3AX       51       100.0
+                            FD1S3IX        3       100.0
+                                GSR        1       100.0
+                                 IB       25       100.0
+                           IFS1P3DX        9       100.0
+                                INV        8       100.0
+                                 OB       30       100.0
+                           OFS1P3BX        4       100.0
+                           OFS1P3DX       11       100.0
+                           OFS1P3JX        1       100.0
+                           ORCALUT4      206       100.0
+                              PFUMX        1       100.0
+                                PUR        1       100.0
+                                VHI        2       100.0
+                                VLO        2       100.0
+SUB MODULES 
+                               REFB        1       100.0
+                            
+                         TOTAL           405           
+----------------------------------------------------------------------
+Report for cell REFB.netlist
+     Instance path:  ufmefb
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                EFB        1       100.0
+                                VHI        1        50.0
+                                VLO        1        50.0
+                            
+                         TOTAL             3           
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn
similarity index 90%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn
index e41242e..178bb21 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn
@@ -4,12 +4,12 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:11 2023
+Wed Aug 16 20:59:44 2023
 
 
-Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf 
 
-Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -22,7 +22,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 
 Running DRC.
 DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+Reading Preference File from LCMXO2_640HC_impl1.prf.
 
 Preference Summary:
 +---------------------------------+---------------------------------+
@@ -70,7 +70,7 @@ Creating bit map...
  
 Bitstream Status: Final           Version 1.95.
  
-Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+Saving bit stream in "LCMXO2_640HC_impl1.jed".
  
 ===========
 UFM Summary.
@@ -79,8 +79,8 @@ UFM Size:        191 Pages (128*191 Bits).
 UFM Utilization: General Purpose Flash Memory.
  
 Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     0 Page.
+Initialized UFM Pages:                     1 Page (Page 190).
  
 Total CPU Time: 1 secs 
 Total REAL Time: 2 secs 
-Peak Memory Usage: 246 MB
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.ncd
new file mode 100644
index 0000000..cdfbb0f
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.ncd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.pad
similarity index 95%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.pad
index 380f4fc..ff49f3a 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.pad
@@ -6,7 +6,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.39
 
-Tue Aug 15 23:30:09 2023
+Wed Aug 16 20:59:41 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -68,9 +68,6 @@ Pinout by Port Name:
 | RD[5]     | 41/2     | LVCMOS33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[6]     | 42/2     | LVCMOS33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[7]     | 43/2     | LVCMOS33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| UFMCLK    | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDI    | 29/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDO    | 27/2     | LVCMOS33_IN   | PB4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
 | nCCAS     | 9/3      | LVCMOS33_IN   | PL3C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nCRAS     | 17/3     | LVCMOS33_IN   | PL6B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nFWE      | 15/3     | LVCMOS33_IN   | PL5D  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
@@ -78,7 +75,6 @@ Pinout by Port Name:
 | nRCS      | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRRAS     | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRWE      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| nUFMCS    | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -121,10 +117,10 @@ Pinout by Pin Number:
 | 21/3     | MAin[3]               | LOCATED    | LVCMOS33_IN   | PL7B  | PCLKC3_0      |           |           |
 | 24/3     | MAin[6]               | LOCATED    | LVCMOS33_IN   | PL7C  |               |           |           |
 | 25/3     | MAin[8]               | LOCATED    | LVCMOS33_IN   | PL7D  |               |           |           |
-| 27/2     | UFMSDO                | LOCATED    | LVCMOS33_IN   | PB4A  | CSSPIN        |           |           |
-| 28/2     | UFMCLK                | LOCATED    | LVCMOS33_OUT  | PB4B  |               |           |           |
-| 29/2     | UFMSDI                | LOCATED    | LVCMOS33_OUT  | PB4C  |               |           |           |
-| 30/2     | nUFMCS                | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |               | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
 | 31/2     |     unused, PULL:DOWN |            |               | PB6A  | MCLK/CCLK     |           |           |
 | 32/2     | MAin[9]               | LOCATED    | LVCMOS33_IN   | PB6B  | SO/SPISO      |           |           |
 | 34/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB6C  | PCLKT2_0      |           |           |
@@ -255,9 +251,6 @@ LOCATE  COMP  "RD[4]"  SITE  "40";
 LOCATE  COMP  "RD[5]"  SITE  "41";
 LOCATE  COMP  "RD[6]"  SITE  "42";
 LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "UFMCLK"  SITE  "28";
-LOCATE  COMP  "UFMSDI"  SITE  "29";
-LOCATE  COMP  "UFMSDO"  SITE  "27";
 LOCATE  COMP  "nCCAS"  SITE  "9";
 LOCATE  COMP  "nCRAS"  SITE  "17";
 LOCATE  COMP  "nFWE"  SITE  "15";
@@ -265,7 +258,6 @@ LOCATE  COMP  "nRCAS"  SITE  "52";
 LOCATE  COMP  "nRCS"  SITE  "57";
 LOCATE  COMP  "nRRAS"  SITE  "54";
 LOCATE  COMP  "nRWE"  SITE  "49";
-LOCATE  COMP  "nUFMCS"  SITE  "30";
 
 
 
@@ -277,5 +269,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:11 2023
+Wed Aug 16 20:59:42 2023
 
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par
similarity index 56%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par
index d3c342b..5638eea 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par
@@ -1,14 +1,14 @@
 
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Sat Oct 09 01:19:16 2021
+Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
+Wed Aug 16 20:59:37 2023
 
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
+Preference file: LCMXO2_640HC_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
 
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -26,62 +26,66 @@ Device utilization summary:
 
    PIO (prelim)   63+4(JTAG)/80      84% used
                   63+4(JTAG)/79      85% bonded
+   IOLOGIC           25/80           31% used
 
-   SLICE            131/320          40% used
+   SLICE            117/320          36% used
 
    EFB                1/1           100% used
 
 
-Number of Signals: 401
-Number of Connections: 1131
+Number of Signals: 380
+Number of Connections: 1008
 
 Pin Constraint Summary:
    63 out of 63 pins locked (100% locked).
 
-The following 4 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 52)
-    PHI2_c (driver: PHI2, clk load #: 13)
-    nCRAS_c (driver: nCRAS, clk load #: 7)
-    nCCAS_c (driver: nCCAS, clk load #: 4)
+The following 3 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 46)
+    PHI2_c (driver: PHI2, clk load #: 19)
+    nCRAS_c (driver: nCRAS, clk load #: 10)
 
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 
-No signal is selected as secondary clock.
+The following 2 signals are selected to use the secondary clock routing resources:
+    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
+    un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
 
+WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
-............
+..............
 Finished Placer Phase 0.  REAL time: 0 secs 
 
 Starting Placer Phase 1.
-....................
-Placer score = 65362.
+...................
+Placer score = 55012.
 Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  65089
+Placer score =  54994
 Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 ------------------ Clock Report ------------------
 
 Global Clock Resources:
-  CLK_PIN    : 1 out of 8 (12%)
-  General PIO: 3 out of 80 (3%)
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 4 out of 80 (5%)
   DCM        : 0 out of 2 (0%)
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
-  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
-  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
+  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
+  SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
 
-  PRIMARY  : 4 out of 8 (50%)
-  SECONDARY: 0 out of 8 (0%)
+  PRIMARY  : 3 out of 8 (37%)
+  SECONDARY: 2 out of 8 (25%)
 
 --------------- End of Clock Report ---------------
 
@@ -102,22 +106,21 @@ I/O Bank Usage Summary:
 | 3        | 18 / 20 ( 90%) | 3.3V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 1131 unrouted.
+0 connections routed; 1008 unrouted.
 Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Completed router resource preassignment. Real time: 6 secs 
+Completed router resource preassignment. Real time: 5 secs 
 
-Start NBR router at 01:19:22 10/09/21
+Start NBR router at 20:59:43 08/16/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -132,53 +135,54 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 01:19:22 10/09/21
+Start NBR special constraint process at 20:59:43 08/16/23
 
-Start NBR section for initial routing at 01:19:22 10/09/21
+Start NBR section for initial routing at 20:59:43 08/16/23
 Level 1, iteration 1
-0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 2, iteration 1
-1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 3, iteration 1
-1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
+7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 01:19:22 10/09/21
+Start NBR section for normal routing at 20:59:43 08/16/23
 Level 1, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 2
-5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
-Level 4, iteration 3
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
-
-Start NBR section for re-routing at 01:19:23 10/09/21
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
+Level 4, iteration 0
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs 
+Level 4, iteration 0
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
 
-Start NBR section for post-routing at 01:19:23 10/09/21
+Start NBR section for re-routing at 20:59:44 08/16/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs 
+
+Start NBR section for post-routing at 20:59:44 08/16/23
 
 End NBR router with 0 unrouted connection
 
@@ -186,7 +190,7 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 1.135ns
+  Estimated worst slack : 4.922ns
   Timing score : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
@@ -196,16 +200,16 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Total CPU time 7 secs 
+Total CPU time 6 secs 
 Total REAL time: 7 secs 
 Completely routed.
-End of route.  1131 routed (100.00%); 0 unrouted.
+End of route.  1008 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
 Timing score: 0 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
 
 All signals are completely routed.
@@ -213,13 +217,13 @@ All signals are completely routed.
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Worst  slack> = 4.922
 PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Worst  slack> = 0.088
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 7 secs 
+Total CPU  time to completion: 6 secs 
 Total REAL time to completion: 7 secs 
 
 par done!
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd
similarity index 69%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd
index 293586e..1e33411 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd
@@ -1,21 +1,25 @@
 [ActiveSupport PAR]
 ; Global primary clocks
-GLOBAL_PRIMARY_USED = 2;
+GLOBAL_PRIMARY_USED = 3;
 ; Global primary clock #0
 GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
 GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_0_LOADNUM = 39;
+GLOBAL_PRIMARY_0_LOADNUM = 46;
 ; Global primary clock #1
 GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
 GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_1_LOADNUM = 18;
+GLOBAL_PRIMARY_1_LOADNUM = 19;
+; Global primary clock #2
+GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
+GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_2_LOADNUM = 10;
 ; # of global secondary clocks
 GLOBAL_SECONDARY_USED = 2;
 ; Global secondary clock #0
-GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
-GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
-GLOBAL_SECONDARY_0_LOADNUM = 11;
-GLOBAL_SECONDARY_0_SIGTYPE = CLK;
+GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i;
+GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
+GLOBAL_SECONDARY_0_LOADNUM = 10;
+GLOBAL_SECONDARY_0_SIGTYPE = CE;
 ; Global secondary clock #1
 GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c;
 GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
@@ -32,7 +36,7 @@ BANK_1_AVAIL = 20;
 BANK_1_VCCIO = 3.3V;
 BANK_1_VREF1 = NA;
 ; I/O Bank 2 Usage
-BANK_2_USED = 16;
+BANK_2_USED = 12;
 BANK_2_AVAIL = 20;
 BANK_2_VCCIO = 3.3V;
 BANK_2_VREF1 = NA;
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par
similarity index 66%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par
index fd2a224..ccd14db 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par
@@ -1,22 +1,22 @@
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Sat Oct 09 01:19:16 2021
+Wed Aug 16 20:59:37 2023
 
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
+LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
+-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
 
 
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Preference file: LCMXO2_640HC_impl1.prf.
 
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            1.135        0            0.304        0            07           Completed
+5_1   *      0            4.922        0            0.088        0            07           Completed
 
 * : Design saved.
 
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.edi b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi
similarity index 51%
rename from CPLD/LCMXO2-640HC/impl1/impl1.edi
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi
index 298000b..f410ddc 100644
--- a/CPLD/LCMXO2-640HC/impl1/impl1.edi
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi
@@ -4,7 +4,7 @@
   (keywordMap (keywordLevel 0))
   (status
     (written
-      (timeStamp 2023 8 15 22 34 24)
+      (timeStamp 2023 8 16 20 59 35)
       (author "Synopsys, Inc.")
       (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
      )
@@ -70,15 +70,6 @@
          )
        )
     )
-    (cell FD1S3AY (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
     (cell FD1S3AX (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -99,6 +90,17 @@
          )
        )
     )
+    (cell FD1P3IX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port SP (direction INPUT))
+           (port CK (direction INPUT))
+           (port CD (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
     (cell OFS1P3DX (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -196,6 +198,536 @@
   (library work
     (edifLevel 0)
     (technology (numberDefinition ))
+    (cell EFB (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port WBCLKI (direction INPUT))
+           (port WBRSTI (direction INPUT))
+           (port WBCYCI (direction INPUT))
+           (port WBSTBI (direction INPUT))
+           (port WBWEI (direction INPUT))
+           (port WBADRI7 (direction INPUT))
+           (port WBADRI6 (direction INPUT))
+           (port WBADRI5 (direction INPUT))
+           (port WBADRI4 (direction INPUT))
+           (port WBADRI3 (direction INPUT))
+           (port WBADRI2 (direction INPUT))
+           (port WBADRI1 (direction INPUT))
+           (port WBADRI0 (direction INPUT))
+           (port WBDATI7 (direction INPUT))
+           (port WBDATI6 (direction INPUT))
+           (port WBDATI5 (direction INPUT))
+           (port WBDATI4 (direction INPUT))
+           (port WBDATI3 (direction INPUT))
+           (port WBDATI2 (direction INPUT))
+           (port WBDATI1 (direction INPUT))
+           (port WBDATI0 (direction INPUT))
+           (port PLL0DATI7 (direction INPUT))
+           (port PLL0DATI6 (direction INPUT))
+           (port PLL0DATI5 (direction INPUT))
+           (port PLL0DATI4 (direction INPUT))
+           (port PLL0DATI3 (direction INPUT))
+           (port PLL0DATI2 (direction INPUT))
+           (port PLL0DATI1 (direction INPUT))
+           (port PLL0DATI0 (direction INPUT))
+           (port PLL0ACKI (direction INPUT))
+           (port PLL1DATI7 (direction INPUT))
+           (port PLL1DATI6 (direction INPUT))
+           (port PLL1DATI5 (direction INPUT))
+           (port PLL1DATI4 (direction INPUT))
+           (port PLL1DATI3 (direction INPUT))
+           (port PLL1DATI2 (direction INPUT))
+           (port PLL1DATI1 (direction INPUT))
+           (port PLL1DATI0 (direction INPUT))
+           (port PLL1ACKI (direction INPUT))
+           (port I2C1SCLI (direction INPUT))
+           (port I2C1SDAI (direction INPUT))
+           (port I2C2SCLI (direction INPUT))
+           (port I2C2SDAI (direction INPUT))
+           (port SPISCKI (direction INPUT))
+           (port SPIMISOI (direction INPUT))
+           (port SPIMOSII (direction INPUT))
+           (port SPISCSN (direction INPUT))
+           (port TCCLKI (direction INPUT))
+           (port TCRSTN (direction INPUT))
+           (port TCIC (direction INPUT))
+           (port UFMSN (direction INPUT))
+           (port WBDATO7 (direction OUTPUT))
+           (port WBDATO6 (direction OUTPUT))
+           (port WBDATO5 (direction OUTPUT))
+           (port WBDATO4 (direction OUTPUT))
+           (port WBDATO3 (direction OUTPUT))
+           (port WBDATO2 (direction OUTPUT))
+           (port WBDATO1 (direction OUTPUT))
+           (port WBDATO0 (direction OUTPUT))
+           (port WBACKO (direction OUTPUT))
+           (port PLLCLKO (direction OUTPUT))
+           (port PLLRSTO (direction OUTPUT))
+           (port PLL0STBO (direction OUTPUT))
+           (port PLL1STBO (direction OUTPUT))
+           (port PLLWEO (direction OUTPUT))
+           (port PLLADRO4 (direction OUTPUT))
+           (port PLLADRO3 (direction OUTPUT))
+           (port PLLADRO2 (direction OUTPUT))
+           (port PLLADRO1 (direction OUTPUT))
+           (port PLLADRO0 (direction OUTPUT))
+           (port PLLDATO7 (direction OUTPUT))
+           (port PLLDATO6 (direction OUTPUT))
+           (port PLLDATO5 (direction OUTPUT))
+           (port PLLDATO4 (direction OUTPUT))
+           (port PLLDATO3 (direction OUTPUT))
+           (port PLLDATO2 (direction OUTPUT))
+           (port PLLDATO1 (direction OUTPUT))
+           (port PLLDATO0 (direction OUTPUT))
+           (port I2C1SCLO (direction OUTPUT))
+           (port I2C1SCLOEN (direction OUTPUT))
+           (port I2C1SDAO (direction OUTPUT))
+           (port I2C1SDAOEN (direction OUTPUT))
+           (port I2C2SCLO (direction OUTPUT))
+           (port I2C2SCLOEN (direction OUTPUT))
+           (port I2C2SDAO (direction OUTPUT))
+           (port I2C2SDAOEN (direction OUTPUT))
+           (port I2C1IRQO (direction OUTPUT))
+           (port I2C2IRQO (direction OUTPUT))
+           (port SPISCKO (direction OUTPUT))
+           (port SPISCKEN (direction OUTPUT))
+           (port SPIMISOO (direction OUTPUT))
+           (port SPIMISOEN (direction OUTPUT))
+           (port SPIMOSIO (direction OUTPUT))
+           (port SPIMOSIEN (direction OUTPUT))
+           (port SPIMCSN0 (direction OUTPUT))
+           (port SPIMCSN1 (direction OUTPUT))
+           (port SPIMCSN2 (direction OUTPUT))
+           (port SPIMCSN3 (direction OUTPUT))
+           (port SPIMCSN4 (direction OUTPUT))
+           (port SPIMCSN5 (direction OUTPUT))
+           (port SPIMCSN6 (direction OUTPUT))
+           (port SPIMCSN7 (direction OUTPUT))
+           (port SPICSNEN (direction OUTPUT))
+           (port SPIIRQO (direction OUTPUT))
+           (port TCINT (direction OUTPUT))
+           (port TCOC (direction OUTPUT))
+           (port WBCUFMIRQ (direction OUTPUT))
+           (port CFGWAKE (direction OUTPUT))
+           (port CFGSTDBY (direction OUTPUT))
+         )
+        (property TC_ICAPTURE (string "DISABLED"))
+        (property TC_OVERFLOW (string "DISABLED"))
+        (property TC_ICR_INT (string "OFF"))
+        (property TC_OCR_INT (string "OFF"))
+        (property TC_OV_INT (string "OFF"))
+        (property TC_TOP_SEL (string "OFF"))
+        (property TC_RESETN (string "ENABLED"))
+        (property TC_OC_MODE (string "TOGGLE"))
+        (property TC_OCR_SET (integer 32767))
+        (property TC_TOP_SET (integer 65535))
+        (property GSR (string "ENABLED"))
+        (property TC_CCLK_SEL (integer 1))
+        (property TC_SCLK_SEL (string "PCLOCK"))
+        (property TC_MODE (string "CTCM"))
+        (property SPI_WAKEUP (string "DISABLED"))
+        (property SPI_INTR_RXOVR (string "DISABLED"))
+        (property SPI_INTR_TXOVR (string "DISABLED"))
+        (property SPI_INTR_RXRDY (string "DISABLED"))
+        (property SPI_INTR_TXRDY (string "DISABLED"))
+        (property SPI_SLAVE_HANDSHAKE (string "DISABLED"))
+        (property SPI_PHASE_ADJ (string "DISABLED"))
+        (property SPI_CLK_INV (string "DISABLED"))
+        (property SPI_LSB_FIRST (string "DISABLED"))
+        (property SPI_CLK_DIVIDER (integer 1))
+        (property SPI_MODE (string "MASTER"))
+        (property I2C2_WAKEUP (string "DISABLED"))
+        (property I2C1_WAKEUP (string "DISABLED"))
+        (property I2C2_GEN_CALL (string "DISABLED"))
+        (property I2C1_GEN_CALL (string "DISABLED"))
+        (property I2C2_CLK_DIVIDER (integer 1))
+        (property I2C1_CLK_DIVIDER (integer 1))
+        (property I2C2_BUS_PERF (string "100kHz"))
+        (property I2C1_BUS_PERF (string "100kHz"))
+        (property I2C2_SLAVE_ADDR (string "0b1000010"))
+        (property I2C1_SLAVE_ADDR (string "0b1000001"))
+        (property I2C2_ADDRESSING (string "7BIT"))
+        (property I2C1_ADDRESSING (string "7BIT"))
+        (property UFM_INIT_FILE_FORMAT (string "HEX"))
+        (property UFM_INIT_FILE_NAME (string "NONE"))
+        (property UFM_INIT_ALL_ZEROS (string "ENABLED"))
+        (property UFM_INIT_START_PAGE (integer 190))
+        (property UFM_INIT_PAGES (integer 1))
+        (property DEV_DENSITY (string "640L"))
+        (property EFB_WB_CLK_FREQ (string "62.5"))
+        (property EFB_UFM (string "ENABLED"))
+        (property EFB_TC_PORTMODE (string "WB"))
+        (property EFB_TC (string "DISABLED"))
+        (property EFB_SPI (string "DISABLED"))
+        (property EFB_I2C2 (string "DISABLED"))
+        (property EFB_I2C1 (string "DISABLED"))
+        (property orig_inst_of (string "EFB"))
+       )
+    )
+    (cell REFB (cellType GENERIC)
+       (view netlist (viewType NETLIST)
+         (interface
+           (port (array (rename wb_dato "wb_dato[1:0]") 2) (direction OUTPUT))
+           (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT))
+           (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT))
+           (port wb_we (direction INPUT))
+           (port wb_cyc_stb (direction INPUT))
+           (port wb_rst (direction INPUT))
+           (port wb_clk (direction INPUT))
+         )
+         (contents
+          (instance EFBInst_0 (viewRef verilog (cellRef EFB))
+           (property UFM_INIT_FILE_FORMAT (string "HEX"))
+           (property UFM_INIT_FILE_NAME (string "NONE"))
+           (property UFM_INIT_ALL_ZEROS (string "ENABLED"))
+           (property UFM_INIT_START_PAGE (integer 190))
+           (property UFM_INIT_PAGES (integer 1))
+           (property DEV_DENSITY (string "640L"))
+           (property EFB_UFM (string "ENABLED"))
+           (property TC_ICAPTURE (string "DISABLED"))
+           (property TC_OVERFLOW (string "DISABLED"))
+           (property TC_ICR_INT (string "OFF"))
+           (property TC_OCR_INT (string "OFF"))
+           (property TC_OV_INT (string "OFF"))
+           (property TC_TOP_SEL (string "OFF"))
+           (property TC_RESETN (string "ENABLED"))
+           (property TC_OC_MODE (string "TOGGLE"))
+           (property TC_OCR_SET (integer 32767))
+           (property TC_TOP_SET (integer 65535))
+           (property GSR (string "ENABLED"))
+           (property TC_CCLK_SEL (integer 1))
+           (property TC_MODE (string "CTCM"))
+           (property TC_SCLK_SEL (string "PCLOCK"))
+           (property EFB_TC_PORTMODE (string "WB"))
+           (property EFB_TC (string "DISABLED"))
+           (property SPI_WAKEUP (string "DISABLED"))
+           (property SPI_INTR_RXOVR (string "DISABLED"))
+           (property SPI_INTR_TXOVR (string "DISABLED"))
+           (property SPI_INTR_RXRDY (string "DISABLED"))
+           (property SPI_INTR_TXRDY (string "DISABLED"))
+           (property SPI_SLAVE_HANDSHAKE (string "DISABLED"))
+           (property SPI_PHASE_ADJ (string "DISABLED"))
+           (property SPI_CLK_INV (string "DISABLED"))
+           (property SPI_LSB_FIRST (string "DISABLED"))
+           (property SPI_CLK_DIVIDER (integer 1))
+           (property SPI_MODE (string "MASTER"))
+           (property EFB_SPI (string "DISABLED"))
+           (property I2C2_WAKEUP (string "DISABLED"))
+           (property I2C2_GEN_CALL (string "DISABLED"))
+           (property I2C2_CLK_DIVIDER (integer 1))
+           (property I2C2_BUS_PERF (string "100kHz"))
+           (property I2C2_SLAVE_ADDR (string "0b1000010"))
+           (property I2C2_ADDRESSING (string "7BIT"))
+           (property EFB_I2C2 (string "DISABLED"))
+           (property I2C1_WAKEUP (string "DISABLED"))
+           (property I2C1_GEN_CALL (string "DISABLED"))
+           (property I2C1_CLK_DIVIDER (integer 1))
+           (property I2C1_BUS_PERF (string "100kHz"))
+           (property I2C1_SLAVE_ADDR (string "0b1000001"))
+           (property I2C1_ADDRESSING (string "7BIT"))
+           (property EFB_I2C1 (string "DISABLED"))
+           (property EFB_WB_CLK_FREQ (string "62.5"))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net wb_clk (joined
+           (portRef wb_clk)
+           (portRef WBCLKI (instanceRef EFBInst_0))
+          ))
+          (net wb_rst (joined
+           (portRef wb_rst)
+           (portRef WBRSTI (instanceRef EFBInst_0))
+          ))
+          (net wb_cyc_stb (joined
+           (portRef wb_cyc_stb)
+           (portRef WBSTBI (instanceRef EFBInst_0))
+           (portRef WBCYCI (instanceRef EFBInst_0))
+          ))
+          (net wb_we (joined
+           (portRef wb_we)
+           (portRef WBWEI (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_7 "wb_adr[7]") (joined
+           (portRef (member wb_adr 0))
+           (portRef WBADRI7 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_6 "wb_adr[6]") (joined
+           (portRef (member wb_adr 1))
+           (portRef WBADRI6 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_5 "wb_adr[5]") (joined
+           (portRef (member wb_adr 2))
+           (portRef WBADRI5 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_4 "wb_adr[4]") (joined
+           (portRef (member wb_adr 3))
+           (portRef WBADRI4 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_3 "wb_adr[3]") (joined
+           (portRef (member wb_adr 4))
+           (portRef WBADRI3 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_2 "wb_adr[2]") (joined
+           (portRef (member wb_adr 5))
+           (portRef WBADRI2 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_1 "wb_adr[1]") (joined
+           (portRef (member wb_adr 6))
+           (portRef WBADRI1 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_adr_0 "wb_adr[0]") (joined
+           (portRef (member wb_adr 7))
+           (portRef WBADRI0 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_7 "wb_dati[7]") (joined
+           (portRef (member wb_dati 0))
+           (portRef WBDATI7 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_6 "wb_dati[6]") (joined
+           (portRef (member wb_dati 1))
+           (portRef WBDATI6 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_5 "wb_dati[5]") (joined
+           (portRef (member wb_dati 2))
+           (portRef WBDATI5 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_4 "wb_dati[4]") (joined
+           (portRef (member wb_dati 3))
+           (portRef WBDATI4 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_3 "wb_dati[3]") (joined
+           (portRef (member wb_dati 4))
+           (portRef WBDATI3 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_2 "wb_dati[2]") (joined
+           (portRef (member wb_dati 5))
+           (portRef WBDATI2 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_1 "wb_dati[1]") (joined
+           (portRef (member wb_dati 6))
+           (portRef WBDATI1 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dati_0 "wb_dati[0]") (joined
+           (portRef (member wb_dati 7))
+           (portRef WBDATI0 (instanceRef EFBInst_0))
+          ))
+          (net GND (joined
+           (portRef Z (instanceRef GND))
+           (portRef TCIC (instanceRef EFBInst_0))
+           (portRef TCRSTN (instanceRef EFBInst_0))
+           (portRef TCCLKI (instanceRef EFBInst_0))
+           (portRef SPISCSN (instanceRef EFBInst_0))
+           (portRef SPIMOSII (instanceRef EFBInst_0))
+           (portRef SPIMISOI (instanceRef EFBInst_0))
+           (portRef SPISCKI (instanceRef EFBInst_0))
+           (portRef I2C2SDAI (instanceRef EFBInst_0))
+           (portRef I2C2SCLI (instanceRef EFBInst_0))
+           (portRef I2C1SDAI (instanceRef EFBInst_0))
+           (portRef I2C1SCLI (instanceRef EFBInst_0))
+           (portRef PLL1ACKI (instanceRef EFBInst_0))
+           (portRef PLL1DATI0 (instanceRef EFBInst_0))
+           (portRef PLL1DATI1 (instanceRef EFBInst_0))
+           (portRef PLL1DATI2 (instanceRef EFBInst_0))
+           (portRef PLL1DATI3 (instanceRef EFBInst_0))
+           (portRef PLL1DATI4 (instanceRef EFBInst_0))
+           (portRef PLL1DATI5 (instanceRef EFBInst_0))
+           (portRef PLL1DATI6 (instanceRef EFBInst_0))
+           (portRef PLL1DATI7 (instanceRef EFBInst_0))
+           (portRef PLL0ACKI (instanceRef EFBInst_0))
+           (portRef PLL0DATI0 (instanceRef EFBInst_0))
+           (portRef PLL0DATI1 (instanceRef EFBInst_0))
+           (portRef PLL0DATI2 (instanceRef EFBInst_0))
+           (portRef PLL0DATI3 (instanceRef EFBInst_0))
+           (portRef PLL0DATI4 (instanceRef EFBInst_0))
+           (portRef PLL0DATI5 (instanceRef EFBInst_0))
+           (portRef PLL0DATI6 (instanceRef EFBInst_0))
+           (portRef PLL0DATI7 (instanceRef EFBInst_0))
+          ))
+          (net VCC (joined
+           (portRef Z (instanceRef VCC))
+           (portRef UFMSN (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_7 "wb_dat_o_1[7]") (joined
+           (portRef WBDATO7 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_6 "wb_dat_o_1[6]") (joined
+           (portRef WBDATO6 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_5 "wb_dat_o_1[5]") (joined
+           (portRef WBDATO5 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_4 "wb_dat_o_1[4]") (joined
+           (portRef WBDATO4 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_3 "wb_dat_o_1[3]") (joined
+           (portRef WBDATO3 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dat_o_1_2 "wb_dat_o_1[2]") (joined
+           (portRef WBDATO2 (instanceRef EFBInst_0))
+          ))
+          (net (rename wb_dato_1 "wb_dato[1]") (joined
+           (portRef WBDATO1 (instanceRef EFBInst_0))
+           (portRef (member wb_dato 0))
+          ))
+          (net (rename wb_dato_0 "wb_dato[0]") (joined
+           (portRef WBDATO0 (instanceRef EFBInst_0))
+           (portRef (member wb_dato 1))
+          ))
+          (net wb_ack_o (joined
+           (portRef WBACKO (instanceRef EFBInst_0))
+          ))
+          (net PLLCLKO (joined
+           (portRef PLLCLKO (instanceRef EFBInst_0))
+          ))
+          (net PLLRSTO (joined
+           (portRef PLLRSTO (instanceRef EFBInst_0))
+          ))
+          (net PLL0STBO (joined
+           (portRef PLL0STBO (instanceRef EFBInst_0))
+          ))
+          (net PLL1STBO (joined
+           (portRef PLL1STBO (instanceRef EFBInst_0))
+          ))
+          (net PLLWEO (joined
+           (portRef PLLWEO (instanceRef EFBInst_0))
+          ))
+          (net PLLADRO4 (joined
+           (portRef PLLADRO4 (instanceRef EFBInst_0))
+          ))
+          (net PLLADRO3 (joined
+           (portRef PLLADRO3 (instanceRef EFBInst_0))
+          ))
+          (net PLLADRO2 (joined
+           (portRef PLLADRO2 (instanceRef EFBInst_0))
+          ))
+          (net PLLADRO1 (joined
+           (portRef PLLADRO1 (instanceRef EFBInst_0))
+          ))
+          (net PLLADRO0 (joined
+           (portRef PLLADRO0 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO7 (joined
+           (portRef PLLDATO7 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO6 (joined
+           (portRef PLLDATO6 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO5 (joined
+           (portRef PLLDATO5 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO4 (joined
+           (portRef PLLDATO4 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO3 (joined
+           (portRef PLLDATO3 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO2 (joined
+           (portRef PLLDATO2 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO1 (joined
+           (portRef PLLDATO1 (instanceRef EFBInst_0))
+          ))
+          (net PLLDATO0 (joined
+           (portRef PLLDATO0 (instanceRef EFBInst_0))
+          ))
+          (net I2C1SCLO (joined
+           (portRef I2C1SCLO (instanceRef EFBInst_0))
+          ))
+          (net I2C1SCLOEN (joined
+           (portRef I2C1SCLOEN (instanceRef EFBInst_0))
+          ))
+          (net I2C1SDAO (joined
+           (portRef I2C1SDAO (instanceRef EFBInst_0))
+          ))
+          (net I2C1SDAOEN (joined
+           (portRef I2C1SDAOEN (instanceRef EFBInst_0))
+          ))
+          (net I2C2SCLO (joined
+           (portRef I2C2SCLO (instanceRef EFBInst_0))
+          ))
+          (net I2C2SCLOEN (joined
+           (portRef I2C2SCLOEN (instanceRef EFBInst_0))
+          ))
+          (net I2C2SDAO (joined
+           (portRef I2C2SDAO (instanceRef EFBInst_0))
+          ))
+          (net I2C2SDAOEN (joined
+           (portRef I2C2SDAOEN (instanceRef EFBInst_0))
+          ))
+          (net I2C1IRQO (joined
+           (portRef I2C1IRQO (instanceRef EFBInst_0))
+          ))
+          (net I2C2IRQO (joined
+           (portRef I2C2IRQO (instanceRef EFBInst_0))
+          ))
+          (net SPISCKO (joined
+           (portRef SPISCKO (instanceRef EFBInst_0))
+          ))
+          (net SPISCKEN (joined
+           (portRef SPISCKEN (instanceRef EFBInst_0))
+          ))
+          (net SPIMISOO (joined
+           (portRef SPIMISOO (instanceRef EFBInst_0))
+          ))
+          (net SPIMISOEN (joined
+           (portRef SPIMISOEN (instanceRef EFBInst_0))
+          ))
+          (net SPIMOSIO (joined
+           (portRef SPIMOSIO (instanceRef EFBInst_0))
+          ))
+          (net SPIMOSIEN (joined
+           (portRef SPIMOSIEN (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN0 (joined
+           (portRef SPIMCSN0 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN1 (joined
+           (portRef SPIMCSN1 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN2 (joined
+           (portRef SPIMCSN2 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN3 (joined
+           (portRef SPIMCSN3 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN4 (joined
+           (portRef SPIMCSN4 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN5 (joined
+           (portRef SPIMCSN5 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN6 (joined
+           (portRef SPIMCSN6 (instanceRef EFBInst_0))
+          ))
+          (net SPIMCSN7 (joined
+           (portRef SPIMCSN7 (instanceRef EFBInst_0))
+          ))
+          (net SPICSNEN (joined
+           (portRef SPICSNEN (instanceRef EFBInst_0))
+          ))
+          (net SPIIRQO (joined
+           (portRef SPIIRQO (instanceRef EFBInst_0))
+          ))
+          (net TCINT (joined
+           (portRef TCINT (instanceRef EFBInst_0))
+          ))
+          (net TCOC (joined
+           (portRef TCOC (instanceRef EFBInst_0))
+          ))
+          (net wbc_ufm_irq (joined
+           (portRef WBCUFMIRQ (instanceRef EFBInst_0))
+          ))
+          (net CFGWAKE (joined
+           (portRef CFGWAKE (instanceRef EFBInst_0))
+          ))
+          (net CFGSTDBY (joined
+           (portRef CFGSTDBY (instanceRef EFBInst_0))
+          ))
+         )
+        (property NGD_DRC_MASK (integer 1))
+        (property orig_inst_of (string "REFB"))
+       )
+    )
     (cell RAM2GS (cellType GENERIC)
        (view verilog (viewType NETLIST)
          (interface
@@ -219,39 +751,75 @@
            (port nRCAS (direction OUTPUT))
            (port RDQMH (direction OUTPUT))
            (port RDQML (direction OUTPUT))
-           (port nUFMCS (direction OUTPUT))
-           (port UFMCLK (direction OUTPUT))
-           (port UFMSDI (direction OUTPUT))
-           (port UFMSDO (direction INPUT))
          )
          (contents
           (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
           (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
           (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
           )
+          (instance wb_rst_RNO_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
           (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
           (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
           (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
           (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance nFWE_pad_RNI420B (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance (rename FS_RNI1T8E_7 "FS_RNI1T8E[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename FS_RNIPIOA_11 "FS_RNIPIOA[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance C1Submitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B+A)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename FS_RNIPIOA_0_11 "FS_RNIPIOA_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (!B A))"))
+          )
+          (instance wb_cyc_stb_65_0_iv_0_a2_2_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C !A)"))
+          )
           (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C (!B A))"))
           )
+          (instance (rename wb_adr_10_0_a2_RNIQ1AL_1 "wb_adr_10_0_a2_RNIQ1AL[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename FS_RNIU61E_5 "FS_RNIU61E[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (!B !A))+D (!B !A))"))
+          )
           (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
           )
+          (instance wb_clk_9_iv_i_o2_2_RNIOE4Q (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename wb_adr_10_0_a2_RNIIJC01_1 "wb_adr_10_0_a2_RNIIJC01[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B+A)+C B)+D B)"))
+          )
           (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
           )
+          (instance wb_we_0_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance wb_rst_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance (rename wb_adr_10_0_o2_0_RNI0U1R_0 "wb_adr_10_0_o2_0_RNI0U1R[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename wb_dati_10_0_iv_0_RNO_0 "wb_dati_10_0_iv_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
           (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
           )
-          (instance UFMSDI_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!B !A))"))
+          (instance wb_clk_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance wb_clk_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
           )
-          (instance UFMSDI_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
+          (instance wb_clk_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
           )
           (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+A)"))
@@ -259,6 +827,9 @@
           (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+A)"))
           )
+          (instance CmdSubmitted_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
           (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+A)"))
           )
@@ -319,9 +890,6 @@
           (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
            (property IOB (string "FALSE"))
           )
-          (instance UFMCLK_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
           (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
            (property IOB (string "FALSE"))
           )
@@ -334,7 +902,45 @@
           (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT)))
            (property IOB (string "FALSE"))
           )
-          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          (instance wb_we (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance wb_rst (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance wb_clk (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
@@ -342,8 +948,6 @@
           )
           (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
           (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
@@ -398,6 +1002,8 @@
           )
           (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance FWEr_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
           (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
           (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
@@ -438,11 +1044,9 @@
           )
           (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          (instance CmdUFMData (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          (instance CmdSubmitted_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
           (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
@@ -450,6 +1054,10 @@
           )
           (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
+          (instance CMDUFMWrite (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CBR_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
           (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
           (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
@@ -462,10 +1070,6 @@
           )
           (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
-          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
@@ -538,95 +1142,182 @@
           (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
           )
+          (instance wb_cyc_stb_65_0_iv_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_4 "wb_dati_10_1_iv_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B !A)))"))
+          )
+          (instance (rename wb_adr_10_0_0 "wb_adr_10_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance wb_we_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B !A)))"))
+          )
           (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(!C A+C B))"))
           )
-          (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+A)+D (!C (!B+A)))"))
+          (instance un1_FS_7_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B A)))"))
           )
-          (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
+          (instance (rename wb_adr_10_0_i_o2_6 "wb_adr_10_0_i_o2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (B+A))"))
+          )
+          (instance (rename wb_adr_10_0_i_o2_5 "wb_adr_10_0_i_o2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (B+A))"))
+          )
+          (instance (rename wb_adr_10_0_i_o2_4 "wb_adr_10_0_i_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (B+A))"))
+          )
+          (instance (rename wb_dati_10_0_iv_0_0 "wb_dati_10_0_iv_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_3 "wb_dati_10_1_iv_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_7 "wb_dati_10_1_iv_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (!B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_1_4 "wb_dati_10_1_iv_0_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance ADSubmitted_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
           )
           (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
+           (property lut_function (string "(C (!B A))"))
           )
-          (instance UFMCLK_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B+A)))"))
+          (instance (rename wb_dati_10_1_iv_0_2 "wb_dati_10_1_iv_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
           )
-          (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
+          (instance (rename wb_dati_10_1_iv_0_5 "wb_dati_10_1_iv_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
           )
-          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
+          (instance (rename wb_dati_10_1_iv_0_1 "wb_dati_10_1_iv_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
           )
-          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
+          (instance wb_cyc_stb_65_0_iv_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)+C !A)+D !A)"))
           )
-          (instance CmdEnable17_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
+          (instance (rename wb_adr_10_0_1 "wb_adr_10_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
           )
-          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B+A)+C (B !A))+D (!C+!A))"))
+          (instance (rename wb_dati_10_1_iv_0_a4_3 "wb_dati_10_1_iv_0_a4[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_FS_7_i_a4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance XOR8MEG18_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_1_7 "wb_dati_10_1_iv_0_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance wb_we_0_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance wb_we_0_0_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
+          )
+          (instance (rename wb_adr_10_0_3_0 "wb_adr_10_0_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C B+C (B+A)))"))
+          )
+          (instance (rename wb_adr_10_0_4_0 "wb_adr_10_0_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a4_1_3 "wb_dati_10_1_iv_0_a4_1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a4_2_4 "wb_dati_10_1_iv_0_a4_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance (rename wb_adr_10_0_a4_1 "wb_adr_10_0_a4[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a4_1_4 "wb_dati_10_1_iv_0_a4_1[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance (rename wb_adr_10_0_a4_7_0 "wb_adr_10_0_a4_7[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance CmdEnable_0_sqmuxa_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_0_7 "wb_dati_10_1_iv_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
+          )
+          (instance (rename wb_dati_10_0_iv_0_0_0 "wb_dati_10_0_iv_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
           )
           (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
+           (property lut_function (string "(!D (!C !A+C (B !A))+D !A)"))
           )
           (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (B !A))"))
+           (property lut_function (string "(!D !A+D (!C (B !A)+C !A))"))
+          )
+          (instance (rename wb_adr_10_0_a2_6_0 "wb_adr_10_0_a2_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
           )
           (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(!C+(B+A)))"))
           )
-          (instance un1_FS_13_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename wb_adr_10_0_a4_1_1 "wb_adr_10_0_a4_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C (B A))"))
           )
-          (instance un1_FS_14_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
-          )
-          (instance un1_CmdEnable20_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance un1_ADWR_i_o4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(!B+!A)))"))
           )
-          (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (B !A)))"))
+          (instance wb_cyc_stb_65_0_iv_0_o2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C B+C (B+!A)))"))
           )
-          (instance UFMCLK_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A))"))
+          (instance wb_we_0_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance (rename wb_adr_10_0_1_0 "wb_adr_10_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance (rename wb_adr_10_0_a4_6_0 "wb_adr_10_0_a4_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a2_7 "wb_dati_10_1_iv_0_a2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance (rename wb_adr_10_0_a2_11_0 "wb_adr_10_0_a2_11[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance wb_we_0_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D (B !A))"))
+          )
+          (instance nRCS_9_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (B+A)))"))
+          )
+          (instance wb_we_0_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C B))"))
+          )
+          (instance un1_CmdEnable20_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance wb_cyc_stb_65_0_iv_0_o2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
+          )
+          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)))"))
           )
           (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D C+D (C+(!B+!A)))"))
           )
-          (instance nRWE_s_i_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
+          (instance wb_cyc_stb_65_0_iv_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (!B !A))+D (C+B))"))
           )
-          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))"))
+          (instance wb_cyc_stb_65_0_iv_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C !A))"))
           )
-          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance wb_cyc_stb_65_0_iv_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (!B A)))"))
           )
-          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C (!B A)+C !B))"))
-          )
-          (instance C1WR_7_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance un1_CmdEnable20_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !A)+D (!C (!B !A)+C !A))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
-          )
-          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance nUFMCS_s_0_m4_yy (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
+          (instance (rename wb_adr_10_0_a4_3_0 "wb_adr_10_0_a4_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
           )
           (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
@@ -634,182 +1325,167 @@
           (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))"))
           )
-          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D A)"))
+          (instance un1_ADWR_i_o4_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+!A)))"))
           )
-          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance wb_clk_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
           )
-          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
           (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (!B A)))"))
           )
           (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
           )
+          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_10_0_5_tz_0 "wb_adr_10_0_5_tz[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C !A+C (B+!A)))"))
+          )
           (instance nRCAS_r_i_a3_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D !C+D (C (!B A)))"))
           )
+          (instance InitReady3_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A)))"))
+          )
           (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (!C (!B A)))"))
           )
-          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
-          (instance un1_CmdEnable20_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance C1WR_7_0_o3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D+(C+(B+!A)))"))
-          )
-          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance nRCS_9_u_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (!C (B !A)+C !A))"))
           )
           (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C (B A)+C (!B+!A))"))
           )
-          (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
+          (instance XOR8MEG_3_u_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C+(B+A)))"))
           )
-          (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance CmdLEDEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C+(B !A))"))
           )
-          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A))"))
-          )
           (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(B A)))"))
-          )
-          (instance CmdEnable16_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
+           (property lut_function (string "(!D (C+(!B A)))"))
           )
           (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C+(!B+A))"))
           )
-          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
+          (instance wb_we_0_0_a4_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
           )
-          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance wb_clk_9_iv_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C+(B+A))"))
           )
-          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
+          (instance CmdEnable_0_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
           )
           (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (!B !A)))"))
           )
+          (instance XOR8MEG_3_u_0_a4_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a4_1_0_7 "wb_dati_10_1_iv_0_a4_1_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)+C (!B !A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_a4_1_1 "wb_dati_10_1_iv_0_a4_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B+!A)))"))
+          )
+          (instance un1_FS_7_i_a4_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
+          )
           (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
           )
-          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
+          (instance (rename wb_adr_10_0_a4_0_0_0 "wb_adr_10_0_a4_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (!C A))"))
           )
           (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+!A)"))
           )
-          (instance XOR8MEG_3_u_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance C1Submitted_s_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+!A))"))
-          )
           (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C+(B+A))"))
           )
           (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C+(!B+!A))"))
           )
+          (instance (rename wb_adr_10_0_a2_1 "wb_adr_10_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
           (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!B+A)"))
           )
           (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+A)"))
           )
-          (instance UFMCLK_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance CmdEnable16_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
+          (instance wb_clk_9_iv_i_o2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
           )
           (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (!C (B A)))"))
           )
-          (instance C1WR_7_0_o3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance InitReady3_0_a4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance un1_ADWR_i_o4_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance un1_ADWR_i_o4_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          )
+          (instance un1_ADWR_i_o4_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D+(!C+(!B+!A)))"))
           )
-          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
+          (instance (rename wb_dati_10_1_iv_0_a4_1_0_0_3 "wb_dati_10_1_iv_0_a4_1_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
           )
-          (instance un1_CmdEnable20_0_o3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(!B+!A))"))
+          (instance (rename wb_dati_10_1_iv_0_a4_0_0_4 "wb_dati_10_1_iv_0_a4_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (C (!B !A)))"))
           )
-          (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance CmdEnable17_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
+          (instance (rename wb_dati_10_1_iv_0_a4_0_1_6 "wb_dati_10_1_iv_0_a4_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)+C (B A)))"))
           )
           (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_0 "un9_RA_i_m3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance LEDEN_6_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance n8MEGEN_6_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance (rename un9_RA_i_m2_0 "un9_RA_i_m2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_1 "un9_RA_i_m3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_1 "un9_RA_i_m2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_2 "un9_RA_i_m3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_2 "un9_RA_i_m2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_3 "un9_RA_i_m3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_3 "un9_RA_i_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_4 "un9_RA_i_m3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_4 "un9_RA_i_m2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_5 "un9_RA_i_m3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_5 "un9_RA_i_m2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_6 "un9_RA_i_m3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_6 "un9_RA_i_m2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_7 "un9_RA_i_m3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_7 "un9_RA_i_m2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance (rename un9_RA_i_m3_9 "un9_RA_i_m3[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un9_RA_i_m2_9 "un9_RA_i_m2[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C B+C A)"))
           )
-          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
+          (instance (rename wb_dati_10_1_iv_0_m2_3 "wb_dati_10_1_iv_0_m2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
           )
           (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B+A)"))
@@ -817,14 +1493,59 @@
           (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!B A+B !A)"))
           )
+          (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance CMDUFMWrite_1_sqmuxa_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance XOR8MEG_3_u_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename wb_adr_10_0_o2_0 "wb_adr_10_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance XOR8MEG_3_u_0_o2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename wb_adr_10_0_o2_1 "wb_adr_10_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename wb_adr_10_0_o2_0_0 "wb_adr_10_0_o2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance wb_we_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance wb_we_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename wb_adr_10_7 "wb_adr_10[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_10_3 "wb_adr_10[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_10_2 "wb_adr_10[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
           (instance un1_PHI2r3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B !A)"))
           )
-          (instance C1WR_7_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
+          (instance wb_we_0_0_a4_0_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
           )
-          (instance CmdEnable17_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
+          (instance un1_FS_7_i_a4_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_o2_1_5 "wb_dati_10_1_iv_0_o2_1[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !A)+D (C (!B !A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_o2_5 "wb_dati_10_1_iv_0_o2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A))+D (!C (B+!A)+C !A))"))
           )
           (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
@@ -832,33 +1553,57 @@
           (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
           )
+          (instance (rename wb_dati_10_1_iv_0_1_6 "wb_dati_10_1_iv_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+!B)+D (!C A+C (!B A)))"))
+          )
+          (instance (rename wb_dati_10_1_iv_0_6 "wb_dati_10_1_iv_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D (C A))"))
+          )
+          (instance CmdEnable_s_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !B)+D (!C (!B+!A)+C (B !A)))"))
+          )
+          (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (!B !A)))"))
+          )
+          (instance CMDUFMWrite_RNIHQ1E1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D+(C (B !A)))"))
+          )
+          (instance PHI2r3_RNIFT0I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(!B !A))+D (C+!A))"))
+          )
+          (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D+(!C (B !A)))"))
+          )
+          (instance nRWE_0io_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+A))"))
+          )
+          (instance nRWE_0io_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance nRWE_0io_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+A)+D (!C A+C !B))"))
+          )
           (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C !B)+D (!C !B+C (!B !A)))"))
           )
           (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C !B+C (!B !A))"))
           )
-          (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A))+D A)"))
-          )
-          (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+A)+D (!C A+C !B))"))
-          )
           (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))"))
           )
-          (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
           (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(B A)"))
           )
@@ -898,17 +1643,29 @@
           (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(!B+!A)))"))
           )
-          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance un1_CmdEnable20_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance CMDUFMWrite_1_sqmuxa_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (!B A)))"))
           )
-          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A))+D (!B A))"))
+          (instance (rename wb_adr_10_0_a2_1_0 "wb_adr_10_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
           )
-          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
+          (instance CmdLEDEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+!A))"))
           )
-          (instance nRRAS_5_u_i_0_RNILD5I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
+          (instance (rename wb_adr_10_0_a2_3_0 "wb_adr_10_0_a2_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance wb_rst_3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance CmdLEDEN_4_u_i_a4_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance nRCS_9_u_i_0_0_RNIOMAB (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (B !A))+D (B !A))"))
           )
           (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!B !A)"))
@@ -916,6 +1673,24 @@
           (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!C (!B !A+B A)+C A)"))
           )
+          (instance CmdEnable16_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdSubmitted_1_sqmuxa_0_a4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A))+D (!B A))"))
+          )
+          (instance (rename wb_adr_10_0_a2_0_0 "wb_adr_10_0_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename wb_adr_10_0_a2_7_0 "wb_adr_10_0_a2_7[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)))"))
+          )
+          (instance (rename wb_adr_10_0_a2_12_0 "wb_adr_10_0_a2_12[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)))"))
+          )
+          (instance wb_we_0_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
           (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
            (property INIT0 (string "0x5002"))
            (property INJECT1_1 (string "NO"))
@@ -976,38 +1751,187 @@
            (property INJECT1_0 (string "NO"))
            (property INIT1 (string "0x300A"))
           )
+          (instance ufmefb (viewRef netlist (cellRef REFB))
+          )
+          (net wb_clk (joined
+           (portRef Q (instanceRef wb_clk))
+           (portRef wb_clk (instanceRef ufmefb))
+          ))
+          (net wb_rst (joined
+           (portRef Q (instanceRef wb_rst))
+           (portRef wb_rst (instanceRef ufmefb))
+          ))
+          (net wb_cyc_stb (joined
+           (portRef Q (instanceRef wb_cyc_stb))
+           (portRef wb_cyc_stb (instanceRef ufmefb))
+           (portRef D (instanceRef wb_we_0_0_1))
+          ))
+          (net wb_we (joined
+           (portRef Q (instanceRef wb_we))
+           (portRef wb_we (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_10_0_iv_0_0_0))
+          ))
+          (net (rename wb_adr_0 "wb_adr[0]") (joined
+           (portRef Q (instanceRef wb_adr_0))
+           (portRef (member wb_adr 7) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_adr_10_0_1))
+          ))
+          (net (rename wb_adr_1 "wb_adr[1]") (joined
+           (portRef Q (instanceRef wb_adr_1))
+           (portRef (member wb_adr 6) (instanceRef ufmefb))
+           (portRef B (instanceRef wb_adr_10_2))
+          ))
+          (net (rename wb_adr_2 "wb_adr[2]") (joined
+           (portRef Q (instanceRef wb_adr_2))
+           (portRef (member wb_adr 5) (instanceRef ufmefb))
+           (portRef B (instanceRef wb_adr_10_3))
+          ))
+          (net (rename wb_adr_3 "wb_adr[3]") (joined
+           (portRef Q (instanceRef wb_adr_3))
+           (portRef (member wb_adr 4) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_adr_10_0_i_o2_4))
+          ))
+          (net (rename wb_adr_4 "wb_adr[4]") (joined
+           (portRef Q (instanceRef wb_adr_4))
+           (portRef (member wb_adr 3) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_adr_10_0_i_o2_5))
+          ))
+          (net (rename wb_adr_5 "wb_adr[5]") (joined
+           (portRef Q (instanceRef wb_adr_5))
+           (portRef (member wb_adr 2) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_adr_10_0_i_o2_6))
+          ))
+          (net (rename wb_adr_6 "wb_adr[6]") (joined
+           (portRef Q (instanceRef wb_adr_6))
+           (portRef (member wb_adr 1) (instanceRef ufmefb))
+           (portRef B (instanceRef wb_adr_10_7))
+          ))
+          (net (rename wb_adr_7 "wb_adr[7]") (joined
+           (portRef Q (instanceRef wb_adr_7))
+           (portRef (member wb_adr 0) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_0 "wb_dati[0]") (joined
+           (portRef Q (instanceRef wb_dati_0))
+           (portRef (member wb_dati 7) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_1))
+          ))
+          (net (rename wb_dati_1 "wb_dati[1]") (joined
+           (portRef Q (instanceRef wb_dati_1))
+           (portRef (member wb_dati 6) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_2))
+          ))
+          (net (rename wb_dati_2 "wb_dati[2]") (joined
+           (portRef Q (instanceRef wb_dati_2))
+           (portRef (member wb_dati 5) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_3))
+          ))
+          (net (rename wb_dati_3 "wb_dati[3]") (joined
+           (portRef Q (instanceRef wb_dati_3))
+           (portRef (member wb_dati 4) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_1_4))
+          ))
+          (net (rename wb_dati_4 "wb_dati[4]") (joined
+           (portRef Q (instanceRef wb_dati_4))
+           (portRef (member wb_dati 3) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_5))
+          ))
+          (net (rename wb_dati_5 "wb_dati[5]") (joined
+           (portRef Q (instanceRef wb_dati_5))
+           (portRef (member wb_dati 2) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_6))
+          ))
+          (net (rename wb_dati_6 "wb_dati[6]") (joined
+           (portRef Q (instanceRef wb_dati_6))
+           (portRef (member wb_dati 1) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_0_7))
+          ))
+          (net (rename wb_dati_7 "wb_dati[7]") (joined
+           (portRef Q (instanceRef wb_dati_7))
+           (portRef (member wb_dati 0) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_adr_10_0_1_0))
+          ))
+          (net (rename wb_dato_0 "wb_dato[0]") (joined
+           (portRef (member wb_dato 1) (instanceRef ufmefb))
+           (portRef C (instanceRef n8MEGEN_6_i_m2))
+          ))
+          (net (rename wb_dato_1 "wb_dato[1]") (joined
+           (portRef (member wb_dato 0) (instanceRef ufmefb))
+           (portRef C (instanceRef LEDEN_6_i_m2))
+          ))
           (net CBR (joined
            (portRef Q (instanceRef CBR))
-           (portRef A (instanceRef nRCS_0io_RNO_0))
-           (portRef A (instanceRef nRWE_0io_RNO_1))
            (portRef A (instanceRef nRCAS_0io_RNO_0))
            (portRef A (instanceRef RCKEEN_8_u))
            (portRef B (instanceRef nRowColSel_0_0_a3_0))
            (portRef A (instanceRef LED_pad_RNO))
-           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
+          ))
+          (net InitReady (joined
+           (portRef Q (instanceRef InitReady))
+           (portRef C (instanceRef wb_we_0_0_a2))
+           (portRef C (instanceRef wb_adr_10_0_a2_12_0))
+           (portRef C (instanceRef wb_adr_10_0_a2_7_0))
+           (portRef C (instanceRef wb_adr_10_0_a2_0_0))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef D (instanceRef CMDUFMWrite_RNIHQ1E1))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_6))
+           (portRef A (instanceRef wb_adr_10_2))
+           (portRef A (instanceRef wb_adr_10_3))
+           (portRef A (instanceRef wb_adr_10_7))
+           (portRef B (instanceRef n8MEGEN_6_i_m2))
+           (portRef B (instanceRef LEDEN_6_i_m2))
+           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef wb_clk_RNO_0))
+           (portRef A (instanceRef wb_we_0_0_2))
+           (portRef B (instanceRef wb_adr_10_0_a2_11_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a2_7))
+           (portRef A (instanceRef wb_adr_10_0_a4_6_0))
+           (portRef A (instanceRef wb_adr_10_0_1_0))
+           (portRef A (instanceRef wb_we_0_0_1))
+           (portRef A (instanceRef wb_dati_10_0_iv_0_0_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_0_7))
+           (portRef A (instanceRef wb_adr_10_0_1))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_a2))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_1))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_5))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_2))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_1_4))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_3))
+           (portRef A (instanceRef wb_adr_10_0_i_o2_4))
+           (portRef A (instanceRef wb_adr_10_0_i_o2_5))
+           (portRef A (instanceRef wb_adr_10_0_i_o2_6))
+           (portRef B (instanceRef un1_FS_7_i_0))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0))
+           (portRef B (instanceRef InitReady_RNO))
+           (portRef C0 (instanceRef wb_clk_RNO))
+           (portRef D (instanceRef Ready_RNO))
+           (portRef D (instanceRef wb_adr_10_0_o2_0_RNI0U1R_0))
+           (portRef D (instanceRef wb_we_0_0_1_RNO))
+           (portRef A (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q))
+           (portRef C (instanceRef RCKEEN_8_u_0_0))
+           (portRef A (instanceRef wb_rst_RNO_0))
           ))
           (net C1Submitted (joined
            (portRef Q (instanceRef C1Submitted))
-           (portRef A (instanceRef C1Submitted_s_0))
-           (portRef A (instanceRef un1_CmdEnable20_0_a2_1))
+           (portRef A (instanceRef CmdEnable_s_RNO_0))
+           (portRef B (instanceRef C1Submitted_RNO))
           ))
           (net (rename Bank_2 "Bank[2]") (joined
            (portRef Q (instanceRef Bank_0io_2))
-           (portRef B (instanceRef C1WR_7_0_o3_6))
+           (portRef B (instanceRef un1_ADWR_i_o4_10))
           ))
           (net Ready (joined
            (portRef Q (instanceRef Ready))
            (portRef B (instanceRef IS_RNO_0))
            (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
            (portRef D (instanceRef nRCS_0io_RNO))
-           (portRef C (instanceRef nRWE_0io_RNO_1))
+           (portRef B (instanceRef nRWE_0io_RNO_2))
            (portRef D (instanceRef RCKEEN_8_u))
            (portRef D (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0))
+           (portRef D (instanceRef nRCS_9_u_i_0_0))
            (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
+           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
            (portRef C (instanceRef nRowColSel_0_0))
            (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
            (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
            (portRef A (instanceRef Ready_RNO))
            (portRef A (instanceRef RCKEEN_8_u_0_0))
@@ -1016,12 +1940,12 @@
           (net n8MEGEN (joined
            (portRef Q (instanceRef n8MEGEN))
            (portRef D (instanceRef RA11d))
-           (portRef C (instanceRef Cmdn8MEGEN_RNO))
+           (portRef D (instanceRef Cmdn8MEGEN_RNO))
           ))
           (net CO0 (joined
            (portRef Q (instanceRef S_0))
            (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRWE_0io_RNO_0))
+           (portRef C (instanceRef nRWE_0io_RNO_4))
            (portRef B (instanceRef RCKEEN_8_u_1_0))
            (portRef A (instanceRef S_0_i_o2_1))
            (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
@@ -1033,10 +1957,10 @@
           (net (rename S_1 "S[1]") (joined
            (portRef Q (instanceRef S_1))
            (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRCS_0io_RNO_0))
-           (portRef D (instanceRef nRWE_0io_RNO_1))
            (portRef C (instanceRef nRCAS_0io_RNO_0))
            (portRef D (instanceRef nRCAS_0io_RNO))
+           (portRef B (instanceRef nRCS_0io_RNO_0))
+           (portRef D (instanceRef nRWE_0io_RNO_4))
            (portRef D (instanceRef RCKEEN_8_u_1_0))
            (portRef B (instanceRef S_0_i_o2_1))
            (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
@@ -1048,57 +1972,49 @@
           (net RASr2 (joined
            (portRef Q (instanceRef RASr2))
            (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
+           (portRef A (instanceRef nRWE_0io_RNO_3))
            (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
            (portRef B (instanceRef RCKE_2_0))
-           (portRef B (instanceRef nRRAS_5_u_i_0))
+           (portRef B (instanceRef nRCS_9_u_i_0_0))
            (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef A (instanceRef nRWE_s_i_tz_0))
            (portRef D (instanceRef RASr3))
            (portRef B (instanceRef RCKEEN_8_u_0_0))
            (portRef A (instanceRef RASr2_RNIAFR1))
           ))
-          (net InitReady (joined
-           (portRef Q (instanceRef InitReady))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef LEDEN_RNO))
-           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef PHI2r3_RNITCN41))
-           (portRef B (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef A (instanceRef UFMSDI_ens2_i_a0))
-           (portRef A (instanceRef UFMCLK_0io_RNO_1))
-           (portRef B (instanceRef un1_FS_13_i_0))
-           (portRef B (instanceRef un1_FS_14_i_0))
-           (portRef B (instanceRef UFMCLK_0io_RNO))
-           (portRef B (instanceRef InitReady_RNO))
-           (portRef D (instanceRef Ready_RNO))
-           (portRef C (instanceRef RCKEEN_8_u_0_0))
+          (net (rename FS_4 "FS[4]") (joined
+           (portRef Q (instanceRef FS_4))
+           (portRef A1 (instanceRef FS_cry_0_3))
+           (portRef C (instanceRef un1_FS_7_i_a4_0_3))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0))
+          ))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef Q (instanceRef FS_9))
+           (portRef A0 (instanceRef FS_cry_0_9))
+           (portRef A (instanceRef wb_rst_3_0_a2))
+           (portRef C (instanceRef wb_we_0_0_a4_0_0))
+           (portRef A (instanceRef wb_adr_10_0_a4_3_0))
           ))
           (net FWEr (joined
            (portRef Q (instanceRef FWEr))
-           (portRef B (instanceRef nRWE_0io_RNO_1))
+           (portRef B (instanceRef nRWE_0io_RNO_0))
            (portRef C (instanceRef RCKEEN_8_u_1_0))
            (portRef C (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRCAS_r_i_a3_1_1_tz))
           ))
           (net CASr3 (joined
            (portRef Q (instanceRef CASr3))
-           (portRef B (instanceRef nRWE_0io_RNO_0))
+           (portRef B (instanceRef nRWE_0io_RNO_4))
            (portRef A (instanceRef nRowColSel_0_0_a3_0))
            (portRef B (instanceRef nRCAS_r_i_a3_1_1_tz))
           ))
           (net (rename IS_0 "IS[0]") (joined
            (portRef Q (instanceRef IS_0))
            (portRef A (instanceRef IS_RNO_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0_RNILD5I))
+           (portRef D (instanceRef nRCS_9_u_i_0_0_RNIOMAB))
+           (portRef A (instanceRef nRWE_0io_RNO_1))
            (portRef A (instanceRef IS_n1_0_x2))
            (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
            (portRef A (instanceRef IS_RNO_2))
-           (portRef A (instanceRef nRRAS_5_u_i))
-           (portRef A (instanceRef nRWE_s_i_a3_1_0))
+           (portRef A (instanceRef nRCS_9_u_i_0))
            (portRef D (instanceRef IS_RNO_3))
            (portRef A (instanceRef RA10_0io_RNO))
           ))
@@ -1109,147 +2025,229 @@
            (portRef C (instanceRef RA10_0io_RNO_0))
            (portRef A (instanceRef IS_RNO_3))
           ))
-          (net (rename IS_2 "IS[2]") (joined
-           (portRef Q (instanceRef IS_2))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef IS_RNO_2))
-           (portRef C (instanceRef nRWE_s_i_a3_1_0))
-           (portRef B (instanceRef RA10_0io_RNO_0))
-           (portRef B (instanceRef IS_RNO_3))
-          ))
           (net (rename IS_1 "IS[1]") (joined
            (portRef Q (instanceRef IS_1))
+           (portRef B (instanceRef nRWE_0io_RNO_1))
            (portRef B (instanceRef IS_n1_0_x2))
            (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
            (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
            (portRef B (instanceRef IS_RNO_2))
-           (portRef B (instanceRef nRWE_s_i_a3_1_0))
            (portRef A (instanceRef RA10_0io_RNO_0))
            (portRef C (instanceRef IS_RNO_3))
           ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A0 (instanceRef FS_cry_0_5))
-           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_13_i_a2_1))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A1 (instanceRef FS_cry_0_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef B (instanceRef un1_FS_13_i_a2_6))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A0 (instanceRef FS_cry_0_7))
-           (portRef C (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A1 (instanceRef FS_cry_0_7))
-           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A0 (instanceRef FS_cry_0_9))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef un1_FS_13_i_a2_8))
+          (net (rename IS_2 "IS[2]") (joined
+           (portRef Q (instanceRef IS_2))
+           (portRef C (instanceRef nRWE_0io_RNO_1))
+           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef IS_RNO_2))
+           (portRef B (instanceRef RA10_0io_RNO_0))
+           (portRef B (instanceRef IS_RNO_3))
           ))
           (net (rename FS_0 "FS[0]") (joined
            (portRef Q (instanceRef FS_0))
            (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_1))
+           (portRef A (instanceRef un1_FS_7_i_a4_0_0))
           ))
           (net (rename FS_1 "FS[1]") (joined
            (portRef Q (instanceRef FS_1))
            (portRef A0 (instanceRef FS_cry_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef UFMCLK_r_i_m2))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A1 (instanceRef FS_cry_0_1))
-           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef B (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_3 "FS[3]") (joined
-           (portRef Q (instanceRef FS_3))
-           (portRef A0 (instanceRef FS_cry_0_3))
-           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_13_i_a2_1))
+           (portRef A (instanceRef un1_FS_7_i_a4_0_3))
           ))
           (net (rename FS_10 "FS[10]") (joined
            (portRef Q (instanceRef FS_10))
            (portRef A1 (instanceRef FS_cry_0_9))
-           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef nUFMCS15_0_a2))
+           (portRef C (instanceRef wb_adr_10_0_a2_3_0))
+           (portRef A (instanceRef wb_adr_10_0_a2_1_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_o2_5))
+           (portRef A (instanceRef wb_we_0_0_a2_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_0_1_6))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_0_0_4))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_0_0_3))
+           (portRef B (instanceRef wb_adr_10_0_a4_0_0_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_1_1))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_0_7))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_a2_4))
+           (portRef B (instanceRef wb_adr_10_0_a4_7_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_1_4))
+           (portRef B (instanceRef wb_adr_10_0_a4_1))
+           (portRef A (instanceRef wb_we_0_0_5))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_3))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_7))
+           (portRef B (instanceRef wb_adr_10_0_o2_0_RNI0U1R_0))
+           (portRef B (instanceRef wb_rst_RNO))
+           (portRef B (instanceRef wb_adr_10_0_a2_RNIQ1AL_1))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO))
+           (portRef A (instanceRef FS_RNIPIOA_0_11))
+           (portRef A (instanceRef FS_RNIPIOA_11))
+           (portRef D (instanceRef FS_RNI1T8E_7))
           ))
           (net (rename FS_11 "FS[11]") (joined
            (portRef Q (instanceRef FS_11))
            (portRef A0 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef InitReady3_0_a2_3))
-           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef C (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef un1_FS_13_i_a2_8))
+           (portRef B (instanceRef wb_adr_10_0_a2_3_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_o2_1_5))
+           (portRef B (instanceRef wb_we_0_0_a2_0))
+           (portRef A (instanceRef wb_we_0_0_o2))
+           (portRef A (instanceRef wb_adr_10_0_o2_0_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_m2_3))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_0_1_6))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_0_0_4))
+           (portRef B (instanceRef wb_adr_10_0_a2_1))
+           (portRef C (instanceRef wb_adr_10_0_a4_0_0_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_1))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_0_7))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_o2_1))
+           (portRef A (instanceRef wb_adr_10_0_a2_6_0))
+           (portRef D (instanceRef wb_dati_10_0_iv_0_RNO_0))
+           (portRef D (instanceRef wb_rst_RNO))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO))
+           (portRef C (instanceRef FS_RNIPIOA_0_11))
+           (portRef C (instanceRef FS_RNIPIOA_11))
+           (portRef C (instanceRef FS_RNI1T8E_7))
           ))
           (net (rename FS_12 "FS[12]") (joined
            (portRef Q (instanceRef FS_12))
            (portRef A1 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef A (instanceRef InitReady3_0_a2_5))
+           (portRef A (instanceRef wb_adr_10_0_a2_3_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_1_6))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_o2_1_5))
+           (portRef B (instanceRef wb_we_0_0_o2))
+           (portRef B (instanceRef wb_adr_10_0_o2_0_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_m2_3))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_0_1_6))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_0_0_4))
+           (portRef C (instanceRef wb_adr_10_0_a2_1))
+           (portRef D (instanceRef wb_adr_10_0_a4_0_0_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_1))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2_4))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_o2_1))
+           (portRef A (instanceRef wb_we_0_0_a4))
+           (portRef B (instanceRef wb_adr_10_0_a2_6_0))
+           (portRef C (instanceRef wb_adr_10_0_a4_7_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_4))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_1_7))
+           (portRef A (instanceRef wb_we_0_0))
+           (portRef C (instanceRef wb_dati_10_0_iv_0_RNO_0))
+           (portRef C (instanceRef wb_rst_RNO))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO))
+           (portRef B (instanceRef FS_RNIPIOA_0_11))
+           (portRef B (instanceRef FS_RNIPIOA_11))
+           (portRef A (instanceRef FS_RNI1T8E_7))
           ))
           (net (rename FS_13 "FS[13]") (joined
            (portRef Q (instanceRef FS_13))
            (portRef A0 (instanceRef FS_cry_0_13))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef B (instanceRef InitReady3_0_a2_5))
+           (portRef D (instanceRef wb_rst_3_0_a2))
+           (portRef A (instanceRef InitReady3_0_a4_2))
+           (portRef A (instanceRef wb_clk_9_iv_i_o2))
+           (portRef D (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q))
           ))
           (net (rename FS_14 "FS[14]") (joined
            (portRef Q (instanceRef FS_14))
            (portRef A1 (instanceRef FS_cry_0_13))
-           (portRef B (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
+           (portRef B (instanceRef InitReady3_0_a4_2))
+           (portRef A (instanceRef wb_clk_9_iv_i_o2_2))
           ))
           (net (rename FS_15 "FS[15]") (joined
            (portRef Q (instanceRef FS_15))
            (portRef A0 (instanceRef FS_cry_0_15))
-           (portRef C (instanceRef InitReady3_0_a2_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
+           (portRef B (instanceRef wb_clk_9_iv_i_o2_2))
+           (portRef A (instanceRef InitReady3_0_a4))
           ))
           (net (rename FS_16 "FS[16]") (joined
            (portRef Q (instanceRef FS_16))
            (portRef A1 (instanceRef FS_cry_0_15))
-           (portRef B (instanceRef InitReady3_0_a2))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
+           (portRef C (instanceRef wb_clk_9_iv_i_o2_2))
+           (portRef B (instanceRef InitReady3_0_a4))
           ))
           (net (rename FS_17 "FS[17]") (joined
            (portRef Q (instanceRef FS_17))
            (portRef A0 (instanceRef FS_s_0_17))
-           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef D (instanceRef InitReady3_0_a2_5))
+           (portRef C (instanceRef wb_rst_3_0_a2))
+           (portRef C (instanceRef InitReady3_0_a4_2))
+           (portRef B (instanceRef wb_clk_9_iv_i_o2))
+           (portRef C (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q))
+          ))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef Q (instanceRef FS_5))
+           (portRef A0 (instanceRef FS_cry_0_5))
+           (portRef A (instanceRef wb_adr_10_0_a2_0_0))
+           (portRef A (instanceRef wb_we_0_0_a4_0_0_1))
+           (portRef A (instanceRef wb_adr_10_0_o2_1))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_1_0_0_3))
+           (portRef A (instanceRef wb_adr_10_0_a2_1))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_1_0_7))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_2_4))
+           (portRef D (instanceRef FS_RNIU61E_5))
+          ))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef Q (instanceRef FS_6))
+           (portRef A1 (instanceRef FS_cry_0_5))
+           (portRef C (instanceRef wb_adr_10_0_a2_1_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_1_6))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_o2_1_5))
+           (portRef B (instanceRef wb_we_0_0_a4_0_0_1))
+           (portRef B (instanceRef wb_adr_10_0_o2_1))
+           (portRef A (instanceRef wb_adr_10_0_o2_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_0_0_3))
+           (portRef A (instanceRef wb_adr_10_0_a4_0_0_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_2_4))
+           (portRef A (instanceRef un1_FS_7_i_a4_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_3))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_4))
+           (portRef D (instanceRef wb_adr_10_0_a2_RNIIJC01_1))
+           (portRef C (instanceRef FS_RNIU61E_5))
+           (portRef D (instanceRef wb_adr_10_0_a2_RNIQ1AL_1))
+          ))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef Q (instanceRef FS_7))
+           (portRef A0 (instanceRef FS_cry_0_7))
+           (portRef A (instanceRef wb_adr_10_0_a2_7_0))
+           (portRef B (instanceRef wb_adr_10_0_a2_1_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_o2_1_5))
+           (portRef B (instanceRef wb_adr_10_0_o2_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_m2_3))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_0_1_6))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_0_0_4))
+           (portRef A (instanceRef wb_we_0_0_a4_0_0))
+           (portRef A (instanceRef wb_adr_10_0_5_tz_0))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_o2_1))
+           (portRef A (instanceRef wb_adr_10_0_a4_7_0))
+           (portRef A (instanceRef wb_adr_10_0_a4_1))
+           (portRef C (instanceRef wb_adr_10_0_a2_RNIIJC01_1))
+           (portRef B (instanceRef FS_RNIU61E_5))
+           (portRef C (instanceRef wb_adr_10_0_a2_RNIQ1AL_1))
+           (portRef B (instanceRef FS_RNI1T8E_7))
+          ))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef Q (instanceRef FS_8))
+           (portRef A1 (instanceRef FS_cry_0_7))
+           (portRef D (instanceRef wb_we_0_0_a2))
+           (portRef D (instanceRef wb_adr_10_0_a2_12_0))
+           (portRef D (instanceRef wb_adr_10_0_a2_7_0))
+           (portRef D (instanceRef wb_adr_10_0_a2_0_0))
+           (portRef B (instanceRef wb_we_0_0_a4_0_0))
+           (portRef A (instanceRef wb_adr_10_0_a2_11_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a2_7))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_o2_2_0))
+           (portRef A (instanceRef FS_RNIU61E_5))
           ))
           (net PHI2r2 (joined
            (portRef Q (instanceRef PHI2r2))
+           (portRef A (instanceRef PHI2r3_RNIFT0I))
            (portRef A (instanceRef un1_PHI2r3_0))
-           (portRef C (instanceRef PHI2r3_RNITCN41))
+           (portRef C (instanceRef wb_clk_RNO_0))
            (portRef D (instanceRef PHI2r3))
           ))
-          (net CmdUFMCS (joined
-           (portRef Q (instanceRef CmdUFMCS))
-           (portRef A (instanceRef nUFMCS_s_0_m4_yy))
+          (net CMDUFMWrite (joined
+           (portRef Q (instanceRef CMDUFMWrite))
+           (portRef A (instanceRef CMDUFMWrite_RNIHQ1E1))
+           (portRef A (instanceRef wb_clk_RNO_1))
           ))
           (net CASr2 (joined
            (portRef Q (instanceRef CASr2))
-           (portRef A (instanceRef nRWE_0io_RNO_0))
+           (portRef A (instanceRef nRWE_0io_RNO_4))
            (portRef A (instanceRef RCKEEN_8_u_1_0))
            (portRef A (instanceRef nRCAS_r_i_a3_1_1_tz))
            (portRef D (instanceRef CASr3))
@@ -1269,63 +2267,63 @@
           ))
           (net (rename Bank_0 "Bank[0]") (joined
            (portRef Q (instanceRef Bank_0io_0))
-           (portRef A (instanceRef C1WR_7_0_o3_6))
+           (portRef A (instanceRef un1_ADWR_i_o4_10))
           ))
           (net (rename Bank_1 "Bank[1]") (joined
            (portRef Q (instanceRef Bank_0io_1))
-           (portRef A (instanceRef C1WR_7_0_o3_7))
+           (portRef A (instanceRef un1_ADWR_i_o4_11))
           ))
           (net (rename Bank_3 "Bank[3]") (joined
            (portRef Q (instanceRef Bank_0io_3))
-           (portRef B (instanceRef C1WR_7_0_o3_7))
+           (portRef B (instanceRef un1_ADWR_i_o4_11))
           ))
           (net (rename Bank_4 "Bank[4]") (joined
            (portRef Q (instanceRef Bank_0io_4))
-           (portRef C (instanceRef C1WR_7_0_o3_7))
+           (portRef C (instanceRef un1_ADWR_i_o4_11))
           ))
           (net (rename Bank_5 "Bank[5]") (joined
            (portRef Q (instanceRef Bank_0io_5))
-           (portRef D (instanceRef C1WR_7_0_o3_7))
+           (portRef D (instanceRef un1_ADWR_i_o4_11))
           ))
           (net (rename Bank_6 "Bank[6]") (joined
            (portRef Q (instanceRef Bank_0io_6))
-           (portRef A (instanceRef C1WR_7_0_o3))
+           (portRef A (instanceRef un1_ADWR_i_o4))
           ))
           (net (rename Bank_7 "Bank[7]") (joined
            (portRef Q (instanceRef Bank_0io_7))
-           (portRef B (instanceRef C1WR_7_0_o3))
+           (portRef B (instanceRef un1_ADWR_i_o4))
           ))
           (net (rename RowA_0 "RowA[0]") (joined
            (portRef Q (instanceRef RowA_0))
-           (portRef B (instanceRef un9_RA_i_m3_0))
+           (portRef B (instanceRef un9_RA_i_m2_0))
           ))
           (net (rename RowA_1 "RowA[1]") (joined
            (portRef Q (instanceRef RowA_1))
-           (portRef B (instanceRef un9_RA_i_m3_1))
+           (portRef B (instanceRef un9_RA_i_m2_1))
           ))
           (net (rename RowA_2 "RowA[2]") (joined
            (portRef Q (instanceRef RowA_2))
-           (portRef B (instanceRef un9_RA_i_m3_2))
+           (portRef B (instanceRef un9_RA_i_m2_2))
           ))
           (net (rename RowA_3 "RowA[3]") (joined
            (portRef Q (instanceRef RowA_3))
-           (portRef B (instanceRef un9_RA_i_m3_3))
+           (portRef B (instanceRef un9_RA_i_m2_3))
           ))
           (net (rename RowA_4 "RowA[4]") (joined
            (portRef Q (instanceRef RowA_4))
-           (portRef B (instanceRef un9_RA_i_m3_4))
+           (portRef B (instanceRef un9_RA_i_m2_4))
           ))
           (net (rename RowA_5 "RowA[5]") (joined
            (portRef Q (instanceRef RowA_5))
-           (portRef B (instanceRef un9_RA_i_m3_5))
+           (portRef B (instanceRef un9_RA_i_m2_5))
           ))
           (net (rename RowA_6 "RowA[6]") (joined
            (portRef Q (instanceRef RowA_6))
-           (portRef B (instanceRef un9_RA_i_m3_6))
+           (portRef B (instanceRef un9_RA_i_m2_6))
           ))
           (net (rename RowA_7 "RowA[7]") (joined
            (portRef Q (instanceRef RowA_7))
-           (portRef B (instanceRef un9_RA_i_m3_7))
+           (portRef B (instanceRef un9_RA_i_m2_7))
           ))
           (net (rename RowA_8 "RowA[8]") (joined
            (portRef Q (instanceRef RowA_8))
@@ -1333,7 +2331,7 @@
           ))
           (net (rename RowA_9 "RowA[9]") (joined
            (portRef Q (instanceRef RowA_9))
-           (portRef B (instanceRef un9_RA_i_m3_9))
+           (portRef B (instanceRef un9_RA_i_m2_9))
           ))
           (net (rename WRD_0 "WRD[0]") (joined
            (portRef Q (instanceRef WRD_0io_0))
@@ -1370,15 +2368,15 @@
           (net nRowColSel (joined
            (portRef Q (instanceRef nRowColSel))
            (portRef B (instanceRef RDQML_0))
-           (portRef C (instanceRef un9_RA_i_m3_9))
-           (portRef C (instanceRef un9_RA_i_m3_7))
-           (portRef C (instanceRef un9_RA_i_m3_6))
-           (portRef C (instanceRef un9_RA_i_m3_5))
-           (portRef C (instanceRef un9_RA_i_m3_4))
-           (portRef C (instanceRef un9_RA_i_m3_3))
-           (portRef C (instanceRef un9_RA_i_m3_2))
-           (portRef C (instanceRef un9_RA_i_m3_1))
-           (portRef C (instanceRef un9_RA_i_m3_0))
+           (portRef C (instanceRef un9_RA_i_m2_9))
+           (portRef C (instanceRef un9_RA_i_m2_7))
+           (portRef C (instanceRef un9_RA_i_m2_6))
+           (portRef C (instanceRef un9_RA_i_m2_5))
+           (portRef C (instanceRef un9_RA_i_m2_4))
+           (portRef C (instanceRef un9_RA_i_m2_3))
+           (portRef C (instanceRef un9_RA_i_m2_2))
+           (portRef C (instanceRef un9_RA_i_m2_1))
+           (portRef C (instanceRef un9_RA_i_m2_0))
            (portRef C (instanceRef un9_RA_8))
            (portRef B (instanceRef RDQMH_pad_RNO))
           ))
@@ -1392,36 +2390,31 @@
            (portRef B (instanceRef XOR8MEG_3_u_0_0))
            (portRef B (instanceRef CmdLEDEN_RNO))
           ))
+          (net CmdLEDEN (joined
+           (portRef Q (instanceRef CmdLEDEN))
+           (portRef A (instanceRef LEDEN_6_i_m2))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_0))
+          ))
           (net Cmdn8MEGEN (joined
            (portRef Q (instanceRef Cmdn8MEGEN))
-           (portRef A (instanceRef n8MEGEN_5_i_m2))
+           (portRef A (instanceRef n8MEGEN_6_i_m2))
            (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
           ))
           (net PHI2r3 (joined
            (portRef Q (instanceRef PHI2r3))
+           (portRef B (instanceRef PHI2r3_RNIFT0I))
            (portRef B (instanceRef un1_PHI2r3_0))
-           (portRef D (instanceRef PHI2r3_RNITCN41))
+           (portRef D (instanceRef wb_clk_RNO_0))
           ))
           (net CmdSubmitted (joined
            (portRef Q (instanceRef CmdSubmitted))
-           (portRef A (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef un1_FS_13_i_0))
-           (portRef A (instanceRef un1_FS_14_i_0))
+           (portRef A (instanceRef wb_clk_RNO_0))
+           (portRef A (instanceRef un1_FS_7_i_0))
            (portRef B (instanceRef CmdSubmitted_RNO))
-          ))
-          (net CmdLEDEN (joined
-           (portRef Q (instanceRef CmdLEDEN))
-           (portRef A (instanceRef LEDEN_RNO))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_0))
-          ))
-          (net (rename FS_4 "FS[4]") (joined
-           (portRef Q (instanceRef FS_4))
-           (portRef A1 (instanceRef FS_cry_0_3))
-           (portRef B (instanceRef UFMCLK_r_i_m2))
-           (portRef A (instanceRef un1_FS_13_i_a2_8))
+           (portRef C (instanceRef wb_clk_RNO_1))
           ))
           (net InitReady3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2))
+           (portRef Z (instanceRef InitReady3_0_a4))
            (portRef A (instanceRef InitReady_RNO))
           ))
           (net RCKEEN (joined
@@ -1431,22 +2424,13 @@
           (net XOR8MEG (joined
            (portRef Q (instanceRef XOR8MEG))
            (portRef C (instanceRef RA11d))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a2))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a4))
           ))
           (net nRRAS_0_sqmuxa (joined
            (portRef Z (instanceRef S_RNICVV51_0))
-           (portRef C (instanceRef nRWE_s_i_tz_0))
+           (portRef C (instanceRef nRWE_0io_RNO_3))
            (portRef CD (instanceRef nRowColSel))
           ))
-          (net nUFMCS15 (joined
-           (portRef Z (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMCLK_0io_RNO_0))
-           (portRef C (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef C (instanceRef UFMCLK_0io_RNO))
-           (portRef B (instanceRef UFMSDI_RNO_1))
-           (portRef B (instanceRef UFMSDI_RNO_0))
-          ))
           (net Ready_0_sqmuxa (joined
            (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
            (portRef A (instanceRef Ready_fast_RNO))
@@ -1457,75 +2441,96 @@
           ))
           (net nRCAS_0_sqmuxa_1 (joined
            (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef A (instanceRef nRWE_0io_RNO))
            (portRef B (instanceRef nRCAS_0io_RNO))
+           (portRef C (instanceRef nRWE_0io_RNO))
+          ))
+          (net wb_clk23 (joined
+           (portRef Z (instanceRef wb_adr_10_0_o2_0_RNI0U1R_0))
+           (portRef CD (instanceRef wb_clk))
+           (portRef CD (instanceRef wb_cyc_stb))
+           (portRef CD (instanceRef wb_we))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef Q (instanceRef FS_2))
+           (portRef A1 (instanceRef FS_cry_0_1))
+           (portRef B (instanceRef un1_FS_7_i_a4_0_3))
+           (portRef C (instanceRef wb_clk_RNO_2))
+          ))
+          (net (rename FS_3 "FS[3]") (joined
+           (portRef Q (instanceRef FS_3))
+           (portRef A0 (instanceRef FS_cry_0_3))
+           (portRef B (instanceRef un1_FS_7_i_a4_0_0))
           ))
           (net XOR8MEG18 (joined
-           (portRef Z (instanceRef XOR8MEG18))
-           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
+           (portRef Z (instanceRef XOR8MEG18_0_a2))
+           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a4))
+           (portRef A (instanceRef CMDUFMWrite_1_sqmuxa_0_a4))
            (portRef SP (instanceRef CmdLEDEN))
            (portRef SP (instanceRef Cmdn8MEGEN))
            (portRef SP (instanceRef XOR8MEG))
           ))
           (net CmdEnable (joined
            (portRef Q (instanceRef CmdEnable))
-           (portRef B (instanceRef XOR8MEG18))
+           (portRef A (instanceRef XOR8MEG18_0_a2))
            (portRef A (instanceRef CmdEnable_s))
           ))
           (net CmdEnable16 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef C1Submitted_s_0))
+           (portRef Z (instanceRef CmdEnable16_0_a4))
            (portRef D (instanceRef ADSubmitted_r_0))
+           (portRef A (instanceRef C1Submitted_RNO))
           ))
           (net CmdEnable17 (joined
            (portRef Z (instanceRef CmdEnable17_0_a2))
            (portRef C (instanceRef ADSubmitted_r_0))
            (portRef B (instanceRef CmdEnable_s))
           ))
+          (net CMDUFMWrite_1_sqmuxa (joined
+           (portRef Z (instanceRef CMDUFMWrite_1_sqmuxa_0_a4))
+           (portRef SP (instanceRef CMDUFMWrite))
+           (portRef SP (instanceRef CmdUFMData))
+          ))
           (net CmdSubmitted_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
+           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a4))
            (portRef A (instanceRef CmdSubmitted_RNO))
+           (portRef A (instanceRef CmdSubmitted_fast_RNO))
           ))
-          (net CmdUFMCLK_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdUFMCLK))
-           (portRef SP (instanceRef CmdUFMCS))
-           (portRef SP (instanceRef CmdUFMSDI))
-          ))
-          (net CmdUFMCLK (joined
-           (portRef Q (instanceRef CmdUFMCLK))
-           (portRef A (instanceRef UFMCLK_0io_RNO))
-          ))
-          (net CmdUFMSDI (joined
-           (portRef Q (instanceRef CmdUFMSDI))
-           (portRef D (instanceRef UFMSDI_RNO_0))
+          (net CmdUFMData (joined
+           (portRef Q (instanceRef CmdUFMData))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0))
           ))
           (net ADSubmitted (joined
            (portRef Q (instanceRef ADSubmitted))
            (portRef A (instanceRef ADSubmitted_r_0))
-           (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2))
+           (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a4))
           ))
           (net CmdEnable_0_sqmuxa (joined
-           (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2))
+           (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a4))
            (portRef D (instanceRef CmdEnable_s))
           ))
-          (net C1Submitted_s_0 (joined
-           (portRef Z (instanceRef C1Submitted_s_0))
+          (net wb_cyc_stb_65 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0))
+           (portRef D (instanceRef wb_cyc_stb))
+          ))
+          (net (rename wb_dati_10_7 "wb_dati_10[7]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_7))
+           (portRef D (instanceRef wb_dati_7))
+          ))
+          (net C1Submitted_RNO (joined
+           (portRef Z (instanceRef C1Submitted_RNO))
            (portRef D (instanceRef C1Submitted))
           ))
           (net ADSubmitted_r_0 (joined
            (portRef Z (instanceRef ADSubmitted_r_0))
            (portRef D (instanceRef ADSubmitted))
           ))
-          (net UFMSDI_RNO (joined
-           (portRef Z (instanceRef UFMSDI_RNO))
-           (portRef D (instanceRef UFMSDI))
-          ))
           (net CmdEnable_s (joined
            (portRef Z (instanceRef CmdEnable_s))
            (portRef D (instanceRef CmdEnable))
           ))
+          (net wb_we_0_0 (joined
+           (portRef Z (instanceRef wb_we_0_0))
+           (portRef D (instanceRef wb_we))
+          ))
           (net nRowColSel_0_0 (joined
            (portRef Z (instanceRef nRowColSel_0_0))
            (portRef D (instanceRef nRowColSel))
@@ -1534,221 +2539,483 @@
            (portRef Z (instanceRef XOR8MEG_3_u_0_0))
            (portRef D (instanceRef XOR8MEG))
           ))
+          (net (rename wb_adr_10_0 "wb_adr_10[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_0))
+           (portRef D (instanceRef wb_adr_0))
+          ))
           (net RCKEEN_8 (joined
            (portRef Z (instanceRef RCKEEN_8_u))
            (portRef D (instanceRef RCKEEN))
           ))
-          (net N_26 (joined
-           (portRef Z (instanceRef un1_FS_14_i_0))
-           (portRef SP (instanceRef n8MEGEN))
-          ))
-          (net N_28 (joined
-           (portRef Z (instanceRef un1_FS_13_i_0))
-           (portRef SP (instanceRef LEDEN))
-          ))
-          (net N_24 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i))
-           (portRef B (instanceRef nRCS_0io_RNO_0))
-          ))
           (net un1_nRCAS_6_sqmuxa_i_0 (joined
            (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
            (portRef B (instanceRef nRCAS_0io_RNO_0))
           ))
-          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
+          (net N_49 (joined
            (portRef Z (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef nRRAS_5_u_i_0))
+           (portRef A (instanceRef nRCS_9_u_i_0_0))
            (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
            (portRef D (instanceRef S_1))
            (portRef D (instanceRef RCKEEN_8_u_0_0))
           ))
-          (net N_46 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3))
-           (portRef C (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef D (instanceRef CMDWR))
-          ))
-          (net N_45 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_0))
-           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_36 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-          ))
-          (net CMDWR (joined
-           (portRef Z (instanceRef CMDWR))
-           (portRef A (instanceRef XOR8MEG18))
-           (portRef A (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_151 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef B (instanceRef C1Submitted_s_0))
-           (portRef B (instanceRef ADSubmitted_r_0))
-           (portRef D (instanceRef CmdEnable17_0_a2_0))
-           (portRef B (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_189 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_183 (joined
+          (net IS_0_sqmuxa_0_o2_0 (joined
            (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
            (portRef C (instanceRef IS_RNO_0))
            (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRRAS_5_u_i_0_RNILD5I))
+           (portRef B (instanceRef nRCS_9_u_i_0_0_RNIOMAB))
            (portRef A (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef nRRAS_5_u_i))
+           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef C (instanceRef nRCS_9_u_i_0))
           ))
-          (net N_188 (joined
+          (net IS_0_sqmuxa_0_o2 (joined
            (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef D (instanceRef nRWE_s_i_a3_1_0))
+           (portRef D (instanceRef nRWE_0io_RNO))
            (portRef D (instanceRef RA10_0io_RNO_0))
           ))
-          (net N_160 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a2))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a2_0_2))
+          (net N_58 (joined
+           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
+           (portRef C (instanceRef nRCS_9_u_i_0_0_RNIOMAB))
+           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
+           (portRef B (instanceRef nRCS_9_u_i_0))
           ))
-          (net N_139_8 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_8))
-           (portRef B (instanceRef un1_FS_14_i_a2_0))
-           (portRef B (instanceRef un1_FS_13_i_a2))
-          ))
-          (net N_139_6 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef un1_FS_14_i_a2_0))
-           (portRef A (instanceRef un1_FS_13_i_a2))
-          ))
-          (net N_177 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_0))
-           (portRef A (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_178 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef D (instanceRef un1_CmdEnable20_0_a2_0_0))
-          ))
-          (net N_168 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef C (instanceRef un1_CmdEnable20_0_a2_0_0))
-          ))
-          (net N_76 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_0))
-          ))
-          (net N_94 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef C (instanceRef CmdLEDEN_RNO))
-           (portRef B (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net N_131 (joined
-           (portRef Z (instanceRef n8MEGEN_5_i_m2))
-           (portRef D (instanceRef n8MEGEN))
-          ))
-          (net N_205 (joined
-           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
-           (portRef B (instanceRef nRowColSel_0_0))
-          ))
-          (net N_137_5 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_5))
-           (portRef D (instanceRef InitReady3_0_a2))
-           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
-          ))
-          (net N_137_3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef InitReady3_0_a2))
-           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
-          ))
-          (net N_129 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef D (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef C (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_34 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_145 (joined
-           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef D (instanceRef un1_FS_13_i_a2_8))
-           (portRef C (instanceRef UFMSDI_RNO_0))
-          ))
-          (net N_50 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef UFMCLK_0io_RNO_1))
-          ))
-          (net N_139 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0))
-           (portRef C (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_140 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2))
-           (portRef C (instanceRef un1_FS_13_i_0))
-          ))
-          (net N_215 (joined
-           (portRef Z (instanceRef IS_n1_0_x2))
-           (portRef D (instanceRef IS_1))
-          ))
-          (net N_56 (joined
+          (net N_65 (joined
            (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
            (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
            (portRef C (instanceRef Ready_RNO))
           ))
-          (net nRWE_s_i_a3_1_0 (joined
-           (portRef Z (instanceRef nRWE_s_i_a3_1_0))
-           (portRef D (instanceRef nRWE_s_i_tz_0))
+          (net N_97 (joined
+           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
+           (portRef B (instanceRef nRowColSel_0_0))
+          ))
+          (net N_62_i (joined
+           (portRef Z (instanceRef IS_n1_0_x2))
+           (portRef D (instanceRef IS_1))
+          ))
+          (net N_18 (joined
+           (portRef Z (instanceRef un1_FS_7_i_0))
+           (portRef SP (instanceRef LEDEN))
+           (portRef SP (instanceRef n8MEGEN))
+          ))
+          (net wb_we_0_0_o2 (joined
+           (portRef Z (instanceRef wb_we_0_0_o2))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_o2_5))
+           (portRef B (instanceRef wb_we_0_0_5))
+          ))
+          (net wb_clk_9_iv_i_o2 (joined
+           (portRef Z (instanceRef wb_clk_9_iv_i_o2))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_a2_2))
+           (portRef A (instanceRef wb_cyc_stb_65_0_iv_0_o2_0_0))
+           (portRef B (instanceRef wb_clk_RNO_2))
+           (portRef C (instanceRef wb_adr_10_0_o2_0_RNI0U1R_0))
+           (portRef C (instanceRef wb_we_0_0_1_RNO))
+          ))
+          (net (rename wb_adr_10_0_o2_0 "wb_adr_10_0_o2[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_o2_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_o2_5))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_1_1))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_1_0_7))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_4))
+           (portRef A (instanceRef wb_adr_10_0_4_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_7))
+          ))
+          (net (rename wb_adr_10_0_o2_0_0 "wb_adr_10_0_o2_0[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_o2_0_0))
+           (portRef B (instanceRef wb_adr_10_0_5_tz_0))
+           (portRef A (instanceRef wb_dati_10_1_iv_0_a4_1_3))
+           (portRef A (instanceRef wb_adr_10_0_o2_0_RNI0U1R_0))
+          ))
+          (net XOR8MEG_3_u_0_o2_1 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_o2_1))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a4_0_2))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a4))
+          ))
+          (net CmdLEDEN_4_u_i_o2_0 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_o2_0))
+           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a4))
+           (portRef B (instanceRef CMDUFMWrite_1_sqmuxa_0_a4))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_o2))
+           (portRef C (instanceRef CmdLEDEN_RNO))
+           (portRef B (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net N_113 (joined
+           (portRef Z (instanceRef wb_adr_10_0_o2_1))
+           (portRef A (instanceRef wb_adr_10_0_a2_12_0))
+           (portRef C (instanceRef wb_adr_10_0_a4_1))
+          ))
+          (net N_122 (joined
+           (portRef Z (instanceRef un1_ADWR_i_o4))
+           (portRef B (instanceRef CmdEnable16_0_a4))
+           (portRef A (instanceRef CmdEnable_s_RNO))
+           (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a4))
+           (portRef D (instanceRef XOR8MEG18_0_a2))
+           (portRef B (instanceRef CmdEnable17_0_a2))
+           (portRef B (instanceRef ADSubmitted_r_0_RNO))
+           (portRef C (instanceRef C1Submitted_RNO))
+          ))
+          (net N_126 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_RNIIJC01_1))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_o2_2_0))
+           (portRef A (instanceRef wb_adr_10_0_3_0))
+          ))
+          (net N_129 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_o2))
+           (portRef D (instanceRef CmdLEDEN_4_u_i_0))
+           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
+          ))
+          (net LEDEN_6_i_m2 (joined
+           (portRef Z (instanceRef LEDEN_6_i_m2))
+           (portRef D (instanceRef LEDEN))
+          ))
+          (net n8MEGEN_6_i_m2 (joined
+           (portRef Z (instanceRef n8MEGEN_6_i_m2))
+           (portRef D (instanceRef n8MEGEN))
+          ))
+          (net wb_cyc_stb_65_0_iv_0_o2_1 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_o2_1))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_o2_2_0))
+          ))
+          (net N_200 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_3_0))
+           (portRef B (instanceRef wb_adr_10_0_1_0))
+          ))
+          (net N_203 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_6_0))
+           (portRef C (instanceRef wb_adr_10_0_1_0))
+          ))
+          (net N_204 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_7_0))
+           (portRef B (instanceRef wb_adr_10_0_3_0))
+          ))
+          (net un1_FS_7_i_a4_0 (joined
+           (portRef Z (instanceRef un1_FS_7_i_a4_0))
+           (portRef C (instanceRef un1_FS_7_i_0))
+          ))
+          (net XOR8MEG_3_u_0_a4 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a4))
+           (portRef C (instanceRef XOR8MEG_3_u_0_0))
+          ))
+          (net (rename wb_dati_10_1_iv_0_a2_7 "wb_dati_10_1_iv_0_a2[7]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a2_7))
+           (portRef C (instanceRef wb_adr_10_0_a2_6_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_0_7))
+          ))
+          (net (rename wb_adr_10_0_a2_0_0 "wb_adr_10_0_a2_0[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_0_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_6))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_1_4))
+           (portRef B (instanceRef un1_FS_7_i_a4_0))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_3))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_1))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_5))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_2))
+           (portRef A (instanceRef wb_adr_10_0_0))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_4))
+           (portRef B (instanceRef wb_dati_10_0_iv_0_RNO_0))
+          ))
+          (net wb_cyc_stb_65_0_iv_0_a2_2_RNO (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_a2_2_RNO))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2_2))
+          ))
+          (net (rename wb_adr_10_0_a2_1_0 "wb_adr_10_0_a2_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_1_0))
+           (portRef A (instanceRef wb_we_0_0_a2))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_1_6))
+           (portRef C (instanceRef wb_adr_10_0_5_tz_0))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_o2_1))
+           (portRef A (instanceRef wb_adr_10_0_a4_1_1))
+           (portRef A (instanceRef wb_dati_10_0_iv_0_RNO_0))
+          ))
+          (net XOR8MEG_3_u_0_a2 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a2))
+           (portRef C (instanceRef XOR8MEG_3_u_0_a4_0_2))
+          ))
+          (net CMDUFMWrite_1_sqmuxa_0_a2_0 (joined
+           (portRef Z (instanceRef CMDUFMWrite_1_sqmuxa_0_a2_0))
+           (portRef C (instanceRef un1_CmdEnable20_0_a2_0))
+           (portRef D (instanceRef CmdLEDEN_RNO))
+           (portRef C (instanceRef Cmdn8MEGEN_RNO))
+          ))
+          (net un1_CmdEnable20_0_a2 (joined
+           (portRef Z (instanceRef un1_CmdEnable20_0_a2))
+           (portRef C (instanceRef CmdEnable16_0_a4))
+           (portRef B (instanceRef CmdEnable_s_RNO))
+           (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2))
+          ))
+          (net (rename wb_adr_10_0_a2_3_0 "wb_adr_10_0_a2_3[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_3_0))
+           (portRef B (instanceRef wb_adr_10_0_a4_3_0))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_o2_0_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_2_4))
+           (portRef B (instanceRef wb_adr_10_0_a2_RNIIJC01_1))
+          ))
+          (net CmdEnable_0_sqmuxa_0_a2 (joined
+           (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2))
+           (portRef D (instanceRef un1_CmdEnable20_0_a2_0))
+           (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a4))
+          ))
+          (net XOR8MEG_3_u_0_a2_0 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0))
+           (portRef D (instanceRef XOR8MEG_3_u_0_a4_0_2))
+           (portRef D (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+          ))
+          (net (rename wb_adr_10_0_a2_1 "wb_adr_10_0_a2[1]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_1))
+           (portRef B (instanceRef wb_adr_10_0_a4_1_1))
+           (portRef A (instanceRef wb_adr_10_0_a2_RNIIJC01_1))
+           (portRef A (instanceRef wb_adr_10_0_a2_RNIQ1AL_1))
+          ))
+          (net (rename FS_RNIU61E_5 "FS_RNIU61E[5]") (joined
+           (portRef Z (instanceRef FS_RNIU61E_5))
+           (portRef C (instanceRef wb_adr_10_0_a4_3_0))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_a2_4))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_o2_0_0))
+           (portRef C (instanceRef wb_we_0_0_a4))
+          ))
+          (net wb_clk_9_iv_i_o2_2_RNIOE4Q (joined
+           (portRef Z (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q))
+           (portRef D (instanceRef wb_adr_10_0_a4_3_0))
+           (portRef D (instanceRef wb_we_0_0_a4))
+          ))
+          (net (rename wb_adr_10_0_a2_6_0 "wb_adr_10_0_a2_6[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_6_0))
+           (portRef D (instanceRef wb_adr_10_0_a4_1))
+           (portRef B (instanceRef wb_adr_10_0_4_0))
+           (portRef C (instanceRef wb_we_0_0_5))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_7))
+          ))
+          (net (rename wb_adr_10_0_a2_7_0 "wb_adr_10_0_a2_7[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_7_0))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_a4_2_4))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_a4_1_3))
+           (portRef C (instanceRef wb_adr_10_0_4_0))
+           (portRef D (instanceRef wb_we_0_0_5))
+          ))
+          (net CmdEnable_0_sqmuxa_0_a2_0 (joined
+           (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+           (portRef A (instanceRef CmdEnable16_0_a4))
+           (portRef C (instanceRef CmdEnable_s_RNO))
+           (portRef D (instanceRef CmdEnable_0_sqmuxa_0_a4))
+          ))
+          (net (rename FS_RNIPIOA_0_11 "FS_RNIPIOA_0[11]") (joined
+           (portRef Z (instanceRef FS_RNIPIOA_0_11))
+           (portRef D (instanceRef wb_adr_10_0_5_tz_0))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_a2_2))
+          ))
+          (net (rename FS_RNI1T8E_7 "FS_RNI1T8E[7]") (joined
+           (portRef Z (instanceRef FS_RNI1T8E_7))
+           (portRef C (instanceRef wb_adr_10_0_a4_6_0))
+           (portRef C (instanceRef un1_FS_7_i_a4_0))
+           (portRef B (instanceRef wb_dati_10_0_iv_0_0))
+          ))
+          (net un1_CmdEnable20_0_a2_0 (joined
+           (portRef Z (instanceRef un1_CmdEnable20_0_a2_0))
+           (portRef D (instanceRef CmdEnable_s_RNO_0))
+           (portRef C (instanceRef CmdEnable17_0_a2))
+          ))
+          (net (rename wb_adr_10_0_a2_11_0 "wb_adr_10_0_a2_11[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_11_0))
+           (portRef C (instanceRef wb_adr_10_0_a4_1_1))
+           (portRef B (instanceRef wb_dati_10_0_iv_0_0_0))
+           (portRef C (instanceRef wb_adr_10_0_3_0))
+          ))
+          (net wb_we_0_0_a2 (joined
+           (portRef Z (instanceRef wb_we_0_0_a2))
+           (portRef A (instanceRef wb_we_0_0_3))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_1_7))
+          ))
+          (net (rename wb_adr_10_0_a2_12_0 "wb_adr_10_0_a2_12[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_12_0))
+           (portRef D (instanceRef wb_adr_10_0_a4_7_0))
+           (portRef C (instanceRef wb_dati_10_0_iv_0_0))
+           (portRef B (instanceRef wb_we_0_0))
+          ))
+          (net N_208 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_1_1))
+           (portRef C (instanceRef wb_adr_10_0_1))
+          ))
+          (net N_259 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_1_4))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_1_4))
+          ))
+          (net N_261 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_3))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_3))
+          ))
+          (net N_183 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_m2_3))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_3))
+          ))
+          (net N_269 (joined
+           (portRef Z (instanceRef wb_dati_10_0_iv_0_RNO_0))
+           (portRef A (instanceRef wb_dati_10_0_iv_0_0))
+          ))
+          (net wb_rst_3 (joined
+           (portRef Z (instanceRef wb_rst_RNO))
+           (portRef D (instanceRef wb_rst))
+          ))
+          (net N_309 (joined
+           (portRef Z (instanceRef wb_rst_3_0_a2))
+           (portRef B (instanceRef wb_we_0_0_a2))
+           (portRef B (instanceRef wb_adr_10_0_a2_12_0))
+           (portRef B (instanceRef wb_adr_10_0_a2_7_0))
+           (portRef B (instanceRef wb_adr_10_0_a2_0_0))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_a2_4))
+           (portRef B (instanceRef wb_we_0_0_2))
+           (portRef C (instanceRef wb_adr_10_0_a2_11_0))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a2_7))
+           (portRef B (instanceRef wb_adr_10_0_a4_6_0))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_o2_2_0))
+           (portRef A (instanceRef wb_rst_RNO))
+          ))
+          (net N_272 (joined
+           (portRef Z (instanceRef wb_we_0_0_a4))
+           (portRef B (instanceRef wb_we_0_0_1))
+          ))
+          (net N_314 (joined
+           (portRef Z (instanceRef wb_we_0_0_a2_0))
+           (portRef B (instanceRef wb_we_0_0_a4))
+           (portRef C (instanceRef wb_we_0_0_2))
+          ))
+          (net N_308 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_a2_4))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_a2))
+          ))
+          (net (rename wb_adr_10_1 "wb_adr_10[1]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_1))
+           (portRef D (instanceRef wb_adr_1))
+          ))
+          (net N_205 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_1))
+           (portRef B (instanceRef wb_adr_10_0_1))
+          ))
+          (net (rename wb_dati_10_3 "wb_dati_10[3]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_3))
+           (portRef D (instanceRef wb_dati_3))
+          ))
+          (net N_263 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_1_3))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_3))
+          ))
+          (net N_260 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_2_4))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_1_4))
+          ))
+          (net N_110 (joined
+           (portRef Z (instanceRef FS_RNIPIOA_11))
+           (portRef D (instanceRef InitReady3_0_a4))
+           (portRef A (instanceRef wb_clk_RNO_2))
+           (portRef B (instanceRef wb_we_0_0_1_RNO))
+          ))
+          (net N_273 (joined
+           (portRef Z (instanceRef wb_we_0_0_1_RNO))
+           (portRef C (instanceRef wb_we_0_0_1))
+          ))
+          (net N_306 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_a2_2))
+           (portRef B (instanceRef wb_cyc_stb_65_0_iv_0_o2_0_0))
+          ))
+          (net (rename wb_dati_10_4 "wb_dati_10[4]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_4))
+           (portRef D (instanceRef wb_dati_4))
+          ))
+          (net (rename wb_dati_10_0 "wb_dati_10[0]") (joined
+           (portRef Z (instanceRef wb_dati_10_0_iv_0_0))
+           (portRef D (instanceRef wb_dati_0))
+          ))
+          (net N_239 (joined
+           (portRef Z (instanceRef wb_adr_10_0_i_o2_6))
+           (portRef D (instanceRef wb_adr_6))
+          ))
+          (net N_341 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_a2))
+           (portRef B (instanceRef wb_adr_10_0_i_o2_4))
+           (portRef B (instanceRef wb_adr_10_0_i_o2_5))
+           (portRef B (instanceRef wb_adr_10_0_i_o2_6))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0))
+          ))
+          (net N_238 (joined
+           (portRef Z (instanceRef wb_adr_10_0_i_o2_5))
+           (portRef D (instanceRef wb_adr_5))
+          ))
+          (net N_237 (joined
+           (portRef Z (instanceRef wb_adr_10_0_i_o2_4))
+           (portRef D (instanceRef wb_adr_4))
+          ))
+          (net N_118 (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_o2_5))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_5))
+           (portRef B (instanceRef wb_dati_10_1_iv_0_2))
+          ))
+          (net (rename wb_dati_10_2 "wb_dati_10[2]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_2))
+           (portRef D (instanceRef wb_dati_2))
+          ))
+          (net (rename wb_dati_10_5 "wb_dati_10[5]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_5))
+           (portRef D (instanceRef wb_dati_5))
+          ))
+          (net (rename wb_dati_10_1 "wb_dati_10[1]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_1))
+           (portRef D (instanceRef wb_dati_1))
+          ))
+          (net (rename wb_dati_10_6 "wb_dati_10[6]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_6))
+           (portRef D (instanceRef wb_dati_6))
+          ))
+          (net (rename wb_adr_10_2 "wb_adr_10[2]") (joined
+           (portRef Z (instanceRef wb_adr_10_2))
+           (portRef D (instanceRef wb_adr_2))
+          ))
+          (net (rename wb_adr_10_3 "wb_adr_10[3]") (joined
+           (portRef Z (instanceRef wb_adr_10_3))
+           (portRef D (instanceRef wb_adr_3))
+          ))
+          (net (rename wb_adr_10_7 "wb_adr_10[7]") (joined
+           (portRef Z (instanceRef wb_adr_10_7))
+           (portRef D (instanceRef wb_adr_7))
           ))
           (net RCKEEN_8_u_0_0 (joined
            (portRef Z (instanceRef RCKEEN_8_u_0_0))
            (portRef B (instanceRef RCKEEN_8_u))
           ))
-          (net UFMCLK_r_i_a2_2_2 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef D (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef UFMCLK_0io_RNO_1))
+          (net wb_we_0_0_2 (joined
+           (portRef Z (instanceRef wb_we_0_0_2))
+           (portRef C (instanceRef wb_we_0_0_3))
           ))
-          (net i1_i (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO))
-           (portRef D (instanceRef UFMCLK_0io))
+          (net (rename wb_adr_10_0_5_tz_0 "wb_adr_10_0_5_tz[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_5_tz_0))
+           (portRef D (instanceRef wb_adr_10_0_0))
           ))
-          (net UFMSDI_ens2_i_a0 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
-           (portRef A (instanceRef UFMSDI_RNO_0))
-          ))
-          (net nUFMCS_s_0_m4_yy (joined
-           (portRef Z (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
-          ))
-          (net N_27_i_1 (joined
+          (net N_32_i_1 (joined
            (portRef Z (instanceRef nRCAS_r_i_a3_1_1_tz))
-           (portRef B (instanceRef nRCS_0io_RNO))
            (portRef A (instanceRef nRCAS_0io_RNO))
+           (portRef B (instanceRef nRCS_0io_RNO))
           ))
-          (net CmdLEDEN_4_u_i_a2_0_0 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+          (net CmdLEDEN_4_u_i_a4_0_0 (joined
+           (portRef Z (instanceRef CmdLEDEN_4_u_i_a4_0_0))
            (portRef B (instanceRef CmdLEDEN_4_u_i_0))
            (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
           ))
-          (net CmdEnable16_0_a2_0 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2))
+          (net wb_we_0_0_a4_0_0 (joined
+           (portRef Z (instanceRef wb_we_0_0_a4_0_0))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_a2_2))
+           (portRef A (instanceRef wb_we_0_0_1_RNO))
+          ))
+          (net nRCS_9_u_i_0 (joined
+           (portRef Z (instanceRef nRCS_9_u_i_0))
+           (portRef C (instanceRef nRCS_0io_RNO_0))
+          ))
+          (net wb_we_0_0_a4_6_0 (joined
+           (portRef Z (instanceRef wb_adr_10_0_a2_RNIQ1AL_1))
+           (portRef D (instanceRef wb_we_0_0_2))
+           (portRef D (instanceRef wb_dati_10_0_iv_0_0_0))
           ))
           (net nCRAS_c_i (joined
            (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
            (portRef CK (instanceRef CBR))
+           (portRef CK (instanceRef CBR_fast))
            (portRef CK (instanceRef FWEr))
+           (portRef CK (instanceRef FWEr_fast))
            (portRef CK (instanceRef RowA_9))
            (portRef CK (instanceRef RowA_8))
            (portRef CK (instanceRef RowA_7))
@@ -1762,12 +3029,6 @@
            (portRef SCLK (instanceRef RBA_0io_1))
            (portRef SCLK (instanceRef RBA_0io_0))
           ))
-          (net N_188_i (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef SP (instanceRef IS_3))
-           (portRef SP (instanceRef IS_2))
-           (portRef SP (instanceRef IS_1))
-          ))
           (net RD_1_i (joined
            (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
            (portRef T (instanceRef RD_pad_0))
@@ -1779,68 +3040,89 @@
            (portRef T (instanceRef RD_pad_6))
            (portRef T (instanceRef RD_pad_7))
           ))
-          (net N_27_i (joined
-           (portRef Z (instanceRef nRCS_0io_RNO))
-           (portRef D (instanceRef nRCS_0io))
+          (net N_193_i (joined
+           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
+           (portRef SP (instanceRef IS_3))
+           (portRef SP (instanceRef IS_2))
+           (portRef SP (instanceRef IS_1))
           ))
-          (net N_179_i (joined
-           (portRef Z (instanceRef nRCAS_0io_RNO))
-           (portRef D (instanceRef nRCAS_0io))
-          ))
-          (net N_24_i (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0_RNILD5I))
+          (net N_29_i (joined
+           (portRef Z (instanceRef nRCS_9_u_i_0_0_RNIOMAB))
            (portRef A (instanceRef nRCS_0io_RNO))
            (portRef D (instanceRef nRRAS_0io))
           ))
-          (net nUFMCS_s_0_N_5_i (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef D (instanceRef nUFMCS))
+          (net N_32_i (joined
+           (portRef Z (instanceRef nRCS_0io_RNO))
+           (portRef D (instanceRef nRCS_0io))
           ))
-          (net N_180_i (joined
+          (net N_186_i (joined
+           (portRef Z (instanceRef nRCAS_0io_RNO))
+           (portRef D (instanceRef nRCAS_0io))
+          ))
+          (net N_44_i (joined
            (portRef Z (instanceRef nRWE_0io_RNO))
            (portRef D (instanceRef nRWE_0io))
           ))
-          (net N_60_i_i (joined
+          (net N_71_i_i (joined
            (portRef Z (instanceRef IS_RNO_0))
            (portRef D (instanceRef IS_0))
           ))
-          (net N_58_i_i (joined
+          (net N_69_i_i (joined
            (portRef Z (instanceRef IS_RNO_3))
            (portRef D (instanceRef IS_3))
           ))
-          (net N_57_i_i (joined
+          (net N_66_i_i (joined
            (portRef Z (instanceRef IS_RNO_2))
            (portRef D (instanceRef IS_2))
           ))
-          (net N_203_i (joined
+          (net N_95_i (joined
            (portRef Z (instanceRef S_RNO_0))
            (portRef D (instanceRef S_0))
           ))
-          (net N_14_i (joined
+          (net N_86_i (joined
+           (portRef Z (instanceRef wb_clk_RNO))
+           (portRef D (instanceRef wb_clk))
+          ))
+          (net N_245_i (joined
+           (portRef Z (instanceRef wb_clk_RNO_0))
+           (portRef SP (instanceRef wb_clk))
+          ))
+          (net un1_wb_clk32_i (joined
+           (portRef Z (instanceRef CMDUFMWrite_RNIHQ1E1))
+           (portRef SP (instanceRef wb_adr_7))
+           (portRef SP (instanceRef wb_adr_6))
+           (portRef SP (instanceRef wb_adr_5))
+           (portRef SP (instanceRef wb_adr_4))
+           (portRef SP (instanceRef wb_adr_3))
+           (portRef SP (instanceRef wb_adr_2))
+           (portRef SP (instanceRef wb_adr_1))
+           (portRef SP (instanceRef wb_adr_0))
+           (portRef SP (instanceRef wb_cyc_stb))
+           (portRef SP (instanceRef wb_dati_7))
+           (portRef SP (instanceRef wb_dati_6))
+           (portRef SP (instanceRef wb_dati_5))
+           (portRef SP (instanceRef wb_dati_4))
+           (portRef SP (instanceRef wb_dati_3))
+           (portRef SP (instanceRef wb_dati_2))
+           (portRef SP (instanceRef wb_dati_1))
+           (portRef SP (instanceRef wb_dati_0))
+           (portRef SP (instanceRef wb_we))
+          ))
+          (net N_72_i (joined
            (portRef Z (instanceRef CmdLEDEN_RNO))
            (portRef D (instanceRef CmdLEDEN))
           ))
-          (net N_12_i (joined
+          (net N_210_i (joined
            (portRef Z (instanceRef Cmdn8MEGEN_RNO))
            (portRef D (instanceRef Cmdn8MEGEN))
           ))
-          (net N_74_i (joined
-           (portRef Z (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef LEDEN))
-          ))
           (net un1_CmdEnable20_i (joined
            (portRef Z (instanceRef CmdEnable_s_RNO))
            (portRef C (instanceRef CmdEnable_s))
           ))
-          (net N_141_i (joined
-           (portRef Z (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef UFMCLK_0io_RNO_0))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef C0 (instanceRef UFMSDI_RNO))
-          ))
-          (net i2_i (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO_0))
-           (portRef SP (instanceRef UFMCLK_0io))
+          (net N_209_i (joined
+           (portRef Z (instanceRef ADSubmitted_r_0_RNO))
+           (portRef B (instanceRef ADSubmitted_r_0))
           ))
           (net (rename FS_cry_0 "FS_cry[0]") (joined
            (portRef COUT (instanceRef FS_cry_0_0))
@@ -1956,8 +3238,8 @@
           ))
           (net un1_PHI2r3_0 (joined
            (portRef Z (instanceRef un1_PHI2r3_0))
-           (portRef D (instanceRef un1_FS_13_i_0))
-           (portRef D (instanceRef un1_FS_14_i_0))
+           (portRef D (instanceRef un1_FS_7_i_0))
+           (portRef B (instanceRef wb_clk_RNO_1))
           ))
           (net Cmdn8MEGEN_4_u_i_0 (joined
            (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
@@ -1967,76 +3249,129 @@
            (portRef Z (instanceRef CmdLEDEN_4_u_i_0))
            (portRef A (instanceRef CmdLEDEN_RNO))
           ))
-          (net d_m3_0_a2_0 (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO_1))
-           (portRef D (instanceRef UFMCLK_0io_RNO))
+          (net wb_clk_9_iv_i_o2_2 (joined
+           (portRef Z (instanceRef wb_clk_9_iv_i_o2_2))
+           (portRef B (instanceRef wb_rst_3_0_a2))
+           (portRef C (instanceRef wb_clk_9_iv_i_o2))
+           (portRef B (instanceRef wb_clk_9_iv_i_o2_2_RNIOE4Q))
           ))
-          (net XOR8MEG_3_u_0_a2_0_2 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0_2))
+          (net wb_we_0_0_a4_0_0_1 (joined
+           (portRef Z (instanceRef wb_we_0_0_a4_0_0_1))
+           (portRef D (instanceRef wb_we_0_0_a4_0_0))
+          ))
+          (net XOR8MEG_3_u_0_a4_0_2 (joined
+           (portRef Z (instanceRef XOR8MEG_3_u_0_a4_0_2))
            (portRef D (instanceRef XOR8MEG_3_u_0_0))
           ))
-          (net UFMSDI_ens2_i_o2_0_3 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
           (net Ready_0_sqmuxa_0_a3_2 (joined
            (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
            (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
            (portRef B (instanceRef Ready_RNO))
           ))
-          (net C1WR_7_0_o3_0 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_0))
-           (portRef C (instanceRef C1WR_7_0_o3_6))
+          (net InitReady3_0_a4_2 (joined
+           (portRef Z (instanceRef InitReady3_0_a4_2))
+           (portRef C (instanceRef InitReady3_0_a4))
           ))
-          (net C1WR_7_0_o3_6 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_6))
-           (portRef C (instanceRef C1WR_7_0_o3))
+          (net un1_ADWR_i_o4_3 (joined
+           (portRef Z (instanceRef un1_ADWR_i_o4_3))
+           (portRef C (instanceRef un1_ADWR_i_o4_10))
           ))
-          (net C1WR_7_0_o3_7 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_7))
-           (portRef D (instanceRef C1WR_7_0_o3))
+          (net un1_ADWR_i_o4_4 (joined
+           (portRef Z (instanceRef un1_ADWR_i_o4_4))
+           (portRef D (instanceRef un1_ADWR_i_o4_10))
           ))
-          (net nRWE_s_i_tz_0 (joined
-           (portRef Z (instanceRef nRWE_s_i_tz_0))
-           (portRef D (instanceRef nRWE_0io_RNO))
+          (net un1_ADWR_i_o4_10 (joined
+           (portRef Z (instanceRef un1_ADWR_i_o4_10))
+           (portRef C (instanceRef un1_ADWR_i_o4))
           ))
-          (net UFMSDI_ens2_i_a2_4_2 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef UFMSDI_ens2_i_a0))
+          (net un1_ADWR_i_o4_11 (joined
+           (portRef Z (instanceRef un1_ADWR_i_o4_11))
+           (portRef D (instanceRef un1_ADWR_i_o4))
           ))
-          (net nRRAS_5_u_i_0 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0))
-           (portRef A (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef D (instanceRef nRRAS_5_u_i))
+          (net nRCS_9_u_i_0_0 (joined
+           (portRef Z (instanceRef nRCS_9_u_i_0_0))
+           (portRef A (instanceRef nRCS_9_u_i_0_0_RNIOMAB))
+           (portRef D (instanceRef nRCS_9_u_i_0))
           ))
-          (net un1_CmdEnable20_0_o3_0_1 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_o3_0_1))
-           (portRef D (instanceRef un1_CmdEnable20_0_o3_0))
+          (net (rename wb_dati_10_1_iv_0_a4_1_7 "wb_dati_10_1_iv_0_a4_1[7]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_1_0_7))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_0_7))
           ))
-          (net CMDWR_2 (joined
-           (portRef Z (instanceRef CMDWR_2))
-           (portRef A (instanceRef CMDWR))
+          (net wb_cyc_stb_65_0_iv_0_o2_0 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_o2_0_0))
+           (portRef C (instanceRef wb_cyc_stb_65_0_iv_0_a2))
           ))
-          (net un1_FS_13_i_a2_1 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_1))
-           (portRef C (instanceRef un1_FS_13_i_a2))
+          (net wb_cyc_stb_65_0_iv_0_o2_2 (joined
+           (portRef Z (instanceRef wb_cyc_stb_65_0_iv_0_o2_2_0))
+           (portRef D (instanceRef wb_cyc_stb_65_0_iv_0_a2))
           ))
-          (net un1_FS_14_i_a2_0_1 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_14_i_a2_0))
+          (net (rename wb_adr_10_0_a4_0_0 "wb_adr_10_0_a4_0[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_a4_0_0_0))
+           (portRef D (instanceRef wb_adr_10_0_4_0))
           ))
-          (net un1_CmdEnable20_0_a2_0_0 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_a2_0_0))
-           (portRef D (instanceRef CmdEnable_s_RNO))
+          (net (rename wb_dati_10_1_iv_0_a4_1_0_0_3 "wb_dati_10_1_iv_0_a4_1_0_0[3]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_1_0_0_3))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_a4_1_3))
           ))
-          (net CmdEnable17_0_a2_0 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef A (instanceRef CmdEnable17_0_a2))
+          (net (rename wb_dati_10_1_iv_0_a4_1_1 "wb_dati_10_1_iv_0_a4_1[1]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_1_1))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_1))
           ))
-          (net CmdEnable17_0_a2_1 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef B (instanceRef CmdEnable17_0_a2))
+          (net (rename wb_dati_10_1_iv_0_a4_0_4 "wb_dati_10_1_iv_0_a4_0[4]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_0_0_4))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_4))
+          ))
+          (net (rename wb_dati_10_1_iv_0_a4_0_6 "wb_dati_10_1_iv_0_a4_0[6]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_a4_0_1_6))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_1_6))
+          ))
+          (net (rename wb_dati_10_1_iv_0_0_7 "wb_dati_10_1_iv_0_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_0_7))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_1_7))
+          ))
+          (net (rename wb_dati_10_1_iv_0_1_7 "wb_dati_10_1_iv_0_1[7]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_1_7))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_7))
+          ))
+          (net (rename wb_dati_10_0_iv_0_0_0 "wb_dati_10_0_iv_0_0[0]") (joined
+           (portRef Z (instanceRef wb_dati_10_0_iv_0_0_0))
+           (portRef D (instanceRef wb_dati_10_0_iv_0_0))
+          ))
+          (net un1_FS_7_i_a4_0_0 (joined
+           (portRef Z (instanceRef un1_FS_7_i_a4_0_0))
+           (portRef D (instanceRef un1_FS_7_i_a4_0_3))
+          ))
+          (net un1_FS_7_i_a4_0_3 (joined
+           (portRef Z (instanceRef un1_FS_7_i_a4_0_3))
+           (portRef D (instanceRef un1_FS_7_i_a4_0))
+          ))
+          (net wb_we_0_0_1 (joined
+           (portRef Z (instanceRef wb_we_0_0_1))
+           (portRef B (instanceRef wb_we_0_0_3))
+          ))
+          (net wb_we_0_0_3 (joined
+           (portRef Z (instanceRef wb_we_0_0_3))
+           (portRef C (instanceRef wb_we_0_0))
+          ))
+          (net wb_we_0_0_5 (joined
+           (portRef Z (instanceRef wb_we_0_0_5))
+           (portRef D (instanceRef wb_we_0_0))
+          ))
+          (net (rename wb_dati_10_1_iv_0_1_4 "wb_dati_10_1_iv_0_1[4]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_1_4))
+           (portRef C (instanceRef wb_dati_10_1_iv_0_4))
+          ))
+          (net (rename wb_adr_10_0_1_0 "wb_adr_10_0_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_1_0))
+           (portRef D (instanceRef wb_adr_10_0_3_0))
+          ))
+          (net (rename wb_adr_10_0_3_0 "wb_adr_10_0_3[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_3_0))
+           (portRef B (instanceRef wb_adr_10_0_0))
+          ))
+          (net (rename wb_adr_10_0_4_0 "wb_adr_10_0_4[0]") (joined
+           (portRef Z (instanceRef wb_adr_10_0_4_0))
+           (portRef C (instanceRef wb_adr_10_0_0))
           ))
           (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined
            (portRef S0 (instanceRef FS_cry_0_0))
@@ -2047,10 +3382,22 @@
           (net (rename FS_s_0_COUT_17 "FS_s_0_COUT[17]") (joined
            (portRef COUT (instanceRef FS_s_0_17))
           ))
+          (net (rename wb_dati_10_1_iv_0_o2_1_5 "wb_dati_10_1_iv_0_o2_1[5]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_o2_1_5))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_o2_5))
+          ))
           (net RCKEEN_8_u_1_0 (joined
            (portRef Z (instanceRef RCKEEN_8_u_1_0))
            (portRef C (instanceRef RCKEEN_8_u))
           ))
+          (net (rename wb_dati_10_1_iv_0_1_6 "wb_dati_10_1_iv_0_1[6]") (joined
+           (portRef Z (instanceRef wb_dati_10_1_iv_0_1_6))
+           (portRef D (instanceRef wb_dati_10_1_iv_0_6))
+          ))
+          (net un1_CmdEnable20_i_1 (joined
+           (portRef Z (instanceRef CmdEnable_s_RNO_0))
+           (portRef D (instanceRef CmdEnable_s_RNO))
+          ))
           (net (rename RowAd_0_3 "RowAd_0[3]") (joined
            (portRef Z (instanceRef RowAd_3))
            (portRef D (instanceRef RowA_3))
@@ -2103,6 +3450,15 @@
            (portRef Z (instanceRef RA11d))
            (portRef D (instanceRef RA11_0io))
           ))
+          (net G_8_0_a3_0_0 (joined
+           (portRef Z (instanceRef PHI2r3_RNIFT0I))
+           (portRef C (instanceRef CMDUFMWrite_RNIHQ1E1))
+          ))
+          (net CmdSubmitted_fast (joined
+           (portRef Q (instanceRef CmdSubmitted_fast))
+           (portRef B (instanceRef CMDUFMWrite_RNIHQ1E1))
+           (portRef B (instanceRef CmdSubmitted_fast_RNO))
+          ))
           (net Ready_fast (joined
            (portRef Q (instanceRef Ready_fast))
            (portRef B (instanceRef RBAd_0))
@@ -2120,32 +3476,54 @@
            (portRef B (instanceRef RA11d))
            (portRef B (instanceRef Ready_fast_RNO))
           ))
-          (net N_179_i_1 (joined
-           (portRef Z (instanceRef nRCAS_0io_RNO_0))
-           (portRef C (instanceRef nRCAS_0io_RNO))
+          (net CBR_fast (joined
+           (portRef Q (instanceRef CBR_fast))
+           (portRef A (instanceRef nRCS_0io_RNO_0))
+           (portRef A (instanceRef nRWE_0io_RNO_0))
+           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
           ))
-          (net nRWE_0io_RNO_0 (joined
-           (portRef Z (instanceRef nRWE_0io_RNO_0))
-           (portRef B (instanceRef nRWE_0io_RNO))
+          (net FWEr_fast (joined
+           (portRef Q (instanceRef FWEr_fast))
+           (portRef D (instanceRef nRCAS_r_i_a3_1_1_tz))
+          ))
+          (net nRWE_0io_RNO_4 (joined
+           (portRef Z (instanceRef nRWE_0io_RNO_4))
+           (portRef A (instanceRef nRWE_0io_RNO_2))
           ))
           (net nRWE_0io_RNO_1 (joined
            (portRef Z (instanceRef nRWE_0io_RNO_1))
-           (portRef C (instanceRef nRWE_0io_RNO))
+           (portRef B (instanceRef nRWE_0io_RNO))
           ))
-          (net N_27_i_sn (joined
+          (net nRWE_0io_RNO_2 (joined
+           (portRef Z (instanceRef nRWE_0io_RNO_2))
+           (portRef C (instanceRef nRWE_0io_RNO_0))
+          ))
+          (net nRWE_0io_RNO_3 (joined
+           (portRef Z (instanceRef nRWE_0io_RNO_3))
+           (portRef D (instanceRef nRWE_0io_RNO_0))
+          ))
+          (net N_44_i_1 (joined
+           (portRef Z (instanceRef nRWE_0io_RNO_0))
+           (portRef A (instanceRef nRWE_0io_RNO))
+          ))
+          (net N_32_i_sn (joined
            (portRef Z (instanceRef nRCS_0io_RNO_0))
            (portRef C (instanceRef nRCS_0io_RNO))
           ))
+          (net nRCAS_0io_RNO_0 (joined
+           (portRef Z (instanceRef nRCAS_0io_RNO_0))
+           (portRef C (instanceRef nRCAS_0io_RNO))
+          ))
           (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
            (portRef Z (instanceRef XOR8MEG_CN))
            (portRef CK (instanceRef ADSubmitted))
            (portRef CK (instanceRef C1Submitted))
+           (portRef CK (instanceRef CMDUFMWrite))
            (portRef CK (instanceRef CmdEnable))
            (portRef CK (instanceRef CmdLEDEN))
            (portRef CK (instanceRef CmdSubmitted))
-           (portRef CK (instanceRef CmdUFMCLK))
-           (portRef CK (instanceRef CmdUFMCS))
-           (portRef CK (instanceRef CmdUFMSDI))
+           (portRef CK (instanceRef CmdSubmitted_fast))
+           (portRef CK (instanceRef CmdUFMData))
            (portRef CK (instanceRef Cmdn8MEGEN))
            (portRef CK (instanceRef XOR8MEG))
           ))
@@ -2245,7 +3623,6 @@
            (portRef CD (instanceRef RA11_0io))
            (portRef CD (instanceRef RBA_0io_1))
            (portRef CD (instanceRef RBA_0io_0))
-           (portRef CD (instanceRef UFMCLK_0io))
            (portRef PD (instanceRef nRCAS_0io))
            (portRef PD (instanceRef nRCS_0io))
            (portRef PD (instanceRef nRRAS_0io))
@@ -2289,11 +3666,11 @@
           (net (rename MAin_c_0 "MAin_c[0]") (joined
            (portRef O (instanceRef MAin_pad_0))
            (portRef A (instanceRef RowAd_0))
-           (portRef A (instanceRef un9_RA_i_m3_0))
-           (portRef D (instanceRef CmdEnable16_0_a2_0))
-           (portRef D (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef B (instanceRef CMDWR))
-           (portRef C (instanceRef CmdEnable17_0_a2))
+           (portRef B (instanceRef CmdEnable_s_RNO_0))
+           (portRef A (instanceRef un9_RA_i_m2_0))
+           (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+           (portRef B (instanceRef XOR8MEG18_0_a2))
+           (portRef A (instanceRef CmdEnable17_0_a2))
           ))
           (net (rename MAin_0 "MAin[0]") (joined
            (portRef (member main 9))
@@ -2301,10 +3678,14 @@
           ))
           (net (rename MAin_c_1 "MAin_c[1]") (joined
            (portRef O (instanceRef MAin_pad_1))
+           (portRef D (instanceRef CmdEnable16_0_a4))
            (portRef A (instanceRef RowAd_1))
-           (portRef A (instanceRef un9_RA_i_m3_1))
-           (portRef A (instanceRef CMDWR_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_o3_0))
+           (portRef C (instanceRef CmdEnable_s_RNO_0))
+           (portRef A (instanceRef un9_RA_i_m2_1))
+           (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2))
+           (portRef C (instanceRef XOR8MEG18_0_a2))
+           (portRef A (instanceRef ADSubmitted_r_0_RNO))
+           (portRef D (instanceRef C1Submitted_RNO))
           ))
           (net (rename MAin_1 "MAin[1]") (joined
            (portRef (member main 8))
@@ -2313,9 +3694,8 @@
           (net (rename MAin_c_2 "MAin_c[2]") (joined
            (portRef O (instanceRef MAin_pad_2))
            (portRef A (instanceRef RowAd_2))
-           (portRef A (instanceRef un9_RA_i_m3_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef C (instanceRef CMDWR))
+           (portRef A (instanceRef un9_RA_i_m2_2))
+           (portRef A (instanceRef un1_ADWR_i_o4_4))
           ))
           (net (rename MAin_2 "MAin[2]") (joined
            (portRef (member main 7))
@@ -2324,9 +3704,8 @@
           (net (rename MAin_c_3 "MAin_c[3]") (joined
            (portRef O (instanceRef MAin_pad_3))
            (portRef A (instanceRef RowAd_3))
-           (portRef A (instanceRef un9_RA_i_m3_3))
-           (portRef B (instanceRef CMDWR_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_o3_0_1))
+           (portRef A (instanceRef un9_RA_i_m2_3))
+           (portRef B (instanceRef un1_ADWR_i_o4_4))
           ))
           (net (rename MAin_3 "MAin[3]") (joined
            (portRef (member main 6))
@@ -2335,9 +3714,8 @@
           (net (rename MAin_c_4 "MAin_c[4]") (joined
            (portRef O (instanceRef MAin_pad_4))
            (portRef A (instanceRef RowAd_4))
-           (portRef A (instanceRef un9_RA_i_m3_4))
-           (portRef C (instanceRef CMDWR_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_o3_0_1))
+           (portRef A (instanceRef un9_RA_i_m2_4))
+           (portRef A (instanceRef un1_ADWR_i_o4_3))
           ))
           (net (rename MAin_4 "MAin[4]") (joined
            (portRef (member main 5))
@@ -2346,8 +3724,8 @@
           (net (rename MAin_c_5 "MAin_c[5]") (joined
            (portRef O (instanceRef MAin_pad_5))
            (portRef A (instanceRef RowAd_5))
-           (portRef A (instanceRef C1WR_7_0_o3_0))
-           (portRef A (instanceRef un9_RA_i_m3_5))
+           (portRef A (instanceRef un9_RA_i_m2_5))
+           (portRef B (instanceRef un1_ADWR_i_o4_3))
           ))
           (net (rename MAin_5 "MAin[5]") (joined
            (portRef (member main 4))
@@ -2356,8 +3734,8 @@
           (net (rename MAin_c_6 "MAin_c[6]") (joined
            (portRef O (instanceRef MAin_pad_6))
            (portRef A (instanceRef RowAd_6))
-           (portRef A (instanceRef un9_RA_i_m3_6))
-           (portRef D (instanceRef C1WR_7_0_o3_6))
+           (portRef A (instanceRef un9_RA_i_m2_6))
+           (portRef C (instanceRef un1_ADWR_i_o4_4))
           ))
           (net (rename MAin_6 "MAin[6]") (joined
            (portRef (member main 3))
@@ -2366,8 +3744,8 @@
           (net (rename MAin_c_7 "MAin_c[7]") (joined
            (portRef O (instanceRef MAin_pad_7))
            (portRef A (instanceRef RowAd_7))
-           (portRef B (instanceRef C1WR_7_0_o3_0))
-           (portRef A (instanceRef un9_RA_i_m3_7))
+           (portRef A (instanceRef un9_RA_i_m2_7))
+           (portRef C (instanceRef un1_ADWR_i_o4_3))
           ))
           (net (rename MAin_7 "MAin[7]") (joined
            (portRef (member main 2))
@@ -2386,7 +3764,7 @@
            (portRef O (instanceRef MAin_pad_9))
            (portRef A (instanceRef RowAd_9))
            (portRef A (instanceRef RDQML_0))
-           (portRef A (instanceRef un9_RA_i_m3_9))
+           (portRef A (instanceRef un9_RA_i_m2_9))
            (portRef A (instanceRef RDQMH_pad_RNO))
           ))
           (net (rename MAin_9 "MAin[9]") (joined
@@ -2411,10 +3789,10 @@
           ))
           (net (rename Din_c_0 "Din_c[0]") (joined
            (portRef O (instanceRef Din_pad_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a2_0_2))
+           (portRef D (instanceRef un1_CmdEnable20_0_a2))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a2))
            (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
-           (portRef A (instanceRef CmdEnable17_0_a2_0))
-           (portRef D (instanceRef CmdUFMSDI))
+           (portRef D (instanceRef CmdUFMData))
            (portRef D (instanceRef Bank_0io_0))
            (portRef D (instanceRef WRD_0io_0))
           ))
@@ -2424,10 +3802,10 @@
           ))
           (net (rename Din_c_1 "Din_c[1]") (joined
            (portRef O (instanceRef Din_pad_1))
+           (portRef B (instanceRef un1_CmdEnable20_0_a2))
            (portRef C (instanceRef CmdLEDEN_4_u_i_0))
            (portRef A (instanceRef XOR8MEG_3_u_0_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_0))
-           (portRef D (instanceRef CmdUFMCLK))
+           (portRef D (instanceRef CMDUFMWrite))
            (portRef D (instanceRef Bank_0io_1))
            (portRef D (instanceRef WRD_0io_1))
           ))
@@ -2437,10 +3815,8 @@
           ))
           (net (rename Din_c_2 "Din_c[2]") (joined
            (portRef O (instanceRef Din_pad_2))
-           (portRef A (instanceRef CmdEnable17_0_a2_1))
-           (portRef A (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef D (instanceRef CmdUFMCS))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a2_0))
+           (portRef A (instanceRef un1_CmdEnable20_0_a2_0))
            (portRef D (instanceRef Bank_0io_2))
            (portRef D (instanceRef WRD_0io_2))
           ))
@@ -2450,13 +3826,12 @@
           ))
           (net (rename Din_c_3 "Din_c[3]") (joined
            (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef CmdEnable16_0_a2_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
+           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a4))
+           (portRef D (instanceRef CMDUFMWrite_1_sqmuxa_0_a4))
+           (portRef A (instanceRef CMDUFMWrite_1_sqmuxa_0_a2_0))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a4_0_2))
+           (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_o2))
            (portRef D (instanceRef Bank_0io_3))
            (portRef D (instanceRef WRD_0io_3))
           ))
@@ -2466,13 +3841,11 @@
           ))
           (net (rename Din_c_4 "Din_c[4]") (joined
            (portRef O (instanceRef Din_pad_4))
-           (portRef D (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef A (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef A (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_a2_0_0))
+           (portRef D (instanceRef CmdLEDEN_4_u_i_a4_0_0))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_o2_0))
+           (portRef C (instanceRef un1_CmdEnable20_0_a2))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a2))
+           (portRef A (instanceRef XOR8MEG_3_u_0_a4))
            (portRef D (instanceRef Bank_0io_4))
            (portRef D (instanceRef WRD_0io_4))
           ))
@@ -2482,16 +3855,13 @@
           ))
           (net (rename Din_c_5 "Din_c[5]") (joined
            (portRef O (instanceRef Din_pad_5))
-           (portRef C (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef C (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef B (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_a2_0_0))
+           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a4))
+           (portRef A (instanceRef CmdLEDEN_4_u_i_a4_0_0))
+           (portRef C (instanceRef CMDUFMWrite_1_sqmuxa_0_a4))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a2_0))
+           (portRef B (instanceRef CMDUFMWrite_1_sqmuxa_0_a2_0))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_o2))
+           (portRef B (instanceRef XOR8MEG_3_u_0_a4))
            (portRef D (instanceRef Bank_0io_5))
            (portRef D (instanceRef WRD_0io_5))
           ))
@@ -2501,13 +3871,12 @@
           ))
           (net (rename Din_c_6 "Din_c[6]") (joined
            (portRef O (instanceRef Din_pad_6))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_a4_0_0))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_o2_0))
            (portRef A (instanceRef RA11d))
-           (portRef B (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef C (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef C (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef C (instanceRef un1_CmdEnable20_0_a2_1))
+           (portRef A (instanceRef XOR8MEG_3_u_0_o2_1))
+           (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2_0))
+           (portRef B (instanceRef un1_CmdEnable20_0_a2_0))
            (portRef D (instanceRef Bank_0io_6))
            (portRef D (instanceRef WRD_0io_6))
           ))
@@ -2517,10 +3886,10 @@
           ))
           (net (rename Din_c_7 "Din_c[7]") (joined
            (portRef O (instanceRef Din_pad_7))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef C (instanceRef CmdEnable17_0_a2_0))
+           (portRef C (instanceRef CmdLEDEN_4_u_i_a4_0_0))
+           (portRef B (instanceRef CmdLEDEN_4_u_i_o2_0))
+           (portRef A (instanceRef un1_CmdEnable20_0_a2))
+           (portRef B (instanceRef XOR8MEG_3_u_0_o2_1))
            (portRef D (instanceRef Bank_0io_7))
            (portRef D (instanceRef WRD_0io_7))
           ))
@@ -2581,10 +3950,9 @@
           ))
           (net nFWE_c (joined
            (portRef O (instanceRef nFWE_pad))
-           (portRef D (instanceRef CMDWR_2))
-           (portRef C (instanceRef un1_CmdEnable20_0_o3_0_1))
+           (portRef D (instanceRef un1_ADWR_i_o4_4))
            (portRef B (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef FWEr_RNO))
+           (portRef A (instanceRef nFWE_pad_RNI420B))
           ))
           (net nFWE (joined
            (portRef nFWE)
@@ -2615,7 +3983,7 @@
            (portRef (member rba 0))
           ))
           (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_0))
+           (portRef Z (instanceRef un9_RA_i_m2_0))
            (portRef I (instanceRef RA_pad_0))
           ))
           (net (rename RA_0 "RA[0]") (joined
@@ -2623,7 +3991,7 @@
            (portRef (member ra 11))
           ))
           (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_1))
+           (portRef Z (instanceRef un9_RA_i_m2_1))
            (portRef I (instanceRef RA_pad_1))
           ))
           (net (rename RA_1 "RA[1]") (joined
@@ -2631,7 +3999,7 @@
            (portRef (member ra 10))
           ))
           (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_2))
+           (portRef Z (instanceRef un9_RA_i_m2_2))
            (portRef I (instanceRef RA_pad_2))
           ))
           (net (rename RA_2 "RA[2]") (joined
@@ -2639,7 +4007,7 @@
            (portRef (member ra 9))
           ))
           (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_3))
+           (portRef Z (instanceRef un9_RA_i_m2_3))
            (portRef I (instanceRef RA_pad_3))
           ))
           (net (rename RA_3 "RA[3]") (joined
@@ -2647,7 +4015,7 @@
            (portRef (member ra 8))
           ))
           (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_4))
+           (portRef Z (instanceRef un9_RA_i_m2_4))
            (portRef I (instanceRef RA_pad_4))
           ))
           (net (rename RA_4 "RA[4]") (joined
@@ -2655,7 +4023,7 @@
            (portRef (member ra 7))
           ))
           (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_5))
+           (portRef Z (instanceRef un9_RA_i_m2_5))
            (portRef I (instanceRef RA_pad_5))
           ))
           (net (rename RA_5 "RA[5]") (joined
@@ -2663,7 +4031,7 @@
            (portRef (member ra 6))
           ))
           (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_6))
+           (portRef Z (instanceRef un9_RA_i_m2_6))
            (portRef I (instanceRef RA_pad_6))
           ))
           (net (rename RA_6 "RA[6]") (joined
@@ -2671,7 +4039,7 @@
            (portRef (member ra 5))
           ))
           (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_7))
+           (portRef Z (instanceRef un9_RA_i_m2_7))
            (portRef I (instanceRef RA_pad_7))
           ))
           (net (rename RA_7 "RA[7]") (joined
@@ -2687,7 +4055,7 @@
            (portRef (member ra 3))
           ))
           (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_9))
+           (portRef Z (instanceRef un9_RA_i_m2_9))
            (portRef I (instanceRef RA_pad_9))
           ))
           (net (rename RA_9 "RA[9]") (joined
@@ -2822,12 +4190,29 @@
            (portRef CK (instanceRef Ready_fast))
            (portRef CK (instanceRef S_1))
            (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef UFMSDI))
            (portRef CK (instanceRef n8MEGEN))
            (portRef CK (instanceRef nRowColSel))
-           (portRef CK (instanceRef nUFMCS))
+           (portRef CK (instanceRef wb_adr_7))
+           (portRef CK (instanceRef wb_adr_6))
+           (portRef CK (instanceRef wb_adr_5))
+           (portRef CK (instanceRef wb_adr_4))
+           (portRef CK (instanceRef wb_adr_3))
+           (portRef CK (instanceRef wb_adr_2))
+           (portRef CK (instanceRef wb_adr_1))
+           (portRef CK (instanceRef wb_adr_0))
+           (portRef CK (instanceRef wb_clk))
+           (portRef CK (instanceRef wb_cyc_stb))
+           (portRef CK (instanceRef wb_dati_7))
+           (portRef CK (instanceRef wb_dati_6))
+           (portRef CK (instanceRef wb_dati_5))
+           (portRef CK (instanceRef wb_dati_4))
+           (portRef CK (instanceRef wb_dati_3))
+           (portRef CK (instanceRef wb_dati_2))
+           (portRef CK (instanceRef wb_dati_1))
+           (portRef CK (instanceRef wb_dati_0))
+           (portRef CK (instanceRef wb_rst))
+           (portRef CK (instanceRef wb_we))
            (portRef SCLK (instanceRef RA10_0io))
-           (portRef SCLK (instanceRef UFMCLK_0io))
            (portRef SCLK (instanceRef nRCAS_0io))
            (portRef SCLK (instanceRef nRCS_0io))
            (portRef SCLK (instanceRef nRRAS_0io))
@@ -2840,8 +4225,8 @@
           ))
           (net RCKE_c (joined
            (portRef Q (instanceRef RCKE))
-           (portRef C (instanceRef nRRAS_5_u_i_0))
-           (portRef B (instanceRef nRWE_s_i_tz_0))
+           (portRef B (instanceRef nRWE_0io_RNO_3))
+           (portRef C (instanceRef nRCS_9_u_i_0_0))
            (portRef I (instanceRef RCKE_pad))
           ))
           (net RCKE (joined
@@ -2888,59 +4273,30 @@
            (portRef O (instanceRef RDQML_pad))
            (portRef RDQML)
           ))
-          (net nUFMCS_c (joined
-           (portRef Q (instanceRef nUFMCS))
-           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef I (instanceRef nUFMCS_pad))
-          ))
-          (net nUFMCS (joined
-           (portRef O (instanceRef nUFMCS_pad))
-           (portRef nUFMCS)
-          ))
-          (net UFMCLK_c (joined
-           (portRef Q (instanceRef UFMCLK_0io))
-           (portRef I (instanceRef UFMCLK_pad))
-          ))
-          (net UFMCLK (joined
-           (portRef O (instanceRef UFMCLK_pad))
-           (portRef UFMCLK)
-          ))
-          (net UFMSDI_c (joined
-           (portRef Q (instanceRef UFMSDI))
-           (portRef I (instanceRef UFMSDI_pad))
-           (portRef A (instanceRef UFMSDI_RNO_1))
-          ))
-          (net UFMSDI (joined
-           (portRef O (instanceRef UFMSDI_pad))
-           (portRef UFMSDI)
-          ))
-          (net UFMSDO_c (joined
-           (portRef O (instanceRef UFMSDO_pad))
-           (portRef C (instanceRef n8MEGEN_5_i_m2))
-          ))
-          (net UFMSDO (joined
-           (portRef UFMSDO)
-           (portRef I (instanceRef UFMSDO_pad))
-          ))
-          (net N_415_0 (joined
+          (net N_545_0 (joined
            (portRef Z (instanceRef CmdSubmitted_RNO))
            (portRef D (instanceRef CmdSubmitted))
           ))
-          (net N_416_0 (joined
+          (net N_548_0 (joined
+           (portRef Z (instanceRef CmdSubmitted_fast_RNO))
+           (portRef D (instanceRef CmdSubmitted_fast))
+          ))
+          (net N_546_0 (joined
            (portRef Z (instanceRef InitReady_RNO))
            (portRef D (instanceRef InitReady))
           ))
-          (net N_417_0 (joined
+          (net N_547_0 (joined
            (portRef Z (instanceRef Ready_RNO))
            (portRef D (instanceRef Ready))
           ))
-          (net N_418_0 (joined
+          (net N_549_0 (joined
            (portRef Z (instanceRef Ready_fast_RNO))
            (portRef D (instanceRef Ready_fast))
           ))
           (net nFWE_c_i (joined
-           (portRef Z (instanceRef FWEr_RNO))
+           (portRef Z (instanceRef nFWE_pad_RNI420B))
            (portRef D (instanceRef FWEr))
+           (portRef D (instanceRef FWEr_fast))
           ))
           (net nCRAS_c_i_0 (joined
            (portRef Z (instanceRef RASr_RNO))
@@ -2950,6 +4306,7 @@
            (portRef Z (instanceRef nCCAS_pad_RNISUR8))
            (portRef D (instanceRef CASr))
            (portRef D (instanceRef CBR))
+           (portRef D (instanceRef CBR_fast))
            (portRef SCLK (instanceRef WRD_0io_7))
            (portRef SCLK (instanceRef WRD_0io_6))
            (portRef SCLK (instanceRef WRD_0io_5))
@@ -2968,13 +4325,17 @@
            (portRef CD (instanceRef S_1))
            (portRef CD (instanceRef S_0))
           ))
-          (net UFMSDI_RNO_1 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_1))
-           (portRef BLUT (instanceRef UFMSDI_RNO))
+          (net InitReady_i (joined
+           (portRef Z (instanceRef wb_rst_RNO_0))
+           (portRef SP (instanceRef wb_rst))
           ))
-          (net UFMSDI_RNO_0 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_0))
-           (portRef ALUT (instanceRef UFMSDI_RNO))
+          (net wb_clk_RNO_2 (joined
+           (portRef Z (instanceRef wb_clk_RNO_2))
+           (portRef BLUT (instanceRef wb_clk_RNO))
+          ))
+          (net wb_clk_RNO_1 (joined
+           (portRef Z (instanceRef wb_clk_RNO_1))
+           (portRef ALUT (instanceRef wb_clk_RNO))
           ))
           (net N_1 (joined
            (portRef CIN (instanceRef FS_cry_0_0))
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.fse b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.fse
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.fse
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.fse
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm
new file mode 100644
index 0000000..c6b7d36
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm
@@ -0,0 +1,9 @@
+
+ 
+ syntmp/LCMXO2_640HC_impl1_srr.htm log file
+ 
+ 
+ 
+ 				 
+
+ 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
similarity index 74%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
index bf90645..5236a9c 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
@@ -2,18 +2,14 @@
 NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
 NOTE All Rights Reserved.*
-NOTE DATE CREATED:	Tue Aug 15 23:30:12 2023*
-NOTE DESIGN NAME:	RAM2GS_LCMXO2_640HC_impl1.ncd*
+NOTE DATE CREATED:	Wed Aug 16 20:59:44 2023*
+NOTE DESIGN NAME:	LCMXO2_640HC_impl1.ncd*
 NOTE DEVICE NAME:	LCMXO2-640HC-4TQFP100*
 NOTE JEDEC FILE STATUS:	Final   Version 1.95*
 NOTE PIN ASSIGNMENTS*
 NOTE PINS RD[0] : 36 : inout*
 NOTE PINS Dout[0] : 76 : out*
 NOTE PINS PHI2 : 8 : in*
-NOTE PINS UFMSDO : 27 : in*
-NOTE PINS UFMSDI : 29 : out*
-NOTE PINS UFMCLK : 28 : out*
-NOTE PINS nUFMCS : 30 : out*
 NOTE PINS RDQML : 48 : out*
 NOTE PINS RDQMH : 51 : out*
 NOTE PINS nRCAS : 52 : out*
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diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.log
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp
similarity index 58%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp
index d92d1b7..f3b47ce 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp
@@ -6,37 +6,36 @@ Design Information
 ------------------
 
 Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
-     -ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd
-     -pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:
-     /OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640
-     HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-
-     640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+     LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
+     LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
+     s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
+     -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
+     -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO2-640HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  23:30:05
+Mapped on:  08/16/23  20:59:36
 
 Design Summary
 --------------
 
-   Number of registers:     93 out of   877 (11%)
-      PFU registers:           64 out of   640 (10%)
-      PIO registers:           29 out of   237 (12%)
-   Number of SLICEs:        81 out of   320 (25%)
-      SLICEs as Logic/ROM:     81 out of   320 (25%)
+   Number of registers:    109 out of   877 (12%)
+      PFU registers:           84 out of   640 (13%)
+      PIO registers:           25 out of   237 (11%)
+   Number of SLICEs:       117 out of   320 (37%)
+      SLICEs as Logic/ROM:    117 out of   320 (37%)
       SLICEs as RAM:            0 out of   240 (0%)
       SLICEs as Carry:         10 out of   320 (3%)
-   Number of LUT4s:        159 out of   640 (25%)
-      Number used as logic LUTs:        139
+   Number of LUT4s:        230 out of   640 (36%)
+      Number used as logic LUTs:        210
       Number used as distributed RAM:     0
       Number used as ripple logic:       20
       Number used as shift registers:     0
-   Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
    Number of block RAMs:  0 out of 2 (0%)
    Number of GSRs:        0 out of 1 (0%)
-   EFB used :        No
+   EFB used :        Yes
    JTAG used :       No
    Readback used :   No
    Oscillator used : No
@@ -52,67 +51,65 @@ Design Summary
      distributed RAMs) + 2*(Number of ripple logic)
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
+   Number of clocks:  5
+     Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
+     Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
+     Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
      Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  6
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net i2_i: 1 loads, 0 LSLICEs
+   Number of Clock Enables:  7
+     Net N_245_i: 1 loads, 1 LSLICEs
+     Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
 
                                     Page 1
 
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  23:30:05
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
 
 Design Summary (cont)
 ---------------------
-     Net N_26: 1 loads, 1 LSLICEs
-     Net N_28: 1 loads, 1 LSLICEs
-     Net N_188_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
-   Number of LSRs:  3
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
+     Net N_18: 2 loads, 2 LSLICEs
+     Net XOR8MEG18: 3 loads, 3 LSLICEs
+     Net N_193_i: 2 loads, 2 LSLICEs
+   Number of LSRs:  5
      Net RA10s_i: 1 loads, 0 LSLICEs
+     Net wb_clk23: 3 loads, 3 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
      Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
      Net RASr2: 2 loads, 2 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net InitReady: 17 loads
+     Net InitReady: 42 loads
+     Net FS[12]: 27 loads
+     Net FS[10]: 25 loads
+     Net FS[11]: 22 loads
+     Net FS[7]: 17 loads
+     Net FS[6]: 16 loads
      Net Ready: 15 loads
      Net Ready_fast: 14 loads
-     Net Din_c[5]: 12 loads
      Net nRowColSel: 12 loads
      Net S[1]: 12 loads
-     Net RASr2: 10 loads
-     Net CO0: 9 loads
-     Net Din_c[3]: 9 loads
-     Net Din_c[4]: 9 loads
 
 
 
 
-   Number of warnings:  6
+   Number of warnings:  1
    Number of errors:    0
      
 
 Design Errors/Warnings
 ----------------------
 
-WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad.
-WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad.
-WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad.
-WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
-WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
-WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
+WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+     temporarily disable certain features of the device including Power
+     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
+     Functionality is restored after the Flash Memory (UFM/Configuration)
+     Interface is disabled using Disable Configuration Interface command 0x26
+     followed by Bypass command 0xFF. 
 
 IO (PIO) Attributes
 -------------------
@@ -126,27 +123,19 @@ IO (PIO) Attributes
 | Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI2                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
 
                                     Page 2
 
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  23:30:05
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
 
 IO (PIO) Attributes (cont)
 --------------------------
-+---------------------+-----------+-----------+------------+
-| UFMSDO              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| UFMSDI              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| UFMCLK              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nUFMCS              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RDQML               | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
 | RDQMH               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | nRCAS               | OUTPUT    | LVCMOS33  | OUT        |
@@ -155,7 +144,7 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | nRWE                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RCKE                | OUTPUT    | LVCMOS33  | OUT        |
+| RCKE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RCLK                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -192,16 +181,6 @@ IO (PIO) Attributes (cont)
 | RA[4]               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RA[3]               | OUTPUT    | LVCMOS33  |            |
-
-                                    Page 3
-
-
-
-
-Design:  RAM2GS                                        Date:  08/15/23  23:30:05
-
-IO (PIO) Attributes (cont)
---------------------------
 +---------------------+-----------+-----------+------------+
 | RA[2]               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -213,6 +192,16 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | RBA[0]              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
+
+IO (PIO) Attributes (cont)
+--------------------------
 | LED                 | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | nFWE                | INPUT     | LVCMOS33  |            |
@@ -258,16 +247,6 @@ IO (PIO) Attributes (cont)
 | MAin[9]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | MAin[8]             | INPUT     | LVCMOS33  |            |
-
-                                    Page 4
-
-
-
-
-Design:  RAM2GS                                        Date:  08/15/23  23:30:05
-
-IO (PIO) Attributes (cont)
---------------------------
 +---------------------+-----------+-----------+------------+
 | MAin[7]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -279,6 +258,16 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | MAin[3]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
+
+IO (PIO) Attributes (cont)
+--------------------------
 | MAin[2]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | MAin[1]             | INPUT     | LVCMOS33  |            |
@@ -292,25 +281,151 @@ Removed logic
 Block GSR_INST undriven or does not drive anything - clipped.
 Signal nCRAS_c_i was merged into signal nCRAS_c
 Signal RASr2_i was merged into signal RASr2
+Signal InitReady_i was merged into signal InitReady
 Signal XOR8MEG.CN was merged into signal PHI2_c
 Signal GND undriven or does not drive anything - clipped.
+Signal ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
+Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
+Signal ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+
+                                    Page 5
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
+
+Removed logic (cont)
+--------------------
+Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
 Block nCRAS_pad_RNIBPVB was optimized away.
 Block RASr2_RNIAFR1 was optimized away.
+Block wb_rst_RNO_0 was optimized away.
 Block XOR8MEG.CN was optimized away.
 Block GND was optimized away.
+Block ufmefb/VCC was optimized away.
+Block ufmefb/GND was optimized away.
 
      
 
+Embedded Functional Block Connection Summary
+--------------------------------------------
+
+   Desired WISHBONE clock frequency: 62.5 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            WB
+      UFM Connection:                ENABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+
+                                    Page 6
+
+
+
+
+Design:  RAM2GS                                        Date:  08/16/23  20:59:36
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Initialized UFM Pages:  1 Pages (1*128 Bits)
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb/EFBInst_0
+         Type: EFB
+
 Run Time and Memory Usage
 -------------------------
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 36 MB
+   Peak Memory Usage: 37 MB
         
 
 
@@ -325,7 +440,24 @@ Run Time and Memory Usage
 
 
 
-                                    Page 5
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 7
 
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ncd
new file mode 100644
index 0000000..cdfbb0f
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ncd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngd
new file mode 100644
index 0000000..6da6705
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngo b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngo
new file mode 100644
index 0000000..3c49ac6
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngo differ
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p3t b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p3t
new file mode 100644
index 0000000..991bdc8
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "LCMXO2_640HC_impl1.log"
+-o "LCMXO2_640HC_impl1.csv"
+-pr "LCMXO2_640HC_impl1.prf"
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad
similarity index 95%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad
index 380f4fc..ff49f3a 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.39
 
-Tue Aug 15 23:30:09 2023
+Wed Aug 16 20:59:41 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -68,9 +68,6 @@ Pinout by Port Name:
 | RD[5]     | 41/2     | LVCMOS33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[6]     | 42/2     | LVCMOS33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[7]     | 43/2     | LVCMOS33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| UFMCLK    | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDI    | 29/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDO    | 27/2     | LVCMOS33_IN   | PB4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
 | nCCAS     | 9/3      | LVCMOS33_IN   | PL3C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nCRAS     | 17/3     | LVCMOS33_IN   | PL6B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nFWE      | 15/3     | LVCMOS33_IN   | PL5D  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
@@ -78,7 +75,6 @@ Pinout by Port Name:
 | nRCS      | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRRAS     | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRWE      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| nUFMCS    | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -121,10 +117,10 @@ Pinout by Pin Number:
 | 21/3     | MAin[3]               | LOCATED    | LVCMOS33_IN   | PL7B  | PCLKC3_0      |           |           |
 | 24/3     | MAin[6]               | LOCATED    | LVCMOS33_IN   | PL7C  |               |           |           |
 | 25/3     | MAin[8]               | LOCATED    | LVCMOS33_IN   | PL7D  |               |           |           |
-| 27/2     | UFMSDO                | LOCATED    | LVCMOS33_IN   | PB4A  | CSSPIN        |           |           |
-| 28/2     | UFMCLK                | LOCATED    | LVCMOS33_OUT  | PB4B  |               |           |           |
-| 29/2     | UFMSDI                | LOCATED    | LVCMOS33_OUT  | PB4C  |               |           |           |
-| 30/2     | nUFMCS                | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |               | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
 | 31/2     |     unused, PULL:DOWN |            |               | PB6A  | MCLK/CCLK     |           |           |
 | 32/2     | MAin[9]               | LOCATED    | LVCMOS33_IN   | PB6B  | SO/SPISO      |           |           |
 | 34/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB6C  | PCLKT2_0      |           |           |
@@ -255,9 +251,6 @@ LOCATE  COMP  "RD[4]"  SITE  "40";
 LOCATE  COMP  "RD[5]"  SITE  "41";
 LOCATE  COMP  "RD[6]"  SITE  "42";
 LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "UFMCLK"  SITE  "28";
-LOCATE  COMP  "UFMSDI"  SITE  "29";
-LOCATE  COMP  "UFMSDO"  SITE  "27";
 LOCATE  COMP  "nCCAS"  SITE  "9";
 LOCATE  COMP  "nCRAS"  SITE  "17";
 LOCATE  COMP  "nFWE"  SITE  "15";
@@ -265,7 +258,6 @@ LOCATE  COMP  "nRCAS"  SITE  "52";
 LOCATE  COMP  "nRCS"  SITE  "57";
 LOCATE  COMP  "nRRAS"  SITE  "54";
 LOCATE  COMP  "nRWE"  SITE  "49";
-LOCATE  COMP  "nUFMCS"  SITE  "30";
 
 
 
@@ -277,5 +269,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:11 2023
+Wed Aug 16 20:59:42 2023
 
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par
similarity index 57%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.par
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par
index bd39bdc..4ca9e57 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.par
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par
@@ -1,22 +1,22 @@
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Sat Oct 09 01:19:16 2021
+Wed Aug 16 20:59:37 2023
 
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
+LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
+-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
 
 
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Preference file: LCMXO2_640HC_impl1.prf.
 
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            1.135        0            0.304        0            07           Completed
+5_1   *      0            4.922        0            0.088        0            07           Completed
 
 * : Design saved.
 
@@ -26,16 +26,16 @@ par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Sat Oct 09 01:19:16 2021
+Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
+Wed Aug 16 20:59:37 2023
 
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
+Preference file: LCMXO2_640HC_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
 
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -53,62 +53,66 @@ Device utilization summary:
 
    PIO (prelim)   63+4(JTAG)/80      84% used
                   63+4(JTAG)/79      85% bonded
+   IOLOGIC           25/80           31% used
 
-   SLICE            131/320          40% used
+   SLICE            117/320          36% used
 
    EFB                1/1           100% used
 
 
-Number of Signals: 401
-Number of Connections: 1131
+Number of Signals: 380
+Number of Connections: 1008
 
 Pin Constraint Summary:
    63 out of 63 pins locked (100% locked).
 
-The following 4 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 52)
-    PHI2_c (driver: PHI2, clk load #: 13)
-    nCRAS_c (driver: nCRAS, clk load #: 7)
-    nCCAS_c (driver: nCCAS, clk load #: 4)
+The following 3 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 46)
+    PHI2_c (driver: PHI2, clk load #: 19)
+    nCRAS_c (driver: nCRAS, clk load #: 10)
 
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 
-No signal is selected as secondary clock.
+The following 2 signals are selected to use the secondary clock routing resources:
+    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
+    un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
 
+WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
-............
+..............
 Finished Placer Phase 0.  REAL time: 0 secs 
 
 Starting Placer Phase 1.
-....................
-Placer score = 65362.
+...................
+Placer score = 55012.
 Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  65089
+Placer score =  54994
 Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 ------------------ Clock Report ------------------
 
 Global Clock Resources:
-  CLK_PIN    : 1 out of 8 (12%)
-  General PIO: 3 out of 80 (3%)
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 4 out of 80 (5%)
   DCM        : 0 out of 2 (0%)
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
-  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
-  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
+  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
+  SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
 
-  PRIMARY  : 4 out of 8 (50%)
-  SECONDARY: 0 out of 8 (0%)
+  PRIMARY  : 3 out of 8 (37%)
+  SECONDARY: 2 out of 8 (25%)
 
 --------------- End of Clock Report ---------------
 
@@ -129,22 +133,21 @@ I/O Bank Usage Summary:
 | 3        | 18 / 20 ( 90%) | 3.3V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 1131 unrouted.
+0 connections routed; 1008 unrouted.
 Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Completed router resource preassignment. Real time: 6 secs 
+Completed router resource preassignment. Real time: 5 secs 
 
-Start NBR router at 01:19:22 10/09/21
+Start NBR router at 20:59:43 08/16/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -159,53 +162,54 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 01:19:22 10/09/21
+Start NBR special constraint process at 20:59:43 08/16/23
 
-Start NBR section for initial routing at 01:19:22 10/09/21
+Start NBR section for initial routing at 20:59:43 08/16/23
 Level 1, iteration 1
-0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.167ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 2, iteration 1
-1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.141ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 3, iteration 1
-1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
+7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 01:19:22 10/09/21
+Start NBR section for normal routing at 20:59:43 08/16/23
 Level 1, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 2
-5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
-Level 4, iteration 3
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
-
-Start NBR section for re-routing at 01:19:23 10/09/21
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
+Level 4, iteration 0
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs 
+Level 4, iteration 0
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
 
-Start NBR section for post-routing at 01:19:23 10/09/21
+Start NBR section for re-routing at 20:59:44 08/16/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs 
+
+Start NBR section for post-routing at 20:59:44 08/16/23
 
 End NBR router with 0 unrouted connection
 
@@ -213,7 +217,7 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 1.135ns
+  Estimated worst slack : 4.922ns
   Timing score : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
@@ -223,16 +227,16 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Total CPU time 7 secs 
+Total CPU time 6 secs 
 Total REAL time: 7 secs 
 Completely routed.
-End of route.  1131 routed (100.00%); 0 unrouted.
+End of route.  1008 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
 Timing score: 0 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
 
 All signals are completely routed.
@@ -240,13 +244,13 @@ All signals are completely routed.
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 1.135
+PAR_SUMMARY::Worst  slack> = 4.922
 PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Worst  slack> = 0.088
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 7 secs 
+Total CPU  time to completion: 6 secs 
 Total REAL time to completion: 7 secs 
 
 par done!
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf
similarity index 93%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf
index 0109563..ed37f0e 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf
@@ -1,14 +1,10 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 23:30:05 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[0]" SITE "36" ;
 LOCATE COMP "Dout[0]" SITE "76" ;
 LOCATE COMP "PHI2" SITE "8" ;
-LOCATE COMP "UFMSDO" SITE "27" ;
-LOCATE COMP "UFMSDI" SITE "29" ;
-LOCATE COMP "UFMCLK" SITE "28" ;
-LOCATE COMP "nUFMCS" SITE "30" ;
 LOCATE COMP "RDQML" SITE "48" ;
 LOCATE COMP "RDQMH" SITE "51" ;
 LOCATE COMP "nRCAS" SITE "52" ;
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pt
similarity index 100%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pt
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srd
new file mode 100644
index 0000000..c37b3da
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf
similarity index 60%
rename from CPLD/LCMXO2-640HC/impl1/impl1.srr
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf
index 7df6e22..5dab75d 100644
--- a/CPLD/LCMXO2-640HC/impl1/impl1.srr
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf
@@ -3,7 +3,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEPC
 
-# Tue Aug 15 22:34:17 2023
+# Wed Aug 16 20:59:29 2023
 
 #Implementation: impl1
 
@@ -42,37 +42,56 @@ Implementation : impl1
 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
 @N|Running in 64-bit mode
-@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
-
-@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
-
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
-Options changed - recompiling
+
+Compiler output is up to date.  No re-compile necessary
+
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
 @L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
 
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 ###########################################################[
@@ -93,21 +112,22 @@ Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
 @N|Running in 64-bit mode
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_comp.rt.csv
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
 
 @END
 
@@ -116,41 +136,18 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
-###########################################################[
 
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:19 2023
-
-###########################################################]
+@A: multi_srs_gen output is up to date. No run necessary.
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr"
 Premap Report
 
-# Tue Aug 15 22:34:20 2023
+# Wed Aug 16 20:59:30 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -172,11 +169,11 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
 
 Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt"
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@@ -187,7 +184,7 @@ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s
 Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
 
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
@@ -203,68 +200,67 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 @N: FX493 |Applying initial value "0" on instance LEDEN.
 @N: FX493 |Applying initial value "0" on instance n8MEGEN.
 @N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
 @N: FX493 |Applying initial value "0" on instance C1Submitted.
 @N: FX493 |Applying initial value "0" on instance CmdSubmitted.
 @N: FX493 |Applying initial value "0" on instance ADSubmitted.
 @N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 
-
 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
 
 Clock Summary
 ******************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 
 Clock Load Summary
 ***********************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
 
 ICG Latch Removal Summary:
 Number of ICG latches removed: 0
@@ -278,15 +274,15 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
 @KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
 @KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
@@ -297,25 +293,25 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 22:34:21 2023
+# Wed Aug 16 20:59:32 2023
 
 ###########################################################]
 Map & Optimize Report
 
-# Tue Aug 15 22:34:22 2023
+# Wed Aug 16 20:59:32 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -334,7 +330,7 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
@@ -355,95 +351,90 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 
 Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
 
-@N: MT204 |Auto Constrain mode is disabled because the following clocks are already defined:
-
-            RCLK
-            PHI2
-            nCRAS
-            nCCAS
-
 
 Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
 
-   4		0h:00m:01s		    -2.04ns		 140 /        90
+   4		0h:00m:01s		    -1.83ns		 210 /       109
 
 
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 177MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_m.srm
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
 
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
 @N: MT615 |Found clock nCRAS with period 350.00ns 
@@ -451,7 +442,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:0
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 22:34:24 2023
+# Timing report written on Wed Aug 16 20:59:35 2023
 #
 
 
@@ -471,21 +462,22 @@ Performance Summary
 *******************
 
 
-Worst slack in design: -2.389
+Worst slack in design: -1.832
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
 nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
 
 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
@@ -495,17 +487,19 @@ Estimated period and frequency reported as NA means no slack depends directly on
 Clock Relationships
 *******************
 
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
@@ -527,41 +521,41 @@ Detailed Report for Clock: PHI2
 Starting Points with Worst Slack
 ********************************
 
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
 
 
 
@@ -575,122 +569,110 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 2: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
 
 
 Path information for path number 3: 
       Requested Period:                      1.000
-    - Setup time:                            -0.462
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
+    = Required time:                         0.528
 
-    - Propagation time:                      3.214
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 4: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.605
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.517
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdUFMCS / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdUFMCS             FD1P3AX      Q        Out     0.972     0.972 r     -         
-CmdUFMCS             Net          -        -       -         -           1         
-nUFMCS_s_0_m4_yy     ORCALUT4     A        In      0.000     0.972 r     -         
-nUFMCS_s_0_m4_yy     ORCALUT4     Z        Out     1.017     1.989 r     -         
-nUFMCS_s_0_m4_yy     Net          -        -       -         -           1         
-nUFMCS_s_0_N_5_i     ORCALUT4     C        In      0.000     1.989 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.605 f     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.605 f     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 5: 
@@ -699,26 +681,26 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      1.765
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.236
+    = Slack (critical) :                     -1.832
 
     Number of logic level(s):                1
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            LEDEN / SP
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CmdSubmitted       FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted       Net          -        -       -         -           4         
-un1_FS_13_i_0      ORCALUT4     A        In      0.000     1.148 r     -         
-un1_FS_13_i_0      ORCALUT4     Z        Out     0.617     1.765 r     -         
-N_28               Net          -        -       -         -           1         
-LEDEN              FD1P3AX      SP       In      0.000     1.765 r     -         
-=================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 
@@ -739,13 +721,13 @@ Instance       Reference     Type        Pin     Net            Time        Slac
 Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
 LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
 n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
 ==================================================================================
 
 
@@ -925,13 +907,15 @@ Detailed Report for Clock: nCRAS
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
 
 
 Ending Points with Worst Slack
@@ -941,11 +925,11 @@ Ending Points with Worst Slack
 Instance       Reference     Type         Pin     Net                Time         Slack 
                Clock                                                                    
 ----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
 ========================================================================================
 
 
@@ -960,12 +944,12 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -973,15 +957,15 @@ Path information for path number 1:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
 ========================================================================================
 
 
@@ -991,12 +975,12 @@ Path information for path number 2:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRWE_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -1004,15 +988,15 @@ Path information for path number 2:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
 ========================================================================================
 
 
@@ -1022,29 +1006,29 @@ Path information for path number 3:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
+    Starting point:                          CBR / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
 
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
 
 
 Path information for path number 4: 
@@ -1053,28 +1037,28 @@ Path information for path number 4:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                       Pin      Pin               Arrival     No. of    
 Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
 --------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCS_0io_RNO            ORCALUT4     B        In      0.000     2.237 r     -         
-nRCS_0io_RNO            ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_27_i                  Net          -        -       -         -           1         
-nRCS_0io                OFS1P3BX     D        In      0.000     2.853 f     -         
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
 ======================================================================================
 
 
@@ -1084,75 +1068,142 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.837
+    - Propagation time:                      2.741
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.749
+    = Slack (non-critical) :                 -1.653
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                  Pin      Pin               Arrival     No. of    
 Name               Type         Name     Dir     Delay     Time        Fan Out(s)
 ---------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                Net          -        -       -         -           7         
-nRCS_0io_RNO_0     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.221 f     -         
-N_27_i_sn          Net          -        -       -         -           1         
-nRCS_0io_RNO       ORCALUT4     C        In      0.000     2.221 f     -         
-nRCS_0io_RNO       ORCALUT4     Z        Out     0.617     2.837 r     -         
-N_27_i             Net          -        -       -         -           1         
-nRCS_0io           OFS1P3BX     D        In      0.000     2.837 r     -         
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
 =================================================================================
 
 
 
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
 ##### END OF TIMING REPORT #####]
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 90 of 640 (14%)
+Register bits: 109 of 640 (17%)
 PIC Latch:       0
-I/O cells:       67
+I/O cells:       63
 
 
 Details:
 BB:             8
 CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
 FD1S3IX:        3
 GSR:            1
-IB:             26
+IB:             25
 IFS1P3DX:       9
-INV:            7
-OB:             33
+INV:            8
+OB:             30
 OFS1P3BX:       4
-OFS1P3DX:       12
+OFS1P3DX:       11
 OFS1P3JX:       1
-ORCALUT4:       135
+ORCALUT4:       206
 PFUMX:          1
 PUR:            1
-VHI:            1
-VLO:            1
+VHI:            2
+VLO:            2
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 22:34:24 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srm
new file mode 100644
index 0000000..b926cbb
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr
new file mode 100644
index 0000000..5dab75d
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr
@@ -0,0 +1,1209 @@
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEPC
+
+# Wed Aug 16 20:59:29 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+
+@A: multi_srs_gen output is up to date. No run necessary.
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr"
+Premap Report
+
+# Wed Aug 16 20:59:30 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+
+Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Aug 16 20:59:32 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Aug 16 20:59:32 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+Timing driven replication report
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   4		0h:00m:01s		    -1.83ns		 210 /       109
+
+
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
+
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
+
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Wed Aug 16 20:59:35 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -1.832
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+               Starting                                         Arrival           
+Instance       Reference     Type        Pin     Net            Time        Slack 
+               Clock                                                              
+----------------------------------------------------------------------------------
+Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
+LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
+n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
+==================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required           
+Instance       Reference     Type         Pin     Net            Time         Slack 
+               Clock                                                                
+------------------------------------------------------------------------------------
+RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
+RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
+RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
+RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
+RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
+RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
+RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
+RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
+RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
+RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
+====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[0] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[0]          Net          -        -       -         -           1         
+RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[9] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
+RowAd_0[9]         Net          -        -       -         -           1         
+RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[8] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[8]         Net          -        -       -         -           1         
+RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[1] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[1]          Net          -        -       -         -           1         
+RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[6] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[6]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[6]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[6]         Net          -        -       -         -           1         
+RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required           
+Instance       Reference     Type         Pin     Net                Time         Slack 
+               Clock                                                                    
+----------------------------------------------------------------------------------------
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
+========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
+========================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRWE_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
+========================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
+======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 109 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
+FD1S3IX:        3
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            8
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       206
+PFUMX:          1
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr.db b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr.db
new file mode 100644
index 0000000..5ba4139
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srr.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srs b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srs
new file mode 100644
index 0000000..e927913
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html
similarity index 91%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html
index 52bf9a9..6dee59f 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html
@@ -12,12 +12,12 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:11 2023
+Wed Aug 16 20:58:50 2023
 
 
-Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf 
 
-Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -30,7 +30,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 
 Running DRC.
 DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+Reading Preference File from LCMXO2_640HC_impl1.prf.
 
 
 Preference Summary:
@@ -80,7 +80,7 @@ Creating bit map...
  
 Bitstream Status: Final           Version 1.95.
  
-Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+Saving bit stream in "LCMXO2_640HC_impl1.jed".
  
 ===========
 UFM Summary.
@@ -89,7 +89,7 @@ UFM Size:        191 Pages (128*191 Bits).
 UFM Utilization: General Purpose Flash Memory.
  
 Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     0 Page.
+Initialized UFM Pages:                     1 Page (Page 190).
  
 Total CPU Time: 1 secs 
 Total REAL Time: 2 secs 
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt
similarity index 93%
rename from CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt
index ae49f10..5aedfac 100644
--- a/CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEPC
 
 Implementation : impl1
 
-# Written on Tue Aug 15 22:34:21 2023
+# Written on Wed Aug 16 20:59:31 2023
 
 ##### DESIGN INFO #######################################################
 
@@ -37,6 +37,8 @@ Clock Relationships
 
 Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
 -----------------------------------------------------------------------------------------------------------------------------------
+System       RCLK       |     16.000           |     No paths         |     No paths         |     No paths                         
+RCLK         System     |     16.000           |     No paths         |     No paths         |     No paths                         
 RCLK         RCLK       |     16.000           |     No paths         |     No paths         |     No paths                         
 RCLK         PHI2       |     2.000            |     No paths         |     1.000            |     No paths                         
 RCLK         nCRAS      |     No paths         |     No paths         |     1.000            |     No paths                         
@@ -48,8 +50,8 @@ nCRAS        RCLK       |     No paths         |     No paths         |     No p
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
 @W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. 
+@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
 @W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
 @W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. 
 @W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. 
@@ -119,15 +121,11 @@ p:RD[6] (bidir end point)
 p:RD[6] (bidir start point)
 p:RD[7] (bidir end point)
 p:RD[7] (bidir start point)
-p:UFMCLK
-p:UFMSDI
-p:UFMSDO
 p:nFWE
 p:nRCAS
 p:nRCS
 p:nRRAS
 p:nRWE
-p:nUFMCS
 
 
 Inapplicable constraints
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt.db b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db
similarity index 92%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt.db
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db
index 97ba9ca..68c8b1b 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt.db and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt.db differ
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd
similarity index 72%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd
index a89e71e..165a86f 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd
@@ -3,12 +3,12 @@ Device = LCMXO2-640HC;
 Package = TQFP100;
 Performance = 4;
 LUTS_avail = 640;
-LUTS_used = 255;
+LUTS_used = 230;
 FF_avail = 719;
-FF_used = 119;
-INPUT_LVTTL33 = 25;
-OUTPUT_LVTTL33 = 30;
-BIDI_LVTTL33 = 8;
+FF_used = 109;
+INPUT_LVCMOS33 = 25;
+OUTPUT_LVCMOS33 = 30;
+BIDI_LVCMOS33 = 8;
 IO_avail = 79;
 IO_used = 63;
 EBR_avail = 2;
@@ -18,7 +18,7 @@ EBR_used = 0;
 I2C = 0;
 SPI = 0;
 TimerCounter = 0;
-UFM = 0;
+UFM = 1;
 PLL = 0;
 ; end of EFB statistics
 ;
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam
similarity index 73%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam
index 65fe70d..b49ff9d 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam
@@ -2,26 +2,81 @@
 RASr2_i RASr2
 XOR8MEG.CN PHI2_c
 nCRAS_c_i nCRAS_c
+InitReady_i InitReady
 [ END MERGED ]
 [ START CLIPPED ]
 GND
+ufmefb/VCC
+ufmefb/GND
 FS_s_0_S1[17]
 FS_s_0_COUT[17]
+ufmefb/CFGSTDBY
+ufmefb/CFGWAKE
+ufmefb/wbc_ufm_irq
+ufmefb/TCOC
+ufmefb/TCINT
+ufmefb/SPIIRQO
+ufmefb/SPICSNEN
+ufmefb/SPIMCSN7
+ufmefb/SPIMCSN6
+ufmefb/SPIMCSN5
+ufmefb/SPIMCSN4
+ufmefb/SPIMCSN3
+ufmefb/SPIMCSN2
+ufmefb/SPIMCSN1
+ufmefb/SPIMCSN0
+ufmefb/SPIMOSIEN
+ufmefb/SPIMOSIO
+ufmefb/SPIMISOEN
+ufmefb/SPIMISOO
+ufmefb/SPISCKEN
+ufmefb/SPISCKO
+ufmefb/I2C2IRQO
+ufmefb/I2C1IRQO
+ufmefb/I2C2SDAOEN
+ufmefb/I2C2SDAO
+ufmefb/I2C2SCLOEN
+ufmefb/I2C2SCLO
+ufmefb/I2C1SDAOEN
+ufmefb/I2C1SDAO
+ufmefb/I2C1SCLOEN
+ufmefb/I2C1SCLO
+ufmefb/PLLDATO0
+ufmefb/PLLDATO1
+ufmefb/PLLDATO2
+ufmefb/PLLDATO3
+ufmefb/PLLDATO4
+ufmefb/PLLDATO5
+ufmefb/PLLDATO6
+ufmefb/PLLDATO7
+ufmefb/PLLADRO0
+ufmefb/PLLADRO1
+ufmefb/PLLADRO2
+ufmefb/PLLADRO3
+ufmefb/PLLADRO4
+ufmefb/PLLWEO
+ufmefb/PLL1STBO
+ufmefb/PLL0STBO
+ufmefb/PLLRSTO
+ufmefb/PLLCLKO
+ufmefb/wb_ack_o
+ufmefb/wb_dat_o_1[2]
+ufmefb/wb_dat_o_1[3]
+ufmefb/wb_dat_o_1[4]
+ufmefb/wb_dat_o_1[5]
+ufmefb/wb_dat_o_1[6]
+ufmefb/wb_dat_o_1[7]
 FS_cry_0_S0[0]
 N_1
 [ END CLIPPED ]
 [ START DESIGN PREFS ]
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 23:30:05 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[0]" SITE "36" ;
 LOCATE COMP "Dout[0]" SITE "76" ;
 LOCATE COMP "PHI2" SITE "8" ;
-LOCATE COMP "UFMSDO" SITE "27" ;
-LOCATE COMP "UFMSDI" SITE "29" ;
-LOCATE COMP "UFMCLK" SITE "28" ;
-LOCATE COMP "nUFMCS" SITE "30" ;
 LOCATE COMP "RDQML" SITE "48" ;
 LOCATE COMP "RDQMH" SITE "51" ;
 LOCATE COMP "nRCAS" SITE "52" ;
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr
new file mode 100644
index 0000000..b4bdefa
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr
@@ -0,0 +1,20 @@
+---------------------------------------------------
+Report for cell RAM2GS
+   Instance path: RAM2GS
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     117.00        100.0
+                                 IOLGC	      25.00        100.0
+                                  LUT4	     210.00        100.0
+                                 IOREG	         25        100.0
+                                 IOBUF	         63        100.0
+                                PFUREG	         84        100.0
+                                RIPPLE	         10        100.0
+SUB MODULES
+                                  cell	      count    SLC Usage(%)
+                                  REFB	          1         0.0
+---------------------------------------------------
+Report for cell REFB
+   Instance path: RAM2GS/ufmefb
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd
new file mode 100644
index 0000000..3f6e410
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html
similarity index 61%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html
index 8148b08..08af2f2 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html
@@ -14,36 +14,35 @@
 Design Information
 
 Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
-     -ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd
-     -pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:
-     /OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640
-     HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-
-     640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
-     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+     LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
+     LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
+     s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
+     -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
+     -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO2-640HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  23:30:05
+Mapped on:  08/16/23  20:59:36
 
 
 Design Summary
-   Number of registers:     93 out of   877 (11%)
-      PFU registers:           64 out of   640 (10%)
-      PIO registers:           29 out of   237 (12%)
-   Number of SLICEs:        81 out of   320 (25%)
-      SLICEs as Logic/ROM:     81 out of   320 (25%)
+   Number of registers:    109 out of   877 (12%)
+      PFU registers:           84 out of   640 (13%)
+      PIO registers:           25 out of   237 (11%)
+   Number of SLICEs:       117 out of   320 (37%)
+      SLICEs as Logic/ROM:    117 out of   320 (37%)
       SLICEs as RAM:            0 out of   240 (0%)
       SLICEs as Carry:         10 out of   320 (3%)
-   Number of LUT4s:        159 out of   640 (25%)
-      Number used as logic LUTs:        139
+   Number of LUT4s:        230 out of   640 (36%)
+      Number used as logic LUTs:        210
       Number used as distributed RAM:     0
       Number used as ripple logic:       20
       Number used as shift registers:     0
-   Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
    Number of block RAMs:  0 out of 2 (0%)
    Number of GSRs:        0 out of 1 (0%)
-   EFB used :        No
+   EFB used :        Yes
    JTAG used :       No
    Readback used :   No
    Oscillator used : No
@@ -59,40 +58,44 @@ Mapped on:  08/15/23  23:30:05
      distributed RAMs) + 2*(Number of ripple logic)
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
+   Number of clocks:  5
+     Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
+     Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
+     Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
      Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  6
-     Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net i2_i: 1 loads, 0 LSLICEs
+   Number of Clock Enables:  7
+     Net N_245_i: 1 loads, 1 LSLICEs
+     Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
 
-     Net N_26: 1 loads, 1 LSLICEs
-     Net N_28: 1 loads, 1 LSLICEs
-     Net N_188_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
-   Number of LSRs:  3
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
+     Net N_18: 2 loads, 2 LSLICEs
+     Net XOR8MEG18: 3 loads, 3 LSLICEs
+     Net N_193_i: 2 loads, 2 LSLICEs
+   Number of LSRs:  5
      Net RA10s_i: 1 loads, 0 LSLICEs
+     Net wb_clk23: 3 loads, 3 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
      Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
      Net RASr2: 2 loads, 2 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net InitReady: 17 loads
+     Net InitReady: 42 loads
+     Net FS[12]: 27 loads
+     Net FS[10]: 25 loads
+     Net FS[11]: 22 loads
+     Net FS[7]: 17 loads
+     Net FS[6]: 16 loads
      Net Ready: 15 loads
      Net Ready_fast: 14 loads
-     Net Din_c[5]: 12 loads
      Net nRowColSel: 12 loads
      Net S[1]: 12 loads
-     Net RASr2: 10 loads
-     Net CO0: 9 loads
-     Net Din_c[3]: 9 loads
-     Net Din_c[4]: 9 loads
 
 
 
 
-   Number of warnings:  6
+   Number of warnings:  1
    Number of errors:    0
      
 
@@ -101,18 +104,12 @@ Mapped on:  08/15/23  23:30:05
 
 Design Errors/Warnings
 
-WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad.
-WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad.
-WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad.
-WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
-WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
-WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
-     primitive type or preference due to command option or architecture
-     limitation. The register was packed into SLICE instead.
+WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+     temporarily disable certain features of the device including Power
+     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
+     Functionality is restored after the Flash Memory (UFM/Configuration)
+     Interface is disabled using Disable Configuration Interface command 0x26
+     followed by Bypass command 0xFF. 
 
 
 
@@ -127,18 +124,10 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 | Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI2                | INPUT     | LVCMOS33  | IN         |
-
-+---------------------+-----------+-----------+------------+
-| UFMSDO              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| UFMSDI              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| UFMCLK              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nUFMCS              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | RDQML               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
 | RDQMH               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | nRCAS               | OUTPUT    | LVCMOS33  | OUT        |
@@ -147,7 +136,7 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 +---------------------+-----------+-----------+------------+
 | nRWE                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RCKE                | OUTPUT    | LVCMOS33  | OUT        |
+| RCKE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RCLK                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -184,7 +173,6 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 | RA[4]               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RA[3]               | OUTPUT    | LVCMOS33  |            |
-
 +---------------------+-----------+-----------+------------+
 | RA[2]               | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -196,6 +184,7 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 +---------------------+-----------+-----------+------------+
 | RBA[0]              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
+
 | LED                 | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | nFWE                | INPUT     | LVCMOS33  |            |
@@ -241,7 +230,6 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 | MAin[9]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | MAin[8]             | INPUT     | LVCMOS33  |            |
-
 +---------------------+-----------+-----------+------------+
 | MAin[7]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -253,6 +241,7 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 +---------------------+-----------+-----------+------------+
 | MAin[3]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
 | MAin[2]             | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | MAin[1]             | INPUT     | LVCMOS33  |            |
@@ -267,27 +256,138 @@ WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
 Block GSR_INST undriven or does not drive anything - clipped.
 Signal nCRAS_c_i was merged into signal nCRAS_c
 Signal RASr2_i was merged into signal RASr2
+Signal InitReady_i was merged into signal InitReady
 Signal XOR8MEG.CN was merged into signal PHI2_c
 Signal GND undriven or does not drive anything - clipped.
+Signal ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
+Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
+Signal ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+
+Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
+Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
 Block nCRAS_pad_RNIBPVB was optimized away.
 Block RASr2_RNIAFR1 was optimized away.
+Block wb_rst_RNO_0 was optimized away.
 Block XOR8MEG.CN was optimized away.
 Block GND was optimized away.
+Block ufmefb/VCC was optimized away.
+Block ufmefb/GND was optimized away.
 
      
 
 
 
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 62.5 MHz
+   Clock source:                     wb_clk
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            WB
+      UFM Connection:                ENABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Initialized UFM Pages:  1 Pages (1*128 Bits)
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb/EFBInst_0
+         Type: EFB
+
+
+
 Run Time and Memory Usage
 -------------------------
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 36 MB
+   Peak Memory Usage: 37 MB
         
 
 
@@ -300,6 +400,23 @@ Block GND was optimized away.
 
 
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm
new file mode 100644
index 0000000..f3bf63b
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm
@@ -0,0 +1,9 @@
+
+ 
+ syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file
+ 
+ 
+ 
+ 				 
+
+ 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_ngd.asd b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_ngd.asd
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html
similarity index 94%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html
index b7156b7..0371599 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.39
 
-Tue Aug 15 23:30:09 2023
+Wed Aug 16 20:59:41 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -76,9 +76,6 @@ Pinout by Port Name:
 | RD[5]     | 41/2     | LVCMOS33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[6]     | 42/2     | LVCMOS33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[7]     | 43/2     | LVCMOS33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| UFMCLK    | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDI    | 29/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| UFMSDO    | 27/2     | LVCMOS33_IN   | PB4A  |           |           | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL                      |
 | nCCAS     | 9/3      | LVCMOS33_IN   | PL3C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nCRAS     | 17/3     | LVCMOS33_IN   | PL6B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
 | nFWE      | 15/3     | LVCMOS33_IN   | PL5D  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
@@ -86,7 +83,6 @@ Pinout by Port Name:
 | nRCS      | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRRAS     | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 | nRWE      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
-| nUFMCS    | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -130,10 +126,10 @@ Vccio by Bank:
 | 21/3     | MAin[3]               | LOCATED    | LVCMOS33_IN   | PL7B  | PCLKC3_0      |           |           |
 | 24/3     | MAin[6]               | LOCATED    | LVCMOS33_IN   | PL7C  |               |           |           |
 | 25/3     | MAin[8]               | LOCATED    | LVCMOS33_IN   | PL7D  |               |           |           |
-| 27/2     | UFMSDO                | LOCATED    | LVCMOS33_IN   | PB4A  | CSSPIN        |           |           |
-| 28/2     | UFMCLK                | LOCATED    | LVCMOS33_OUT  | PB4B  |               |           |           |
-| 29/2     | UFMSDI                | LOCATED    | LVCMOS33_OUT  | PB4C  |               |           |           |
-| 30/2     | nUFMCS                | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
+| 27/2     |     unused, PULL:DOWN |            |               | PB4A  | CSSPIN        |           |           |
+| 28/2     |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| 29/2     |     unused, PULL:DOWN |            |               | PB4C  |               |           |           |
+| 30/2     |     unused, PULL:DOWN |            |               | PB4D  |               |           |           |
 | 31/2     |     unused, PULL:DOWN |            |               | PB6A  | MCLK/CCLK     |           |           |
 | 32/2     | MAin[9]               | LOCATED    | LVCMOS33_IN   | PB6B  | SO/SPISO      |           |           |
 | 34/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB6C  | PCLKT2_0      |           |           |
@@ -264,9 +260,6 @@ LOCATE  COMP  "RD[4]"  SITE  "40";
 LOCATE  COMP  "RD[5]"  SITE  "41";
 LOCATE  COMP  "RD[6]"  SITE  "42";
 LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "UFMCLK"  SITE  "28";
-LOCATE  COMP  "UFMSDI"  SITE  "29";
-LOCATE  COMP  "UFMSDO"  SITE  "27";
 LOCATE  COMP  "nCCAS"  SITE  "9";
 LOCATE  COMP  "nCRAS"  SITE  "17";
 LOCATE  COMP  "nFWE"  SITE  "15";
@@ -274,7 +267,6 @@ LOCATE  COMP  "nRCAS"  SITE  "52";
 LOCATE  COMP  "nRCS"  SITE  "57";
 LOCATE  COMP  "nRRAS"  SITE  "54";
 LOCATE  COMP  "nRWE"  SITE  "49";
-LOCATE  COMP  "nUFMCS"  SITE  "30";
 
 
 
@@ -286,7 +278,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:11 2023
+Wed Aug 16 20:59:42 2023
 
 
 
diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html
similarity index 61%
rename from CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html
index bbfac58..954f131 100644
--- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html
@@ -6,26 +6,26 @@
 -->
 
 
-
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
+
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Sat Oct 09 01:19:16 2021
+Wed Aug 16 20:59:37 2023
 
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
+LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
+-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
 
 
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Preference file: LCMXO2_640HC_impl1.prf.
 
 Cost Table Summary
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            1.135        0            0.304        0            07           Completed
+5_1   *      0            4.922        0            0.088        0            07           Completed
 * : Design saved.
 
 Total (real) run time for 1-seed: 7 secs 
@@ -34,18 +34,18 @@ par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Sat Oct 09 01:19:16 2021
+Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
+Wed Aug 16 20:59:37 2023
 
 
 Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
+Preference file: LCMXO2_640HC_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
 
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -64,43 +64,46 @@ Ignore Preference Error(s):  True
 
    PIO (prelim)   63+4(JTAG)/80      84% used
                   63+4(JTAG)/79      85% bonded
+   IOLOGIC           25/80           31% used
 
-   SLICE            131/320          40% used
+   SLICE            117/320          36% used
 
    EFB                1/1           100% used
 
 
-Number of Signals: 401
-Number of Connections: 1131
+Number of Signals: 380
+Number of Connections: 1008
 
 Pin Constraint Summary:
    63 out of 63 pins locked (100% locked).
 
-The following 4 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 52)
-    PHI2_c (driver: PHI2, clk load #: 13)
-    nCRAS_c (driver: nCRAS, clk load #: 7)
-    nCCAS_c (driver: nCCAS, clk load #: 4)
+The following 3 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 46)
+    PHI2_c (driver: PHI2, clk load #: 19)
+    nCRAS_c (driver: nCRAS, clk load #: 10)
 
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 
-No signal is selected as secondary clock.
+The following 2 signals are selected to use the secondary clock routing resources:
+    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
+    un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
 
+WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
-............
+..............
 Finished Placer Phase 0.  REAL time: 0 secs 
 
 Starting Placer Phase 1.
-....................
-Placer score = 65362.
+...................
+Placer score = 55012.
 Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  65089
+Placer score =  54994
 Finished Placer Phase 2.  REAL time: 4 secs 
 
 
@@ -108,19 +111,20 @@ Finished Placer Phase 2.  REAL time: 4 secs
 Clock Report
 
 Global Clock Resources:
-  CLK_PIN    : 1 out of 8 (12%)
-  General PIO: 3 out of 80 (3%)
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 4 out of 80 (5%)
   DCM        : 0 out of 2 (0%)
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
-  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
-  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
+  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
+  SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
 
-  PRIMARY  : 4 out of 8 (50%)
-  SECONDARY: 0 out of 8 (0%)
+  PRIMARY  : 3 out of 8 (37%)
+  SECONDARY: 2 out of 8 (25%)
 
 
 
@@ -141,22 +145,21 @@ I/O Bank Usage Summary:
 | 3        | 18 / 20 ( 90%) | 3.3V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 1131 unrouted.
+0 connections routed; 1008 unrouted.
 Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Completed router resource preassignment. Real time: 6 secs 
+Completed router resource preassignment. Real time: 5 secs 
 
-Start NBR router at 01:19:22 10/09/21
+Start NBR router at 20:59:43 08/16/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -171,53 +174,54 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 01:19:22 10/09/21
+Start NBR special constraint process at 20:59:43 08/16/23
 
-Start NBR section for initial routing at 01:19:22 10/09/21
+Start NBR section for initial routing at 20:59:43 08/16/23
 Level 1, iteration 1
-0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 Level 2, iteration 1
-1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 Level 3, iteration 1
-1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs 
+7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 01:19:22 10/09/21
+Start NBR section for normal routing at 20:59:43 08/16/23
 Level 1, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs 
+0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs 
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 2
-5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs 
-Level 4, iteration 3
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
-
-Start NBR section for re-routing at 01:19:23 10/09/21
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
+Level 4, iteration 0
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs 
+Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs 
+Level 4, iteration 0
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs 
 
-Start NBR section for post-routing at 01:19:23 10/09/21
+Start NBR section for re-routing at 20:59:44 08/16/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs 
+
+Start NBR section for post-routing at 20:59:44 08/16/23
 
 End NBR router with 0 unrouted connection
 
@@ -225,7 +229,7 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 1.135ns
+  Estimated worst slack<setup> : 4.922ns
   Timing score<setup> : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
@@ -235,16 +239,16 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=wb_clk loads=1 clock_loads=1
 
-Total CPU time 7 secs 
+Total CPU time 6 secs 
 Total REAL time: 7 secs 
 Completely routed.
-End of route.  1131 routed (100.00%); 0 unrouted.
+End of route.  1008 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
 Timing score: 0 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
 
 All signals are completely routed.
@@ -252,13 +256,13 @@ All signals are completely routed.
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.135
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 4.922
 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.088
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 7 secs 
+Total CPU  time to completion: 6 secs 
 Total REAL time to completion: 7 secs 
 
 par done!
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt
similarity index 51%
rename from CPLD/LCMXO2-640HC/impl1/impl1_scck.rpt
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt
index ed95664..3aad37a 100644
--- a/CPLD/LCMXO2-640HC/impl1/impl1_scck.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEPC
 
 Implementation : impl1
 
-# Written on Tue Aug 15 22:34:20 2023
+# Written on Wed Aug 16 20:59:30 2023
 
 ##### FILES SYNTAX CHECKED ##############################################
 Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
@@ -30,30 +30,34 @@ No issues found in constraint syntax.
 Clock Summary
 *************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 Clock Load Summary
 ******************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt.db b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt.db
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt.db
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt.db
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html
similarity index 93%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html
index 136bdcc..d9a4e22 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html
@@ -8,11 +8,11 @@
 
 
    
 
-
+
-
+
@@ -48,11 +48,11 @@
 
 
-
+
-
+
@@ -62,7 +62,7 @@
 
-
+
@@ -70,7 +70,7 @@
 
-
+
    RAM2GS_LCMXO2_640HC project summaryLCMXO2_640HC project summary
 
    
 
    
 Module Name:RAM2GS_LCMXO2_640HCLCMXO2_640HC
 Synthesis:
 SynplifyPro
 
    
 Logic preference file:RAM2GS_LCMXO2_640HC.lpfRAM2GS-LCMXO2.lpf
 
    
 
    
 Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prfimpl1/LCMXO2_640HC_impl1.prf
 
    
 
    
 Product Version:
    
 
    
 Updated:2023/08/15 23:33:062023/08/16 20:59:46
 
    
 
    
 Implementation Location:
    
 
    
 Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldfD:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf
 
    
 
    
 
    
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html
similarity index 50%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html
index b5301ad..eccc49c 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.html
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html
@@ -12,7 +12,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEPC
 
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 #Implementation: impl1
 
@@ -57,17 +57,38 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
 
 Compiler output is up to date.  No re-compile necessary
 
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
@@ -79,7 +100,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 ###########################################################[
@@ -101,18 +122,21 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
 
 @END
 
@@ -121,38 +145,18 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
-###########################################################[
 
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
+@A: multi_srs_gen output is up to date. No run necessary.
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr"
+Premap Report
 
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:42 2023
-
-###########################################################]
-# Tue Aug 15 23:12:42 2023
+# Wed Aug 16 20:59:30 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -177,22 +181,22 @@ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:0
 Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
 
 Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 @N: FX493 |Applying initial value "0" on instance InitReady.
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@@ -205,67 +209,67 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 @N: FX493 |Applying initial value "0" on instance LEDEN.
 @N: FX493 |Applying initial value "0" on instance n8MEGEN.
 @N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
 @N: FX493 |Applying initial value "0" on instance C1Submitted.
 @N: FX493 |Applying initial value "0" on instance CmdSubmitted.
 @N: FX493 |Applying initial value "0" on instance ADSubmitted.
 @N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
 
 Clock Summary
 ******************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 
 Clock Load Summary
 ***********************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
 
 ICG Latch Removal Summary:
 Number of ICG latches removed: 0
@@ -279,15 +283,15 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
 @KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
 @KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
@@ -298,23 +302,25 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
+# Wed Aug 16 20:59:32 2023
 
 ###########################################################]
-# Tue Aug 15 23:12:44 2023
+Map & Optimize Report
+
+# Wed Aug 16 20:59:32 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -333,7 +339,7 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
@@ -348,7 +354,7 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
 
 
 
@@ -357,85 +363,87 @@ Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapse
 
 Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
 
-   4		0h:00m:01s		    -2.04ns		 140 /        90
+   4		0h:00m:01s		    -1.83ns		 210 /       109
 
 
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
 
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
 @N: MT615 |Found clock nCRAS with period 350.00ns 
@@ -443,14 +451,14 @@ Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:0
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
+# Timing report written on Wed Aug 16 20:59:35 2023
 #
 
 
 Top view:               RAM2GS
 Requested Frequency:    2.9 MHz
 Wire load mode:         top
-Paths requested:        3
+Paths requested:        5
 Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
                        
 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@@ -463,21 +471,22 @@ Performance Summary
 *******************
 
 
-Worst slack in design: -2.389
+Worst slack in design: -1.832
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
 nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
 
 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
@@ -487,17 +496,19 @@ Estimated period and frequency reported as NA means no slack depends directly on
 Clock Relationships
 *******************
 
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
@@ -519,41 +530,41 @@ Detailed Report for Clock: PHI2
 Starting Points with Worst Slack
 ********************************
 
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
 
 
 
@@ -567,91 +578,138 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 2: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
 
 
 Path information for path number 3: 
       Requested Period:                      1.000
-    - Setup time:                            -0.462
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
+    = Required time:                         0.528
 
-    - Propagation time:                      3.214
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 
@@ -672,13 +730,13 @@ Instance       Reference     Type        Pin     Net            Time        Slac
 Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
 LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
 n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
 ==================================================================================
 
 
@@ -791,6 +849,62 @@ RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -
 =================================================================================
 
 
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[1] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[1]          Net          -        -       -         -           1         
+RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[6] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[6]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[6]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[6]         Net          -        -       -         -           1         
+RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
 
 
 ====================================
@@ -802,13 +916,15 @@ Detailed Report for Clock: nCRAS
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
 
 
 Ending Points with Worst Slack
@@ -818,11 +934,11 @@ Ending Points with Worst Slack
 Instance       Reference     Type         Pin     Net                Time         Slack 
                Clock                                                                    
 ----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
 ========================================================================================
 
 
@@ -837,12 +953,12 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -850,15 +966,15 @@ Path information for path number 1:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
 ========================================================================================
 
 
@@ -868,12 +984,12 @@ Path information for path number 2:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRWE_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -881,15 +997,15 @@ Path information for path number 2:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
 ========================================================================================
 
 
@@ -899,28 +1015,156 @@ Path information for path number 3:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
+    Starting point:                          CBR / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
 
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
 Instance / Net                       Pin      Pin               Arrival     No. of    
 Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
 --------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
+======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
 ======================================================================================
 
 
@@ -929,46 +1173,47 @@ nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 90 of 640 (14%)
+Register bits: 109 of 640 (17%)
 PIC Latch:       0
-I/O cells:       67
+I/O cells:       63
 
 
 Details:
 BB:             8
 CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
 FD1S3IX:        3
 GSR:            1
-IB:             26
+IB:             25
 IFS1P3DX:       9
-INV:            7
-OB:             33
+INV:            8
+OB:             30
 OFS1P3BX:       4
-OFS1P3DX:       12
+OFS1P3DX:       11
 OFS1P3JX:       1
-ORCALUT4:       135
+ORCALUT4:       206
 PFUMX:          1
 PUR:            1
-VHI:            1
-VLO:            1
+VHI:            2
+VLO:            2
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl
similarity index 80%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl
index 04a6c81..daed2e3 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+++ b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl
@@ -15,12 +15,12 @@ set_option -resource_sharing true
 set_option -vlog_std v2001
 
 #map options
-set_option -frequency 70
+set_option -frequency 100
 set_option -maxfan 1000
 set_option -auto_constrain_io 0
 set_option -disable_io_insertion false
-set_option -retiming false; set_option -pipe false
-set_option -force_gsr auto
+set_option -retiming false; set_option -pipe true
+set_option -force_gsr false
 set_option -compiler_compatible 0
 set_option -dup false
 
@@ -31,7 +31,7 @@ set_option -default_enum_encoding default
 
 
 #timing analysis options
-set_option -num_critical_paths 3
+
 
 
 #automatic place and route (vendor) options
@@ -47,19 +47,20 @@ set_option -seqshift_no_replicate 0
 
 #-- add_file options
 set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
-add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v}
+add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
+add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
 
 #-- top module name
 set_option -top_module RAM2GS
 
 #-- set result format/file last
-project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi}
+project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
 
 #-- error message log file
-project -log_file {RAM2GS_LCMXO2_640HC_impl1.srf}
+project -log_file {LCMXO2_640HC_impl1.srf}
 
 #-- set any command lines input by customer
 
 
 #-- run Synplify with 'arrange HDL file'
-project -run -clean
+project -run
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp2.lpf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp2.lpf
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp2.lpf
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp2.lpf
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp4.lpf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp4.lpf
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp4.lpf
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp4.lpf
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp8.lpf b/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp8.lpf
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify_tmp8.lpf
rename to CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify_tmp8.lpf
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
deleted file mode 100644
index 84dc5f9..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
+++ /dev/null
@@ -1,75 +0,0 @@
-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Tue Aug 15 23:30:13 2023 *
-NOTE DESIGN NAME: RAM2GS *
-NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
-NOTE PIN ASSIGNMENTS *
-NOTE PINS RD[0] : 36 : inout *
-NOTE PINS Dout[0] : 76 : out *
-NOTE PINS PHI2 : 8 : in *
-NOTE PINS UFMSDO : 27 : in *
-NOTE PINS UFMSDI : 29 : out *
-NOTE PINS UFMCLK : 28 : out *
-NOTE PINS nUFMCS : 30 : out *
-NOTE PINS RDQML : 48 : out *
-NOTE PINS RDQMH : 51 : out *
-NOTE PINS nRCAS : 52 : out *
-NOTE PINS nRRAS : 54 : out *
-NOTE PINS nRWE : 49 : out *
-NOTE PINS RCKE : 53 : out *
-NOTE PINS RCLK : 62 : in *
-NOTE PINS nRCS : 57 : out *
-NOTE PINS RD[7] : 43 : inout *
-NOTE PINS RD[6] : 42 : inout *
-NOTE PINS RD[5] : 41 : inout *
-NOTE PINS RD[4] : 40 : inout *
-NOTE PINS RD[3] : 39 : inout *
-NOTE PINS RD[2] : 38 : inout *
-NOTE PINS RD[1] : 37 : inout *
-NOTE PINS RA[11] : 59 : out *
-NOTE PINS RA[10] : 64 : out *
-NOTE PINS RA[9] : 63 : out *
-NOTE PINS RA[8] : 65 : out *
-NOTE PINS RA[7] : 75 : out *
-NOTE PINS RA[6] : 68 : out *
-NOTE PINS RA[5] : 70 : out *
-NOTE PINS RA[4] : 74 : out *
-NOTE PINS RA[3] : 71 : out *
-NOTE PINS RA[2] : 69 : out *
-NOTE PINS RA[1] : 67 : out *
-NOTE PINS RA[0] : 66 : out *
-NOTE PINS RBA[1] : 60 : out *
-NOTE PINS RBA[0] : 58 : out *
-NOTE PINS LED : 34 : out *
-NOTE PINS nFWE : 15 : in *
-NOTE PINS nCRAS : 17 : in *
-NOTE PINS nCCAS : 9 : in *
-NOTE PINS Dout[7] : 82 : out *
-NOTE PINS Dout[6] : 78 : out *
-NOTE PINS Dout[5] : 84 : out *
-NOTE PINS Dout[4] : 83 : out *
-NOTE PINS Dout[3] : 85 : out *
-NOTE PINS Dout[2] : 87 : out *
-NOTE PINS Dout[1] : 86 : out *
-NOTE PINS Din[7] : 1 : in *
-NOTE PINS Din[6] : 2 : in *
-NOTE PINS Din[5] : 98 : in *
-NOTE PINS Din[4] : 99 : in *
-NOTE PINS Din[3] : 97 : in *
-NOTE PINS Din[2] : 88 : in *
-NOTE PINS Din[1] : 96 : in *
-NOTE PINS Din[0] : 3 : in *
-NOTE PINS CROW[1] : 16 : in *
-NOTE PINS CROW[0] : 10 : in *
-NOTE PINS MAin[9] : 32 : in *
-NOTE PINS MAin[8] : 25 : in *
-NOTE PINS MAin[7] : 18 : in *
-NOTE PINS MAin[6] : 24 : in *
-NOTE PINS MAin[5] : 19 : in *
-NOTE PINS MAin[4] : 20 : in *
-NOTE PINS MAin[3] : 21 : in *
-NOTE PINS MAin[2] : 13 : in *
-NOTE PINS MAin[1] : 12 : in *
-NOTE PINS MAin[0] : 14 : in *
-NOTE CONFIGURATION MODE: NONE *
-NOTE COMPRESSION: on *
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
deleted file mode 100644
index e4fda17..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
+++ /dev/null
@@ -1,21 +0,0 @@
-----------------------------------------------------------------------
-Report for cell RAM2GS.TECH
-Register bits:  102 of 877 (11.631%)
-I/O cells:      67
-                                  Cell usage:
-                               cell     count   Res Usage(%)
-                                 BB         8          100.0
-                              CCU2D        10          100.0
-                            FD1P3AX        29          100.0
-                            FD1P3AY         5          100.0
-                            FD1P3IX         3          100.0
-                            FD1S3AX        47          100.0
-                            FD1S3IX        14          100.0
-                            FD1S3JX         4          100.0
-                                GSR         1          100.0
-                                 IB        26          100.0
-                                INV         3          100.0
-                               LUT4       122          100.0
-                                 OB        33          100.0
-                              PFUMX         1          100.0
-                              TOTAL       306
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr
deleted file mode 100644
index 41b5352..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.areasrr
+++ /dev/null
@@ -1,29 +0,0 @@
-----------------------------------------------------------------------
-Report for cell RAM2GS.verilog
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-                                          Cell usage:
-                               cell       count    Res Usage(%)
-                                 BB        8       100.0
-                              CCU2D       10       100.0
-                            FD1P3AX       11       100.0
-                            FD1S3AX       49       100.0
-                            FD1S3AY        1       100.0
-                            FD1S3IX        3       100.0
-                                GSR        1       100.0
-                                 IB       26       100.0
-                           IFS1P3DX        9       100.0
-                                INV        7       100.0
-                                 OB       33       100.0
-                           OFS1P3BX        4       100.0
-                           OFS1P3DX       12       100.0
-                           OFS1P3JX        1       100.0
-                           ORCALUT4      135       100.0
-                              PFUMX        1       100.0
-                                PUR        1       100.0
-                                VHI        1       100.0
-                                VLO        1       100.0
-                            
-                         TOTAL           314           
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd
deleted file mode 100644
index b1a670d..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
deleted file mode 100644
index cb4a9b3..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
+++ /dev/null
@@ -1,214 +0,0 @@
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Tue Aug 15 23:30:05 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)   67+4(JTAG)/80      89% used
-                  67+4(JTAG)/79      90% bonded
-   IOLOGIC           29/80           36% used
-
-   SLICE             81/320          25% used
-
-
-
-Number of Signals: 292
-Number of Connections: 703
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 18)
-
-WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 2 signals are selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
-    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-...........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-....................
-Placer score = 41844.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  41803
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 4 out of 80 (5%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
-  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 8 (25%)
-  SECONDARY: 2 out of 8 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
-   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
-| 1        | 20 / 20 (100%) | 3.3V       | -         |
-| 2        | 16 / 20 ( 80%) | 3.3V       | -         |
-| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 703 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 23:30:11 08/15/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 23:30:11 08/15/23
-
-Start NBR section for initial routing at 23:30:11 08/15/23
-Level 1, iteration 1
-0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 23:30:11 08/15/23
-Level 4, iteration 1
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23
-
-Start NBR section for re-routing at 23:30:11 08/15/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 23:30:11 08/15/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 5.827ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  703 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 5.827
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.304
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
deleted file mode 100644
index a998d0c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
+++ /dev/null
@@ -1,28 +0,0 @@
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:05 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-
-
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            5.827        0            0.304        0            06           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
deleted file mode 100644
index ec074a2..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
+++ /dev/null
@@ -1 +0,0 @@
-DRC detected 0 errors and 0 warnings.
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi
deleted file mode 100644
index 84a0084..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi
+++ /dev/null
@@ -1,2989 +0,0 @@
-(edif RAM2GS
-  (edifVersion 2 0 0)
-  (edifLevel 0)
-  (keywordMap (keywordLevel 0))
-  (status
-    (written
-      (timeStamp 2023 8 15 23 12 46)
-      (author "Synopsys, Inc.")
-      (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
-     )
-   )
-  (library LUCENT
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell CCU2D (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A0 (direction INPUT))
-           (port B0 (direction INPUT))
-           (port C0 (direction INPUT))
-           (port D0 (direction INPUT))
-           (port A1 (direction INPUT))
-           (port B1 (direction INPUT))
-           (port C1 (direction INPUT))
-           (port D1 (direction INPUT))
-           (port CIN (direction INPUT))
-           (port COUT (direction OUTPUT))
-           (port S0 (direction OUTPUT))
-           (port S1 (direction OUTPUT))
-         )
-        (property INJECT1_1 (string "NO"))
-        (property INJECT1_0 (string "NO"))
-        (property INIT1 (string "0000"))
-        (property INIT0 (string "0000"))
-       )
-    )
-    (cell BB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port B (direction INOUT))
-           (port I (direction INPUT))
-           (port T (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell OB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell IB (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port I (direction INPUT))
-           (port O (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3IX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port CD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AY (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1S3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell OFS1P3JX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port SCLK (direction INPUT))
-           (port PD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell OFS1P3DX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port SCLK (direction INPUT))
-           (port CD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell IFS1P3DX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port SCLK (direction INPUT))
-           (port CD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell OFS1P3BX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port SCLK (direction INPUT))
-           (port PD (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell FD1P3AX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port D (direction INPUT))
-           (port SP (direction INPUT))
-           (port CK (direction INPUT))
-           (port Q (direction OUTPUT))
-         )
-       )
-    )
-    (cell ORCALUT4 (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port B (direction INPUT))
-           (port C (direction INPUT))
-           (port D (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell PFUMX (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port ALUT (direction INPUT))
-           (port BLUT (direction INPUT))
-           (port C0 (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell GSR (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port GSR (direction INPUT))
-         )
-       )
-    )
-    (cell INV (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port A (direction INPUT))
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VHI (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-    (cell VLO (cellType GENERIC)
-       (view PRIM (viewType NETLIST)
-         (interface
-           (port Z (direction OUTPUT))
-         )
-       )
-    )
-  )
-  (library work
-    (edifLevel 0)
-    (technology (numberDefinition ))
-    (cell RAM2GS (cellType GENERIC)
-       (view verilog (viewType NETLIST)
-         (interface
-           (port PHI2 (direction INPUT))
-           (port (array (rename main "MAin[9:0]") 10) (direction INPUT))
-           (port (array (rename crow "CROW[1:0]") 2) (direction INPUT))
-           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
-           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
-           (port nCCAS (direction INPUT))
-           (port nCRAS (direction INPUT))
-           (port nFWE (direction INPUT))
-           (port LED (direction OUTPUT))
-           (port (array (rename rba "RBA[1:0]") 2) (direction OUTPUT))
-           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
-           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
-           (port nRCS (direction OUTPUT))
-           (port RCLK (direction INPUT))
-           (port RCKE (direction OUTPUT))
-           (port nRWE (direction OUTPUT))
-           (port nRRAS (direction OUTPUT))
-           (port nRCAS (direction OUTPUT))
-           (port RDQMH (direction OUTPUT))
-           (port RDQML (direction OUTPUT))
-           (port nUFMCS (direction OUTPUT))
-           (port UFMCLK (direction OUTPUT))
-           (port UFMSDI (direction OUTPUT))
-           (port UFMSDO (direction INPUT))
-         )
-         (contents
-          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
-          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
-          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
-          )
-          (instance RASr2_RNIAFR1 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance RA10_0io_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance nCCAS_pad_RNISUR8 (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance RASr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance FWEr_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename S_RNICVV51_0 "S_RNICVV51[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance RCKEEN_8_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C (!B+!A))+D (C !A))"))
-          )
-          (instance (rename IS_RNO_3 "IS_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))"))
-          )
-          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C (B+A)+C A))"))
-          )
-          (instance UFMSDI_RNO (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
-          (instance UFMSDI_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!B !A))"))
-          )
-          (instance UFMSDI_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A)"))
-          )
-          (instance Ready_fast_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdSubmitted_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nCRAS_pad_RNIBPVB (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename XOR8MEG_CN "XOR8MEG.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance (rename WRD_0io_0 "WRD_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_1 "WRD_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_2 "WRD_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_3 "WRD_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_4 "WRD_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_5 "WRD_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_6 "WRD_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance (rename WRD_0io_7 "WRD_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "TRUE"))
-          )
-          (instance PHI2r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Bank_0io_0 "Bank_0io[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_1 "Bank_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_2 "Bank_0io[2]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_3 "Bank_0io[3]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_4 "Bank_0io[4]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_5 "Bank_0io[5]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_6 "Bank_0io[6]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance (rename Bank_0io_7 "Bank_0io[7]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-          )
-          (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance UFMCLK_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RBA_0io_0 "RBA_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RBA_0io_1 "RBA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance RA11_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance RA10_0io (viewRef PRIM (cellRef OFS1P3JX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nUFMCS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
-          )
-          (instance nRowColSel (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance n8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance XOR8MEG (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDI (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_0 "RowA[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_1 "RowA[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_2 "RowA[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_3 "RowA[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_4 "RowA[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_5 "RowA[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_6 "RowA[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_7 "RowA[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_8 "RowA[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename RowA_9 "RowA[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RCKE (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance PHI2r2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance InitReady (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_0 "IS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_1 "IS[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_2 "IS[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance (rename IS_3 "IS[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance FWEr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_16 "FS[16]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename FS_17 "FS[17]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Cmdn8MEGEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMSDI (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCS (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdUFMCLK (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CmdLEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdEnable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CBR (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr3 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr2 (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance CASr (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance C1Submitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance ADSubmitted (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance UFMSDO_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance UFMSDI_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance UFMCLK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nUFMCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RDQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance RCLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nRCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_1 "RBA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RBA_pad_0 "RBA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nFWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCRAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nCCAS_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance (rename CROW_pad_1 "CROW_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename CROW_pad_0 "CROW_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_9 "MAin_pad[9]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_8 "MAin_pad[8]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_7 "MAin_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_6 "MAin_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_5 "MAin_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_4 "MAin_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_3 "MAin_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_2 "MAin_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_1 "MAin_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance (rename MAin_pad_0 "MAin_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance PHI2_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
-          )
-          (instance CmdEnable_s (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C B))"))
-          )
-          (instance CmdEnable_s_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+A)+D (!C (!B+A)))"))
-          )
-          (instance CmdEnable_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance CmdEnable17_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance UFMCLK_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B+A)))"))
-          )
-          (instance XOR8MEG18 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance un1_FS_14_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance un1_FS_13_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance CmdEnable17_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance nUFMCS_s_0_N_5_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B+A)+C (B !A))+D (!C+!A))"))
-          )
-          (instance Cmdn8MEGEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
-          )
-          (instance CmdLEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (B !A))"))
-          )
-          (instance RA10_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C+(B+A)))"))
-          )
-          (instance un1_FS_13_i_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance un1_FS_14_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance CMDWR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
-          )
-          (instance un1_CmdEnable20_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance nRWE_s_i_tz_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (B !A)))"))
-          )
-          (instance UFMCLK_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A))"))
-          )
-          (instance XOR8MEG_3_u_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(!B+!A)))"))
-          )
-          (instance nRWE_s_i_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance UFMSDI_ens2_i_a0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !A+D (!C (!B !A)+C !A))"))
-          )
-          (instance un1_FS_13_i_a2_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRRAS_5_u_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C (!B A)+C !B))"))
-          )
-          (instance C1WR_7_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance un1_CmdEnable20_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !A)+D (!C (!B !A)+C !A))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(!B+A))+D (!C (!B+A)))"))
-          )
-          (instance UFMSDI_en_ss0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance nUFMCS15_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance nUFMCS_s_0_m4_yy (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C A)+D (!C !B+C (!B+A)))"))
-          )
-          (instance CmdLEDEN_4_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B)+D (!C (B+!A)+C !A))"))
-          )
-          (instance UFMCLK_r_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D A)"))
-          )
-          (instance PHI2r3_RNITCN41 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !B+D (!C (!B+A)+C !B))"))
-          )
-          (instance IS_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance nRCAS_0_sqmuxa_1_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance nRowColSel_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (B+A))+D (!C B+C (B+!A)))"))
-          )
-          (instance nRCAS_r_i_a3_1_1_tz (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D !C+D (C (!B A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
-          (instance un1_CmdEnable20_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)))"))
-          )
-          (instance XOR8MEG_3_u_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance C1WR_7_0_o3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D+(C+(B+!A)))"))
-          )
-          (instance nRRAS_5_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)+C !A))"))
-          )
-          (instance (rename IS_RNO_2 "IS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+!A))"))
-          )
-          (instance XOR8MEG_3_u_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B !A))"))
-          )
-          (instance UFMSDI_ens2_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A))"))
-          )
-          (instance ADSubmitted_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+(B A)))"))
-          )
-          (instance CmdEnable16_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(!B+A))"))
-          )
-          (instance UFMCLK_r_i_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance InitReady3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance nRowColSel_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance RCKE_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !B)+D (C+(B+A)))"))
-          )
-          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance (rename S_RNO_0 "S_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+!A)"))
-          )
-          (instance XOR8MEG_3_u_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance C1Submitted_s_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B A))"))
-          )
-          (instance Cmdn8MEGEN_4_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+!A))"))
-          )
-          (instance un1_nRCAS_6_sqmuxa_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance Ready_0_sqmuxa_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(!B+!A))"))
-          )
-          (instance RDQMH_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance nCCAS_pad_RNI01SJ (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance UFMCLK_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance InitReady3_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance un1_FS_13_i_a2_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance CmdEnable16_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance UFMSDI_ens2_i_o2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance C1WR_7_0_o3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D+(!C+(!B+!A)))"))
-          )
-          (instance UFMSDI_ens2_i_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_CmdEnable20_0_o3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(!B+!A))"))
-          )
-          (instance CMDWR_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance un1_FS_13_i_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance un1_FS_14_i_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance CmdEnable17_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance (rename un9_RA_8 "un9_RA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_0 "un9_RA_i_m3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_1 "un9_RA_i_m3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_2 "un9_RA_i_m3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_3 "un9_RA_i_m3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_4 "un9_RA_i_m3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_5 "un9_RA_i_m3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_6 "un9_RA_i_m3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_7 "un9_RA_i_m3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance (rename un9_RA_i_m3_9 "un9_RA_i_m3[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C A)"))
-          )
-          (instance n8MEGEN_5_i_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C (B A))"))
-          )
-          (instance RDQML_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance InitReady3_0_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename S_0_i_o2_1 "S_0_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance IS_n1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B A+B !A)"))
-          )
-          (instance un1_PHI2r3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B !A)"))
-          )
-          (instance C1WR_7_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance CmdEnable17_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance RCKEEN_8_u_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+B)+D (C (!B+!A)))"))
-          )
-          (instance RCKEEN_8_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D B+D (!C B+C (B+!A)))"))
-          )
-          (instance nRCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B)+D (!C !B+C (!B !A)))"))
-          )
-          (instance nRCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C (!B !A))"))
-          )
-          (instance nRWE_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A))+D A)"))
-          )
-          (instance nRWE_0io_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance nRWE_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nRCS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance nRCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+A)+D (!C A+C !B))"))
-          )
-          (instance RA11d (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)+C (B !A))+D (C B))"))
-          )
-          (instance CmdLEDEN_4_u_i_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance (rename RowAd_3 "RowAd[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_0 "RowAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_1 "RowAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_2 "RowAd[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_7 "RowAd[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_4 "RowAd[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_5 "RowAd[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance (rename RowAd_6 "RowAd[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RBAd_1 "RBAd[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_8 "RowAd[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename RowAd_9 "RowAd[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance (rename RBAd_0 "RBAd[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance CmdUFMCLK_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance CmdSubmitted_1_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A))+D (!B A))"))
-          )
-          (instance CmdEnable16_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance nRRAS_5_u_i_0_RNILD5I (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C !A)+D (C !A))"))
-          )
-          (instance IS_0_sqmuxa_0_o2_0_RNIS63D (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance (rename IS_RNO_0 "IS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A+B A)+C A)"))
-          )
-          (instance (rename FS_s_0_17 "FS_s_0[17]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x5002"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_15 "FS_cry_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
-           (property INIT0 (string "0x300A"))
-           (property INJECT1_1 (string "NO"))
-           (property INJECT1_0 (string "NO"))
-           (property INIT1 (string "0x300A"))
-          )
-          (net CBR (joined
-           (portRef Q (instanceRef CBR))
-           (portRef A (instanceRef nRCS_0io_RNO_0))
-           (portRef A (instanceRef nRWE_0io_RNO_1))
-           (portRef A (instanceRef nRCAS_0io_RNO_0))
-           (portRef A (instanceRef RCKEEN_8_u))
-           (portRef B (instanceRef nRowColSel_0_0_a3_0))
-           (portRef A (instanceRef LED_pad_RNO))
-           (portRef A (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-          ))
-          (net C1Submitted (joined
-           (portRef Q (instanceRef C1Submitted))
-           (portRef A (instanceRef C1Submitted_s_0))
-           (portRef A (instanceRef un1_CmdEnable20_0_a2_1))
-          ))
-          (net (rename Bank_2 "Bank[2]") (joined
-           (portRef Q (instanceRef Bank_0io_2))
-           (portRef B (instanceRef C1WR_7_0_o3_6))
-          ))
-          (net Ready (joined
-           (portRef Q (instanceRef Ready))
-           (portRef B (instanceRef IS_RNO_0))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef D (instanceRef nRCS_0io_RNO))
-           (portRef C (instanceRef nRWE_0io_RNO_1))
-           (portRef D (instanceRef RCKEEN_8_u))
-           (portRef D (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef A (instanceRef Ready_RNO))
-           (portRef A (instanceRef RCKEEN_8_u_0_0))
-           (portRef A (instanceRef S_RNICVV51_0))
-          ))
-          (net n8MEGEN (joined
-           (portRef Q (instanceRef n8MEGEN))
-           (portRef D (instanceRef RA11d))
-           (portRef C (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net CO0 (joined
-           (portRef Q (instanceRef S_0))
-           (portRef D (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRWE_0io_RNO_0))
-           (portRef B (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef A (instanceRef S_RNO_0))
-           (portRef C (instanceRef nRCAS_r_i_a3_1_1_tz))
-           (portRef A (instanceRef nRowColSel_0_0))
-           (portRef C (instanceRef S_RNICVV51_0))
-          ))
-          (net (rename S_1 "S[1]") (joined
-           (portRef Q (instanceRef S_1))
-           (portRef C (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef nRCS_0io_RNO_0))
-           (portRef D (instanceRef nRWE_0io_RNO_1))
-           (portRef C (instanceRef nRCAS_0io_RNO_0))
-           (portRef D (instanceRef nRCAS_0io_RNO))
-           (portRef D (instanceRef RCKEEN_8_u_1_0))
-           (portRef B (instanceRef S_0_i_o2_1))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef S_RNO_0))
-           (portRef D (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef S_RNICVV51_0))
-          ))
-          (net RASr2 (joined
-           (portRef Q (instanceRef RASr2))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef B (instanceRef RCKE_2_0))
-           (portRef B (instanceRef nRRAS_5_u_i_0))
-           (portRef C (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef A (instanceRef nRWE_s_i_tz_0))
-           (portRef D (instanceRef RASr3))
-           (portRef B (instanceRef RCKEEN_8_u_0_0))
-           (portRef A (instanceRef RASr2_RNIAFR1))
-          ))
-          (net InitReady (joined
-           (portRef Q (instanceRef InitReady))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef B (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef LEDEN_RNO))
-           (portRef B (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef PHI2r3_RNITCN41))
-           (portRef B (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef A (instanceRef UFMSDI_ens2_i_a0))
-           (portRef A (instanceRef UFMCLK_0io_RNO_1))
-           (portRef B (instanceRef un1_FS_13_i_0))
-           (portRef B (instanceRef un1_FS_14_i_0))
-           (portRef B (instanceRef UFMCLK_0io_RNO))
-           (portRef B (instanceRef InitReady_RNO))
-           (portRef D (instanceRef Ready_RNO))
-           (portRef C (instanceRef RCKEEN_8_u_0_0))
-          ))
-          (net FWEr (joined
-           (portRef Q (instanceRef FWEr))
-           (portRef B (instanceRef nRWE_0io_RNO_1))
-           (portRef C (instanceRef RCKEEN_8_u_1_0))
-           (portRef C (instanceRef nRowColSel_0_0_a3_0))
-           (portRef D (instanceRef nRCAS_r_i_a3_1_1_tz))
-          ))
-          (net CASr3 (joined
-           (portRef Q (instanceRef CASr3))
-           (portRef B (instanceRef nRWE_0io_RNO_0))
-           (portRef A (instanceRef nRowColSel_0_0_a3_0))
-           (portRef B (instanceRef nRCAS_r_i_a3_1_1_tz))
-          ))
-          (net (rename IS_0 "IS[0]") (joined
-           (portRef Q (instanceRef IS_0))
-           (portRef A (instanceRef IS_RNO_0))
-           (portRef D (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef A (instanceRef IS_n1_0_x2))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef A (instanceRef IS_RNO_2))
-           (portRef A (instanceRef nRRAS_5_u_i))
-           (portRef A (instanceRef nRWE_s_i_a3_1_0))
-           (portRef D (instanceRef IS_RNO_3))
-           (portRef A (instanceRef RA10_0io_RNO))
-          ))
-          (net (rename IS_3 "IS[3]") (joined
-           (portRef Q (instanceRef IS_3))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef C (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef RA10_0io_RNO_0))
-           (portRef A (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_2 "IS[2]") (joined
-           (portRef Q (instanceRef IS_2))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef C (instanceRef IS_RNO_2))
-           (portRef C (instanceRef nRWE_s_i_a3_1_0))
-           (portRef B (instanceRef RA10_0io_RNO_0))
-           (portRef B (instanceRef IS_RNO_3))
-          ))
-          (net (rename IS_1 "IS[1]") (joined
-           (portRef Q (instanceRef IS_1))
-           (portRef B (instanceRef IS_n1_0_x2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef IS_RNO_2))
-           (portRef B (instanceRef nRWE_s_i_a3_1_0))
-           (portRef A (instanceRef RA10_0io_RNO_0))
-           (portRef C (instanceRef IS_RNO_3))
-          ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A0 (instanceRef FS_cry_0_5))
-           (portRef D (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef D (instanceRef un1_FS_13_i_a2_1))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A1 (instanceRef FS_cry_0_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef B (instanceRef un1_FS_13_i_a2_6))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A0 (instanceRef FS_cry_0_7))
-           (portRef C (instanceRef un1_FS_13_i_a2_6))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A1 (instanceRef FS_cry_0_7))
-           (portRef B (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef A (instanceRef UFMSDI_en_ss0_0_a2_0))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A0 (instanceRef FS_cry_0_9))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_0 "FS[0]") (joined
-           (portRef Q (instanceRef FS_0))
-           (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_1 "FS[1]") (joined
-           (portRef Q (instanceRef FS_1))
-           (portRef A0 (instanceRef FS_cry_0_1))
-           (portRef A (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef UFMCLK_r_i_m2))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A1 (instanceRef FS_cry_0_1))
-           (portRef B (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef B (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_3 "FS[3]") (joined
-           (portRef Q (instanceRef FS_3))
-           (portRef A0 (instanceRef FS_cry_0_3))
-           (portRef C (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_13_i_a2_1))
-          ))
-          (net (rename FS_10 "FS[10]") (joined
-           (portRef Q (instanceRef FS_10))
-           (portRef A1 (instanceRef FS_cry_0_9))
-           (portRef C (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef nUFMCS15_0_a2))
-          ))
-          (net (rename FS_11 "FS[11]") (joined
-           (portRef Q (instanceRef FS_11))
-           (portRef A0 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef InitReady3_0_a2_3))
-           (portRef D (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef C (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net (rename FS_12 "FS[12]") (joined
-           (portRef Q (instanceRef FS_12))
-           (portRef A1 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef A (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_13 "FS[13]") (joined
-           (portRef Q (instanceRef FS_13))
-           (portRef A0 (instanceRef FS_cry_0_13))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef B (instanceRef InitReady3_0_a2_5))
-          ))
-          (net (rename FS_14 "FS[14]") (joined
-           (portRef Q (instanceRef FS_14))
-           (portRef A1 (instanceRef FS_cry_0_13))
-           (portRef B (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0_3))
-          ))
-          (net (rename FS_15 "FS[15]") (joined
-           (portRef Q (instanceRef FS_15))
-           (portRef A0 (instanceRef FS_cry_0_15))
-           (portRef C (instanceRef InitReady3_0_a2_5))
-           (portRef A (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net (rename FS_16 "FS[16]") (joined
-           (portRef Q (instanceRef FS_16))
-           (portRef A1 (instanceRef FS_cry_0_15))
-           (portRef B (instanceRef InitReady3_0_a2))
-           (portRef B (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef A (instanceRef UFMCLK_r_i_a2_2_2))
-          ))
-          (net (rename FS_17 "FS[17]") (joined
-           (portRef Q (instanceRef FS_17))
-           (portRef A0 (instanceRef FS_s_0_17))
-           (portRef D (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef D (instanceRef InitReady3_0_a2_5))
-          ))
-          (net PHI2r2 (joined
-           (portRef Q (instanceRef PHI2r2))
-           (portRef A (instanceRef un1_PHI2r3_0))
-           (portRef C (instanceRef PHI2r3_RNITCN41))
-           (portRef D (instanceRef PHI2r3))
-          ))
-          (net CmdUFMCS (joined
-           (portRef Q (instanceRef CmdUFMCS))
-           (portRef A (instanceRef nUFMCS_s_0_m4_yy))
-          ))
-          (net CASr2 (joined
-           (portRef Q (instanceRef CASr2))
-           (portRef A (instanceRef nRWE_0io_RNO_0))
-           (portRef A (instanceRef RCKEEN_8_u_1_0))
-           (portRef A (instanceRef nRCAS_r_i_a3_1_1_tz))
-           (portRef D (instanceRef CASr3))
-          ))
-          (net CASr (joined
-           (portRef Q (instanceRef CASr))
-           (portRef D (instanceRef CASr2))
-          ))
-          (net PHI2r (joined
-           (portRef Q (instanceRef PHI2r_0io))
-           (portRef D (instanceRef PHI2r2))
-          ))
-          (net RASr (joined
-           (portRef Q (instanceRef RASr))
-           (portRef A (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RASr2))
-          ))
-          (net (rename Bank_0 "Bank[0]") (joined
-           (portRef Q (instanceRef Bank_0io_0))
-           (portRef A (instanceRef C1WR_7_0_o3_6))
-          ))
-          (net (rename Bank_1 "Bank[1]") (joined
-           (portRef Q (instanceRef Bank_0io_1))
-           (portRef A (instanceRef C1WR_7_0_o3_7))
-          ))
-          (net (rename Bank_3 "Bank[3]") (joined
-           (portRef Q (instanceRef Bank_0io_3))
-           (portRef B (instanceRef C1WR_7_0_o3_7))
-          ))
-          (net (rename Bank_4 "Bank[4]") (joined
-           (portRef Q (instanceRef Bank_0io_4))
-           (portRef C (instanceRef C1WR_7_0_o3_7))
-          ))
-          (net (rename Bank_5 "Bank[5]") (joined
-           (portRef Q (instanceRef Bank_0io_5))
-           (portRef D (instanceRef C1WR_7_0_o3_7))
-          ))
-          (net (rename Bank_6 "Bank[6]") (joined
-           (portRef Q (instanceRef Bank_0io_6))
-           (portRef A (instanceRef C1WR_7_0_o3))
-          ))
-          (net (rename Bank_7 "Bank[7]") (joined
-           (portRef Q (instanceRef Bank_0io_7))
-           (portRef B (instanceRef C1WR_7_0_o3))
-          ))
-          (net (rename RowA_0 "RowA[0]") (joined
-           (portRef Q (instanceRef RowA_0))
-           (portRef B (instanceRef un9_RA_i_m3_0))
-          ))
-          (net (rename RowA_1 "RowA[1]") (joined
-           (portRef Q (instanceRef RowA_1))
-           (portRef B (instanceRef un9_RA_i_m3_1))
-          ))
-          (net (rename RowA_2 "RowA[2]") (joined
-           (portRef Q (instanceRef RowA_2))
-           (portRef B (instanceRef un9_RA_i_m3_2))
-          ))
-          (net (rename RowA_3 "RowA[3]") (joined
-           (portRef Q (instanceRef RowA_3))
-           (portRef B (instanceRef un9_RA_i_m3_3))
-          ))
-          (net (rename RowA_4 "RowA[4]") (joined
-           (portRef Q (instanceRef RowA_4))
-           (portRef B (instanceRef un9_RA_i_m3_4))
-          ))
-          (net (rename RowA_5 "RowA[5]") (joined
-           (portRef Q (instanceRef RowA_5))
-           (portRef B (instanceRef un9_RA_i_m3_5))
-          ))
-          (net (rename RowA_6 "RowA[6]") (joined
-           (portRef Q (instanceRef RowA_6))
-           (portRef B (instanceRef un9_RA_i_m3_6))
-          ))
-          (net (rename RowA_7 "RowA[7]") (joined
-           (portRef Q (instanceRef RowA_7))
-           (portRef B (instanceRef un9_RA_i_m3_7))
-          ))
-          (net (rename RowA_8 "RowA[8]") (joined
-           (portRef Q (instanceRef RowA_8))
-           (portRef B (instanceRef un9_RA_8))
-          ))
-          (net (rename RowA_9 "RowA[9]") (joined
-           (portRef Q (instanceRef RowA_9))
-           (portRef B (instanceRef un9_RA_i_m3_9))
-          ))
-          (net (rename WRD_0 "WRD[0]") (joined
-           (portRef Q (instanceRef WRD_0io_0))
-           (portRef I (instanceRef RD_pad_0))
-          ))
-          (net (rename WRD_1 "WRD[1]") (joined
-           (portRef Q (instanceRef WRD_0io_1))
-           (portRef I (instanceRef RD_pad_1))
-          ))
-          (net (rename WRD_2 "WRD[2]") (joined
-           (portRef Q (instanceRef WRD_0io_2))
-           (portRef I (instanceRef RD_pad_2))
-          ))
-          (net (rename WRD_3 "WRD[3]") (joined
-           (portRef Q (instanceRef WRD_0io_3))
-           (portRef I (instanceRef RD_pad_3))
-          ))
-          (net (rename WRD_4 "WRD[4]") (joined
-           (portRef Q (instanceRef WRD_0io_4))
-           (portRef I (instanceRef RD_pad_4))
-          ))
-          (net (rename WRD_5 "WRD[5]") (joined
-           (portRef Q (instanceRef WRD_0io_5))
-           (portRef I (instanceRef RD_pad_5))
-          ))
-          (net (rename WRD_6 "WRD[6]") (joined
-           (portRef Q (instanceRef WRD_0io_6))
-           (portRef I (instanceRef RD_pad_6))
-          ))
-          (net (rename WRD_7 "WRD[7]") (joined
-           (portRef Q (instanceRef WRD_0io_7))
-           (portRef I (instanceRef RD_pad_7))
-          ))
-          (net nRowColSel (joined
-           (portRef Q (instanceRef nRowColSel))
-           (portRef B (instanceRef RDQML_0))
-           (portRef C (instanceRef un9_RA_i_m3_9))
-           (portRef C (instanceRef un9_RA_i_m3_7))
-           (portRef C (instanceRef un9_RA_i_m3_6))
-           (portRef C (instanceRef un9_RA_i_m3_5))
-           (portRef C (instanceRef un9_RA_i_m3_4))
-           (portRef C (instanceRef un9_RA_i_m3_3))
-           (portRef C (instanceRef un9_RA_i_m3_2))
-           (portRef C (instanceRef un9_RA_i_m3_1))
-           (portRef C (instanceRef un9_RA_i_m3_0))
-           (portRef C (instanceRef un9_RA_8))
-           (portRef B (instanceRef RDQMH_pad_RNO))
-          ))
-          (net RASr3 (joined
-           (portRef Q (instanceRef RASr3))
-           (portRef C (instanceRef RCKE_2_0))
-          ))
-          (net LEDEN (joined
-           (portRef Q (instanceRef LEDEN))
-           (portRef B (instanceRef LED_pad_RNO))
-           (portRef B (instanceRef XOR8MEG_3_u_0_0))
-           (portRef B (instanceRef CmdLEDEN_RNO))
-          ))
-          (net Cmdn8MEGEN (joined
-           (portRef Q (instanceRef Cmdn8MEGEN))
-           (portRef A (instanceRef n8MEGEN_5_i_m2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net PHI2r3 (joined
-           (portRef Q (instanceRef PHI2r3))
-           (portRef B (instanceRef un1_PHI2r3_0))
-           (portRef D (instanceRef PHI2r3_RNITCN41))
-          ))
-          (net CmdSubmitted (joined
-           (portRef Q (instanceRef CmdSubmitted))
-           (portRef A (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef un1_FS_13_i_0))
-           (portRef A (instanceRef un1_FS_14_i_0))
-           (portRef B (instanceRef CmdSubmitted_RNO))
-          ))
-          (net CmdLEDEN (joined
-           (portRef Q (instanceRef CmdLEDEN))
-           (portRef A (instanceRef LEDEN_RNO))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_0))
-          ))
-          (net (rename FS_4 "FS[4]") (joined
-           (portRef Q (instanceRef FS_4))
-           (portRef A1 (instanceRef FS_cry_0_3))
-           (portRef B (instanceRef UFMCLK_r_i_m2))
-           (portRef A (instanceRef un1_FS_13_i_a2_8))
-          ))
-          (net InitReady3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2))
-           (portRef A (instanceRef InitReady_RNO))
-          ))
-          (net RCKEEN (joined
-           (portRef Q (instanceRef RCKEEN))
-           (portRef D (instanceRef RCKE_2_0))
-          ))
-          (net XOR8MEG (joined
-           (portRef Q (instanceRef XOR8MEG))
-           (portRef C (instanceRef RA11d))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a2))
-          ))
-          (net nRRAS_0_sqmuxa (joined
-           (portRef Z (instanceRef S_RNICVV51_0))
-           (portRef C (instanceRef nRWE_s_i_tz_0))
-           (portRef CD (instanceRef nRowColSel))
-          ))
-          (net nUFMCS15 (joined
-           (portRef Z (instanceRef nUFMCS15_0_a2))
-           (portRef B (instanceRef UFMCLK_0io_RNO_0))
-           (portRef C (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef B (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef C (instanceRef UFMCLK_0io_RNO))
-           (portRef B (instanceRef UFMSDI_RNO_1))
-           (portRef B (instanceRef UFMSDI_RNO_0))
-          ))
-          (net Ready_0_sqmuxa (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef A (instanceRef Ready_fast_RNO))
-          ))
-          (net RCKE_2 (joined
-           (portRef Z (instanceRef RCKE_2_0))
-           (portRef D (instanceRef RCKE))
-          ))
-          (net nRCAS_0_sqmuxa_1 (joined
-           (portRef Z (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef A (instanceRef nRWE_0io_RNO))
-           (portRef B (instanceRef nRCAS_0io_RNO))
-          ))
-          (net XOR8MEG18 (joined
-           (portRef Z (instanceRef XOR8MEG18))
-           (portRef A (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdLEDEN))
-           (portRef SP (instanceRef Cmdn8MEGEN))
-           (portRef SP (instanceRef XOR8MEG))
-          ))
-          (net CmdEnable (joined
-           (portRef Q (instanceRef CmdEnable))
-           (portRef B (instanceRef XOR8MEG18))
-           (portRef A (instanceRef CmdEnable_s))
-          ))
-          (net CmdEnable16 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef C1Submitted_s_0))
-           (portRef D (instanceRef ADSubmitted_r_0))
-          ))
-          (net CmdEnable17 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef ADSubmitted_r_0))
-           (portRef B (instanceRef CmdEnable_s))
-          ))
-          (net CmdSubmitted_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdSubmitted_RNO))
-          ))
-          (net CmdUFMCLK_1_sqmuxa (joined
-           (portRef Z (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef SP (instanceRef CmdUFMCLK))
-           (portRef SP (instanceRef CmdUFMCS))
-           (portRef SP (instanceRef CmdUFMSDI))
-          ))
-          (net CmdUFMCLK (joined
-           (portRef Q (instanceRef CmdUFMCLK))
-           (portRef A (instanceRef UFMCLK_0io_RNO))
-          ))
-          (net CmdUFMSDI (joined
-           (portRef Q (instanceRef CmdUFMSDI))
-           (portRef D (instanceRef UFMSDI_RNO_0))
-          ))
-          (net ADSubmitted (joined
-           (portRef Q (instanceRef ADSubmitted))
-           (portRef A (instanceRef ADSubmitted_r_0))
-           (portRef A (instanceRef CmdEnable_0_sqmuxa_0_a2))
-          ))
-          (net CmdEnable_0_sqmuxa (joined
-           (portRef Z (instanceRef CmdEnable_0_sqmuxa_0_a2))
-           (portRef D (instanceRef CmdEnable_s))
-          ))
-          (net C1Submitted_s_0 (joined
-           (portRef Z (instanceRef C1Submitted_s_0))
-           (portRef D (instanceRef C1Submitted))
-          ))
-          (net ADSubmitted_r_0 (joined
-           (portRef Z (instanceRef ADSubmitted_r_0))
-           (portRef D (instanceRef ADSubmitted))
-          ))
-          (net UFMSDI_RNO (joined
-           (portRef Z (instanceRef UFMSDI_RNO))
-           (portRef D (instanceRef UFMSDI))
-          ))
-          (net CmdEnable_s (joined
-           (portRef Z (instanceRef CmdEnable_s))
-           (portRef D (instanceRef CmdEnable))
-          ))
-          (net nRowColSel_0_0 (joined
-           (portRef Z (instanceRef nRowColSel_0_0))
-           (portRef D (instanceRef nRowColSel))
-          ))
-          (net XOR8MEG_3 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_0))
-           (portRef D (instanceRef XOR8MEG))
-          ))
-          (net RCKEEN_8 (joined
-           (portRef Z (instanceRef RCKEEN_8_u))
-           (portRef D (instanceRef RCKEEN))
-          ))
-          (net N_26 (joined
-           (portRef Z (instanceRef un1_FS_14_i_0))
-           (portRef SP (instanceRef n8MEGEN))
-          ))
-          (net N_28 (joined
-           (portRef Z (instanceRef un1_FS_13_i_0))
-           (portRef SP (instanceRef LEDEN))
-          ))
-          (net N_24 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i))
-           (portRef B (instanceRef nRCS_0io_RNO_0))
-          ))
-          (net un1_nRCAS_6_sqmuxa_i_0 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef nRCAS_0io_RNO_0))
-          ))
-          (net (rename S_0_i_o2_1 "S_0_i_o2[1]") (joined
-           (portRef Z (instanceRef S_0_i_o2_1))
-           (portRef A (instanceRef nRRAS_5_u_i_0))
-           (portRef B (instanceRef nRCAS_0_sqmuxa_1_0_a3))
-           (portRef D (instanceRef S_1))
-           (portRef D (instanceRef RCKEEN_8_u_0_0))
-          ))
-          (net N_46 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3))
-           (portRef C (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef D (instanceRef CMDWR))
-          ))
-          (net N_45 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_0))
-           (portRef D (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net N_36 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef B (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-          ))
-          (net CMDWR (joined
-           (portRef Z (instanceRef CMDWR))
-           (portRef A (instanceRef XOR8MEG18))
-           (portRef A (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_151 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef B (instanceRef C1Submitted_s_0))
-           (portRef B (instanceRef ADSubmitted_r_0))
-           (portRef D (instanceRef CmdEnable17_0_a2_0))
-           (portRef B (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_189 (joined
-           (portRef Z (instanceRef un1_nRCAS_6_sqmuxa_i_o2))
-           (portRef B (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef B (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef C (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_183 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0))
-           (portRef C (instanceRef IS_RNO_0))
-           (portRef B (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef C (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef A (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef A (instanceRef un1_nRCAS_6_sqmuxa_i_0))
-           (portRef B (instanceRef nRRAS_5_u_i))
-          ))
-          (net N_188 (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2))
-           (portRef D (instanceRef nRWE_s_i_a3_1_0))
-           (portRef D (instanceRef RA10_0io_RNO_0))
-          ))
-          (net N_160 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a2))
-           (portRef D (instanceRef XOR8MEG_3_u_0_a2_0_2))
-          ))
-          (net N_139_8 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_8))
-           (portRef B (instanceRef un1_FS_14_i_a2_0))
-           (portRef B (instanceRef un1_FS_13_i_a2))
-          ))
-          (net N_139_6 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_6))
-           (portRef A (instanceRef un1_FS_14_i_a2_0))
-           (portRef A (instanceRef un1_FS_13_i_a2))
-          ))
-          (net N_177 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_0))
-           (portRef A (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef CmdEnable17_0_a2))
-           (portRef C (instanceRef CmdEnable_0_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdEnable_s_RNO))
-          ))
-          (net N_178 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef D (instanceRef un1_CmdEnable20_0_a2_0_0))
-          ))
-          (net N_168 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef C (instanceRef un1_CmdEnable20_0_a2_0_0))
-          ))
-          (net N_76 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_0))
-          ))
-          (net N_94 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef C (instanceRef CmdLEDEN_RNO))
-           (portRef B (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net N_131 (joined
-           (portRef Z (instanceRef n8MEGEN_5_i_m2))
-           (portRef D (instanceRef n8MEGEN))
-          ))
-          (net N_205 (joined
-           (portRef Z (instanceRef nRowColSel_0_0_a3_0))
-           (portRef B (instanceRef nRowColSel_0_0))
-          ))
-          (net N_137_5 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_5))
-           (portRef D (instanceRef InitReady3_0_a2))
-           (portRef D (instanceRef UFMCLK_r_i_a2_2_2))
-          ))
-          (net N_137_3 (joined
-           (portRef Z (instanceRef InitReady3_0_a2_3))
-           (portRef C (instanceRef InitReady3_0_a2))
-           (portRef C (instanceRef UFMCLK_r_i_a2_2_2))
-          ))
-          (net N_129 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0))
-           (portRef D (instanceRef UFMCLK_r_i_m2))
-           (portRef D (instanceRef nUFMCS15_0_a2))
-           (portRef C (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef C (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_34 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2))
-           (portRef B (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net N_145 (joined
-           (portRef Z (instanceRef UFMSDI_en_ss0_0_a2_0))
-           (portRef D (instanceRef un1_FS_13_i_a2_8))
-           (portRef C (instanceRef UFMSDI_RNO_0))
-          ))
-          (net N_50 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_m2))
-           (portRef B (instanceRef UFMCLK_0io_RNO_1))
-          ))
-          (net N_139 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0))
-           (portRef C (instanceRef un1_FS_14_i_0))
-          ))
-          (net N_140 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2))
-           (portRef C (instanceRef un1_FS_13_i_0))
-          ))
-          (net N_215 (joined
-           (portRef Z (instanceRef IS_n1_0_x2))
-           (portRef D (instanceRef IS_1))
-          ))
-          (net N_56 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_o2))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef C (instanceRef Ready_RNO))
-          ))
-          (net nRWE_s_i_a3_1_0 (joined
-           (portRef Z (instanceRef nRWE_s_i_a3_1_0))
-           (portRef D (instanceRef nRWE_s_i_tz_0))
-          ))
-          (net RCKEEN_8_u_0_0 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_0_0))
-           (portRef B (instanceRef RCKEEN_8_u))
-          ))
-          (net UFMCLK_r_i_a2_2_2 (joined
-           (portRef Z (instanceRef UFMCLK_r_i_a2_2_2))
-           (portRef D (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef UFMCLK_0io_RNO_1))
-          ))
-          (net i1_i (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO))
-           (portRef D (instanceRef UFMCLK_0io))
-          ))
-          (net UFMSDI_ens2_i_a0 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a0))
-           (portRef A (instanceRef UFMSDI_RNO_0))
-          ))
-          (net nUFMCS_s_0_m4_yy (joined
-           (portRef Z (instanceRef nUFMCS_s_0_m4_yy))
-           (portRef C (instanceRef nUFMCS_s_0_N_5_i))
-          ))
-          (net N_27_i_1 (joined
-           (portRef Z (instanceRef nRCAS_r_i_a3_1_1_tz))
-           (portRef B (instanceRef nRCS_0io_RNO))
-           (portRef A (instanceRef nRCAS_0io_RNO))
-          ))
-          (net CmdLEDEN_4_u_i_a2_0_0 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_0))
-          ))
-          (net CmdEnable16_0_a2_0 (joined
-           (portRef Z (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef B (instanceRef CmdEnable_0_sqmuxa_0_a2))
-          ))
-          (net nCRAS_c_i (joined
-           (portRef Z (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef CK (instanceRef CBR))
-           (portRef CK (instanceRef FWEr))
-           (portRef CK (instanceRef RowA_9))
-           (portRef CK (instanceRef RowA_8))
-           (portRef CK (instanceRef RowA_7))
-           (portRef CK (instanceRef RowA_6))
-           (portRef CK (instanceRef RowA_5))
-           (portRef CK (instanceRef RowA_4))
-           (portRef CK (instanceRef RowA_3))
-           (portRef CK (instanceRef RowA_2))
-           (portRef CK (instanceRef RowA_1))
-           (portRef CK (instanceRef RowA_0))
-           (portRef SCLK (instanceRef RBA_0io_1))
-           (portRef SCLK (instanceRef RBA_0io_0))
-          ))
-          (net N_188_i (joined
-           (portRef Z (instanceRef IS_0_sqmuxa_0_o2_0_RNIS63D))
-           (portRef SP (instanceRef IS_3))
-           (portRef SP (instanceRef IS_2))
-           (portRef SP (instanceRef IS_1))
-          ))
-          (net RD_1_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef T (instanceRef RD_pad_0))
-           (portRef T (instanceRef RD_pad_1))
-           (portRef T (instanceRef RD_pad_2))
-           (portRef T (instanceRef RD_pad_3))
-           (portRef T (instanceRef RD_pad_4))
-           (portRef T (instanceRef RD_pad_5))
-           (portRef T (instanceRef RD_pad_6))
-           (portRef T (instanceRef RD_pad_7))
-          ))
-          (net N_27_i (joined
-           (portRef Z (instanceRef nRCS_0io_RNO))
-           (portRef D (instanceRef nRCS_0io))
-          ))
-          (net N_179_i (joined
-           (portRef Z (instanceRef nRCAS_0io_RNO))
-           (portRef D (instanceRef nRCAS_0io))
-          ))
-          (net N_24_i (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef A (instanceRef nRCS_0io_RNO))
-           (portRef D (instanceRef nRRAS_0io))
-          ))
-          (net nUFMCS_s_0_N_5_i (joined
-           (portRef Z (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef D (instanceRef nUFMCS))
-          ))
-          (net N_180_i (joined
-           (portRef Z (instanceRef nRWE_0io_RNO))
-           (portRef D (instanceRef nRWE_0io))
-          ))
-          (net N_60_i_i (joined
-           (portRef Z (instanceRef IS_RNO_0))
-           (portRef D (instanceRef IS_0))
-          ))
-          (net N_58_i_i (joined
-           (portRef Z (instanceRef IS_RNO_3))
-           (portRef D (instanceRef IS_3))
-          ))
-          (net N_57_i_i (joined
-           (portRef Z (instanceRef IS_RNO_2))
-           (portRef D (instanceRef IS_2))
-          ))
-          (net N_203_i (joined
-           (portRef Z (instanceRef S_RNO_0))
-           (portRef D (instanceRef S_0))
-          ))
-          (net N_14_i (joined
-           (portRef Z (instanceRef CmdLEDEN_RNO))
-           (portRef D (instanceRef CmdLEDEN))
-          ))
-          (net N_12_i (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_RNO))
-           (portRef D (instanceRef Cmdn8MEGEN))
-          ))
-          (net N_74_i (joined
-           (portRef Z (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef LEDEN))
-          ))
-          (net un1_CmdEnable20_i (joined
-           (portRef Z (instanceRef CmdEnable_s_RNO))
-           (portRef C (instanceRef CmdEnable_s))
-          ))
-          (net N_141_i (joined
-           (portRef Z (instanceRef PHI2r3_RNITCN41))
-           (portRef A (instanceRef UFMCLK_0io_RNO_0))
-           (portRef A (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef C0 (instanceRef UFMSDI_RNO))
-          ))
-          (net i2_i (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO_0))
-           (portRef SP (instanceRef UFMCLK_0io))
-          ))
-          (net (rename FS_cry_0 "FS_cry[0]") (joined
-           (portRef COUT (instanceRef FS_cry_0_0))
-           (portRef CIN (instanceRef FS_cry_0_1))
-          ))
-          (net (rename FS_s_0 "FS_s[0]") (joined
-           (portRef S1 (instanceRef FS_cry_0_0))
-           (portRef D (instanceRef FS_0))
-          ))
-          (net (rename FS_s_1 "FS_s[1]") (joined
-           (portRef S0 (instanceRef FS_cry_0_1))
-           (portRef D (instanceRef FS_1))
-          ))
-          (net (rename FS_cry_2 "FS_cry[2]") (joined
-           (portRef COUT (instanceRef FS_cry_0_1))
-           (portRef CIN (instanceRef FS_cry_0_3))
-          ))
-          (net (rename FS_s_2 "FS_s[2]") (joined
-           (portRef S1 (instanceRef FS_cry_0_1))
-           (portRef D (instanceRef FS_2))
-          ))
-          (net (rename FS_s_3 "FS_s[3]") (joined
-           (portRef S0 (instanceRef FS_cry_0_3))
-           (portRef D (instanceRef FS_3))
-          ))
-          (net (rename FS_cry_4 "FS_cry[4]") (joined
-           (portRef COUT (instanceRef FS_cry_0_3))
-           (portRef CIN (instanceRef FS_cry_0_5))
-          ))
-          (net (rename FS_s_4 "FS_s[4]") (joined
-           (portRef S1 (instanceRef FS_cry_0_3))
-           (portRef D (instanceRef FS_4))
-          ))
-          (net (rename FS_s_5 "FS_s[5]") (joined
-           (portRef S0 (instanceRef FS_cry_0_5))
-           (portRef D (instanceRef FS_5))
-          ))
-          (net (rename FS_cry_6 "FS_cry[6]") (joined
-           (portRef COUT (instanceRef FS_cry_0_5))
-           (portRef CIN (instanceRef FS_cry_0_7))
-          ))
-          (net (rename FS_s_6 "FS_s[6]") (joined
-           (portRef S1 (instanceRef FS_cry_0_5))
-           (portRef D (instanceRef FS_6))
-          ))
-          (net (rename FS_s_7 "FS_s[7]") (joined
-           (portRef S0 (instanceRef FS_cry_0_7))
-           (portRef D (instanceRef FS_7))
-          ))
-          (net (rename FS_cry_8 "FS_cry[8]") (joined
-           (portRef COUT (instanceRef FS_cry_0_7))
-           (portRef CIN (instanceRef FS_cry_0_9))
-          ))
-          (net (rename FS_s_8 "FS_s[8]") (joined
-           (portRef S1 (instanceRef FS_cry_0_7))
-           (portRef D (instanceRef FS_8))
-          ))
-          (net (rename FS_s_9 "FS_s[9]") (joined
-           (portRef S0 (instanceRef FS_cry_0_9))
-           (portRef D (instanceRef FS_9))
-          ))
-          (net (rename FS_cry_10 "FS_cry[10]") (joined
-           (portRef COUT (instanceRef FS_cry_0_9))
-           (portRef CIN (instanceRef FS_cry_0_11))
-          ))
-          (net (rename FS_s_10 "FS_s[10]") (joined
-           (portRef S1 (instanceRef FS_cry_0_9))
-           (portRef D (instanceRef FS_10))
-          ))
-          (net (rename FS_s_11 "FS_s[11]") (joined
-           (portRef S0 (instanceRef FS_cry_0_11))
-           (portRef D (instanceRef FS_11))
-          ))
-          (net (rename FS_cry_12 "FS_cry[12]") (joined
-           (portRef COUT (instanceRef FS_cry_0_11))
-           (portRef CIN (instanceRef FS_cry_0_13))
-          ))
-          (net (rename FS_s_12 "FS_s[12]") (joined
-           (portRef S1 (instanceRef FS_cry_0_11))
-           (portRef D (instanceRef FS_12))
-          ))
-          (net (rename FS_s_13 "FS_s[13]") (joined
-           (portRef S0 (instanceRef FS_cry_0_13))
-           (portRef D (instanceRef FS_13))
-          ))
-          (net (rename FS_cry_14 "FS_cry[14]") (joined
-           (portRef COUT (instanceRef FS_cry_0_13))
-           (portRef CIN (instanceRef FS_cry_0_15))
-          ))
-          (net (rename FS_s_14 "FS_s[14]") (joined
-           (portRef S1 (instanceRef FS_cry_0_13))
-           (portRef D (instanceRef FS_14))
-          ))
-          (net (rename FS_s_15 "FS_s[15]") (joined
-           (portRef S0 (instanceRef FS_cry_0_15))
-           (portRef D (instanceRef FS_15))
-          ))
-          (net (rename FS_cry_16 "FS_cry[16]") (joined
-           (portRef COUT (instanceRef FS_cry_0_15))
-           (portRef CIN (instanceRef FS_s_0_17))
-          ))
-          (net (rename FS_s_16 "FS_s[16]") (joined
-           (portRef S1 (instanceRef FS_cry_0_15))
-           (portRef D (instanceRef FS_16))
-          ))
-          (net (rename FS_s_17 "FS_s[17]") (joined
-           (portRef S0 (instanceRef FS_s_0_17))
-           (portRef D (instanceRef FS_17))
-          ))
-          (net RA10s_i (joined
-           (portRef Z (instanceRef RA10_0io_RNO_0))
-           (portRef PD (instanceRef RA10_0io))
-          ))
-          (net un1_PHI2r3_0 (joined
-           (portRef Z (instanceRef un1_PHI2r3_0))
-           (portRef D (instanceRef un1_FS_13_i_0))
-           (portRef D (instanceRef un1_FS_14_i_0))
-          ))
-          (net Cmdn8MEGEN_4_u_i_0 (joined
-           (portRef Z (instanceRef Cmdn8MEGEN_4_u_i_0))
-           (portRef A (instanceRef Cmdn8MEGEN_RNO))
-          ))
-          (net CmdLEDEN_4_u_i_0 (joined
-           (portRef Z (instanceRef CmdLEDEN_4_u_i_0))
-           (portRef A (instanceRef CmdLEDEN_RNO))
-          ))
-          (net d_m3_0_a2_0 (joined
-           (portRef Z (instanceRef UFMCLK_0io_RNO_1))
-           (portRef D (instanceRef UFMCLK_0io_RNO))
-          ))
-          (net XOR8MEG_3_u_0_a2_0_2 (joined
-           (portRef Z (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef D (instanceRef XOR8MEG_3_u_0_0))
-          ))
-          (net UFMSDI_ens2_i_o2_0_3 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_o2_0_3))
-           (portRef C (instanceRef UFMSDI_ens2_i_o2_0))
-          ))
-          (net Ready_0_sqmuxa_0_a3_2 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a3_2))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a3))
-           (portRef B (instanceRef Ready_RNO))
-          ))
-          (net C1WR_7_0_o3_0 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_0))
-           (portRef C (instanceRef C1WR_7_0_o3_6))
-          ))
-          (net C1WR_7_0_o3_6 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_6))
-           (portRef C (instanceRef C1WR_7_0_o3))
-          ))
-          (net C1WR_7_0_o3_7 (joined
-           (portRef Z (instanceRef C1WR_7_0_o3_7))
-           (portRef D (instanceRef C1WR_7_0_o3))
-          ))
-          (net nRWE_s_i_tz_0 (joined
-           (portRef Z (instanceRef nRWE_s_i_tz_0))
-           (portRef D (instanceRef nRWE_0io_RNO))
-          ))
-          (net UFMSDI_ens2_i_a2_4_2 (joined
-           (portRef Z (instanceRef UFMSDI_ens2_i_a2_4_2))
-           (portRef D (instanceRef UFMSDI_ens2_i_a0))
-          ))
-          (net nRRAS_5_u_i_0 (joined
-           (portRef Z (instanceRef nRRAS_5_u_i_0))
-           (portRef A (instanceRef nRRAS_5_u_i_0_RNILD5I))
-           (portRef D (instanceRef nRRAS_5_u_i))
-          ))
-          (net un1_CmdEnable20_0_o3_0_1 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_o3_0_1))
-           (portRef D (instanceRef un1_CmdEnable20_0_o3_0))
-          ))
-          (net CMDWR_2 (joined
-           (portRef Z (instanceRef CMDWR_2))
-           (portRef A (instanceRef CMDWR))
-          ))
-          (net un1_FS_13_i_a2_1 (joined
-           (portRef Z (instanceRef un1_FS_13_i_a2_1))
-           (portRef C (instanceRef un1_FS_13_i_a2))
-          ))
-          (net un1_FS_14_i_a2_0_1 (joined
-           (portRef Z (instanceRef un1_FS_14_i_a2_0_1))
-           (portRef C (instanceRef un1_FS_14_i_a2_0))
-          ))
-          (net un1_CmdEnable20_0_a2_0_0 (joined
-           (portRef Z (instanceRef un1_CmdEnable20_0_a2_0_0))
-           (portRef D (instanceRef CmdEnable_s_RNO))
-          ))
-          (net CmdEnable17_0_a2_0 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef A (instanceRef CmdEnable17_0_a2))
-          ))
-          (net CmdEnable17_0_a2_1 (joined
-           (portRef Z (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef B (instanceRef CmdEnable17_0_a2))
-          ))
-          (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined
-           (portRef S0 (instanceRef FS_cry_0_0))
-          ))
-          (net (rename FS_s_0_S1_17 "FS_s_0_S1[17]") (joined
-           (portRef S1 (instanceRef FS_s_0_17))
-          ))
-          (net (rename FS_s_0_COUT_17 "FS_s_0_COUT[17]") (joined
-           (portRef COUT (instanceRef FS_s_0_17))
-          ))
-          (net RCKEEN_8_u_1_0 (joined
-           (portRef Z (instanceRef RCKEEN_8_u_1_0))
-           (portRef C (instanceRef RCKEEN_8_u))
-          ))
-          (net (rename RowAd_0_3 "RowAd_0[3]") (joined
-           (portRef Z (instanceRef RowAd_3))
-           (portRef D (instanceRef RowA_3))
-          ))
-          (net (rename RowAd_0_0 "RowAd_0[0]") (joined
-           (portRef Z (instanceRef RowAd_0))
-           (portRef D (instanceRef RowA_0))
-          ))
-          (net (rename RowAd_0_1 "RowAd_0[1]") (joined
-           (portRef Z (instanceRef RowAd_1))
-           (portRef D (instanceRef RowA_1))
-          ))
-          (net (rename RowAd_0_2 "RowAd_0[2]") (joined
-           (portRef Z (instanceRef RowAd_2))
-           (portRef D (instanceRef RowA_2))
-          ))
-          (net (rename RowAd_0_7 "RowAd_0[7]") (joined
-           (portRef Z (instanceRef RowAd_7))
-           (portRef D (instanceRef RowA_7))
-          ))
-          (net (rename RowAd_0_4 "RowAd_0[4]") (joined
-           (portRef Z (instanceRef RowAd_4))
-           (portRef D (instanceRef RowA_4))
-          ))
-          (net (rename RowAd_0_5 "RowAd_0[5]") (joined
-           (portRef Z (instanceRef RowAd_5))
-           (portRef D (instanceRef RowA_5))
-          ))
-          (net (rename RowAd_0_6 "RowAd_0[6]") (joined
-           (portRef Z (instanceRef RowAd_6))
-           (portRef D (instanceRef RowA_6))
-          ))
-          (net (rename RBAd_0_1 "RBAd_0[1]") (joined
-           (portRef Z (instanceRef RBAd_1))
-           (portRef D (instanceRef RBA_0io_1))
-          ))
-          (net (rename RowAd_0_8 "RowAd_0[8]") (joined
-           (portRef Z (instanceRef RowAd_8))
-           (portRef D (instanceRef RowA_8))
-          ))
-          (net (rename RowAd_0_9 "RowAd_0[9]") (joined
-           (portRef Z (instanceRef RowAd_9))
-           (portRef D (instanceRef RowA_9))
-          ))
-          (net (rename RBAd_0_0 "RBAd_0[0]") (joined
-           (portRef Z (instanceRef RBAd_0))
-           (portRef D (instanceRef RBA_0io_0))
-          ))
-          (net RA11d_0 (joined
-           (portRef Z (instanceRef RA11d))
-           (portRef D (instanceRef RA11_0io))
-          ))
-          (net Ready_fast (joined
-           (portRef Q (instanceRef Ready_fast))
-           (portRef B (instanceRef RBAd_0))
-           (portRef B (instanceRef RowAd_9))
-           (portRef B (instanceRef RowAd_8))
-           (portRef B (instanceRef RBAd_1))
-           (portRef B (instanceRef RowAd_6))
-           (portRef B (instanceRef RowAd_5))
-           (portRef B (instanceRef RowAd_4))
-           (portRef B (instanceRef RowAd_7))
-           (portRef B (instanceRef RowAd_2))
-           (portRef B (instanceRef RowAd_1))
-           (portRef B (instanceRef RowAd_0))
-           (portRef B (instanceRef RowAd_3))
-           (portRef B (instanceRef RA11d))
-           (portRef B (instanceRef Ready_fast_RNO))
-          ))
-          (net N_179_i_1 (joined
-           (portRef Z (instanceRef nRCAS_0io_RNO_0))
-           (portRef C (instanceRef nRCAS_0io_RNO))
-          ))
-          (net nRWE_0io_RNO_0 (joined
-           (portRef Z (instanceRef nRWE_0io_RNO_0))
-           (portRef B (instanceRef nRWE_0io_RNO))
-          ))
-          (net nRWE_0io_RNO_1 (joined
-           (portRef Z (instanceRef nRWE_0io_RNO_1))
-           (portRef C (instanceRef nRWE_0io_RNO))
-          ))
-          (net N_27_i_sn (joined
-           (portRef Z (instanceRef nRCS_0io_RNO_0))
-           (portRef C (instanceRef nRCS_0io_RNO))
-          ))
-          (net (rename XOR8MEG_CN "XOR8MEG.CN") (joined
-           (portRef Z (instanceRef XOR8MEG_CN))
-           (portRef CK (instanceRef ADSubmitted))
-           (portRef CK (instanceRef C1Submitted))
-           (portRef CK (instanceRef CmdEnable))
-           (portRef CK (instanceRef CmdLEDEN))
-           (portRef CK (instanceRef CmdSubmitted))
-           (portRef CK (instanceRef CmdUFMCLK))
-           (portRef CK (instanceRef CmdUFMCS))
-           (portRef CK (instanceRef CmdUFMSDI))
-           (portRef CK (instanceRef Cmdn8MEGEN))
-           (portRef CK (instanceRef XOR8MEG))
-          ))
-          (net VCC (joined
-           (portRef Z (instanceRef VCC))
-           (portRef B0 (instanceRef FS_cry_0_0))
-           (portRef SP (instanceRef RA10_0io))
-           (portRef SP (instanceRef RA11_0io))
-           (portRef SP (instanceRef RBA_0io_1))
-           (portRef SP (instanceRef RBA_0io_0))
-           (portRef SP (instanceRef nRCAS_0io))
-           (portRef SP (instanceRef nRCS_0io))
-           (portRef SP (instanceRef nRRAS_0io))
-           (portRef SP (instanceRef nRWE_0io))
-           (portRef SP (instanceRef Bank_0io_7))
-           (portRef SP (instanceRef Bank_0io_6))
-           (portRef SP (instanceRef Bank_0io_5))
-           (portRef SP (instanceRef Bank_0io_4))
-           (portRef SP (instanceRef Bank_0io_3))
-           (portRef SP (instanceRef Bank_0io_2))
-           (portRef SP (instanceRef Bank_0io_1))
-           (portRef SP (instanceRef Bank_0io_0))
-           (portRef SP (instanceRef PHI2r_0io))
-           (portRef SP (instanceRef WRD_0io_7))
-           (portRef SP (instanceRef WRD_0io_6))
-           (portRef SP (instanceRef WRD_0io_5))
-           (portRef SP (instanceRef WRD_0io_4))
-           (portRef SP (instanceRef WRD_0io_3))
-           (portRef SP (instanceRef WRD_0io_2))
-           (portRef SP (instanceRef WRD_0io_1))
-           (portRef SP (instanceRef WRD_0io_0))
-           (portRef GSR (instanceRef GSR_INST))
-          ))
-          (net GND (joined
-           (portRef Z (instanceRef GND))
-           (portRef D1 (instanceRef FS_cry_0_0))
-           (portRef C1 (instanceRef FS_cry_0_0))
-           (portRef B1 (instanceRef FS_cry_0_0))
-           (portRef D0 (instanceRef FS_cry_0_0))
-           (portRef C0 (instanceRef FS_cry_0_0))
-           (portRef A0 (instanceRef FS_cry_0_0))
-           (portRef D1 (instanceRef FS_cry_0_1))
-           (portRef C1 (instanceRef FS_cry_0_1))
-           (portRef B1 (instanceRef FS_cry_0_1))
-           (portRef D0 (instanceRef FS_cry_0_1))
-           (portRef C0 (instanceRef FS_cry_0_1))
-           (portRef B0 (instanceRef FS_cry_0_1))
-           (portRef D1 (instanceRef FS_cry_0_3))
-           (portRef C1 (instanceRef FS_cry_0_3))
-           (portRef B1 (instanceRef FS_cry_0_3))
-           (portRef D0 (instanceRef FS_cry_0_3))
-           (portRef C0 (instanceRef FS_cry_0_3))
-           (portRef B0 (instanceRef FS_cry_0_3))
-           (portRef D1 (instanceRef FS_cry_0_5))
-           (portRef C1 (instanceRef FS_cry_0_5))
-           (portRef B1 (instanceRef FS_cry_0_5))
-           (portRef D0 (instanceRef FS_cry_0_5))
-           (portRef C0 (instanceRef FS_cry_0_5))
-           (portRef B0 (instanceRef FS_cry_0_5))
-           (portRef D1 (instanceRef FS_cry_0_7))
-           (portRef C1 (instanceRef FS_cry_0_7))
-           (portRef B1 (instanceRef FS_cry_0_7))
-           (portRef D0 (instanceRef FS_cry_0_7))
-           (portRef C0 (instanceRef FS_cry_0_7))
-           (portRef B0 (instanceRef FS_cry_0_7))
-           (portRef D1 (instanceRef FS_cry_0_9))
-           (portRef C1 (instanceRef FS_cry_0_9))
-           (portRef B1 (instanceRef FS_cry_0_9))
-           (portRef D0 (instanceRef FS_cry_0_9))
-           (portRef C0 (instanceRef FS_cry_0_9))
-           (portRef B0 (instanceRef FS_cry_0_9))
-           (portRef D1 (instanceRef FS_cry_0_11))
-           (portRef C1 (instanceRef FS_cry_0_11))
-           (portRef B1 (instanceRef FS_cry_0_11))
-           (portRef D0 (instanceRef FS_cry_0_11))
-           (portRef C0 (instanceRef FS_cry_0_11))
-           (portRef B0 (instanceRef FS_cry_0_11))
-           (portRef D1 (instanceRef FS_cry_0_13))
-           (portRef C1 (instanceRef FS_cry_0_13))
-           (portRef B1 (instanceRef FS_cry_0_13))
-           (portRef D0 (instanceRef FS_cry_0_13))
-           (portRef C0 (instanceRef FS_cry_0_13))
-           (portRef B0 (instanceRef FS_cry_0_13))
-           (portRef D1 (instanceRef FS_cry_0_15))
-           (portRef C1 (instanceRef FS_cry_0_15))
-           (portRef B1 (instanceRef FS_cry_0_15))
-           (portRef D0 (instanceRef FS_cry_0_15))
-           (portRef C0 (instanceRef FS_cry_0_15))
-           (portRef B0 (instanceRef FS_cry_0_15))
-           (portRef D1 (instanceRef FS_s_0_17))
-           (portRef C1 (instanceRef FS_s_0_17))
-           (portRef B1 (instanceRef FS_s_0_17))
-           (portRef A1 (instanceRef FS_s_0_17))
-           (portRef D0 (instanceRef FS_s_0_17))
-           (portRef C0 (instanceRef FS_s_0_17))
-           (portRef B0 (instanceRef FS_s_0_17))
-           (portRef CD (instanceRef RA11_0io))
-           (portRef CD (instanceRef RBA_0io_1))
-           (portRef CD (instanceRef RBA_0io_0))
-           (portRef CD (instanceRef UFMCLK_0io))
-           (portRef PD (instanceRef nRCAS_0io))
-           (portRef PD (instanceRef nRCS_0io))
-           (portRef PD (instanceRef nRRAS_0io))
-           (portRef PD (instanceRef nRWE_0io))
-           (portRef CD (instanceRef Bank_0io_7))
-           (portRef CD (instanceRef Bank_0io_6))
-           (portRef CD (instanceRef Bank_0io_5))
-           (portRef CD (instanceRef Bank_0io_4))
-           (portRef CD (instanceRef Bank_0io_3))
-           (portRef CD (instanceRef Bank_0io_2))
-           (portRef CD (instanceRef Bank_0io_1))
-           (portRef CD (instanceRef Bank_0io_0))
-           (portRef CD (instanceRef PHI2r_0io))
-           (portRef CD (instanceRef WRD_0io_7))
-           (portRef CD (instanceRef WRD_0io_6))
-           (portRef CD (instanceRef WRD_0io_5))
-           (portRef CD (instanceRef WRD_0io_4))
-           (portRef CD (instanceRef WRD_0io_3))
-           (portRef CD (instanceRef WRD_0io_2))
-           (portRef CD (instanceRef WRD_0io_1))
-           (portRef CD (instanceRef WRD_0io_0))
-          ))
-          (net PHI2_c (joined
-           (portRef O (instanceRef PHI2_pad))
-           (portRef SCLK (instanceRef RA11_0io))
-           (portRef SCLK (instanceRef Bank_0io_7))
-           (portRef SCLK (instanceRef Bank_0io_6))
-           (portRef SCLK (instanceRef Bank_0io_5))
-           (portRef SCLK (instanceRef Bank_0io_4))
-           (portRef SCLK (instanceRef Bank_0io_3))
-           (portRef SCLK (instanceRef Bank_0io_2))
-           (portRef SCLK (instanceRef Bank_0io_1))
-           (portRef SCLK (instanceRef Bank_0io_0))
-           (portRef D (instanceRef PHI2r_0io))
-           (portRef A (instanceRef XOR8MEG_CN))
-          ))
-          (net PHI2 (joined
-           (portRef PHI2)
-           (portRef I (instanceRef PHI2_pad))
-          ))
-          (net (rename MAin_c_0 "MAin_c[0]") (joined
-           (portRef O (instanceRef MAin_pad_0))
-           (portRef A (instanceRef RowAd_0))
-           (portRef A (instanceRef un9_RA_i_m3_0))
-           (portRef D (instanceRef CmdEnable16_0_a2_0))
-           (portRef D (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef B (instanceRef CMDWR))
-           (portRef C (instanceRef CmdEnable17_0_a2))
-          ))
-          (net (rename MAin_0 "MAin[0]") (joined
-           (portRef (member main 9))
-           (portRef I (instanceRef MAin_pad_0))
-          ))
-          (net (rename MAin_c_1 "MAin_c[1]") (joined
-           (portRef O (instanceRef MAin_pad_1))
-           (portRef A (instanceRef RowAd_1))
-           (portRef A (instanceRef un9_RA_i_m3_1))
-           (portRef A (instanceRef CMDWR_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_o3_0))
-          ))
-          (net (rename MAin_1 "MAin[1]") (joined
-           (portRef (member main 8))
-           (portRef I (instanceRef MAin_pad_1))
-          ))
-          (net (rename MAin_c_2 "MAin_c[2]") (joined
-           (portRef O (instanceRef MAin_pad_2))
-           (portRef A (instanceRef RowAd_2))
-           (portRef A (instanceRef un9_RA_i_m3_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_o3_0))
-           (portRef C (instanceRef CMDWR))
-          ))
-          (net (rename MAin_2 "MAin[2]") (joined
-           (portRef (member main 7))
-           (portRef I (instanceRef MAin_pad_2))
-          ))
-          (net (rename MAin_c_3 "MAin_c[3]") (joined
-           (portRef O (instanceRef MAin_pad_3))
-           (portRef A (instanceRef RowAd_3))
-           (portRef A (instanceRef un9_RA_i_m3_3))
-           (portRef B (instanceRef CMDWR_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_o3_0_1))
-          ))
-          (net (rename MAin_3 "MAin[3]") (joined
-           (portRef (member main 6))
-           (portRef I (instanceRef MAin_pad_3))
-          ))
-          (net (rename MAin_c_4 "MAin_c[4]") (joined
-           (portRef O (instanceRef MAin_pad_4))
-           (portRef A (instanceRef RowAd_4))
-           (portRef A (instanceRef un9_RA_i_m3_4))
-           (portRef C (instanceRef CMDWR_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_o3_0_1))
-          ))
-          (net (rename MAin_4 "MAin[4]") (joined
-           (portRef (member main 5))
-           (portRef I (instanceRef MAin_pad_4))
-          ))
-          (net (rename MAin_c_5 "MAin_c[5]") (joined
-           (portRef O (instanceRef MAin_pad_5))
-           (portRef A (instanceRef RowAd_5))
-           (portRef A (instanceRef C1WR_7_0_o3_0))
-           (portRef A (instanceRef un9_RA_i_m3_5))
-          ))
-          (net (rename MAin_5 "MAin[5]") (joined
-           (portRef (member main 4))
-           (portRef I (instanceRef MAin_pad_5))
-          ))
-          (net (rename MAin_c_6 "MAin_c[6]") (joined
-           (portRef O (instanceRef MAin_pad_6))
-           (portRef A (instanceRef RowAd_6))
-           (portRef A (instanceRef un9_RA_i_m3_6))
-           (portRef D (instanceRef C1WR_7_0_o3_6))
-          ))
-          (net (rename MAin_6 "MAin[6]") (joined
-           (portRef (member main 3))
-           (portRef I (instanceRef MAin_pad_6))
-          ))
-          (net (rename MAin_c_7 "MAin_c[7]") (joined
-           (portRef O (instanceRef MAin_pad_7))
-           (portRef A (instanceRef RowAd_7))
-           (portRef B (instanceRef C1WR_7_0_o3_0))
-           (portRef A (instanceRef un9_RA_i_m3_7))
-          ))
-          (net (rename MAin_7 "MAin[7]") (joined
-           (portRef (member main 2))
-           (portRef I (instanceRef MAin_pad_7))
-          ))
-          (net (rename MAin_c_8 "MAin_c[8]") (joined
-           (portRef O (instanceRef MAin_pad_8))
-           (portRef A (instanceRef RowAd_8))
-           (portRef A (instanceRef un9_RA_8))
-          ))
-          (net (rename MAin_8 "MAin[8]") (joined
-           (portRef (member main 1))
-           (portRef I (instanceRef MAin_pad_8))
-          ))
-          (net (rename MAin_c_9 "MAin_c[9]") (joined
-           (portRef O (instanceRef MAin_pad_9))
-           (portRef A (instanceRef RowAd_9))
-           (portRef A (instanceRef RDQML_0))
-           (portRef A (instanceRef un9_RA_i_m3_9))
-           (portRef A (instanceRef RDQMH_pad_RNO))
-          ))
-          (net (rename MAin_9 "MAin[9]") (joined
-           (portRef (member main 0))
-           (portRef I (instanceRef MAin_pad_9))
-          ))
-          (net (rename CROW_c_0 "CROW_c[0]") (joined
-           (portRef O (instanceRef CROW_pad_0))
-           (portRef A (instanceRef RBAd_0))
-          ))
-          (net (rename CROW_0 "CROW[0]") (joined
-           (portRef (member crow 1))
-           (portRef I (instanceRef CROW_pad_0))
-          ))
-          (net (rename CROW_c_1 "CROW_c[1]") (joined
-           (portRef O (instanceRef CROW_pad_1))
-           (portRef A (instanceRef RBAd_1))
-          ))
-          (net (rename CROW_1 "CROW[1]") (joined
-           (portRef (member crow 0))
-           (portRef I (instanceRef CROW_pad_1))
-          ))
-          (net (rename Din_c_0 "Din_c[0]") (joined
-           (portRef O (instanceRef Din_pad_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_0))
-           (portRef A (instanceRef CmdEnable17_0_a2_0))
-           (portRef D (instanceRef CmdUFMSDI))
-           (portRef D (instanceRef Bank_0io_0))
-           (portRef D (instanceRef WRD_0io_0))
-          ))
-          (net (rename Din_0 "Din[0]") (joined
-           (portRef (member din 7))
-           (portRef I (instanceRef Din_pad_0))
-          ))
-          (net (rename Din_c_1 "Din_c[1]") (joined
-           (portRef O (instanceRef Din_pad_1))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_0))
-           (portRef B (instanceRef CmdEnable17_0_a2_0))
-           (portRef D (instanceRef CmdUFMCLK))
-           (portRef D (instanceRef Bank_0io_1))
-           (portRef D (instanceRef WRD_0io_1))
-          ))
-          (net (rename Din_1 "Din[1]") (joined
-           (portRef (member din 6))
-           (portRef I (instanceRef Din_pad_1))
-          ))
-          (net (rename Din_c_2 "Din_c[2]") (joined
-           (portRef O (instanceRef Din_pad_2))
-           (portRef A (instanceRef CmdEnable17_0_a2_1))
-           (portRef A (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef D (instanceRef CmdUFMCS))
-           (portRef D (instanceRef Bank_0io_2))
-           (portRef D (instanceRef WRD_0io_2))
-          ))
-          (net (rename Din_2 "Din[2]") (joined
-           (portRef (member din 5))
-           (portRef I (instanceRef Din_pad_2))
-          ))
-          (net (rename Din_c_3 "Din_c[3]") (joined
-           (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef D (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef B (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef CmdEnable16_0_a2_0))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef C (instanceRef XOR8MEG_3_u_0_a2_0_2))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef D (instanceRef Bank_0io_3))
-           (portRef D (instanceRef WRD_0io_3))
-          ))
-          (net (rename Din_3 "Din[3]") (joined
-           (portRef (member din 4))
-           (portRef I (instanceRef Din_pad_3))
-          ))
-          (net (rename Din_c_4 "Din_c[4]") (joined
-           (portRef O (instanceRef Din_pad_4))
-           (portRef D (instanceRef CmdEnable16_0_a2))
-           (portRef D (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef A (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef A (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef A (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef A (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef A (instanceRef un1_CmdEnable20_0_a2_0_0))
-           (portRef D (instanceRef Bank_0io_4))
-           (portRef D (instanceRef WRD_0io_4))
-          ))
-          (net (rename Din_4 "Din[4]") (joined
-           (portRef (member din 3))
-           (portRef I (instanceRef Din_pad_4))
-          ))
-          (net (rename Din_c_5 "Din_c[5]") (joined
-           (portRef O (instanceRef Din_pad_5))
-           (portRef C (instanceRef CmdEnable16_0_a2))
-           (portRef C (instanceRef CmdSubmitted_1_sqmuxa_0_a2))
-           (portRef C (instanceRef CmdUFMCLK_1_sqmuxa_0_a2))
-           (portRef A (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef C (instanceRef CmdEnable17_0_a2_1))
-           (portRef B (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef B (instanceRef CmdEnable16_0_a2_0_2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_a2_2))
-           (portRef B (instanceRef un1_CmdEnable20_0_a2_0_0))
-           (portRef D (instanceRef Bank_0io_5))
-           (portRef D (instanceRef WRD_0io_5))
-          ))
-          (net (rename Din_5 "Din[5]") (joined
-           (portRef (member din 2))
-           (portRef I (instanceRef Din_pad_5))
-          ))
-          (net (rename Din_c_6 "Din_c[6]") (joined
-           (portRef O (instanceRef Din_pad_6))
-           (portRef C (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef A (instanceRef RA11d))
-           (portRef B (instanceRef CmdEnable17_0_a2_0_2))
-           (portRef C (instanceRef CmdEnable16_0_a2_0))
-           (portRef B (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef C (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef C (instanceRef un1_CmdEnable20_0_a2_1))
-           (portRef D (instanceRef Bank_0io_6))
-           (portRef D (instanceRef WRD_0io_6))
-          ))
-          (net (rename Din_6 "Din[6]") (joined
-           (portRef (member din 1))
-           (portRef I (instanceRef Din_pad_6))
-          ))
-          (net (rename Din_c_7 "Din_c[7]") (joined
-           (portRef O (instanceRef Din_pad_7))
-           (portRef B (instanceRef CmdLEDEN_4_u_i_a2_0_0))
-           (portRef C (instanceRef Cmdn8MEGEN_4_u_i_o2_0))
-           (portRef D (instanceRef XOR8MEG_3_u_0_o3_0))
-           (portRef C (instanceRef CmdEnable17_0_a2_0))
-           (portRef D (instanceRef Bank_0io_7))
-           (portRef D (instanceRef WRD_0io_7))
-          ))
-          (net (rename Din_7 "Din[7]") (joined
-           (portRef (member din 0))
-           (portRef I (instanceRef Din_pad_7))
-          ))
-          (net (rename Dout_0 "Dout[0]") (joined
-           (portRef O (instanceRef Dout_pad_0))
-           (portRef (member dout 7))
-          ))
-          (net (rename Dout_1 "Dout[1]") (joined
-           (portRef O (instanceRef Dout_pad_1))
-           (portRef (member dout 6))
-          ))
-          (net (rename Dout_2 "Dout[2]") (joined
-           (portRef O (instanceRef Dout_pad_2))
-           (portRef (member dout 5))
-          ))
-          (net (rename Dout_3 "Dout[3]") (joined
-           (portRef O (instanceRef Dout_pad_3))
-           (portRef (member dout 4))
-          ))
-          (net (rename Dout_4 "Dout[4]") (joined
-           (portRef O (instanceRef Dout_pad_4))
-           (portRef (member dout 3))
-          ))
-          (net (rename Dout_5 "Dout[5]") (joined
-           (portRef O (instanceRef Dout_pad_5))
-           (portRef (member dout 2))
-          ))
-          (net (rename Dout_6 "Dout[6]") (joined
-           (portRef O (instanceRef Dout_pad_6))
-           (portRef (member dout 1))
-          ))
-          (net (rename Dout_7 "Dout[7]") (joined
-           (portRef O (instanceRef Dout_pad_7))
-           (portRef (member dout 0))
-          ))
-          (net nCCAS_c (joined
-           (portRef O (instanceRef nCCAS_pad))
-           (portRef A (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef nCCAS_pad_RNISUR8))
-          ))
-          (net nCCAS (joined
-           (portRef nCCAS)
-           (portRef I (instanceRef nCCAS_pad))
-          ))
-          (net nCRAS_c (joined
-           (portRef O (instanceRef nCRAS_pad))
-           (portRef C (instanceRef LED_pad_RNO))
-           (portRef A (instanceRef nCRAS_pad_RNIBPVB))
-           (portRef A (instanceRef RASr_RNO))
-          ))
-          (net nCRAS (joined
-           (portRef nCRAS)
-           (portRef I (instanceRef nCRAS_pad))
-          ))
-          (net nFWE_c (joined
-           (portRef O (instanceRef nFWE_pad))
-           (portRef D (instanceRef CMDWR_2))
-           (portRef C (instanceRef un1_CmdEnable20_0_o3_0_1))
-           (portRef B (instanceRef nCCAS_pad_RNI01SJ))
-           (portRef A (instanceRef FWEr_RNO))
-          ))
-          (net nFWE (joined
-           (portRef nFWE)
-           (portRef I (instanceRef nFWE_pad))
-          ))
-          (net LED_c (joined
-           (portRef Z (instanceRef LED_pad_RNO))
-           (portRef I (instanceRef LED_pad))
-          ))
-          (net LED (joined
-           (portRef O (instanceRef LED_pad))
-           (portRef LED)
-          ))
-          (net (rename RBA_c_0 "RBA_c[0]") (joined
-           (portRef Q (instanceRef RBA_0io_0))
-           (portRef I (instanceRef RBA_pad_0))
-          ))
-          (net (rename RBA_0 "RBA[0]") (joined
-           (portRef O (instanceRef RBA_pad_0))
-           (portRef (member rba 1))
-          ))
-          (net (rename RBA_c_1 "RBA_c[1]") (joined
-           (portRef Q (instanceRef RBA_0io_1))
-           (portRef I (instanceRef RBA_pad_1))
-          ))
-          (net (rename RBA_1 "RBA[1]") (joined
-           (portRef O (instanceRef RBA_pad_1))
-           (portRef (member rba 0))
-          ))
-          (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_0))
-           (portRef I (instanceRef RA_pad_0))
-          ))
-          (net (rename RA_0 "RA[0]") (joined
-           (portRef O (instanceRef RA_pad_0))
-           (portRef (member ra 11))
-          ))
-          (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_1))
-           (portRef I (instanceRef RA_pad_1))
-          ))
-          (net (rename RA_1 "RA[1]") (joined
-           (portRef O (instanceRef RA_pad_1))
-           (portRef (member ra 10))
-          ))
-          (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_2))
-           (portRef I (instanceRef RA_pad_2))
-          ))
-          (net (rename RA_2 "RA[2]") (joined
-           (portRef O (instanceRef RA_pad_2))
-           (portRef (member ra 9))
-          ))
-          (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_3))
-           (portRef I (instanceRef RA_pad_3))
-          ))
-          (net (rename RA_3 "RA[3]") (joined
-           (portRef O (instanceRef RA_pad_3))
-           (portRef (member ra 8))
-          ))
-          (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_4))
-           (portRef I (instanceRef RA_pad_4))
-          ))
-          (net (rename RA_4 "RA[4]") (joined
-           (portRef O (instanceRef RA_pad_4))
-           (portRef (member ra 7))
-          ))
-          (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_5))
-           (portRef I (instanceRef RA_pad_5))
-          ))
-          (net (rename RA_5 "RA[5]") (joined
-           (portRef O (instanceRef RA_pad_5))
-           (portRef (member ra 6))
-          ))
-          (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_6))
-           (portRef I (instanceRef RA_pad_6))
-          ))
-          (net (rename RA_6 "RA[6]") (joined
-           (portRef O (instanceRef RA_pad_6))
-           (portRef (member ra 5))
-          ))
-          (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_7))
-           (portRef I (instanceRef RA_pad_7))
-          ))
-          (net (rename RA_7 "RA[7]") (joined
-           (portRef O (instanceRef RA_pad_7))
-           (portRef (member ra 4))
-          ))
-          (net (rename RA_c_8 "RA_c[8]") (joined
-           (portRef Z (instanceRef un9_RA_8))
-           (portRef I (instanceRef RA_pad_8))
-          ))
-          (net (rename RA_8 "RA[8]") (joined
-           (portRef O (instanceRef RA_pad_8))
-           (portRef (member ra 3))
-          ))
-          (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Z (instanceRef un9_RA_i_m3_9))
-           (portRef I (instanceRef RA_pad_9))
-          ))
-          (net (rename RA_9 "RA[9]") (joined
-           (portRef O (instanceRef RA_pad_9))
-           (portRef (member ra 2))
-          ))
-          (net (rename RA_c_10 "RA_c[10]") (joined
-           (portRef Q (instanceRef RA10_0io))
-           (portRef I (instanceRef RA_pad_10))
-          ))
-          (net (rename RA_10 "RA[10]") (joined
-           (portRef O (instanceRef RA_pad_10))
-           (portRef (member ra 1))
-          ))
-          (net (rename RA_c_11 "RA_c[11]") (joined
-           (portRef Q (instanceRef RA11_0io))
-           (portRef I (instanceRef RA_pad_11))
-          ))
-          (net (rename RA_11 "RA[11]") (joined
-           (portRef O (instanceRef RA_pad_11))
-           (portRef (member ra 0))
-          ))
-          (net (rename RD_in_0 "RD_in[0]") (joined
-           (portRef O (instanceRef RD_pad_0))
-           (portRef I (instanceRef Dout_pad_0))
-          ))
-          (net (rename RD_0 "RD[0]") (joined
-           (portRef B (instanceRef RD_pad_0))
-           (portRef (member rd 7))
-          ))
-          (net (rename RD_in_1 "RD_in[1]") (joined
-           (portRef O (instanceRef RD_pad_1))
-           (portRef I (instanceRef Dout_pad_1))
-          ))
-          (net (rename RD_1 "RD[1]") (joined
-           (portRef B (instanceRef RD_pad_1))
-           (portRef (member rd 6))
-          ))
-          (net (rename RD_in_2 "RD_in[2]") (joined
-           (portRef O (instanceRef RD_pad_2))
-           (portRef I (instanceRef Dout_pad_2))
-          ))
-          (net (rename RD_2 "RD[2]") (joined
-           (portRef B (instanceRef RD_pad_2))
-           (portRef (member rd 5))
-          ))
-          (net (rename RD_in_3 "RD_in[3]") (joined
-           (portRef O (instanceRef RD_pad_3))
-           (portRef I (instanceRef Dout_pad_3))
-          ))
-          (net (rename RD_3 "RD[3]") (joined
-           (portRef B (instanceRef RD_pad_3))
-           (portRef (member rd 4))
-          ))
-          (net (rename RD_in_4 "RD_in[4]") (joined
-           (portRef O (instanceRef RD_pad_4))
-           (portRef I (instanceRef Dout_pad_4))
-          ))
-          (net (rename RD_4 "RD[4]") (joined
-           (portRef B (instanceRef RD_pad_4))
-           (portRef (member rd 3))
-          ))
-          (net (rename RD_in_5 "RD_in[5]") (joined
-           (portRef O (instanceRef RD_pad_5))
-           (portRef I (instanceRef Dout_pad_5))
-          ))
-          (net (rename RD_5 "RD[5]") (joined
-           (portRef B (instanceRef RD_pad_5))
-           (portRef (member rd 2))
-          ))
-          (net (rename RD_in_6 "RD_in[6]") (joined
-           (portRef O (instanceRef RD_pad_6))
-           (portRef I (instanceRef Dout_pad_6))
-          ))
-          (net (rename RD_6 "RD[6]") (joined
-           (portRef B (instanceRef RD_pad_6))
-           (portRef (member rd 1))
-          ))
-          (net (rename RD_in_7 "RD_in[7]") (joined
-           (portRef O (instanceRef RD_pad_7))
-           (portRef I (instanceRef Dout_pad_7))
-          ))
-          (net (rename RD_7 "RD[7]") (joined
-           (portRef B (instanceRef RD_pad_7))
-           (portRef (member rd 0))
-          ))
-          (net nRCS_c (joined
-           (portRef Q (instanceRef nRCS_0io))
-           (portRef I (instanceRef nRCS_pad))
-          ))
-          (net nRCS (joined
-           (portRef O (instanceRef nRCS_pad))
-           (portRef nRCS)
-          ))
-          (net RCLK_c (joined
-           (portRef O (instanceRef RCLK_pad))
-           (portRef CK (instanceRef CASr))
-           (portRef CK (instanceRef CASr2))
-           (portRef CK (instanceRef CASr3))
-           (portRef CK (instanceRef FS_17))
-           (portRef CK (instanceRef FS_16))
-           (portRef CK (instanceRef FS_15))
-           (portRef CK (instanceRef FS_14))
-           (portRef CK (instanceRef FS_13))
-           (portRef CK (instanceRef FS_12))
-           (portRef CK (instanceRef FS_11))
-           (portRef CK (instanceRef FS_10))
-           (portRef CK (instanceRef FS_9))
-           (portRef CK (instanceRef FS_8))
-           (portRef CK (instanceRef FS_7))
-           (portRef CK (instanceRef FS_6))
-           (portRef CK (instanceRef FS_5))
-           (portRef CK (instanceRef FS_4))
-           (portRef CK (instanceRef FS_3))
-           (portRef CK (instanceRef FS_2))
-           (portRef CK (instanceRef FS_1))
-           (portRef CK (instanceRef FS_0))
-           (portRef CK (instanceRef IS_3))
-           (portRef CK (instanceRef IS_2))
-           (portRef CK (instanceRef IS_1))
-           (portRef CK (instanceRef IS_0))
-           (portRef CK (instanceRef InitReady))
-           (portRef CK (instanceRef LEDEN))
-           (portRef CK (instanceRef PHI2r2))
-           (portRef CK (instanceRef PHI2r3))
-           (portRef CK (instanceRef RASr))
-           (portRef CK (instanceRef RASr2))
-           (portRef CK (instanceRef RASr3))
-           (portRef CK (instanceRef RCKE))
-           (portRef CK (instanceRef RCKEEN))
-           (portRef CK (instanceRef Ready))
-           (portRef CK (instanceRef Ready_fast))
-           (portRef CK (instanceRef S_1))
-           (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef UFMSDI))
-           (portRef CK (instanceRef n8MEGEN))
-           (portRef CK (instanceRef nRowColSel))
-           (portRef CK (instanceRef nUFMCS))
-           (portRef SCLK (instanceRef RA10_0io))
-           (portRef SCLK (instanceRef UFMCLK_0io))
-           (portRef SCLK (instanceRef nRCAS_0io))
-           (portRef SCLK (instanceRef nRCS_0io))
-           (portRef SCLK (instanceRef nRRAS_0io))
-           (portRef SCLK (instanceRef nRWE_0io))
-           (portRef SCLK (instanceRef PHI2r_0io))
-          ))
-          (net RCLK (joined
-           (portRef RCLK)
-           (portRef I (instanceRef RCLK_pad))
-          ))
-          (net RCKE_c (joined
-           (portRef Q (instanceRef RCKE))
-           (portRef C (instanceRef nRRAS_5_u_i_0))
-           (portRef B (instanceRef nRWE_s_i_tz_0))
-           (portRef I (instanceRef RCKE_pad))
-          ))
-          (net RCKE (joined
-           (portRef O (instanceRef RCKE_pad))
-           (portRef RCKE)
-          ))
-          (net nRWE_c (joined
-           (portRef Q (instanceRef nRWE_0io))
-           (portRef I (instanceRef nRWE_pad))
-          ))
-          (net nRWE (joined
-           (portRef O (instanceRef nRWE_pad))
-           (portRef nRWE)
-          ))
-          (net nRRAS_c (joined
-           (portRef Q (instanceRef nRRAS_0io))
-           (portRef I (instanceRef nRRAS_pad))
-          ))
-          (net nRRAS (joined
-           (portRef O (instanceRef nRRAS_pad))
-           (portRef nRRAS)
-          ))
-          (net nRCAS_c (joined
-           (portRef Q (instanceRef nRCAS_0io))
-           (portRef I (instanceRef nRCAS_pad))
-          ))
-          (net nRCAS (joined
-           (portRef O (instanceRef nRCAS_pad))
-           (portRef nRCAS)
-          ))
-          (net RDQMH_c (joined
-           (portRef Z (instanceRef RDQMH_pad_RNO))
-           (portRef I (instanceRef RDQMH_pad))
-          ))
-          (net RDQMH (joined
-           (portRef O (instanceRef RDQMH_pad))
-           (portRef RDQMH)
-          ))
-          (net RDQML_c (joined
-           (portRef Z (instanceRef RDQML_0))
-           (portRef I (instanceRef RDQML_pad))
-          ))
-          (net RDQML (joined
-           (portRef O (instanceRef RDQML_pad))
-           (portRef RDQML)
-          ))
-          (net nUFMCS_c (joined
-           (portRef Q (instanceRef nUFMCS))
-           (portRef D (instanceRef nUFMCS_s_0_N_5_i))
-           (portRef I (instanceRef nUFMCS_pad))
-          ))
-          (net nUFMCS (joined
-           (portRef O (instanceRef nUFMCS_pad))
-           (portRef nUFMCS)
-          ))
-          (net UFMCLK_c (joined
-           (portRef Q (instanceRef UFMCLK_0io))
-           (portRef I (instanceRef UFMCLK_pad))
-          ))
-          (net UFMCLK (joined
-           (portRef O (instanceRef UFMCLK_pad))
-           (portRef UFMCLK)
-          ))
-          (net UFMSDI_c (joined
-           (portRef Q (instanceRef UFMSDI))
-           (portRef I (instanceRef UFMSDI_pad))
-           (portRef A (instanceRef UFMSDI_RNO_1))
-          ))
-          (net UFMSDI (joined
-           (portRef O (instanceRef UFMSDI_pad))
-           (portRef UFMSDI)
-          ))
-          (net UFMSDO_c (joined
-           (portRef O (instanceRef UFMSDO_pad))
-           (portRef C (instanceRef n8MEGEN_5_i_m2))
-          ))
-          (net UFMSDO (joined
-           (portRef UFMSDO)
-           (portRef I (instanceRef UFMSDO_pad))
-          ))
-          (net N_415_0 (joined
-           (portRef Z (instanceRef CmdSubmitted_RNO))
-           (portRef D (instanceRef CmdSubmitted))
-          ))
-          (net N_416_0 (joined
-           (portRef Z (instanceRef InitReady_RNO))
-           (portRef D (instanceRef InitReady))
-          ))
-          (net N_417_0 (joined
-           (portRef Z (instanceRef Ready_RNO))
-           (portRef D (instanceRef Ready))
-          ))
-          (net N_418_0 (joined
-           (portRef Z (instanceRef Ready_fast_RNO))
-           (portRef D (instanceRef Ready_fast))
-          ))
-          (net nFWE_c_i (joined
-           (portRef Z (instanceRef FWEr_RNO))
-           (portRef D (instanceRef FWEr))
-          ))
-          (net nCRAS_c_i_0 (joined
-           (portRef Z (instanceRef RASr_RNO))
-           (portRef D (instanceRef RASr))
-          ))
-          (net nCCAS_c_i (joined
-           (portRef Z (instanceRef nCCAS_pad_RNISUR8))
-           (portRef D (instanceRef CASr))
-           (portRef D (instanceRef CBR))
-           (portRef SCLK (instanceRef WRD_0io_7))
-           (portRef SCLK (instanceRef WRD_0io_6))
-           (portRef SCLK (instanceRef WRD_0io_5))
-           (portRef SCLK (instanceRef WRD_0io_4))
-           (portRef SCLK (instanceRef WRD_0io_3))
-           (portRef SCLK (instanceRef WRD_0io_2))
-           (portRef SCLK (instanceRef WRD_0io_1))
-           (portRef SCLK (instanceRef WRD_0io_0))
-          ))
-          (net (rename IS_i_0 "IS_i[0]") (joined
-           (portRef Z (instanceRef RA10_0io_RNO))
-           (portRef D (instanceRef RA10_0io))
-          ))
-          (net RASr2_i (joined
-           (portRef Z (instanceRef RASr2_RNIAFR1))
-           (portRef CD (instanceRef S_1))
-           (portRef CD (instanceRef S_0))
-          ))
-          (net UFMSDI_RNO_1 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_1))
-           (portRef BLUT (instanceRef UFMSDI_RNO))
-          ))
-          (net UFMSDI_RNO_0 (joined
-           (portRef Z (instanceRef UFMSDI_RNO_0))
-           (portRef ALUT (instanceRef UFMSDI_RNO))
-          ))
-          (net N_1 (joined
-           (portRef CIN (instanceRef FS_cry_0_0))
-          ))
-         )
-        (property orig_inst_of (string "RAM2GS"))
-       )
-    )
-  )
-  (design RAM2GS (cellRef RAM2GS (libraryRef work))
-	(property PART (string "lcmxo2_640hc-4") ))
-)
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm
deleted file mode 100644
index c490adf..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.htm
+++ /dev/null
@@ -1,9 +0,0 @@
-
- 
- syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm log file
- 
- 
- 
- 				 
-
- 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
deleted file mode 100644
index d0353b8..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
+++ /dev/null
@@ -1,4 +0,0 @@
----- MParTrce Tool Log File ----
-
-==== Par Standard Out ====
-==== End of Par Standard Out ====
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
deleted file mode 100644
index 2743d95..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
+++ /dev/null
@@ -1,4 +0,0 @@
-#BLOCK ASYNCPATHS;
-#BLOCK RESETPATHS;
-
-#FREQUENCY 200.000000 MHz;
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
deleted file mode 100644
index 83564a7..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
+++ /dev/null
@@ -1,6331 +0,0 @@
-
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diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
deleted file mode 100644
index 2d70ad1..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
+++ /dev/null
@@ -1,9 +0,0 @@
--v
-1
-
-
--gt
-
-
--mapchkpnt 0
--sethld
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd
deleted file mode 100644
index b1a670d..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd
deleted file mode 100644
index 7aed624..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngo
deleted file mode 100644
index f3a26c7..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngo and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t
deleted file mode 100644
index 16daf53..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t
+++ /dev/null
@@ -1,9 +0,0 @@
--w
--l 5
--i 6
--n 1
--t 1
--s 1
--c 0
--e 0
--exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t
deleted file mode 100644
index 6ff5632..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t
+++ /dev/null
@@ -1,5 +0,0 @@
--rem
--distrce
--log "RAM2GS_LCMXO2_640HC_impl1.log"
--o "RAM2GS_LCMXO2_640HC_impl1.csv"
--pr "RAM2GS_LCMXO2_640HC_impl1.prf"
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par
deleted file mode 100644
index 0d7d1ec..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par
+++ /dev/null
@@ -1,242 +0,0 @@
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:05 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-
-
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            5.827        0            0.304        0            06           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Tue Aug 15 23:30:05 2023
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-Device utilization summary:
-
-   PIO (prelim)   67+4(JTAG)/80      89% used
-                  67+4(JTAG)/79      90% bonded
-   IOLOGIC           29/80           36% used
-
-   SLICE             81/320          25% used
-
-
-
-Number of Signals: 292
-Number of Connections: 703
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 18)
-
-WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 2 signals are selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
-    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-...........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-....................
-Placer score = 41844.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  41803
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
------------------- Clock Report ------------------
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 4 out of 80 (5%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
-  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 8 (25%)
-  SECONDARY: 2 out of 8 (25%)
-
---------------- End of Clock Report ---------------
-
-
-I/O Usage Summary (final):
-   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
-   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
-| 1        | 20 / 20 (100%) | 3.3V       | -         |
-| 2        | 16 / 20 ( 80%) | 3.3V       | -         |
-| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 703 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 23:30:11 08/15/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 23:30:11 08/15/23
-
-Start NBR section for initial routing at 23:30:11 08/15/23
-Level 1, iteration 1
-0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 23:30:11 08/15/23
-Level 4, iteration 1
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23
-
-Start NBR section for re-routing at 23:30:11 08/15/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 23:30:11 08/15/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 5.827ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  703 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 5.827
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.304
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
deleted file mode 100644
index e5e32de..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt
+++ /dev/null
@@ -1,10 +0,0 @@
--v
-10
-
-
-
-
--gt
--sethld
--sp 4
--sphld m
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srd
deleted file mode 100644
index 0c57533..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf
deleted file mode 100644
index f622489..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf
+++ /dev/null
@@ -1,964 +0,0 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Tue Aug 15 23:12:41 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:42 2023
-
-###########################################################]
-# Tue Aug 15 23:12:42 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
-
-###########################################################]
-# Tue Aug 15 23:12:44 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -2.04ns		 140 /        90
-
-
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.389
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
-
-    - Propagation time:                      3.214
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
-========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.853
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srm
deleted file mode 100644
index 33a15e2..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr
deleted file mode 100644
index f622489..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr
+++ /dev/null
@@ -1,964 +0,0 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Tue Aug 15 23:12:41 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:42 2023
-
-###########################################################]
-# Tue Aug 15 23:12:42 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
-
-###########################################################]
-# Tue Aug 15 23:12:44 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -2.04ns		 140 /        90
-
-
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.389
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
-
-    - Propagation time:                      3.214
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
-========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.853
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr.db b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr.db
deleted file mode 100644
index 5deabf5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srs b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srs
deleted file mode 100644
index 2e048d5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
deleted file mode 100644
index 8c774fb..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
+++ /dev/null
@@ -1,417 +0,0 @@
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:32 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:              10.424ns  (36.2% logic, 63.8% route), 7 logic levels.
-
- Constraint Details:
-
-     10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1   e 1.234 *n[3]_MGIOL.IN to    SLICE_43.C1 Bank[3]
-CTOF_DEL    ---     0.495    SLICE_43.C1 to    SLICE_43.F1 SLICE_43
-ROUTE         1   e 1.234    SLICE_43.F1 to    SLICE_69.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495    SLICE_69.D0 to    SLICE_69.F0 SLICE_69
-ROUTE         5   e 1.234    SLICE_69.F0 to    SLICE_60.D0 un1_Bank_1
-CTOF_DEL    ---     0.495    SLICE_60.D0 to    SLICE_60.F0 SLICE_60
-ROUTE         2   e 1.234    SLICE_60.F0 to    SLICE_46.A1 ADWR
-CTOF_DEL    ---     0.495    SLICE_46.A1 to    SLICE_46.F1 SLICE_46
-ROUTE         3   e 0.480    SLICE_46.F1 to    SLICE_46.D0 un1_ADWR
-CTOF_DEL    ---     0.495    SLICE_46.D0 to    SLICE_46.F0 SLICE_46
-ROUTE         1   e 1.234    SLICE_46.F0 to    SLICE_18.C0 un1_CMDWR
-CTOOFX_DEL  ---     0.721    SLICE_18.C0 to  SLICE_18.OFX0 SLICE_18
-ROUTE         1   e 0.001  SLICE_18.OFX0 to   SLICE_18.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                   10.424   (36.2% logic, 63.8% route), 7 logic levels.
-
-Report:   47.214MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 4.412ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
-
- Constraint Details:
-
-     11.306ns physical path delay SLICE_1 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3   e 1.234     SLICE_1.Q0 to    SLICE_72.D1 FS[17]
-CTOF_DEL    ---     0.495    SLICE_72.D1 to    SLICE_72.F1 SLICE_72
-ROUTE         1   e 1.234    SLICE_72.F1 to    SLICE_64.C1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_59.C1 N_129
-CTOF_DEL    ---     0.495    SLICE_59.C1 to    SLICE_59.F1 SLICE_59
-ROUTE         2   e 0.480    SLICE_59.F1 to    SLICE_59.D0 N_145
-CTOF_DEL    ---     0.495    SLICE_59.D0 to    SLICE_59.F0 SLICE_59
-ROUTE         2   e 1.234    SLICE_59.F0 to    SLICE_56.B0 N_139_8
-CTOF_DEL    ---     0.495    SLICE_56.B0 to    SLICE_56.F0 SLICE_56
-ROUTE         1   e 1.234    SLICE_56.F0 to    SLICE_54.C0 N_140
-CTOF_DEL    ---     0.495    SLICE_54.C0 to    SLICE_54.F0 SLICE_54
-ROUTE         1   e 1.234    SLICE_54.F0 to    SLICE_27.CE N_28 (to RCLK_c)
-                  --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
-
-Report:   86.296MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   47.214 MHz|   7  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   86.296 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:32 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_10 to SLICE_10 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_10.CLK to    SLICE_10.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2   e 0.199    SLICE_10.Q0 to    SLICE_10.A0 ADSubmitted
-CTOF_DEL    ---     0.101    SLICE_10.A0 to    SLICE_10.F0 SLICE_10
-ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.332ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_14.Q0 to    SLICE_14.M1 CASr (to RCLK_c)
-                  --------
-                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
deleted file mode 100644
index b451cd5..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
+++ /dev/null
@@ -1,2253 +0,0 @@
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:39 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 163.401ns (weighted slack = 326.802ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.950ns  (28.6% logic, 71.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.950ns physical path delay Din[3]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.401ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.950   (28.6% logic, 71.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.452ns (weighted slack = 326.904ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.899ns  (28.7% logic, 71.3% route), 5 logic levels.
-
- Constraint Details:
-
-      8.899ns physical path delay Din[7]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.452ns
-
- Physical Path Details:
-
-      Data path Din[7]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_L2A.CLK to     IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_L2A.IN to       R3C6A.D1 Bank[7]
-CTOF_DEL    ---     0.495       R3C6A.D1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.899   (28.7% logic, 71.3% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[7]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.522ns (weighted slack = 327.044ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[4]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.829ns  (29.0% logic, 71.0% route), 5 logic levels.
-
- Constraint Details:
-
-      8.829ns physical path delay Din[4]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.522ns
-
- Physical Path Details:
-
-      Data path Din[4]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6A.CLK to     IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_T6A.IN to       R4C6A.D1 Bank[4]
-CTOF_DEL    ---     0.495       R4C6A.D1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.829   (29.0% logic, 71.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.573ns (weighted slack = 327.146ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.502ns  (44.4% logic, 55.6% route), 7 logic levels.
-
- Constraint Details:
-
-      8.502ns physical path delay Din[3]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.573ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.502   (44.4% logic, 55.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.624ns (weighted slack = 327.248ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.451ns  (44.6% logic, 55.4% route), 7 logic levels.
-
- Constraint Details:
-
-      8.451ns physical path delay Din[7]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.624ns
-
- Physical Path Details:
-
-      Data path Din[7]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_L2A.CLK to     IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_L2A.IN to       R3C6A.D1 Bank[7]
-CTOF_DEL    ---     0.495       R3C6A.D1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.451   (44.6% logic, 55.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[7]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.694ns (weighted slack = 327.388ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[4]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.381ns  (45.0% logic, 55.0% route), 7 logic levels.
-
- Constraint Details:
-
-      8.381ns physical path delay Din[4]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.694ns
-
- Physical Path Details:
-
-      Data path Din[4]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6A.CLK to     IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_T6A.IN to       R4C6A.D1 Bank[4]
-CTOF_DEL    ---     0.495       R4C6A.D1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.381   (45.0% logic, 55.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.812ns (weighted slack = 327.624ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.712ns  (27.9% logic, 72.1% route), 5 logic levels.
-
- Constraint Details:
-
-      8.712ns physical path delay SLICE_63 to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-     -0.173ns skew and
-      0.063ns CE_SET requirement (totaling 172.524ns) by 163.812ns
-
- Physical Path Details:
-
-      Data path SLICE_63 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C7A.CLK to       R4C7A.Q0 SLICE_63 (from PHI2_c)
-ROUTE         1     1.383       R4C7A.Q0 to       R4C6A.A1 Bank[0]
-CTOF_DEL    ---     0.495       R4C6A.A1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.712   (27.9% logic, 72.1% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R4C7A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.984ns (weighted slack = 327.968ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.264ns  (44.1% logic, 55.9% route), 7 logic levels.
-
- Constraint Details:
-
-      8.264ns physical path delay SLICE_63 to SLICE_18 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 172.248ns) by 163.984ns
-
- Physical Path Details:
-
-      Data path SLICE_63 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C7A.CLK to       R4C7A.Q0 SLICE_63 (from PHI2_c)
-ROUTE         1     1.383       R4C7A.Q0 to       R4C6A.A1 Bank[0]
-CTOF_DEL    ---     0.495       R4C6A.A1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.264   (44.1% logic, 55.9% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R4C7A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 164.041ns (weighted slack = 328.082ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               8.034ns  (38.0% logic, 62.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.034ns physical path delay Din[3]_MGIOL to SLICE_10 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 164.041ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8B.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8B.C1 to       R3C8B.F1 SLICE_10
-ROUTE         2     1.013       R3C8B.F1 to       R3C8B.B0 CmdEnable17
-CTOF_DEL    ---     0.495       R3C8B.B0 to       R3C8B.F0 SLICE_10
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    8.034   (38.0% logic, 62.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 164.046ns (weighted slack = 328.092ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[2]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.478ns  (28.7% logic, 71.3% route), 5 logic levels.
-
- Constraint Details:
-
-      8.478ns physical path delay SLICE_68 to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-     -0.173ns skew and
-      0.063ns CE_SET requirement (totaling 172.524ns) by 164.046ns
-
- Physical Path Details:
-
-      Data path SLICE_68 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R3C9C.CLK to       R3C9C.Q0 SLICE_68 (from PHI2_c)
-ROUTE         1     1.079       R3C9C.Q0 to       R3C6A.C1 Bank[2]
-CTOF_DEL    ---     0.495       R3C6A.C1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.478   (28.7% logic, 71.3% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_68:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C9C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   55.475MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 6.127ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.591ns  (35.7% logic, 64.3% route), 7 logic levels.
-
- Constraint Details:
-
-      9.591ns physical path delay SLICE_4 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.127ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.177       R6C4C.Q1 to       R6C5D.C1 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.C1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.591   (35.7% logic, 64.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.287ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.431ns  (36.3% logic, 63.7% route), 7 logic levels.
-
- Constraint Details:
-
-      9.431ns physical path delay SLICE_1 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.287ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3     1.017       R6C5B.Q0 to       R6C5D.B1 FS[17]
-CTOF_DEL    ---     0.495       R6C5D.B1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.431   (36.3% logic, 63.7% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.319ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.399ns  (36.4% logic, 63.6% route), 7 logic levels.
-
- Constraint Details:
-
-      9.399ns physical path delay SLICE_3 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.319ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.985       R6C4D.Q0 to       R6C5D.A1 FS[13]
-CTOF_DEL    ---     0.495       R6C5D.A1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.399   (36.4% logic, 63.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.646ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[14]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.072ns  (37.7% logic, 62.3% route), 7 logic levels.
-
- Constraint Details:
-
-      9.072ns physical path delay SLICE_3 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.646ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     0.658       R6C4D.Q1 to       R6C5D.D1 FS[14]
-CTOF_DEL    ---     0.495       R6C5D.D1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.072   (37.7% logic, 62.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.977ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.741ns  (39.1% logic, 60.9% route), 7 logic levels.
-
- Constraint Details:
-
-      8.741ns physical path delay SLICE_4 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.977ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.177       R6C4C.Q1 to       R6C5D.C1 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.C1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.741   (39.1% logic, 60.9% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.097ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[16]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.621ns  (34.0% logic, 66.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.621ns physical path delay SLICE_2 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.097ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q1 SLICE_2 (from RCLK_c)
-ROUTE         4     1.017       R6C5A.Q1 to       R6C5C.B1 FS[16]
-CTOF_DEL    ---     0.495       R6C5C.B1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    8.621   (34.0% logic, 66.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.137ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.581ns  (39.9% logic, 60.1% route), 7 logic levels.
-
- Constraint Details:
-
-      8.581ns physical path delay SLICE_1 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.137ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3     1.017       R6C5B.Q0 to       R6C5D.B1 FS[17]
-CTOF_DEL    ---     0.495       R6C5D.B1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.581   (39.9% logic, 60.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.169ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.549ns  (40.0% logic, 60.0% route), 7 logic levels.
-
- Constraint Details:
-
-      8.549ns physical path delay SLICE_3 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.169ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.985       R6C4D.Q0 to       R6C5D.A1 FS[13]
-CTOF_DEL    ---     0.495       R6C5D.A1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.549   (40.0% logic, 60.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.281ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_0io  (to RCLK_c +)
-
-   Delay:               8.739ns  (27.8% logic, 72.2% route), 5 logic levels.
-
- Constraint Details:
-
-      8.739ns physical path delay SLICE_4 to UFMCLK_MGIOL meets
-     16.000ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 16.020ns) by 7.281ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to UFMCLK_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.434       R6C4C.Q1 to       R6C5D.B0 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.B0 to       R6C5D.F0 SLICE_72
-ROUTE         2     1.902       R6C5D.F0 to       R5C5C.A1 N_137_5
-CTOF_DEL    ---     0.495       R5C5C.A1 to       R5C5C.F1 SLICE_48
-ROUTE         2     0.982       R5C5C.F1 to       R5C5C.A0 UFMCLK_r_i_a2_2_2
-CTOF_DEL    ---     0.495       R5C5C.A0 to       R5C5C.F0 SLICE_48
-ROUTE         1     0.693       R5C5C.F0 to       R5C5D.B0 d_m3_0_a2_0
-CTOF_DEL    ---     0.495       R5C5D.B0 to       R5C5D.F0 SLICE_47
-ROUTE         1     1.296       R5C5D.F0 to   IOL_B4C.OPOS i1_i (to RCLK_c)
-                  --------
-                    8.739   (27.8% logic, 72.2% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to UFMCLK_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.243       62.PADDI to    IOL_B4C.CLK RCLK_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.354ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.364ns  (35.0% logic, 65.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.364ns physical path delay SLICE_2 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.354ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     0.760       R6C5A.Q0 to       R6C5C.C1 FS[15]
-CTOF_DEL    ---     0.495       R6C5C.C1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    8.364   (35.0% logic, 65.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  101.286MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   55.475 MHz|   5  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  101.286 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:39 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_10 to SLICE_10 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 ADSubmitted
-CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_10
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_13 to SLICE_13 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_13 (from PHI2_c)
-ROUTE         2     0.132       R3C8A.Q0 to       R3C8A.A0 C1Submitted
-CTOF_DEL    ---     0.101       R3C8A.A0 to       R3C8A.F0 SLICE_13
-ROUTE         1     0.000       R3C8A.F0 to      R3C8A.DI0 C1Submitted_s (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_20 to SLICE_20 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_20 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C8B.CLK to       R4C8B.Q0 SLICE_20 (from PHI2_c)
-ROUTE         4     0.132       R4C8B.Q0 to       R4C8B.A0 CmdSubmitted
-CTOF_DEL    ---     0.101       R4C8B.A0 to       R4C8B.F0 SLICE_20
-ROUTE         1     0.000       R4C8B.F0 to      R4C8B.DI0 N_412_0 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R4C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R4C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_42 to SLICE_42 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_42 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q0 SLICE_42 (from PHI2_c)
-ROUTE         2     0.132       R5C9B.Q0 to       R5C9B.A0 XOR8MEG
-CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_42
-ROUTE         1     0.000       R5C9B.F0 to      R5C9B.DI0 XOR8MEG_3 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.435ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.422ns  (68.5% logic, 31.5% route), 2 logic levels.
-
- Constraint Details:
-
-      0.422ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.435ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8C.CLK to       R3C8C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         3     0.133       R3C8C.Q0 to       R3C8C.A0 CmdEnable
-CTOOFX_DEL  ---     0.156       R3C8C.A0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.422   (68.5% logic, 31.5% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.440ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.427ns  (67.7% logic, 32.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.427ns physical path delay SLICE_10 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.440ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2     0.138       R3C8B.Q0 to       R3C8C.C1 ADSubmitted
-CTOOFX_DEL  ---     0.156       R3C8C.C1 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.427   (67.7% logic, 32.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.526ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.513ns  (56.3% logic, 43.7% route), 2 logic levels.
-
- Constraint Details:
-
-      0.513ns physical path delay SLICE_13 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.526ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_13 (from PHI2_c)
-ROUTE         2     0.224       R3C8A.Q0 to       R3C8C.B0 C1Submitted
-CTOOFX_DEL  ---     0.156       R3C8C.B0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.513   (56.3% logic, 43.7% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.527ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.514ns  (56.2% logic, 43.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.514ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.527ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8C.CLK to       R3C8C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         3     0.225       R3C8C.Q0 to       R3C8C.B1 CmdEnable
-CTOOFX_DEL  ---     0.156       R3C8C.B1 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.514   (56.2% logic, 43.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.616ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDEN  (from PHI2_c -)
-   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
-
-   Delay:               0.603ns  (55.6% logic, 44.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.603ns physical path delay SLICE_19 to SLICE_19 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.616ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C8B.CLK to       R5C8B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.212       R5C8B.Q0 to       R5C8A.A1 CmdLEDEN
-CTOF_DEL    ---     0.101       R5C8A.A1 to       R5C8A.F1 SLICE_70
-ROUTE         1     0.056       R5C8A.F1 to       R5C8B.C0 N_59
-CTOF_DEL    ---     0.101       R5C8B.C0 to       R5C8B.F0 SLICE_19
-ROUTE         1     0.000       R5C8B.F0 to      R5C8B.DI0 N_14_i (to PHI2_c)
-                  --------
-                    0.603   (55.6% logic, 44.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.702ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Cmdn8MEGEN  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)
-
-   Delay:               0.689ns  (48.6% logic, 51.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.689ns physical path delay SLICE_21 to SLICE_21 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.702ns
-
- Physical Path Details:
-
-      Data path SLICE_21 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C8D.CLK to       R5C8D.Q0 SLICE_21 (from PHI2_c)
-ROUTE         2     0.224       R5C8D.Q0 to       R5C8C.B1 Cmdn8MEGEN
-CTOF_DEL    ---     0.101       R5C8C.B1 to       R5C8C.F1 SLICE_50
-ROUTE         1     0.130       R5C8C.F1 to       R5C8D.A0 Cmdn8MEGEN_4_u_i_0
-CTOF_DEL    ---     0.101       R5C8D.A0 to       R5C8D.F0 SLICE_21
-ROUTE         1     0.000       R5C8D.F0 to      R5C8D.DI0 N_12_i (to PHI2_c)
-                  --------
-                    0.689   (48.6% logic, 51.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8D.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8D.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9A.CLK to       R5C9A.Q0 SLICE_14 (from RCLK_c)
-ROUTE         1     0.152       R5C9A.Q0 to       R5C9A.M1 CASr (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.309ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr  (from RCLK_c +)
-   Destination:    FF         Data in        RASr2  (to RCLK_c +)
-
-   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.290ns physical path delay SLICE_29 to SLICE_29 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.309ns
-
- Physical Path Details:
-
-      Data path SLICE_29 to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R6C12B.CLK to      R6C12B.Q0 SLICE_29 (from RCLK_c)
-ROUTE         2     0.157      R6C12B.Q0 to      R6C12B.M1 RASr (to RCLK_c)
-                  --------
-                    0.290   (45.9% logic, 54.1% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.311ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr2  (from RCLK_c +)
-   Destination:    FF         Data in        RASr3  (to RCLK_c +)
-
-   Delay:               0.292ns  (45.5% logic, 54.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.292ns physical path delay SLICE_29 to SLICE_32 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.311ns
-
- Physical Path Details:
-
-      Data path SLICE_29 to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R6C12B.CLK to      R6C12B.Q1 SLICE_29 (from RCLK_c)
-ROUTE        10     0.159      R6C12B.Q1 to      R6C12A.M1 RASr2 (to RCLK_c)
-                  --------
-                    0.292   (45.5% logic, 54.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.311ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r2  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r3  (to RCLK_c +)
-
-   Delay:               0.292ns  (45.5% logic, 54.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.292ns physical path delay SLICE_65 to SLICE_65 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.311ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C4B.CLK to       R4C4B.Q0 SLICE_65 (from RCLK_c)
-ROUTE         3     0.159       R4C4B.Q0 to       R4C4B.M1 PHI2r2 (to RCLK_c)
-                  --------
-                    0.292   (45.5% logic, 54.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R4C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R4C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[0]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[0]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C3A.CLK to       R6C3A.Q1 SLICE_0 (from RCLK_c)
-ROUTE         3     0.132       R6C3A.Q1 to       R6C3A.A1 FS[0]
-CTOF_DEL    ---     0.101       R6C3A.A1 to       R6C3A.F1 SLICE_0
-ROUTE         1     0.000       R6C3A.F1 to      R6C3A.DI1 FS_s[0] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[13]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_3 to SLICE_3 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.132       R6C4D.Q0 to       R6C4D.A0 FS[13]
-CTOF_DEL    ---     0.101       R6C4D.A0 to       R6C4D.F0 SLICE_3
-ROUTE         1     0.000       R6C4D.F0 to      R6C4D.DI0 FS_s[13] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Ready_fast  (from RCLK_c +)
-   Destination:    FF         Data in        Ready_fast  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_34 to SLICE_34 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C13C.CLK to      R4C13C.Q0 SLICE_34 (from RCLK_c)
-ROUTE        14     0.132      R4C13C.Q0 to      R4C13C.A0 Ready_fast
-CTOF_DEL    ---     0.101      R4C13C.A0 to      R4C13C.F0 SLICE_34
-ROUTE         1     0.000      R4C13C.F0 to     R4C13C.DI0 N_415_0 (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R4C13C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R4C13C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[12]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_4 to SLICE_4 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     0.132       R6C4C.Q1 to       R6C4C.A1 FS[12]
-CTOF_DEL    ---     0.101       R6C4C.A1 to       R6C4C.F1 SLICE_4
-ROUTE         1     0.000       R6C4C.F1 to      R6C4C.DI1 FS_s[12] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nUFMCS  (from RCLK_c +)
-   Destination:    FF         Data in        nUFMCS  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_45 to SLICE_45 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_45 to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5A.CLK to       R5C5A.Q0 SLICE_45 (from RCLK_c)
-ROUTE         1     0.130       R5C5A.Q0 to       R5C5A.A0 nUFMCS_c
-CTOF_DEL    ---     0.101       R5C5A.A0 to       R5C5A.F0 SLICE_45
-ROUTE         2     0.002       R5C5A.F0 to      R5C5A.DI0 nUFMCS_s_0_N_5_i (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C5A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C5A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[9]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[9]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_5 to SLICE_5 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4B.CLK to       R6C4B.Q0 SLICE_5 (from RCLK_c)
-ROUTE         3     0.132       R6C4B.Q0 to       R6C4B.A0 FS[9]
-CTOF_DEL    ---     0.101       R6C4B.A0 to       R6C4B.F0 SLICE_5
-ROUTE         1     0.000       R6C4B.F0 to      R6C4B.DI0 FS_s[9] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt
deleted file mode 100644
index a668f03..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_cck.rpt
+++ /dev/null
@@ -1,155 +0,0 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-
-# Written on Tue Aug 15 23:12:44 2023
-
-##### DESIGN INFO #######################################################
-
-Top View:                "RAM2GS"
-Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
-
-
-
-
-##### SUMMARY ############################################################
-
-Found 0 issues in 0 out of 4 constraints
-
-
-##### DETAILS ############################################################
-
-
-
-Clock Relationships
-*******************
-
-Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
------------------------------------------------------------------------------------------------------------------------------------
-RCLK         RCLK       |     16.000           |     No paths         |     No paths         |     No paths                         
-RCLK         PHI2       |     2.000            |     No paths         |     1.000            |     No paths                         
-RCLK         nCRAS      |     No paths         |     No paths         |     1.000            |     No paths                         
-PHI2         RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
-PHI2         PHI2       |     No paths         |     350.000          |     175.000          |     175.000                          
-nCRAS        RCLK       |     No paths         |     No paths         |     No paths         |     1.000                            
-===================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. 
-@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. 
-
-
-Unconstrained Start/End Points
-******************************
-
-p:CROW[0]
-p:CROW[1]
-p:Din[0]
-p:Din[1]
-p:Din[2]
-p:Din[3]
-p:Din[4]
-p:Din[5]
-p:Din[6]
-p:Din[7]
-p:Dout[0]
-p:Dout[1]
-p:Dout[2]
-p:Dout[3]
-p:Dout[4]
-p:Dout[5]
-p:Dout[6]
-p:Dout[7]
-p:MAin[0]
-p:MAin[1]
-p:MAin[2]
-p:MAin[3]
-p:MAin[4]
-p:MAin[5]
-p:MAin[6]
-p:MAin[7]
-p:MAin[8]
-p:MAin[9]
-p:RA[0]
-p:RA[1]
-p:RA[2]
-p:RA[3]
-p:RA[4]
-p:RA[5]
-p:RA[6]
-p:RA[7]
-p:RA[8]
-p:RA[9]
-p:RA[10]
-p:RA[11]
-p:RBA[0]
-p:RBA[1]
-p:RCKE
-p:RDQMH
-p:RDQML
-p:RD[0] (bidir end point)
-p:RD[0] (bidir start point)
-p:RD[1] (bidir end point)
-p:RD[1] (bidir start point)
-p:RD[2] (bidir end point)
-p:RD[2] (bidir start point)
-p:RD[3] (bidir end point)
-p:RD[3] (bidir start point)
-p:RD[4] (bidir end point)
-p:RD[4] (bidir start point)
-p:RD[5] (bidir end point)
-p:RD[5] (bidir start point)
-p:RD[6] (bidir end point)
-p:RD[6] (bidir start point)
-p:RD[7] (bidir end point)
-p:RD[7] (bidir start point)
-p:UFMCLK
-p:UFMSDI
-p:UFMSDO
-p:nFWE
-p:nRCAS
-p:nRCS
-p:nRRAS
-p:nRWE
-p:nUFMCS
-
-
-Inapplicable constraints
-************************
-
-(none)
-
-
-Applicable constraints with issues
-**********************************
-
-(none)
-
-
-Constraints with matching wildcard expressions
-**********************************************
-
-(none)
-
-
-Library Report
-**************
-
-
-# End of Constraint Checker Report
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
deleted file mode 100644
index acbafe8..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
+++ /dev/null
@@ -1,203 +0,0 @@
-
-I/O Timing Report
-
-
-
    I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 22:56:41 2023
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     3.268      4      -0.395     M
-CROW[1] nCRAS F     1.999      4      -0.040     M
-Din[0]  PHI2  F     4.389      4       3.636     4
-Din[0]  nCCAS F     0.646      4       0.538     4
-Din[1]  PHI2  F     4.456      4       3.516     4
-Din[1]  nCCAS F     1.108      4       0.143     4
-Din[2]  PHI2  F     4.106      4       3.516     4
-Din[2]  nCCAS F     1.315      4       0.036     M
-Din[3]  PHI2  F     4.427      4       3.516     4
-Din[3]  nCCAS F     1.893      4      -0.089     M
-Din[4]  PHI2  F     4.612      4       3.516     4
-Din[4]  nCCAS F     0.714      4       0.460     4
-Din[5]  PHI2  F     4.805      4       3.516     4
-Din[5]  nCCAS F     1.636      4      -0.054     M
-Din[6]  PHI2  F     4.266      4       3.636     4
-Din[6]  nCCAS F     1.078      4       0.185     4
-Din[7]  PHI2  F     5.607      4       3.636     4
-Din[7]  nCCAS F     2.050      4      -0.188     M
-MAin[0] PHI2  F     6.493      4      -0.289     M
-MAin[0] nCRAS F     0.832      4       0.632     4
-MAin[1] PHI2  F     5.109      4       0.055     M
-MAin[1] nCRAS F     1.627      4       0.047     M
-MAin[2] PHI2  F     5.349      4       0.695     4
-MAin[2] nCRAS F     1.684      4       0.048     M
-MAin[3] PHI2  F     7.301      4      -0.533     M
-MAin[3] nCRAS F     1.660      4       0.035     M
-MAin[4] PHI2  F     6.167      4      -0.223     M
-MAin[4] nCRAS F     1.339      4       0.181     4
-MAin[5] PHI2  F     6.923      4      -0.449     M
-MAin[5] nCRAS F     1.082      4       0.412     4
-MAin[6] PHI2  F     6.784      4      -0.408     M
-MAin[6] nCRAS F     0.961      4       0.423     4
-MAin[7] PHI2  F     6.547      4      -0.171     M
-MAin[7] nCRAS F     1.331      4       0.186     4
-MAin[8] nCRAS F     0.454      4       0.874     4
-MAin[9] nCRAS F     0.782      4       0.684     4
-PHI2    RCLK  R    -0.312      M       3.167     4
-UFMSDO  RCLK  R     0.397      4       0.958     4
-nCCAS   RCLK  R     2.272      4      -0.095     M
-nCCAS   nCRAS F     3.094      4      -0.308     M
-nCRAS   RCLK  R     1.843      4       0.009     M
-nFWE    PHI2  F     5.987      4      -0.179     M
-nFWE    nCRAS F     0.594      4       0.839     4
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.623         4        3.337          M
-LED    nCRAS F    10.867         4        3.086          M
-RA[0]  RCLK  R    10.387         4        3.085          M
-RA[0]  nCRAS F    10.473         4        3.018          M
-RA[10] RCLK  R     8.141         4        2.620          M
-RA[11] PHI2  R     8.610         4        2.756          M
-RA[1]  RCLK  R    11.208         4        3.281          M
-RA[1]  nCRAS F    10.655         4        3.096          M
-RA[2]  RCLK  R    11.477         4        3.355          M
-RA[2]  nCRAS F    10.655         4        3.096          M
-RA[3]  RCLK  R    10.954         4        3.201          M
-RA[3]  nCRAS F    10.693         4        3.092          M
-RA[4]  RCLK  R    12.338         4        3.584          M
-RA[4]  nCRAS F    10.776         4        3.099          M
-RA[5]  RCLK  R    11.516         4        3.347          M
-RA[5]  nCRAS F    11.072         4        3.177          M
-RA[6]  RCLK  R    11.068         4        3.255          M
-RA[6]  nCRAS F    10.655         4        3.096          M
-RA[7]  RCLK  R    10.823         4        3.207          M
-RA[7]  nCRAS F    11.129         4        3.214          M
-RA[8]  RCLK  R    11.034         4        3.275          M
-RA[8]  nCRAS F    10.664         4        3.099          M
-RA[9]  RCLK  R    10.925         4        3.239          M
-RA[9]  nCRAS F    10.710         4        3.093          M
-RBA[0] nCRAS F     8.157         4        2.563          M
-RBA[1] nCRAS F     8.157         4        2.563          M
-RCKE   RCLK  R     8.141         4        2.620          M
-RDQMH  RCLK  R    11.337         4        3.355          M
-RDQML  RCLK  R    10.800         4        3.223          M
-RD[0]  nCCAS F     7.888         4        2.510          M
-RD[1]  nCCAS F     7.888         4        2.510          M
-RD[2]  nCCAS F     7.888         4        2.510          M
-RD[3]  nCCAS F     7.888         4        2.510          M
-RD[4]  nCCAS F     7.888         4        2.510          M
-RD[5]  nCCAS F     7.888         4        2.510          M
-RD[6]  nCCAS F     7.888         4        2.510          M
-RD[7]  nCCAS F     7.888         4        2.510          M
-UFMCLK RCLK  R     8.121         4        2.627          M
-UFMSDI RCLK  R     8.121         4        2.627          M
-nRCAS  RCLK  R     8.141         4        2.620          M
-nRCS   RCLK  R     8.141         4        2.620          M
-nRRAS  RCLK  R     8.141         4        2.620          M
-nRWE   RCLK  R     8.121         4        2.627          M
-nUFMCS RCLK  R     8.121         4        2.627          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: M
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
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-
    
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-
    
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-
    
-
    
-
    
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-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
deleted file mode 100644
index c4e5990..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
+++ /dev/null
@@ -1,41 +0,0 @@
--a "MachXO2"
--d LCMXO2-640HC
--t TQFP100
--s 4
--frequency 200
--optimization_goal Balanced
--bram_utilization 100
--ramstyle Auto
--romstyle auto
--dsp_utilization 100
--use_dsp 1
--use_carry_chain 1
--carry_chain_length 0
--force_gsr Auto
--resource_sharing 1
--propagate_constants 1
--remove_duplicate_regs 1
--mux_style Auto
--max_fanout 1000
--fsm_encoding_style Auto
--twr_paths 3
--fix_gated_clocks 1
--loop_limit 1950
-
-
-
--use_io_insertion 1
--resolve_mixed_drivers 0
--use_io_reg auto
-
-
--lpf 1
--p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"
--ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
--top RAM2GS
-
-
--p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"
-
--ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
deleted file mode 100644
index 0053977..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd
+++ /dev/null
@@ -1,15 +0,0 @@
-[ActiveSupport MAP]
-Device = LCMXO2-640HC;
-Package = TQFP100;
-Performance = 4;
-LUTS_avail = 640;
-LUTS_used = 159;
-FF_avail = 719;
-FF_used = 93;
-INPUT_LVCMOS33 = 26;
-OUTPUT_LVCMOS33 = 33;
-BIDI_LVCMOS33 = 8;
-IO_avail = 79;
-IO_used = 67;
-EBR_avail = 2;
-EBR_used = 0;
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
deleted file mode 100644
index bc09ec9..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
+++ /dev/null
@@ -1,12 +0,0 @@
----------------------------------------------------
-Report for cell RAM2GS
-   Instance path: RAM2GS
-                     Cell usage:
-                                  cell	      count    Res Usage(%)
-                                  SLIC	      81.00        100.0
-                                 IOLGC	      29.00        100.0
-                                  LUT4	     139.00        100.0
-                                 IOREG	         29        100.0
-                                 IOBUF	         67        100.0
-                                PFUREG	         64        100.0
-                                RIPPLE	         10        100.0
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
deleted file mode 100644
index 0fa9172..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf
deleted file mode 100644
index ffcef35..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf
+++ /dev/null
@@ -1,3483 +0,0 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 22:56:33 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_17")
-    (INSTANCE SLICE_17I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_18")
-    (INSTANCE SLICE_18I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_23")
-    (INSTANCE SLICE_23I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_24")
-    (INSTANCE SLICE_24I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_25")
-    (INSTANCE SLICE_25I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_27")
-    (INSTANCE SLICE_27I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_34")
-    (INSTANCE SLICE_34I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_35")
-    (INSTANCE SLICE_35I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_36")
-    (INSTANCE SLICE_36I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_37")
-    (INSTANCE SLICE_37I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_38")
-    (INSTANCE SLICE_38I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_B")
-    (INSTANCE RD_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD0 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD0 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_MGIOL")
-    (INSTANCE RD_0_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_B")
-    (INSTANCE Dout_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2B")
-    (INSTANCE PHI2I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2S PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2S) (3330:3330:3330))
-      (WIDTH (negedge PHI2S) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2_MGIOL")
-    (INSTANCE PHI2_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDOB")
-    (INSTANCE UFMSDOI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDOS PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDOS) (3330:3330:3330))
-      (WIDTH (negedge UFMSDOS) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDIB")
-    (INSTANCE UFMSDII)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO UFMSDIS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI_MGIOL")
-    (INSTANCE UFMSDI_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLKB")
-    (INSTANCE UFMCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO UFMCLKS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK_MGIOL")
-    (INSTANCE UFMCLK_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCSB")
-    (INSTANCE nUFMCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nUFMCSS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nUFMCS_MGIOL")
-    (INSTANCE nUFMCS_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMLB")
-    (INSTANCE RDQMLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMLS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RDQMHB")
-    (INSTANCE RDQMHI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RDQMHS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCASB")
-    (INSTANCE nRCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nRCASS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCAS_MGIOL")
-    (INSTANCE nRCAS_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRASB")
-    (INSTANCE nRRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nRRASS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRRAS_MGIOL")
-    (INSTANCE nRRAS_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWEB")
-    (INSTANCE nRWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nRWES (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRWE_MGIOL")
-    (INSTANCE nRWE_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKEB")
-    (INSTANCE RCKEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RCKES (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE_MGIOL")
-    (INSTANCE RCKE_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RCLKB")
-    (INSTANCE RCLKI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH RCLKS PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge RCLKS) (3330:3330:3330))
-      (WIDTH (negedge RCLKS) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCSB")
-    (INSTANCE nRCSI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nRCSS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nRCS_MGIOL")
-    (INSTANCE nRCS_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_B")
-    (INSTANCE RD_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD7 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD7 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_7_MGIOL")
-    (INSTANCE RD_7_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_B")
-    (INSTANCE RD_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD6 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD6 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_6_MGIOL")
-    (INSTANCE RD_6_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_B")
-    (INSTANCE RD_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD5 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD5 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_5_MGIOL")
-    (INSTANCE RD_5_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_B")
-    (INSTANCE RD_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD4 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD4 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_4_MGIOL")
-    (INSTANCE RD_4_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_B")
-    (INSTANCE RD_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD3 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD3 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_3_MGIOL")
-    (INSTANCE RD_3_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_B")
-    (INSTANCE RD_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD2 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD2 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_2_MGIOL")
-    (INSTANCE RD_2_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_B")
-    (INSTANCE RD_1_I0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD1 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD1 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_1_MGIOL")
-    (INSTANCE RD_1_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_B")
-    (INSTANCE RA_11_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA11 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_11_MGIOL")
-    (INSTANCE RA_11_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_B")
-    (INSTANCE RA_10_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA10 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_MGIOL")
-    (INSTANCE RA_10_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_B")
-    (INSTANCE RA_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA9 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_B")
-    (INSTANCE RA_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA8 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_B")
-    (INSTANCE RA_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA7 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_6_B")
-    (INSTANCE RA_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA6 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_5_B")
-    (INSTANCE RA_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA5 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_4_B")
-    (INSTANCE RA_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA4 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_3_B")
-    (INSTANCE RA_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA3 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2_B")
-    (INSTANCE RA_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA2 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_1_B")
-    (INSTANCE RA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA1 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_0_B")
-    (INSTANCE RA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO RA0 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_B")
-    (INSTANCE RBA_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RBA1 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_1_MGIOL")
-    (INSTANCE RBA_1_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_B")
-    (INSTANCE RBA_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RBA0 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RBA_0_MGIOL")
-    (INSTANCE RBA_0_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "LEDB")
-    (INSTANCE LEDI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO LEDS (2371:2455:2540)(2371:2455:2540))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "nFWEB")
-    (INSTANCE nFWEI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nFWES PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nFWES) (3330:3330:3330))
-      (WIDTH (negedge nFWES) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCRASB")
-    (INSTANCE nCRASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCRASS PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCRASS) (3330:3330:3330))
-      (WIDTH (negedge nCRASS) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "nCCASB")
-    (INSTANCE nCCASI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nCCASS PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nCCASS) (3330:3330:3330))
-      (WIDTH (negedge nCCASS) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_7_B")
-    (INSTANCE Dout_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout7 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_6_B")
-    (INSTANCE Dout_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout6 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_5_B")
-    (INSTANCE Dout_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout5 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_4_B")
-    (INSTANCE Dout_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout4 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_3_B")
-    (INSTANCE Dout_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout3 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_2_B")
-    (INSTANCE Dout_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout2 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_1_B")
-    (INSTANCE Dout_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout1 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_B")
-    (INSTANCE Din_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (3330:3330:3330))
-      (WIDTH (negedge Din7) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_7_MGIOL")
-    (INSTANCE Din_7_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_B")
-    (INSTANCE Din_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (3330:3330:3330))
-      (WIDTH (negedge Din6) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_6_MGIOL")
-    (INSTANCE Din_6_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_B")
-    (INSTANCE Din_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din5) (3330:3330:3330))
-      (WIDTH (negedge Din5) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_MGIOL")
-    (INSTANCE Din_5_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_B")
-    (INSTANCE Din_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din4) (3330:3330:3330))
-      (WIDTH (negedge Din4) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_4_MGIOL")
-    (INSTANCE Din_4_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_B")
-    (INSTANCE Din_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din3) (3330:3330:3330))
-      (WIDTH (negedge Din3) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_3_MGIOL")
-    (INSTANCE Din_3_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_B")
-    (INSTANCE Din_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din2) (3330:3330:3330))
-      (WIDTH (negedge Din2) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_2_MGIOL")
-    (INSTANCE Din_2_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_B")
-    (INSTANCE Din_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din1) (3330:3330:3330))
-      (WIDTH (negedge Din1) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_1_MGIOL")
-    (INSTANCE Din_1_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_B")
-    (INSTANCE Din_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din0) (3330:3330:3330))
-      (WIDTH (negedge Din0) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_0_MGIOL")
-    (INSTANCE Din_0_MGIOLI)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK INP (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_1_B")
-    (INSTANCE CROW_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW1) (3330:3330:3330))
-      (WIDTH (negedge CROW1) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "CROW_0_B")
-    (INSTANCE CROW_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CROW0 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CROW0) (3330:3330:3330))
-      (WIDTH (negedge CROW0) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_9_B")
-    (INSTANCE MAin_9_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin9 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin9) (3330:3330:3330))
-      (WIDTH (negedge MAin9) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_8_B")
-    (INSTANCE MAin_8_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin8 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin8) (3330:3330:3330))
-      (WIDTH (negedge MAin8) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_7_B")
-    (INSTANCE MAin_7_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin7 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin7) (3330:3330:3330))
-      (WIDTH (negedge MAin7) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_6_B")
-    (INSTANCE MAin_6_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin6) (3330:3330:3330))
-      (WIDTH (negedge MAin6) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_5_B")
-    (INSTANCE MAin_5_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin5 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin5) (3330:3330:3330))
-      (WIDTH (negedge MAin5) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_4_B")
-    (INSTANCE MAin_4_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin4 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin4) (3330:3330:3330))
-      (WIDTH (negedge MAin4) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_3_B")
-    (INSTANCE MAin_3_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin3 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin3) (3330:3330:3330))
-      (WIDTH (negedge MAin3) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_2_B")
-    (INSTANCE MAin_2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin2 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin2) (3330:3330:3330))
-      (WIDTH (negedge MAin2) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_1_B")
-    (INSTANCE MAin_1_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin1) (3330:3330:3330))
-      (WIDTH (negedge MAin1) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "MAin_0_B")
-    (INSTANCE MAin_0_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH MAin0 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge MAin0) (3330:3330:3330))
-      (WIDTH (negedge MAin0) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
-        (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_56I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/Q1 SLICE_78I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/F1 SLICE_0I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_14I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_17I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_23I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_24I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_27I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_29I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_33I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_40I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_41I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_45I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI SLICE_73I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI PHI2_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI UFMSDI_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI UFMCLK_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI nUFMCS_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI nRCAS_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI nRRAS_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI nRWE_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI RCKE_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI nRCS_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLKI/PADDI RA_10_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0I/FCO SLICE_9I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/Q0 SLICE_72I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1I/F0 SLICE_1I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/FCO SLICE_1I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_26I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_48I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_64I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/Q0 SLICE_72I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/F1 SLICE_2I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2I/F0 SLICE_2I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_72I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q1 SLICE_85I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/Q0 SLICE_72I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/F1 SLICE_3I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3I/F0 SLICE_3I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/FCO SLICE_3I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q1 SLICE_72I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_47I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_58I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/Q0 SLICE_85I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/F1 SLICE_4I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4I/F0 SLICE_4I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_26I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_47I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_58I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q1 SLICE_85I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_59I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/Q0 SLICE_78I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/F1 SLICE_5I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5I/F0 SLICE_5I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/FCO SLICE_5I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_58I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q1 SLICE_59I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_78I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/Q0 SLICE_85I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/F1 SLICE_6I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6I/F0 SLICE_6I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/FCO SLICE_6I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_58I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q1 SLICE_85I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_56I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_78I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/Q0 SLICE_78I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/F1 SLICE_7I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7I/F0 SLICE_7I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/FCO SLICE_7I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_59I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q1 SLICE_64I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/Q0 SLICE_78I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/F1 SLICE_8I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_8I/F0 SLICE_8I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/FCO SLICE_8I/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q1 SLICE_9I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q1 SLICE_56I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q1 SLICE_78I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_64I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/Q0 SLICE_85I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/F1 SLICE_9I/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/F0 SLICE_10I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74I/F0 SLICE_10I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F0 SLICE_10I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F0 SLICE_46I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/F1 SLICE_10I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/F1 SLICE_13I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/F1 SLICE_18I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_10I/F1 SLICE_10I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_10I/F1 SLICE_18I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_46I/F1 SLICE_10I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_46I/F1 SLICE_13I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_46I/F1 SLICE_46I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_10I/Q0 SLICE_10I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_10I/Q0 SLICE_18I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_10I/F0 SLICE_10I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_10I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_13I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_21I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_42I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_63I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI SLICE_68I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI PHI2_MGIOLI/DI (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI RA_11_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_7_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_6_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_5_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_4_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_3_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_2_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_1_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2I/PADDI Din_0_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_13I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_46I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_46I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_57I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F0 SLICE_60I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_13I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_36I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_46I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_46I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_57I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_67I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_2_I/PADDI SLICE_82I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F0 SLICE_13I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F0 SLICE_13I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F0 SLICE_46I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/Q0 SLICE_13I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/Q0 SLICE_18I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13I/F0 SLICE_13I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_14I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_22I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_22I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_63I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT nFWEI/PADDI SLICE_67I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_14I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI SLICE_14I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_0_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_7_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_6_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_5_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_4_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_3_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_2_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCCASI/PADDI RD_1_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F0 SLICE_74I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q0 SLICE_14I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_0_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_7_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_6_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_5_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_4_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_3_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_2_I/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/F1 RD_1_I0/PADDT (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q1 SLICE_66I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q1 SLICE_71I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q1 SLICE_73I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_14I/Q1 SLICE_76I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_17I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_17I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_40I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_44I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_49I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_49I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_51I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_51I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_53I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_76I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40I/Q0 SLICE_76I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_17I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_17I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_31I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_32I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_32I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_40I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_40I/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_49I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_53I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_29I/Q1 SLICE_77I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25I/Q0 SLICE_17I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25I/Q0 SLICE_23I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25I/Q0 SLICE_25I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25I/Q0 SLICE_52I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_17I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_17I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_40I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_44I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_49I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_53I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_66I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_71I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/Q0 SLICE_76I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/F0 SLICE_17I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/F1 SLICE_33I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17I/F1 SLICE_34I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_18I/Q0 SLICE_18I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_18I/Q0 SLICE_18I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_18I/Q0 SLICE_57I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_46I/F0 SLICE_18I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_18I/OFX0 SLICE_18I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_19I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_20I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_21I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_50I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_57I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F0 SLICE_70I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_19I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_20I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_21I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_42I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_50I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_50I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_57I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_68I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_70I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI SLICE_73I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI RD_5_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_I/PADDI Din_5_MGIOLI/DI (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_19I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_63I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_73I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI SLICE_74I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI RD_1_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_I/PADDI Din_1_MGIOLI/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_21I/F1 SLICE_19I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_21I/F1 SLICE_21I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F1 SLICE_19I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_70I/F1 SLICE_19I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_27I/Q0 SLICE_19I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_27I/Q0 SLICE_29I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_27I/Q0 SLICE_74I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_19I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_20I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_21I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_42I/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F0 SLICE_57I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_27I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_20I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_21I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_50I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_57I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_70I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_73I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_74I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI SLICE_74I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI RD_3_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din_3_I/PADDI Din_3_MGIOLI/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_20I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_54I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_55I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_57I/F1 SLICE_20I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/F0 SLICE_20I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/F1 Din_2_MGIOLI/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/F1 Din_1_MGIOLI/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20I/F1 Din_0_MGIOLI/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_21I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43I/Q0 SLICE_84I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F1 SLICE_21I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_21I/F0 SLICE_21I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_21I/Q0 SLICE_50I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_22I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_35I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_60I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_63I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT MAin_1_I/PADDI SLICE_81I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_22I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_63I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F1 SLICE_67I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F1 SLICE_22I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_60I/F1 SLICE_60I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/F0 SLICE_22I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_22I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_29I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_29I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_37I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_38I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_39I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI RBA_1_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI RBA_0_MGIOLI/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT nCRASI/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_44I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_66I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_76I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/Q0 SLICE_76I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/F1 SLICE_46I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_22I/F1 SLICE_57I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_23I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_23I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_31I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_33I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_34I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_40I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_44I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_49I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_53I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_62I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_66I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_76I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_77I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_33I/Q0 SLICE_77I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_23I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_23I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_49I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_52I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_61I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_62I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F1 SLICE_77I/A0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_44I/Q0 SLICE_75I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_79I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_79I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_81I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_81I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_82I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_82I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44I/Q0 SLICE_83I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48I/F1 SLICE_45I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48I/F1 SLICE_48I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_MGIOLI/INP SLICE_45I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45I/Q0 SLICE_45I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45I/F1 SLICE_45I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45I/F0 SLICE_45I/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45I/F0 nUFMCS_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_47I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_58I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_59I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F1 SLICE_64I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48I/F0 SLICE_47I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_1_MGIOLI/INP SLICE_47I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_47I/F0 UFMCLK_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64I/F0 SLICE_48I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_49I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_52I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F1 SLICE_61I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49I/F0 SLICE_51I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50I/F0 SLICE_50I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F1 SLICE_51I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_51I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F0 SLICE_66I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51I/F0 nRCAS_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F1 SLICE_52I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77I/F1 SLICE_61I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F0 SLICE_66I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52I/F0 nRRAS_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F0 SLICE_53I/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53I/F1 SLICE_71I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/Q1 SLICE_54I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/Q1 SLICE_65I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/Q0 SLICE_54I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/Q0 SLICE_65I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/Q0 SLICE_65I/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_54I/F1 SLICE_54I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_54I/F1 SLICE_55I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/F0 SLICE_54I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/F1 SLICE_55I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F0 SLICE_55I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59I/F0 SLICE_56I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/F1 SLICE_55I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85I/F1 SLICE_56I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55I/F1 SLICE_55I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56I/F1 SLICE_56I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58I/F1 SLICE_58I/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78I/F0 SLICE_58I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67I/F0 SLICE_60I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/F0 SLICE_61I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61I/F1 SLICE_66I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 SLICE_62I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62I/F1 RA_10_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63I/F1 SLICE_63I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72I/F1 SLICE_64I/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_MGIOLI/INP SLICE_65I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65I/F1 UFMCLK_MGIOLI/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66I/F1 nRCS_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_68I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_68I/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_74I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI SLICE_74I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI RD_2_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din_2_I/PADDI Din_2_MGIOLI/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73I/F1 SLICE_68I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/F1 SLICE_68I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_7_MGIOLI/INP SLICE_69I/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69I/F1 SLICE_69I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_6_MGIOLI/INP SLICE_69I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din_5_MGIOLI/INP SLICE_69I/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76I/F1 SLICE_71I/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F1 SLICE_71I/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71I/F0 nRWE_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/F0 RA_9_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75I/F1 RDQMLI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F0 RA_8_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79I/F1 RDQMHI/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F0 RA_0_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80I/F1 RA_7_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F0 RA_1_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81I/F1 RA_6_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/F0 RA_2_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82I/F1 RA_5_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/F0 RA_3_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83I/F1 RA_4_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT CROW_0_I/PADDI SLICE_84I/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F0 RA_11_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84I/F1 RBA_0_MGIOLI/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD_0_MGIOLI/IOLDO RD_0_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT UFMSDI_MGIOLI/IOLDO UFMSDII/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT UFMCLK_MGIOLI/IOLDO UFMCLKI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nUFMCS_MGIOLI/IOLDO nUFMCSI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRCAS_MGIOLI/IOLDO nRCASI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRRAS_MGIOLI/IOLDO nRRASI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_MGIOLI/IOLDO nRWEI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RCKE_MGIOLI/IOLDO RCKEI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRCS_MGIOLI/IOLDO nRCSI/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_7_MGIOLI/IOLDO RD_7_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_6_MGIOLI/IOLDO RD_6_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_5_MGIOLI/IOLDO RD_5_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_4_MGIOLI/IOLDO RD_4_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_3_MGIOLI/IOLDO RD_3_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_2_MGIOLI/IOLDO RD_2_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD_1_MGIOLI/IOLDO RD_1_I0/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA_11_MGIOLI/IOLDO RA_11_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA_10_MGIOLI/IOLDO RA_10_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RBA_1_MGIOLI/IOLDO RBA_1_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RBA_0_MGIOLI/IOLDO RBA_0_I/IOLDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho
deleted file mode 100644
index 94c5959..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho
+++ /dev/null
@@ -1,27823 +0,0 @@
-
--- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
--- ldbanno -n VHDL -o RAM2GS_LCMXO2_640HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd 
--- Netlist created on Tue Aug 15 22:56:31 2023
--- Netlist written on Tue Aug 15 22:56:33 2023
--- Design is for device LCMXO2-640HC
--- Design is for package TQFP100
--- Design is for performance grade 4
-
--- entity vmuxregsre
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity vmuxregsre is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
-
-  end vmuxregsre;
-
-  architecture Structure of vmuxregsre is
-  begin
-    INST01: FL1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity vcc
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity vcc is
-    port (PWR1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
-
-  end vcc;
-
-  architecture Structure of vcc is
-  begin
-    INST1: VHI
-      port map (Z=>PWR1);
-  end Structure;
-
--- entity gnd
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity gnd is
-    port (PWR0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
-
-  end gnd;
-
-  architecture Structure of gnd is
-  begin
-    INST1: VLO
-      port map (Z=>PWR0);
-  end Structure;
-
--- entity ccu2B0
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity ccu2B0 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE;
-
-  end ccu2B0;
-
-  architecture Structure of ccu2B0 is
-  begin
-    inst1: CCU2D
-      generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
-  end Structure;
-
--- entity SLICE_0
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_0 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_0";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
-
-  end SLICE_0;
-
-  architecture Structure of SLICE_0 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu2B0
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_cry_0_0: ccu2B0
-      port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out)
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20001
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity ccu20001 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
-
-  end ccu20001;
-
-  architecture Structure of ccu20001 is
-  begin
-    inst1: CCU2D
-      generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
-  end Structure;
-
--- entity SLICE_1
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_1 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_1";
-
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
-
-  end SLICE_1;
-
-  architecture Structure of SLICE_1 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20001
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_17: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_s_0_17: ccu20001
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, 
-                CO1=>open);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity ccu20002
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity ccu20002 is
-    port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-          D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-          C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-          S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE;
-
-  end ccu20002;
-
-  architecture Structure of ccu20002 is
-  begin
-    inst1: CCU2D
-      generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO", 
-                   INJECT1_1 => "NO")
-      port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, 
-                C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
-  end Structure;
-
--- entity SLICE_2
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_2 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_2";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
-
-  end SLICE_2;
-
-  architecture Structure of SLICE_2 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_16: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_15: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_15: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_3
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_3 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_3";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
-
-  end SLICE_3;
-
-  architecture Structure of SLICE_3 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_14: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_13: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_13: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_4
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_4 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_4";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
-
-  end SLICE_4;
-
-  architecture Structure of SLICE_4 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_12: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_11: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_11: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_5
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_5 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_5";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
-
-  end SLICE_5;
-
-  architecture Structure of SLICE_5 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_10: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_9: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_9: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_6
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_6 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_6";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
-
-  end SLICE_6;
-
-  architecture Structure of SLICE_6 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_8: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_7: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_7: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_7
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_7 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_7";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
-
-  end SLICE_7;
-
-  architecture Structure of SLICE_7 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_6: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_5: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_5: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_8
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_8 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_8";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
-
-  end SLICE_8;
-
-  architecture Structure of SLICE_8 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_4: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_3: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_9
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_9 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_9";
-
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_FCI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_FCI_FCO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic; FCO: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
-
-  end SLICE_9;
-
-  architecture Structure of SLICE_9 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal FCI_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-    signal FCO_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component ccu20002
-      port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; 
-            D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; 
-            C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; 
-            S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
-    end component;
-  begin
-    FS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    FS_cry_0_1: ccu20002
-      port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, 
-                C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, 
-                CO1=>FCO_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-      VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, 
-      FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE FCO_zd         	: std_logic := 'X';
-    VARIABLE FCO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-    FCO_zd 	:= FCO_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
-      Paths      => (0 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_FCO,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_FCO,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => FCI_ipd'last_event,
-                           PathDelay => tpd_FCI_FCO,
-                           PathCondition => TRUE)),
-      GlitchData => FCO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut4
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut4 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
-
-  end lut4;
-
-  architecture Structure of lut4 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"8080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40003
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40003 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
-
-  end lut40003;
-
-  architecture Structure of lut40003 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"00F2")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity inverter
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity inverter is
-    port (I: in Std_logic; Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
-
-  end inverter;
-
-  architecture Structure of inverter is
-  begin
-    INST1: INV
-      port map (A=>I, Z=>Z);
-  end Structure;
-
--- entity SLICE_10
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_10 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_10";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE;
-
-  end SLICE_10;
-
-  architecture Structure of SLICE_10 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40003
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable17: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    ADSubmitted_r: lut40003
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    ADSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40004
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40004 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
-
-  end lut40004;
-
-  architecture Structure of lut40004 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"8000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40005
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40005 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
-
-  end lut40005;
-
-  architecture Structure of lut40005 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"F2F2")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_13
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_13 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_13";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_13 : ENTITY IS TRUE;
-
-  end SLICE_13;
-
-  architecture Structure of SLICE_13 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40005
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16: lut40004
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    C1Submitted_s: lut40005
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1Submitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40006
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40006 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
-
-  end lut40006;
-
-  architecture Structure of lut40006 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"EEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40007
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40007 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE;
-
-  end lut40007;
-
-  architecture Structure of lut40007 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5555")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_14
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_14 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_14";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
-
-  end SLICE_14;
-
-  architecture Structure of SLICE_14 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40007
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nCCAS_pad_RNI01SJ: lut40006
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nCCAS_pad_RNISUR8: lut40007
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
-    CASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CASr: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, 
-      F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40008
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40008 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
-
-  end lut40008;
-
-  architecture Structure of lut40008 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0800")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40009
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40009 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
-
-  end lut40009;
-
-  architecture Structure of lut40009 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"DDDD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0010
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity vmuxregsre0010 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0010 : ENTITY IS TRUE;
-
-  end vmuxregsre0010;
-
-  architecture Structure of vmuxregsre0010 is
-  begin
-    INST01: FL1P3IY
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_17
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_17 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_17";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_LSR 	: VitalDelayType := 0 ns;
-      tpw_LSR_posedge	: VitalDelayType := 0 ns;
-      tpw_LSR_negedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE;
-
-  end SLICE_17;
-
-  architecture Structure of SLICE_17 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40009
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0010
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3_2: lut40008
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNO_0: lut40009
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_0: vmuxregsre0010
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_LSR          	: x01 := '0';
-    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => LSR_ipd,
-        TestSignalName => "LSR",
-        Period => tperiod_LSR,
-        PulseWidthHigh => tpw_LSR_posedge,
-        PulseWidthLow => tpw_LSR_negedge,
-        PeriodData => periodcheckinfo_LSR,
-        Violation => tviol_LSR_LSR,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40011
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40011 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
-
-  end lut40011;
-
-  architecture Structure of lut40011 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"EEEE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40012
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40012 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
-
-  end lut40012;
-
-  architecture Structure of lut40012 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"AC8C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity selmux2
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity selmux2 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
-
-  end selmux2;
-
-  architecture Structure of selmux2 is
-  begin
-    INST1: MUX21
-      port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
-  end Structure;
-
--- entity SLICE_18
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_18 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_18";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE;
-
-  end SLICE_18;
-
-  architecture Structure of SLICE_18 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal SLICE_18_SLICE_18_K1_H1: Std_logic;
-    signal SLICE_18_CmdEnable_s_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40011
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40012
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_18_K1: lut40011
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, 
-                Z=>SLICE_18_SLICE_18_K1_H1);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable_s_GATE: lut40012
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, 
-                Z=>SLICE_18_CmdEnable_s_GATE_H0);
-    CmdEnable: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    SLICE_18_K0K1MUX: selmux2
-      port map (D0=>SLICE_18_CmdEnable_s_GATE_H0, D1=>SLICE_18_SLICE_18_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40013
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40013 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
-
-  end lut40013;
-
-  architecture Structure of lut40013 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0101")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40014
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40014 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
-
-  end lut40014;
-
-  architecture Structure of lut40014 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0203")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_19
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_19 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_19";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
-
-  end SLICE_19;
-
-  architecture Structure of SLICE_19 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40014
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2_0: lut40013
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdLEDEN_RNO: lut40014
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CmdLEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40015
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40015 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
-
-  end lut40015;
-
-  architecture Structure of lut40015 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_20
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_20 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_20";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
-
-  end SLICE_20;
-
-  architecture Structure of SLICE_20 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK_1_sqmuxa_0_a2: lut40015
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdSubmitted_RNO: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdSubmitted: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40016
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40016 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
-
-  end lut40016;
-
-  architecture Structure of lut40016 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0808")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40017
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40017 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
-
-  end lut40017;
-
-  architecture Structure of lut40017 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5151")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_21
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_21 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_21";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
-
-  end SLICE_21;
-
-  architecture Structure of SLICE_21 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40017
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_a2_2: lut40016
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Cmdn8MEGEN_RNO: lut40017
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    Cmdn8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40018
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40018 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
-
-  end lut40018;
-
-  architecture Structure of lut40018 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0008")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_22
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_22 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_22";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
-
-  end SLICE_22;
-
-  architecture Structure of SLICE_22 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40007
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40018
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CMDWR_2: lut40018
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    FWEr_RNO: lut40007
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    FWEr: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40019
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40019 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
-
-  end lut40019;
-
-  architecture Structure of lut40019 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FFF7")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40020
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40020 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
-
-  end lut40020;
-
-  architecture Structure of lut40020 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"A9A9")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_23
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_23 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_23";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE;
-
-  end SLICE_23;
-
-  architecture Structure of SLICE_23 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40020
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_0io_RNO: lut40019
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_RNO_0: lut40020
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40021
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40021 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
-
-  end lut40021;
-
-  architecture Structure of lut40021 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"7878")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40022
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40022 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
-
-  end lut40022;
-
-  architecture Structure of lut40022 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"6666")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_24
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_24 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_24";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-          DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE;
-
-  end SLICE_24;
-
-  architecture Structure of SLICE_24 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40021
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40022
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_2: lut40021
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    IS_n1_0_x2: lut40022
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    IS_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    IS_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, 
-      DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_posedge,
-        SetupLow => tsetup_DI1_CLK_noedge_posedge,
-        HoldHigh => thold_DI1_CLK_noedge_posedge,
-        HoldLow => thold_DI1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40023
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40023 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
-
-  end lut40023;
-
-  architecture Structure of lut40023 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"6AAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_25
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_25 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_25";
-
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE;
-
-  end SLICE_25;
-
-  architecture Structure of SLICE_25 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40023
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_RNO_3: lut40023
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    IS_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, 
-      CLK_dly, F0_out, Q0_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_26
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_26 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_26";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
-
-  end SLICE_26;
-
-  architecture Structure of SLICE_26 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    InitReady3_0_a2: lut40004
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady_RNO: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    InitReady: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40024
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40024 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
-
-  end lut40024;
-
-  architecture Structure of lut40024 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"BBBB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_27
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_27 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_27";
-
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE;
-
-  end SLICE_27;
-
-  architecture Structure of SLICE_27 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LEDEN_RNO: lut40024
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    LEDEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, 
-      Q0_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40025
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40025 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
-
-  end lut40025;
-
-  architecture Structure of lut40025 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FBFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_29
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_29 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_29";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
-
-  end SLICE_29;
-
-  architecture Structure of SLICE_29 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40007
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40025
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    LED_pad_RNO: lut40025
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RASr_RNO: lut40007
-      port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RASr2: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    RASr: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40026
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40026 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
-
-  end lut40026;
-
-  architecture Structure of lut40026 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5072")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40027
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40027 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
-
-  end lut40027;
-
-  architecture Structure of lut40027 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"DCCC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_31
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_31 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_31";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
-
-  end SLICE_31;
-
-  architecture Structure of SLICE_31 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40026
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40027
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RCKEEN_8_u_RNO: lut40026
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u: lut40027
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RCKEEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40028
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40028 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
-
-  end lut40028;
-
-  architecture Structure of lut40028 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"8888")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40029
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40029 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
-
-  end lut40029;
-
-  architecture Structure of lut40029 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FE30")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_32
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_32 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_32";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
-
-  end SLICE_32;
-
-  architecture Structure of SLICE_32 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40029
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RBAd_1: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RCKE_2_0: lut40029
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    RASr3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    RCKE: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40030
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40030 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
-
-  end lut40030;
-
-  architecture Structure of lut40030 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"7F7F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40031
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40031 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
-
-  end lut40031;
-
-  architecture Structure of lut40031 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"AEAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_33
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_33 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_33";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
-
-  end SLICE_33;
-
-  architecture Structure of SLICE_33 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40030
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40031
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_o2: lut40030
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_RNO: lut40031
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Ready: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40032
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40032 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
-
-  end lut40032;
-
-  architecture Structure of lut40032 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0200")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_34
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_34 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_34";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE;
-
-  end SLICE_34;
-
-  architecture Structure of SLICE_34 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Ready_0_sqmuxa_0_a3: lut40032
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Ready_fast_RNO: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    Ready_fast: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_35
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_35 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_35";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE;
-
-  end SLICE_35;
-
-  architecture Structure of SLICE_35 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RowAd_1: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RowAd_0: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_1: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    RowA_0: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
-        SetupLow => tsetup_DI1_CLK_noedge_negedge,
-        HoldHigh => thold_DI1_CLK_noedge_negedge,
-        HoldLow => thold_DI1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_36
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_36 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_36";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE;
-
-  end SLICE_36;
-
-  architecture Structure of SLICE_36 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RowAd_3: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RowAd_2: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_3: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    RowA_2: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
-        SetupLow => tsetup_DI1_CLK_noedge_negedge,
-        HoldHigh => thold_DI1_CLK_noedge_negedge,
-        HoldLow => thold_DI1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_37
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_37 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_37";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE;
-
-  end SLICE_37;
-
-  architecture Structure of SLICE_37 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RowAd_5: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RowAd_4: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_5: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    RowA_4: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
-        SetupLow => tsetup_DI1_CLK_noedge_negedge,
-        HoldHigh => thold_DI1_CLK_noedge_negedge,
-        HoldLow => thold_DI1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_38
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_38 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_38";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE;
-
-  end SLICE_38;
-
-  architecture Structure of SLICE_38 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RowAd_7: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RowAd_6: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_7: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    RowA_6: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
-        SetupLow => tsetup_DI1_CLK_noedge_negedge,
-        HoldHigh => thold_DI1_CLK_noedge_negedge,
-        HoldLow => thold_DI1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_39
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_39 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_39";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI1_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI1_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic; Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
-
-  end SLICE_39;
-
-  architecture Structure of SLICE_39 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI1_ipd 	: std_logic := 'X';
-    signal DI1_dly 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RowAd_9: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RowAd_8: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    RowA_9: vmuxregsre
-      port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    RowA_8: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, 
-      CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI1_CLK       	: x01 := '0';
-    VARIABLE DI1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI1_dly,
-        TestSignalName => "DI1",
-        TestDelay => tisd_DI1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI1_CLK_noedge_negedge,
-        SetupLow => tsetup_DI1_CLK_noedge_negedge,
-        HoldHigh => thold_DI1_CLK_noedge_negedge,
-        HoldLow => thold_DI1_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI1_CLK_TimingDatash,
-        Violation => tviol_DI1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_40
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_40 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_40";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_LSR 	: VitalDelayType := 0 ns;
-      tpw_LSR_posedge	: VitalDelayType := 0 ns;
-      tpw_LSR_negedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE;
-
-  end SLICE_40;
-
-  architecture Structure of SLICE_40 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    signal LSR_NOTIN: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0010
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0_sqmuxa_1_0_a3: lut40015
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_0_i_o2_1: lut40006
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    S_1: vmuxregsre0010
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_NOTIN, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    LSR_INVERTERIN: inverter
-      port map (I=>LSR_dly, Z=>LSR_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_LSR          	: x01 := '0';
-    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => LSR_ipd,
-        TestSignalName => "LSR",
-        Period => tperiod_LSR,
-        PulseWidthHigh => tpw_LSR_posedge,
-        PulseWidthLow => tpw_LSR_negedge,
-        PeriodData => periodcheckinfo_LSR,
-        Violation => tviol_LSR_LSR,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40033
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40033 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
-
-  end lut40033;
-
-  architecture Structure of lut40033 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1110")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40034
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40034 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
-
-  end lut40034;
-
-  architecture Structure of lut40034 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_41
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_41 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_41";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_M0_OFX0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          OFX0: out Std_logic; Q0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
-
-  end SLICE_41;
-
-  architecture Structure of SLICE_41 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal OFX0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-
-    signal SLICE_41_SLICE_41_K1_H1: Std_logic;
-    signal GNDI: Std_logic;
-    signal SLICE_41_UFMSDI_RNO_GATE_H0: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component selmux2
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40033
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40034
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    SLICE_41_K1: lut40033
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, 
-                Z=>SLICE_41_SLICE_41_K1_H1);
-    UFMSDI_RNO_GATE: lut40034
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, 
-                Z=>SLICE_41_UFMSDI_RNO_GATE_H0);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMSDI: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    SLICE_41_K0K1MUX: selmux2
-      port map (D0=>SLICE_41_UFMSDI_RNO_GATE_H0, D1=>SLICE_41_SLICE_41_K1_H1, 
-                SD=>M0_ipd, Z=>OFX0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
-    VARIABLE OFX0_zd         	: std_logic := 'X';
-    VARIABLE OFX0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    OFX0_zd 	:= OFX0_out;
-    Q0_zd 	:= Q0_out;
-
-    VitalPathDelay01 (
-      OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_OFX0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_OFX0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_OFX0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_OFX0,
-                           PathCondition => TRUE),
-                     4 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_OFX0,
-                           PathCondition => TRUE),
-                     5 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_OFX0,
-                           PathCondition => TRUE),
-                     6 => (InputChangeTime => M0_ipd'last_event,
-                           PathDelay => tpd_M0_OFX0,
-                           PathCondition => TRUE)),
-      GlitchData => OFX0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40035
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40035 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
-
-  end lut40035;
-
-  architecture Structure of lut40035 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0001")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40036
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40036 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
-
-  end lut40036;
-
-  architecture Structure of lut40036 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"A0CC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_42
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_42 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_42";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
-
-  end SLICE_42;
-
-  architecture Structure of SLICE_42 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40036
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_Din_3: lut40035
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG_3_u: lut40036
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    XOR8MEG: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_negedge,
-        SetupLow => tsetup_DI0_CLK_noedge_negedge,
-        HoldHigh => thold_DI0_CLK_noedge_negedge,
-        HoldLow => thold_DI0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40037
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40037 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
-
-  end lut40037;
-
-  architecture Structure of lut40037 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"8B8B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_43
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_43 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_43";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
-
-  end SLICE_43;
-
-  architecture Structure of SLICE_43 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40037
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_Bank_1_4: lut40004
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    n8MEGEN_5_i_m2: lut40037
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    n8MEGEN: vmuxregsre
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40038
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40038 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
-
-  end lut40038;
-
-  architecture Structure of lut40038 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40039
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40039 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
-
-  end lut40039;
-
-  architecture Structure of lut40039 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"DCEC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_44
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_44 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_44";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_LSR 	: VitalDelayType := 0 ns;
-      tpw_LSR_posedge	: VitalDelayType := 0 ns;
-      tpw_LSR_negedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
-
-  end SLICE_44;
-
-  architecture Structure of SLICE_44 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component vmuxregsre0010
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40039
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRowColSel_0_0_a3_0: lut40038
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRowColSel_0_0: lut40039
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nRowColSel: vmuxregsre0010
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>LSR_dly, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_LSR          	: x01 := '0';
-    VARIABLE periodcheckinfo_LSR	: VitalPeriodDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => LSR_ipd,
-        TestSignalName => "LSR",
-        Period => tperiod_LSR,
-        PulseWidthHigh => tpw_LSR_posedge,
-        PulseWidthLow => tpw_LSR_negedge,
-        PeriodData => periodcheckinfo_LSR,
-        Violation => tviol_LSR_LSR,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40040
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40040 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
-
-  end lut40040;
-
-  architecture Structure of lut40040 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"000B")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40041
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40041 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
-
-  end lut40041;
-
-  architecture Structure of lut40041 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5F4E")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity vmuxregsre0042
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity vmuxregsre0042 is
-    port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-          SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-          Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF vmuxregsre0042 : ENTITY IS TRUE;
-
-  end vmuxregsre0042;
-
-  architecture Structure of vmuxregsre0042 is
-  begin
-    INST01: FL1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity SLICE_45
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_45 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_45";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_DI0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI0_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE;
-
-  end SLICE_45;
-
-  architecture Structure of SLICE_45 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal DI0_ipd 	: std_logic := 'X';
-    signal DI0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40040
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40041
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component vmuxregsre0042
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-  begin
-    nUFMCS_s_0_m4_yy: lut40040
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nUFMCS_s_0_N_5_i: lut40041
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    nUFMCS: vmuxregsre0042
-      port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI0_CLK       	: x01 := '0';
-    VARIABLE DI0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI0_dly,
-        TestSignalName => "DI0",
-        TestDelay => tisd_DI0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI0_CLK_noedge_posedge,
-        SetupLow => tsetup_DI0_CLK_noedge_posedge,
-        HoldHigh => thold_DI0_CLK_noedge_posedge,
-        HoldLow => thold_DI0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI0_CLK_TimingDatash,
-        Violation => tviol_DI0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40043
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40043 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
-
-  end lut40043;
-
-  architecture Structure of lut40043 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"EAAA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40044
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40044 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
-
-  end lut40044;
-
-  architecture Structure of lut40044 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FF80")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_46
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_46 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_46";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE;
-
-  end SLICE_46;
-
-  architecture Structure of SLICE_46 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40043
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40044
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_ADWR: lut40043
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_CMDWR: lut40044
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40045
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40045 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
-
-  end lut40045;
-
-  architecture Structure of lut40045 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0B00")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_47
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_47 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_47";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE;
-
-  end SLICE_47;
-
-  architecture Structure of SLICE_47 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40045
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nUFMCS15_0_a2: lut40035
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_0io_RNO: lut40045
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40046
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40046 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
-
-  end lut40046;
-
-  architecture Structure of lut40046 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0E0E")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_48
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_48 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_48";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE;
-
-  end SLICE_48;
-
-  architecture Structure of SLICE_48 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40046
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_r_i_a2_2_2: lut40015
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMCLK_0io_RNO_1: lut40046
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40047
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40047 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
-
-  end lut40047;
-
-  architecture Structure of lut40047 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0BFB")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_49
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_49 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_49";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE;
-
-  end SLICE_49;
-
-  architecture Structure of SLICE_49 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40019
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40047
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    IS_0_sqmuxa_0_o2_0: lut40019
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_nRCAS_6_sqmuxa_i_0: lut40047
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40048
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40048 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
-
-  end lut40048;
-
-  architecture Structure of lut40048 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2722")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40049
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40049 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
-
-  end lut40049;
-
-  architecture Structure of lut40049 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"F4F4")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_50
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_50 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_50";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
-
-  end SLICE_50;
-
-  architecture Structure of SLICE_50 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40048
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40049
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    Cmdn8MEGEN_4_u_i_0: lut40048
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_4_u_i_o2: lut40049
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40050
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40050 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
-
-  end lut40050;
-
-  architecture Structure of lut40050 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1313")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40051
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40051 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
-
-  end lut40051;
-
-  architecture Structure of lut40051 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1303")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_51
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_51 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_51";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
-
-  end SLICE_51;
-
-  architecture Structure of SLICE_51 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40050
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40051
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCAS_0io_RNO_0: lut40050
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRCAS_0io_RNO: lut40051
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40052
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40052 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
-
-  end lut40052;
-
-  architecture Structure of lut40052 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FEFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40053
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40053 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
-
-  end lut40053;
-
-  architecture Structure of lut40053 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5051")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_52
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_52 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_52";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
-
-  end SLICE_52;
-
-  architecture Structure of SLICE_52 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40053
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_nRCAS_6_sqmuxa_i_o2: lut40052
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRRAS_5_u_i_0_RNILD5I: lut40053
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40054
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40054 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
-
-  end lut40054;
-
-  architecture Structure of lut40054 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FF40")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40055
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40055 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
-
-  end lut40055;
-
-  architecture Structure of lut40055 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0202")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_53
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_53 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_53";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE;
-
-  end SLICE_53;
-
-  architecture Structure of SLICE_53 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40054
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40055
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_s_i_tz_0: lut40054
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    S_RNICVV51_0: lut40055
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40056
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40056 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
-
-  end lut40056;
-
-  architecture Structure of lut40056 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"4444")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40057
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40057 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
-
-  end lut40057;
-
-  architecture Structure of lut40057 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"F8F0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_54
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_54 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_54";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE;
-
-  end SLICE_54;
-
-  architecture Structure of SLICE_54 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_PHI2r3_0: lut40056
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_0: lut40057
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_55
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_55 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_55";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
-
-  end SLICE_55;
-
-  architecture Structure of SLICE_55 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40057
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0: lut4
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_14_i_0: lut40057
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40058
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40058 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
-
-  end lut40058;
-
-  architecture Structure of lut40058 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0100")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_56
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_56 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_56";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
-
-  end SLICE_56;
-
-  architecture Structure of SLICE_56 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut4
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_1: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    un1_FS_13_i_a2: lut4
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40059
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40059 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
-
-  end lut40059;
-
-  architecture Structure of lut40059 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2202")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_57
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_57 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_57";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
-
-  end SLICE_57;
-
-  architecture Structure of SLICE_57 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40059
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdSubmitted_1_sqmuxa_0_a2: lut40059
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    XOR8MEG18: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40060
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40060 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
-
-  end lut40060;
-
-  architecture Structure of lut40060 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5155")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_58
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_58 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_58";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
-
-  end SLICE_58;
-
-  architecture Structure of SLICE_58 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40032
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40060
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_a2_4_2: lut40032
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_a0: lut40060
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_59
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_59 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_59";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
-
-  end SLICE_59;
-
-  architecture Structure of SLICE_59 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40013
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40015
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_en_ss0_0_a2_0: lut40013
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_FS_13_i_a2_8: lut40015
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_60
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_60 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_60";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
-
-  end SLICE_60;
-
-  architecture Structure of SLICE_60 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    ADWR_3: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    ADWR: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40061
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40061 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
-
-  end lut40061;
-
-  architecture Structure of lut40061 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1010")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40062
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40062 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
-
-  end lut40062;
-
-  architecture Structure of lut40062 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FF32")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_61
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_61 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_61";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
-
-  end SLICE_61;
-
-  architecture Structure of SLICE_61 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40061
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40062
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_0io_RNO_0: lut40061
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRRAS_5_u_i: lut40062
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40063
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40063 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
-
-  end lut40063;
-
-  architecture Structure of lut40063 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0002")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_62
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_62 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_62";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
-
-  end SLICE_62;
-
-  architecture Structure of SLICE_62 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40063
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RA10_2_sqmuxa_0_o2: lut40006
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_s_i_a3_1_0: lut40063
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40064
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40064 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
-
-  end lut40064;
-
-  architecture Structure of lut40064 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2222")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_63
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_63 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_63";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
-
-  end SLICE_63;
-
-  architecture Structure of SLICE_63 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    C1WR_1: lut40064
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    C1WR_3: lut40008
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_0io_1: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    Bank_0io_0: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40065
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40065 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
-
-  end lut40065;
-
-  architecture Structure of lut40065 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"AAC0")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_64
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_64 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_64";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
-
-  end SLICE_64;
-
-  architecture Structure of SLICE_64 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40052
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40065
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0: lut40052
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    UFMCLK_r_i_m2: lut40065
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40066
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40066 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
-
-  end lut40066;
-
-  architecture Structure of lut40066 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"3B33")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_65
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_65 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_65";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q1	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M1_CLK	: VitalDelayType := 0 ns;
-      tsetup_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M1_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-          F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-          Q1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE;
-
-  end SLICE_65;
-
-  architecture Structure of SLICE_65 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M1_ipd 	: std_logic := 'X';
-    signal M1_dly 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-    signal Q1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40006
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40066
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMCLK_0io_RNO_0: lut40006
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    PHI2r3_RNITCN41: lut40066
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    PHI2r3: vmuxregsre
-      port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q1_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    PHI2r2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M1_ipd, M1, tipd_M1);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q1_zd         	: std_logic := 'X';
-    VARIABLE Q1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M1_CLK       	: x01 := '0';
-    VARIABLE M1_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M1_dly,
-        TestSignalName => "M1",
-        TestDelay => tisd_M1_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M1_CLK_noedge_posedge,
-        SetupLow => tsetup_M1_CLK_noedge_posedge,
-        HoldHigh => thold_M1_CLK_noedge_posedge,
-        HoldLow => thold_M1_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M1_CLK_TimingDatash,
-        Violation => tviol_M1_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-    Q1_zd 	:= Q1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q1,
-                           PathCondition => TRUE)),
-      GlitchData => Q1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40067
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40067 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
-
-  end lut40067;
-
-  architecture Structure of lut40067 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"3AFA")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40068
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40068 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
-
-  end lut40068;
-
-  architecture Structure of lut40068 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"200F")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_66
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_66 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_66";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
-
-  end SLICE_66;
-
-  architecture Structure of SLICE_66 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40067
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40068
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRCS_0io_RNO: lut40067
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    nRCAS_r_i_a3_1_1_tz: lut40068
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_67
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_67 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_67";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
-
-  end SLICE_67;
-
-  architecture Structure of SLICE_67 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40016
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    ADWR_6: lut40004
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    ADWR_2: lut40016
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_68
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_68 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_68";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-          Q0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
-
-  end SLICE_68;
-
-  architecture Structure of SLICE_68 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    signal VCCI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40008
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40064
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_3: lut40064
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CmdEnable16_5: lut40008
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    Bank_0io_2: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_69
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_69 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_69";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
-
-  end SLICE_69;
-
-  architecture Structure of SLICE_69 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40056
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_Bank_1_3: lut40056
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un1_Bank_1: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40069
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40069 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
-
-  end lut40069;
-
-  architecture Structure of lut40069 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"4454")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40070
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40070 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
-
-  end lut40070;
-
-  architecture Structure of lut40070 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FDFD")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_70
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_70 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_70";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
-
-  end SLICE_70;
-
-  architecture Structure of SLICE_70 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40069
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40070
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdLEDEN_4_u_i_a2: lut40069
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    Cmdn8MEGEN_4_u_i_o2_0: lut40070
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40071
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40071 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
-
-  end lut40071;
-
-  architecture Structure of lut40071 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2020")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40072
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40072 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
-
-  end lut40072;
-
-  architecture Structure of lut40072 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"AABF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_71
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_71 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_71";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
-
-  end SLICE_71;
-
-  architecture Structure of SLICE_71 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40071
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40072
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_0io_RNO_0: lut40071
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    nRWE_0io_RNO: lut40072
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40073
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40073 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
-
-  end lut40073;
-
-  architecture Structure of lut40073 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"FFFE")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_72
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_72 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_72";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
-
-  end SLICE_72;
-
-  architecture Structure of SLICE_72 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40004
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40073
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    UFMSDI_ens2_i_o2_0_3: lut40073
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_5: lut40004
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_73
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_73 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_73";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
-
-  end SLICE_73;
-
-  architecture Structure of SLICE_73 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40038
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    CmdEnable16_4: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdEnable17_5: lut40038
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CASr3: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_posedge,
-        SetupLow => tsetup_M0_CLK_noedge_posedge,
-        HoldHigh => thold_M0_CLK_noedge_posedge,
-        HoldLow => thold_M0_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40074
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40074 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
-
-  end lut40074;
-
-  architecture Structure of lut40074 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"040C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40075
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40075 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
-
-  end lut40075;
-
-  architecture Structure of lut40075 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"0080")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_74
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_74 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_74";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_M0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_Q0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_M0_CLK	: VitalDelayType := 0 ns;
-      tsetup_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_M0_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-          CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
-
-  end SLICE_74;
-
-  architecture Structure of SLICE_74 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal M0_ipd 	: std_logic := 'X';
-    signal M0_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal Q0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    component vmuxregsre
-      port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; 
-            SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; 
-            Q: out Std_logic);
-    end component;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component lut40074
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40075
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    XOR8MEG_3_u_1: lut40074
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    CmdEnable17_4: lut40075
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-    CBR: vmuxregsre
-      port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, 
-                LSR=>GNDI, Q=>Q0_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-      VitalWireDelay(M0_ipd, M0, tipd_M0);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE Q0_zd         	: std_logic := 'X';
-    VARIABLE Q0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_M0_CLK       	: x01 := '0';
-    VARIABLE M0_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => M0_dly,
-        TestSignalName => "M0",
-        TestDelay => tisd_M0_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_M0_CLK_noedge_negedge,
-        SetupLow => tsetup_M0_CLK_noedge_negedge,
-        HoldHigh => thold_M0_CLK_noedge_negedge,
-        HoldLow => thold_M0_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => M0_CLK_TimingDatash,
-        Violation => tviol_M0_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    Q0_zd 	:= Q0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_Q0,
-                           PathCondition => TRUE)),
-      GlitchData => Q0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40076
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40076 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
-
-  end lut40076;
-
-  architecture Structure of lut40076 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"7777")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40077
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40077 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
-
-  end lut40077;
-
-  architecture Structure of lut40077 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"ACAC")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_75
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_75 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_75";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
-
-  end SLICE_75;
-
-  architecture Structure of SLICE_75 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40076
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQML: lut40076
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_9: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40078
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40078 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
-
-  end lut40078;
-
-  architecture Structure of lut40078 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"4000")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40079
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40079 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
-
-  end lut40079;
-
-  architecture Structure of lut40079 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"70CF")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_76
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_76 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_76";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
-
-  end SLICE_76;
-
-  architecture Structure of SLICE_76 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    component lut40078
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40079
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRWE_0io_RNO_1: lut40078
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    RCKEEN_8_u_1_0: lut40079
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, 
-      B0_ipd, A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40080
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40080 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
-
-  end lut40080;
-
-  architecture Structure of lut40080 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"5400")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity lut40081
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40081 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
-
-  end lut40081;
-
-  architecture Structure of lut40081 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"1111")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_77
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_77 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_77";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
-
-  end SLICE_77;
-
-  architecture Structure of SLICE_77 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40080
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40081
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    nRRAS_5_u_i_0: lut40080
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40082
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40082 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
-
-  end lut40082;
-
-  architecture Structure of lut40082 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"2C2C")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_78
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_78 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_78";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-          A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
-
-  end SLICE_78;
-
-  architecture Structure of SLICE_78 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40035
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40082
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_14_i_a2_0_1: lut40035
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    UFMSDI_ens2_i_o2: lut40082
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, 
-      A0_ipd, F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_79
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_79 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_79";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-          B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-          F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
-
-  end SLICE_79;
-
-  architecture Structure of SLICE_79 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40024
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RDQMH: lut40024
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_8: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, 
-      F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_80
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_80 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_80";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
-
-  end SLICE_80;
-
-  architecture Structure of SLICE_80 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_7: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_0: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_81
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_81 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_81";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
-
-  end SLICE_81;
-
-  architecture Structure of SLICE_81 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_6: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_1: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_82
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_82 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_82";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
-
-  end SLICE_82;
-
-  architecture Structure of SLICE_82 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_5: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_2: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_83
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_83 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_83";
-
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
-
-  end SLICE_83;
-
-  architecture Structure of SLICE_83 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40077
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un9_RA_4: lut40077
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    un9_RA_3: lut40077
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity lut40083
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity lut40083 is
-    port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-          Z: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
-
-  end lut40083;
-
-  architecture Structure of lut40083 is
-  begin
-    INST10: ROM16X1A
-      generic map (initval => X"C048")
-      port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
-  end Structure;
-
--- entity SLICE_84
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_84 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_84";
-
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_D0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-          C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
-
-  end SLICE_84;
-
-  architecture Structure of SLICE_84 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal D0_ipd 	: std_logic := 'X';
-    signal C0_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40083
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    RBAd_0: lut40028
-      port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-    RA11d: lut40083
-      port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(D0_ipd, D0, tipd_D0);
-      VitalWireDelay(C0_ipd, C0, tipd_C0);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => D0_ipd'last_event,
-                           PathDelay => tpd_D0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C0_ipd'last_event,
-                           PathDelay => tpd_C0_F0,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity SLICE_85
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity SLICE_85 is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "SLICE_85";
-
-      tipd_D1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_C1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_B0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_A0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_D1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_C1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A1_F1	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_B0_F0	 : VitalDelayType01 := (0 ns, 0 ns);
-      tpd_A0_F0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-          A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-          F0: out Std_logic; F1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
-
-  end SLICE_85;
-
-  architecture Structure of SLICE_85 is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal D1_ipd 	: std_logic := 'X';
-    signal C1_ipd 	: std_logic := 'X';
-    signal B1_ipd 	: std_logic := 'X';
-    signal A1_ipd 	: std_logic := 'X';
-    signal B0_ipd 	: std_logic := 'X';
-    signal A0_ipd 	: std_logic := 'X';
-    signal F0_out 	: std_logic := 'X';
-    signal F1_out 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component lut40028
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-    component lut40058
-      port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; 
-            Z: out Std_logic);
-    end component;
-  begin
-    un1_FS_13_i_a2_6: lut40058
-      port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
-    InitReady3_0_a2_3: lut40028
-      port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(D1_ipd, D1, tipd_D1);
-      VitalWireDelay(C1_ipd, C1, tipd_C1);
-      VitalWireDelay(B1_ipd, B1, tipd_B1);
-      VitalWireDelay(A1_ipd, A1, tipd_A1);
-      VitalWireDelay(B0_ipd, B0, tipd_B0);
-      VitalWireDelay(A0_ipd, A0, tipd_A0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, 
-      F0_out, F1_out)
-    VARIABLE F0_zd         	: std_logic := 'X';
-    VARIABLE F0_GlitchData 	: VitalGlitchDataType;
-    VARIABLE F1_zd         	: std_logic := 'X';
-    VARIABLE F1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    F0_zd 	:= F0_out;
-    F1_zd 	:= F1_out;
-
-    VitalPathDelay01 (
-      OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
-      Paths      => (0 => (InputChangeTime => B0_ipd'last_event,
-                           PathDelay => tpd_B0_F0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => A0_ipd'last_event,
-                           PathDelay => tpd_A0_F0,
-                           PathCondition => TRUE)),
-      GlitchData => F0_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-    VitalPathDelay01 (
-      OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
-      Paths      => (0 => (InputChangeTime => D1_ipd'last_event,
-                           PathDelay => tpd_D1_F1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => C1_ipd'last_event,
-                           PathDelay => tpd_C1_F1,
-                           PathCondition => TRUE),
-                     2 => (InputChangeTime => B1_ipd'last_event,
-                           PathDelay => tpd_B1_F1,
-                           PathCondition => TRUE),
-                     3 => (InputChangeTime => A1_ipd'last_event,
-                           PathDelay => tpd_A1_F1,
-                           PathCondition => TRUE)),
-      GlitchData => F1_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf is
-    port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE;
-
-  end xo2iobuf;
-
-  architecture Structure of xo2iobuf is
-  begin
-    INST1: OBW
-      port map (I=>I, T=>T, O=>PAD);
-  end Structure;
-
--- entity RD_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD0	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
-
-  end RD_0_B;
-
-  architecture Structure of RD_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD0_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_0: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD0_out)
-    VARIABLE RD0_zd         	: std_logic := 'X';
-    VARIABLE RD0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD0_zd 	:= RD0_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD0,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD0,
-                           PathCondition => TRUE)),
-      GlitchData => RD0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mfflsre
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity mfflsre is
-    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-          LSR: in Std_logic; Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE;
-
-  end mfflsre;
-
-  architecture Structure of mfflsre is
-  begin
-    INST01: FD1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity RD_0_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_0_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_0_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE;
-
-  end RD_0_MGIOL;
-
-  architecture Structure of RD_0_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_0: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf0084
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf0084 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf0084 : ENTITY IS TRUE;
-
-  end xo2iobuf0084;
-
-  architecture Structure of xo2iobuf0084 is
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity Dout_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
-
-  end Dout_0_B;
-
-  architecture Structure of Dout_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout0_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_0: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
-    VARIABLE Dout0_zd         	: std_logic := 'X';
-    VARIABLE Dout0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout0_zd 	:= Dout0_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout0,
-                           PathCondition => TRUE)),
-      GlitchData => Dout0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf0085
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf0085 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf0085 : ENTITY IS TRUE;
-
-  end xo2iobuf0085;
-
-  architecture Structure of xo2iobuf0085 is
-  begin
-    INST1: IBPD
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity PHI2B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity PHI2B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2B";
-
-      tipd_PHI2S  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PHI2S_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_PHI2S 	: VitalDelayType := 0 ns;
-      tpw_PHI2S_posedge	: VitalDelayType := 0 ns;
-      tpw_PHI2S_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; PHI2S: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
-
-  end PHI2B;
-
-  architecture Structure of PHI2B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal PHI2S_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0085
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    PHI2_pad: xo2iobuf0085
-      port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_PHI2S_PHI2S          	: x01 := '0';
-    VARIABLE periodcheckinfo_PHI2S	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => PHI2S_ipd,
-        TestSignalName => "PHI2S",
-        Period => tperiod_PHI2S,
-        PulseWidthHigh => tpw_PHI2S_posedge,
-        PulseWidthLow => tpw_PHI2S_negedge,
-        PeriodData => periodcheckinfo_PHI2S,
-        Violation => tviol_PHI2S_PHI2S,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => PHI2S_ipd'last_event,
-                           PathDelay => tpd_PHI2S_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity smuxlregsre
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity smuxlregsre is
-    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-          LSR: in Std_logic; Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE;
-
-  end smuxlregsre;
-
-  architecture Structure of smuxlregsre is
-  begin
-    INST01: IFS1P3DX
-      generic map (GSR => "DISABLED")
-      port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q);
-  end Structure;
-
--- entity PHI2_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity PHI2_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "PHI2_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE;
-
-  end PHI2_MGIOL;
-
-  architecture Structure of PHI2_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    PHI2r_0io: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf0086
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf0086 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf0086 : ENTITY IS TRUE;
-
-  end xo2iobuf0086;
-
-  architecture Structure of xo2iobuf0086 is
-  begin
-    INST1: IB
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity UFMSDOB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity UFMSDOB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDOB";
-
-      tipd_UFMSDOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_UFMSDOS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_UFMSDOS 	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_posedge	: VitalDelayType := 0 ns;
-      tpw_UFMSDOS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
-
-  end UFMSDOB;
-
-  architecture Structure of UFMSDOB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal UFMSDOS_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    UFMSDO_pad: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_UFMSDOS_UFMSDOS          	: x01 := '0';
-    VARIABLE periodcheckinfo_UFMSDOS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => UFMSDOS_ipd,
-        TestSignalName => "UFMSDOS",
-        Period => tperiod_UFMSDOS,
-        PulseWidthHigh => tpw_UFMSDOS_posedge,
-        PulseWidthLow => tpw_UFMSDOS_negedge,
-        PeriodData => periodcheckinfo_UFMSDOS,
-        Violation => tviol_UFMSDOS_UFMSDOS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
-                           PathDelay => tpd_UFMSDOS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMSDIB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity UFMSDIB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDIB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_UFMSDIS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; UFMSDIS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
-
-  end UFMSDIB;
-
-  architecture Structure of UFMSDIB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal UFMSDIS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMSDI_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>UFMSDIS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, UFMSDIS_out)
-    VARIABLE UFMSDIS_zd         	: std_logic := 'X';
-    VARIABLE UFMSDIS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMSDIS_zd 	:= UFMSDIS_out;
-
-    VitalPathDelay01 (
-      OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_UFMSDIS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMSDIS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMSDI_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity UFMSDI_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMSDI_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMSDI_MGIOL : ENTITY IS TRUE;
-
-  end UFMSDI_MGIOL;
-
-  architecture Structure of UFMSDI_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    UFMSDI_r0: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLKB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity UFMCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLKB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_UFMCLKS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; UFMCLKS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
-
-  end UFMCLKB;
-
-  architecture Structure of UFMCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal UFMCLKS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    UFMCLK_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>UFMCLKS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, UFMCLKS_out)
-    VARIABLE UFMCLKS_zd         	: std_logic := 'X';
-    VARIABLE UFMCLKS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    UFMCLKS_zd 	:= UFMCLKS_out;
-
-    VitalPathDelay01 (
-      OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_UFMCLKS,
-                           PathCondition => TRUE)),
-      GlitchData => UFMCLKS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity UFMCLK_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity UFMCLK_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "UFMCLK_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; 
-          CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF UFMCLK_MGIOL : ENTITY IS TRUE;
-
-  end UFMCLK_MGIOL;
-
-  architecture Structure of UFMCLK_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    UFMCLK_0io: mfflsre
-      port map (D0=>OPOS_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CE_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_posedge,
-        SetupLow => tsetup_CE_CLK_noedge_posedge,
-        HoldHigh => thold_CE_CLK_noedge_posedge,
-        HoldLow => thold_CE_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nUFMCSB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nUFMCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCSB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_nUFMCSS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; nUFMCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
-
-  end nUFMCSB;
-
-  architecture Structure of nUFMCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal nUFMCSS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nUFMCS_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>nUFMCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, nUFMCSS_out)
-    VARIABLE nUFMCSS_zd         	: std_logic := 'X';
-    VARIABLE nUFMCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nUFMCSS_zd 	:= nUFMCSS_out;
-
-    VitalPathDelay01 (
-      OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_nUFMCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nUFMCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mfflsre0087
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity mfflsre0087 is
-    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-          LSR: in Std_logic; Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mfflsre0087 : ENTITY IS TRUE;
-
-  end mfflsre0087;
-
-  architecture Structure of mfflsre0087 is
-  begin
-    INST01: FD1P3BX
-      generic map (GSR => "DISABLED")
-      port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity nUFMCS_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nUFMCS_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nUFMCS_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nUFMCS_MGIOL : ENTITY IS TRUE;
-
-  end nUFMCS_MGIOL;
-
-  architecture Structure of nUFMCS_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre0087
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    nUFMCS_r1: mfflsre0087
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMLB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RDQMLB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMLB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMLS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
-
-  end RDQMLB;
-
-  architecture Structure of RDQMLB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMLS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQML_pad: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
-    VARIABLE RDQMLS_zd         	: std_logic := 'X';
-    VARIABLE RDQMLS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMLS_zd 	:= RDQMLS_out;
-
-    VitalPathDelay01 (
-      OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMLS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMLS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RDQMHB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RDQMHB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RDQMHB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RDQMHS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
-
-  end RDQMHB;
-
-  architecture Structure of RDQMHB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RDQMHS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RDQMH_pad: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
-    VARIABLE RDQMHS_zd         	: std_logic := 'X';
-    VARIABLE RDQMHS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RDQMHS_zd 	:= RDQMHS_out;
-
-    VitalPathDelay01 (
-      OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RDQMHS,
-                           PathCondition => TRUE)),
-      GlitchData => RDQMHS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCASB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCASB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_nRCASS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; nRCASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
-
-  end nRCASB;
-
-  architecture Structure of nRCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal nRCASS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCAS_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>nRCASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out)
-    VARIABLE nRCASS_zd         	: std_logic := 'X';
-    VARIABLE nRCASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCASS_zd 	:= nRCASS_out;
-
-    VitalPathDelay01 (
-      OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_nRCASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCAS_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRCAS_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCAS_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE;
-
-  end nRCAS_MGIOL;
-
-  architecture Structure of nRCAS_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre0087
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    nRCAS_0io: mfflsre0087
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRASB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRASB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_nRRASS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; nRRASS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
-
-  end nRRASB;
-
-  architecture Structure of nRRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal nRRASS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRRAS_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>nRRASS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out)
-    VARIABLE nRRASS_zd         	: std_logic := 'X';
-    VARIABLE nRRASS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRRASS_zd 	:= nRRASS_out;
-
-    VitalPathDelay01 (
-      OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_nRRASS,
-                           PathCondition => TRUE)),
-      GlitchData => nRRASS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRRAS_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRRAS_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRRAS_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE;
-
-  end nRRAS_MGIOL;
-
-  architecture Structure of nRRAS_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre0087
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    nRRAS_0io: mfflsre0087
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWEB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWEB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_nRWES	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; nRWES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
-
-  end nRWEB;
-
-  architecture Structure of nRWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal nRWES_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRWE_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>nRWES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out)
-    VARIABLE nRWES_zd         	: std_logic := 'X';
-    VARIABLE nRWES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRWES_zd 	:= nRWES_out;
-
-    VitalPathDelay01 (
-      OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_nRWES,
-                           PathCondition => TRUE)),
-      GlitchData => nRWES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRWE_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRWE_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRWE_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE;
-
-  end nRWE_MGIOL;
-
-  architecture Structure of nRWE_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre0087
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    nRWE_0io: mfflsre0087
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKEB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RCKEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKEB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RCKES	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; RCKES: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
-
-  end RCKEB;
-
-  architecture Structure of RCKEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal RCKES_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RCKE_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>RCKES_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, RCKES_out)
-    VARIABLE RCKES_zd         	: std_logic := 'X';
-    VARIABLE RCKES_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RCKES_zd 	:= RCKES_out;
-
-    VitalPathDelay01 (
-      OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RCKES,
-                           PathCondition => TRUE)),
-      GlitchData => RCKES_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCKE_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RCKE_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCKE_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCKE_MGIOL : ENTITY IS TRUE;
-
-  end RCKE_MGIOL;
-
-  architecture Structure of RCKE_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    RCKE_r2: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RCLKB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RCLKB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RCLKB";
-
-      tipd_RCLKS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_RCLKS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_RCLKS 	: VitalDelayType := 0 ns;
-      tpw_RCLKS_posedge	: VitalDelayType := 0 ns;
-      tpw_RCLKS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; RCLKS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
-
-  end RCLKB;
-
-  architecture Structure of RCLKB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal RCLKS_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    RCLK_pad: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_RCLKS_RCLKS          	: x01 := '0';
-    VARIABLE periodcheckinfo_RCLKS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => RCLKS_ipd,
-        TestSignalName => "RCLKS",
-        Period => tperiod_RCLKS,
-        PulseWidthHigh => tpw_RCLKS_posedge,
-        PulseWidthLow => tpw_RCLKS_negedge,
-        PeriodData => periodcheckinfo_RCLKS,
-        Violation => tviol_RCLKS_RCLKS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => RCLKS_ipd'last_event,
-                           PathDelay => tpd_RCLKS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCSB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRCSB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCSB";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_nRCSS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; nRCSS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
-
-  end nRCSB;
-
-  architecture Structure of nRCSB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal nRCSS_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    nRCS_pad: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>nRCSS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out)
-    VARIABLE nRCSS_zd         	: std_logic := 'X';
-    VARIABLE nRCSS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    nRCSS_zd 	:= nRCSS_out;
-
-    VitalPathDelay01 (
-      OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_nRCSS,
-                           PathCondition => TRUE)),
-      GlitchData => nRCSS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nRCS_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nRCS_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nRCS_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE;
-
-  end nRCS_MGIOL;
-
-  architecture Structure of nRCS_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre0087
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    nRCS_0io: mfflsre0087
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD7	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
-
-  end RD_7_B;
-
-  architecture Structure of RD_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD7_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_7: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD7_out)
-    VARIABLE RD7_zd         	: std_logic := 'X';
-    VARIABLE RD7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD7_zd 	:= RD7_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD7,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD7,
-                           PathCondition => TRUE)),
-      GlitchData => RD7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_7_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_7_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_7_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE;
-
-  end RD_7_MGIOL;
-
-  architecture Structure of RD_7_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_7: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD6	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
-
-  end RD_6_B;
-
-  architecture Structure of RD_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD6_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_6: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD6_out)
-    VARIABLE RD6_zd         	: std_logic := 'X';
-    VARIABLE RD6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD6_zd 	:= RD6_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD6,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD6,
-                           PathCondition => TRUE)),
-      GlitchData => RD6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_6_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_6_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_6_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE;
-
-  end RD_6_MGIOL;
-
-  architecture Structure of RD_6_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_6: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD5	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
-
-  end RD_5_B;
-
-  architecture Structure of RD_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD5_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_5: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD5_out)
-    VARIABLE RD5_zd         	: std_logic := 'X';
-    VARIABLE RD5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD5_zd 	:= RD5_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD5,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD5,
-                           PathCondition => TRUE)),
-      GlitchData => RD5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_5_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_5_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_5_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE;
-
-  end RD_5_MGIOL;
-
-  architecture Structure of RD_5_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_5: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD4	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
-
-  end RD_4_B;
-
-  architecture Structure of RD_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD4_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_4: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD4_out)
-    VARIABLE RD4_zd         	: std_logic := 'X';
-    VARIABLE RD4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD4_zd 	:= RD4_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD4,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD4,
-                           PathCondition => TRUE)),
-      GlitchData => RD4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_4_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_4_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_4_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE;
-
-  end RD_4_MGIOL;
-
-  architecture Structure of RD_4_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_4: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD3	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
-
-  end RD_3_B;
-
-  architecture Structure of RD_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD3_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_3: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD3_out)
-    VARIABLE RD3_zd         	: std_logic := 'X';
-    VARIABLE RD3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD3_zd 	:= RD3_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD3,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD3,
-                           PathCondition => TRUE)),
-      GlitchData => RD3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_3_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_3_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_3_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE;
-
-  end RD_3_MGIOL;
-
-  architecture Structure of RD_3_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_3: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD2	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
-
-  end RD_2_B;
-
-  architecture Structure of RD_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD2_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_2: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD2_out)
-    VARIABLE RD2_zd         	: std_logic := 'X';
-    VARIABLE RD2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD2_zd 	:= RD2_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD2,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD2,
-                           PathCondition => TRUE)),
-      GlitchData => RD2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_2_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_2_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_2_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE;
-
-  end RD_2_MGIOL;
-
-  architecture Structure of RD_2_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_2: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_PADDT  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
-      tpd_PADDT_RD1	 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
-
-  end RD_1_B;
-
-  architecture Structure of RD_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal PADDT_ipd 	: std_logic := 'X';
-    signal RD1_out 	: std_logic := 'X';
-
-    component xo2iobuf
-      port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RD_pad_1: xo2iobuf
-      port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-      VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD1_out)
-    VARIABLE RD1_zd         	: std_logic := 'X';
-    VARIABLE RD1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RD1_zd 	:= RD1_out;
-
-    VitalPathDelay01Z (
-      OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RD1,
-                           PathCondition => TRUE),
-                     1 => (InputChangeTime => PADDT_ipd'last_event,
-                           PathDelay => tpd_PADDT_RD1,
-                           PathCondition => TRUE)),
-      GlitchData => RD1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RD_1_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RD_1_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RD_1_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE;
-
-  end RD_1_MGIOL;
-
-  architecture Structure of RD_1_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    WRD_0io_1: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_11_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RA11	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; RA11: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
-
-  end RA_11_B;
-
-  architecture Structure of RA_11_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal RA11_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_11: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>RA11_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, RA11_out)
-    VARIABLE RA11_zd         	: std_logic := 'X';
-    VARIABLE RA11_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA11_zd 	:= RA11_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RA11,
-                           PathCondition => TRUE)),
-      GlitchData => RA11_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_11_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_11_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_11_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE;
-
-  end RA_11_MGIOL;
-
-  architecture Structure of RA_11_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    RA11_0io: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_10_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_10_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RA10	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; RA10: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
-
-  end RA_10_B;
-
-  architecture Structure of RA_10_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal RA10_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_10: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>RA10_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, RA10_out)
-    VARIABLE RA10_zd         	: std_logic := 'X';
-    VARIABLE RA10_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA10_zd 	:= RA10_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RA10,
-                           PathCondition => TRUE)),
-      GlitchData => RA10_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity mfflsre0088
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity mfflsre0088 is
-    port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-          LSR: in Std_logic; Q: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF mfflsre0088 : ENTITY IS TRUE;
-
-  end mfflsre0088;
-
-  architecture Structure of mfflsre0088 is
-  begin
-    INST01: FD1P3JX
-      generic map (GSR => "DISABLED")
-      port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q);
-  end Structure;
-
--- entity RA_10_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_10_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_10_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_LSR  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tisd_LSR_CLK	: VitalDelayType := 0 ns;
-      tsetup_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_LSR_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; 
-          CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE;
-
-  end RA_10_MGIOL;
-
-  architecture Structure of RA_10_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal LSR_ipd 	: std_logic := 'X';
-    signal LSR_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component mfflsre0088
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    RA10_0io: mfflsre0088
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, 
-                Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_LSR_CLK       	: x01 := '0';
-    VARIABLE LSR_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_posedge,
-        HoldHigh => thold_OPOS_CLK_noedge_posedge,
-        HoldLow => thold_OPOS_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => LSR_dly,
-        TestSignalName => "LSR",
-        TestDelay => tisd_LSR_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_LSR_CLK_noedge_posedge,
-        SetupLow => tsetup_LSR_CLK_noedge_posedge,
-        HoldHigh => thold_LSR_CLK_noedge_posedge,
-        HoldLow => thold_LSR_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => LSR_CLK_TimingDatash,
-        Violation => tviol_LSR_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_9_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_9_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA9	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA9: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
-
-  end RA_9_B;
-
-  architecture Structure of RA_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA9_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_9: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA9_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
-    VARIABLE RA9_zd         	: std_logic := 'X';
-    VARIABLE RA9_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA9_zd 	:= RA9_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA9,
-                           PathCondition => TRUE)),
-      GlitchData => RA9_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_8_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_8_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA8	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA8: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
-
-  end RA_8_B;
-
-  architecture Structure of RA_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA8_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_8: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA8_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
-    VARIABLE RA8_zd         	: std_logic := 'X';
-    VARIABLE RA8_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA8_zd 	:= RA8_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA8,
-                           PathCondition => TRUE)),
-      GlitchData => RA8_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_7_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA7	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
-
-  end RA_7_B;
-
-  architecture Structure of RA_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA7_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_7: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
-    VARIABLE RA7_zd         	: std_logic := 'X';
-    VARIABLE RA7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA7_zd 	:= RA7_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA7,
-                           PathCondition => TRUE)),
-      GlitchData => RA7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_6_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA6	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
-
-  end RA_6_B;
-
-  architecture Structure of RA_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA6_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_6: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
-    VARIABLE RA6_zd         	: std_logic := 'X';
-    VARIABLE RA6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA6_zd 	:= RA6_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA6,
-                           PathCondition => TRUE)),
-      GlitchData => RA6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_5_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA5	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
-
-  end RA_5_B;
-
-  architecture Structure of RA_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA5_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_5: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
-    VARIABLE RA5_zd         	: std_logic := 'X';
-    VARIABLE RA5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA5_zd 	:= RA5_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA5,
-                           PathCondition => TRUE)),
-      GlitchData => RA5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_4_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA4	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
-
-  end RA_4_B;
-
-  architecture Structure of RA_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA4_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_4: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
-    VARIABLE RA4_zd         	: std_logic := 'X';
-    VARIABLE RA4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA4_zd 	:= RA4_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA4,
-                           PathCondition => TRUE)),
-      GlitchData => RA4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_3_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA3	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
-
-  end RA_3_B;
-
-  architecture Structure of RA_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA3_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_3: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
-    VARIABLE RA3_zd         	: std_logic := 'X';
-    VARIABLE RA3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA3_zd 	:= RA3_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA3,
-                           PathCondition => TRUE)),
-      GlitchData => RA3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_2_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA2	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
-
-  end RA_2_B;
-
-  architecture Structure of RA_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA2_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_2: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
-    VARIABLE RA2_zd         	: std_logic := 'X';
-    VARIABLE RA2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA2_zd 	:= RA2_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA2,
-                           PathCondition => TRUE)),
-      GlitchData => RA2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA1	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
-
-  end RA_1_B;
-
-  architecture Structure of RA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA1_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_1: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
-    VARIABLE RA1_zd         	: std_logic := 'X';
-    VARIABLE RA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA1_zd 	:= RA1_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA1,
-                           PathCondition => TRUE)),
-      GlitchData => RA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RA_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RA_0_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_RA0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; RA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
-
-  end RA_0_B;
-
-  architecture Structure of RA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal RA0_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RA_pad_0: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>RA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
-    VARIABLE RA0_zd         	: std_logic := 'X';
-    VARIABLE RA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RA0_zd 	:= RA0_out;
-
-    VitalPathDelay01 (
-      OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_RA0,
-                           PathCondition => TRUE)),
-      GlitchData => RA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RBA_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RBA1	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; RBA1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
-
-  end RBA_1_B;
-
-  architecture Structure of RBA_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal RBA1_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_1: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>RBA1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out)
-    VARIABLE RBA1_zd         	: std_logic := 'X';
-    VARIABLE RBA1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA1_zd 	:= RBA1_out;
-
-    VitalPathDelay01 (
-      OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RBA1,
-                           PathCondition => TRUE)),
-      GlitchData => RBA1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_1_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RBA_1_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_1_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE;
-
-  end RBA_1_MGIOL;
-
-  architecture Structure of RBA_1_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    RBA_0io_1: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RBA_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_B";
-
-      tipd_IOLDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_IOLDO_RBA0	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (IOLDO: in Std_logic; RBA0: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
-
-  end RBA_0_B;
-
-  architecture Structure of RBA_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_ipd 	: std_logic := 'X';
-    signal RBA0_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    RBA_pad_0: xo2iobuf0084
-      port map (I=>IOLDO_ipd, PAD=>RBA0_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out)
-    VARIABLE RBA0_zd         	: std_logic := 'X';
-    VARIABLE RBA0_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    RBA0_zd 	:= RBA0_out;
-
-    VitalPathDelay01 (
-      OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
-      Paths      => (0 => (InputChangeTime => IOLDO_ipd'last_event,
-                           PathDelay => tpd_IOLDO_RBA0,
-                           PathCondition => TRUE)),
-      GlitchData => RBA0_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RBA_0_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RBA_0_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "RBA_0_MGIOL";
-
-      tipd_OPOS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_IOLDO	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_OPOS_CLK	: VitalDelayType := 0 ns;
-      tsetup_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_OPOS_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE;
-
-  end RBA_0_MGIOL;
-
-  architecture Structure of RBA_0_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal IOLDO_out 	: std_logic := 'X';
-    signal OPOS_ipd 	: std_logic := 'X';
-    signal OPOS_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component mfflsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    RBA_0io_0: mfflsre
-      port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
-    VARIABLE IOLDO_zd         	: std_logic := 'X';
-    VARIABLE IOLDO_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_OPOS_CLK       	: x01 := '0';
-    VARIABLE OPOS_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => OPOS_dly,
-        TestSignalName => "OPOS",
-        TestDelay => tisd_OPOS_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
-        SetupLow => tsetup_OPOS_CLK_noedge_negedge,
-        HoldHigh => thold_OPOS_CLK_noedge_negedge,
-        HoldLow => thold_OPOS_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => OPOS_CLK_TimingDatash,
-        Violation => tviol_OPOS_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    IOLDO_zd 	:= IOLDO_out;
-
-    VitalPathDelay01 (
-      OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_IOLDO,
-                           PathCondition => TRUE)),
-      GlitchData => IOLDO_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf0089
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf0089 is
-    port (I: in Std_logic; PAD: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf0089 : ENTITY IS TRUE;
-
-  end xo2iobuf0089;
-
-  architecture Structure of xo2iobuf0089 is
-  begin
-    INST5: OB
-      port map (I=>I, O=>PAD);
-  end Structure;
-
--- entity LEDB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity LEDB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "LEDB";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_LEDS	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; LEDS: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
-
-  end LEDB;
-
-  architecture Structure of LEDB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal LEDS_out 	: std_logic := 'X';
-
-    component xo2iobuf0089
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    LED_pad: xo2iobuf0089
-      port map (I=>PADDO_ipd, PAD=>LEDS_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
-    VARIABLE LEDS_zd         	: std_logic := 'X';
-    VARIABLE LEDS_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    LEDS_zd 	:= LEDS_out;
-
-    VitalPathDelay01 (
-      OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_LEDS,
-                           PathCondition => TRUE)),
-      GlitchData => LEDS_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity xo2iobuf0090
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity xo2iobuf0090 is
-    port (Z: out Std_logic; PAD: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF xo2iobuf0090 : ENTITY IS TRUE;
-
-  end xo2iobuf0090;
-
-  architecture Structure of xo2iobuf0090 is
-  begin
-    INST1: IBPU
-      port map (I=>PAD, O=>Z);
-  end Structure;
-
--- entity nFWEB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nFWEB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nFWEB";
-
-      tipd_nFWES  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nFWES_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nFWES 	: VitalDelayType := 0 ns;
-      tpw_nFWES_posedge	: VitalDelayType := 0 ns;
-      tpw_nFWES_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nFWES: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
-
-  end nFWEB;
-
-  architecture Structure of nFWEB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nFWES_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0090
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nFWE_pad: xo2iobuf0090
-      port map (Z=>PADDI_out, PAD=>nFWES_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nFWES_nFWES          	: x01 := '0';
-    VARIABLE periodcheckinfo_nFWES	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nFWES_ipd,
-        TestSignalName => "nFWES",
-        Period => tperiod_nFWES,
-        PulseWidthHigh => tpw_nFWES_posedge,
-        PulseWidthLow => tpw_nFWES_negedge,
-        PeriodData => periodcheckinfo_nFWES,
-        Violation => tviol_nFWES_nFWES,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nFWES_ipd'last_event,
-                           PathDelay => tpd_nFWES_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCRASB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nCRASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCRASB";
-
-      tipd_nCRASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCRASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCRASS 	: VitalDelayType := 0 ns;
-      tpw_nCRASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCRASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCRASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
-
-  end nCRASB;
-
-  architecture Structure of nCRASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCRASS_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0090
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCRAS_pad: xo2iobuf0090
-      port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCRASS_nCRASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCRASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCRASS_ipd,
-        TestSignalName => "nCRASS",
-        Period => tperiod_nCRASS,
-        PulseWidthHigh => tpw_nCRASS_posedge,
-        PulseWidthLow => tpw_nCRASS_negedge,
-        PeriodData => periodcheckinfo_nCRASS,
-        Violation => tviol_nCRASS_nCRASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCRASS_ipd'last_event,
-                           PathDelay => tpd_nCRASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity nCCASB
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity nCCASB is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "nCCASB";
-
-      tipd_nCCASS  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_nCCASS_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_nCCASS 	: VitalDelayType := 0 ns;
-      tpw_nCCASS_posedge	: VitalDelayType := 0 ns;
-      tpw_nCCASS_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; nCCASS: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
-
-  end nCCASB;
-
-  architecture Structure of nCCASB is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal nCCASS_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0090
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    nCCAS_pad: xo2iobuf0090
-      port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_nCCASS_nCCASS          	: x01 := '0';
-    VARIABLE periodcheckinfo_nCCASS	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => nCCASS_ipd,
-        TestSignalName => "nCCASS",
-        Period => tperiod_nCCASS,
-        PulseWidthHigh => tpw_nCCASS_posedge,
-        PulseWidthLow => tpw_nCCASS_negedge,
-        PeriodData => periodcheckinfo_nCCASS,
-        Violation => tviol_nCCASS_nCCASS,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => nCCASS_ipd'last_event,
-                           PathDelay => tpd_nCCASS_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_7_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_7_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout7	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout7: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
-
-  end Dout_7_B;
-
-  architecture Structure of Dout_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout7_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_7: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout7_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
-    VARIABLE Dout7_zd         	: std_logic := 'X';
-    VARIABLE Dout7_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout7_zd 	:= Dout7_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout7,
-                           PathCondition => TRUE)),
-      GlitchData => Dout7_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_6_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_6_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout6	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout6: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
-
-  end Dout_6_B;
-
-  architecture Structure of Dout_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout6_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_6: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout6_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
-    VARIABLE Dout6_zd         	: std_logic := 'X';
-    VARIABLE Dout6_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout6_zd 	:= Dout6_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout6,
-                           PathCondition => TRUE)),
-      GlitchData => Dout6_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_5_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_5_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout5	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout5: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
-
-  end Dout_5_B;
-
-  architecture Structure of Dout_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout5_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_5: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout5_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
-    VARIABLE Dout5_zd         	: std_logic := 'X';
-    VARIABLE Dout5_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout5_zd 	:= Dout5_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout5,
-                           PathCondition => TRUE)),
-      GlitchData => Dout5_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_4_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_4_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout4	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout4: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
-
-  end Dout_4_B;
-
-  architecture Structure of Dout_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout4_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_4: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout4_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
-    VARIABLE Dout4_zd         	: std_logic := 'X';
-    VARIABLE Dout4_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout4_zd 	:= Dout4_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout4,
-                           PathCondition => TRUE)),
-      GlitchData => Dout4_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_3_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_3_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout3	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout3: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
-
-  end Dout_3_B;
-
-  architecture Structure of Dout_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout3_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_3: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout3_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
-    VARIABLE Dout3_zd         	: std_logic := 'X';
-    VARIABLE Dout3_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout3_zd 	:= Dout3_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout3,
-                           PathCondition => TRUE)),
-      GlitchData => Dout3_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_2_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_2_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout2	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout2: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
-
-  end Dout_2_B;
-
-  architecture Structure of Dout_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout2_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_2: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout2_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
-    VARIABLE Dout2_zd         	: std_logic := 'X';
-    VARIABLE Dout2_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout2_zd 	:= Dout2_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout2,
-                           PathCondition => TRUE)),
-      GlitchData => Dout2_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Dout_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Dout_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Dout_1_B";
-
-      tipd_PADDO  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_PADDO_Dout1	 : VitalDelayType01 := (0 ns, 0 ns));
-
-    port (PADDO: in Std_logic; Dout1: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
-
-  end Dout_1_B;
-
-  architecture Structure of Dout_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDO_ipd 	: std_logic := 'X';
-    signal Dout1_out 	: std_logic := 'X';
-
-    component xo2iobuf0084
-      port (I: in Std_logic; PAD: out Std_logic);
-    end component;
-  begin
-    Dout_pad_1: xo2iobuf0084
-      port map (I=>PADDO_ipd, PAD=>Dout1_out);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
-    VARIABLE Dout1_zd         	: std_logic := 'X';
-    VARIABLE Dout1_GlitchData 	: VitalGlitchDataType;
-
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-
-    END IF;
-
-    Dout1_zd 	:= Dout1_out;
-
-    VitalPathDelay01 (
-      OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
-      Paths      => (0 => (InputChangeTime => PADDO_ipd'last_event,
-                           PathDelay => tpd_PADDO_Dout1,
-                           PathCondition => TRUE)),
-      GlitchData => Dout1_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_B";
-
-      tipd_Din7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din7 	: VitalDelayType := 0 ns;
-      tpw_Din7_posedge	: VitalDelayType := 0 ns;
-      tpw_Din7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
-
-  end Din_7_B;
-
-  architecture Structure of Din_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din7_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_7: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din7_Din7          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din7_ipd,
-        TestSignalName => "Din7",
-        Period => tperiod_Din7,
-        PulseWidthHigh => tpw_Din7_posedge,
-        PulseWidthLow => tpw_Din7_negedge,
-        PeriodData => periodcheckinfo_Din7,
-        Violation => tviol_Din7_Din7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din7_ipd'last_event,
-                           PathDelay => tpd_Din7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_7_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_7_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_7_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE;
-
-  end Din_7_MGIOL;
-
-  architecture Structure of Din_7_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    Bank_0io_7: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_B";
-
-      tipd_Din6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din6 	: VitalDelayType := 0 ns;
-      tpw_Din6_posedge	: VitalDelayType := 0 ns;
-      tpw_Din6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
-
-  end Din_6_B;
-
-  architecture Structure of Din_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din6_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_6: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din6_Din6          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din6_ipd,
-        TestSignalName => "Din6",
-        Period => tperiod_Din6,
-        PulseWidthHigh => tpw_Din6_posedge,
-        PulseWidthLow => tpw_Din6_negedge,
-        PeriodData => periodcheckinfo_Din6,
-        Violation => tviol_Din6_Din6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din6_ipd'last_event,
-                           PathDelay => tpd_Din6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_6_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_6_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_6_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE;
-
-  end Din_6_MGIOL;
-
-  architecture Structure of Din_6_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    Bank_0io_6: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_B";
-
-      tipd_Din5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din5 	: VitalDelayType := 0 ns;
-      tpw_Din5_posedge	: VitalDelayType := 0 ns;
-      tpw_Din5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
-
-  end Din_5_B;
-
-  architecture Structure of Din_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din5_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_5: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din5_Din5          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din5_ipd,
-        TestSignalName => "Din5",
-        Period => tperiod_Din5,
-        PulseWidthHigh => tpw_Din5_posedge,
-        PulseWidthLow => tpw_Din5_negedge,
-        PeriodData => periodcheckinfo_Din5,
-        Violation => tviol_Din5_Din5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din5_ipd'last_event,
-                           PathDelay => tpd_Din5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_5_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_5_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_5_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE;
-
-  end Din_5_MGIOL;
-
-  architecture Structure of Din_5_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    Bank_0io_5: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_B";
-
-      tipd_Din4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din4 	: VitalDelayType := 0 ns;
-      tpw_Din4_posedge	: VitalDelayType := 0 ns;
-      tpw_Din4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
-
-  end Din_4_B;
-
-  architecture Structure of Din_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din4_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_4: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din4_Din4          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din4_ipd,
-        TestSignalName => "Din4",
-        Period => tperiod_Din4,
-        PulseWidthHigh => tpw_Din4_posedge,
-        PulseWidthLow => tpw_Din4_negedge,
-        PeriodData => periodcheckinfo_Din4,
-        Violation => tviol_Din4_Din4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din4_ipd'last_event,
-                           PathDelay => tpd_Din4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_4_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_4_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_4_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE;
-
-  end Din_4_MGIOL;
-
-  architecture Structure of Din_4_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    Bank_0io_4: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_B";
-
-      tipd_Din3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din3 	: VitalDelayType := 0 ns;
-      tpw_Din3_posedge	: VitalDelayType := 0 ns;
-      tpw_Din3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
-
-  end Din_3_B;
-
-  architecture Structure of Din_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din3_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_3: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din3_Din3          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din3_ipd,
-        TestSignalName => "Din3",
-        Period => tperiod_Din3,
-        PulseWidthHigh => tpw_Din3_posedge,
-        PulseWidthLow => tpw_Din3_negedge,
-        PeriodData => periodcheckinfo_Din3,
-        Violation => tviol_Din3_Din3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din3_ipd'last_event,
-                           PathDelay => tpd_Din3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_3_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_3_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_3_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_posedge	: VitalDelayType := 0 ns;
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE;
-
-  end Din_3_MGIOL;
-
-  architecture Structure of Din_3_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal VCCI: Std_logic;
-    signal GNDI: Std_logic;
-    component vcc
-      port (PWR1: out Std_logic);
-    end component;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    Bank_0io_3: smuxlregsre
-      port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
-    DRIVEVCC: vcc
-      port map (PWR1=>VCCI);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_posedge,
-        SetupLow => tsetup_DI_CLK_noedge_posedge,
-        HoldHigh => thold_DI_CLK_noedge_posedge,
-        HoldLow => thold_DI_CLK_noedge_posedge,
-        CheckEnabled => TRUE,
-        RefTransition => '/',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_B";
-
-      tipd_Din2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din2 	: VitalDelayType := 0 ns;
-      tpw_Din2_posedge	: VitalDelayType := 0 ns;
-      tpw_Din2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
-
-  end Din_2_B;
-
-  architecture Structure of Din_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din2_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_2: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din2_Din2          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din2_ipd,
-        TestSignalName => "Din2",
-        Period => tperiod_Din2,
-        PulseWidthHigh => tpw_Din2_posedge,
-        PulseWidthLow => tpw_Din2_negedge,
-        PeriodData => periodcheckinfo_Din2,
-        Violation => tviol_Din2_Din2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din2_ipd'last_event,
-                           PathDelay => tpd_Din2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_2_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_2_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_2_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE;
-
-  end Din_2_MGIOL;
-
-  architecture Structure of Din_2_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCS: smuxlregsre
-      port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_negedge,
-        SetupLow => tsetup_DI_CLK_noedge_negedge,
-        HoldHigh => thold_DI_CLK_noedge_negedge,
-        HoldLow => thold_DI_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_B";
-
-      tipd_Din1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din1 	: VitalDelayType := 0 ns;
-      tpw_Din1_posedge	: VitalDelayType := 0 ns;
-      tpw_Din1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
-
-  end Din_1_B;
-
-  architecture Structure of Din_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din1_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_1: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din1_Din1          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din1_ipd,
-        TestSignalName => "Din1",
-        Period => tperiod_Din1,
-        PulseWidthHigh => tpw_Din1_posedge,
-        PulseWidthLow => tpw_Din1_negedge,
-        PeriodData => periodcheckinfo_Din1,
-        Violation => tviol_Din1_Din1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din1_ipd'last_event,
-                           PathDelay => tpd_Din1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_1_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_1_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_1_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE;
-
-  end Din_1_MGIOL;
-
-  architecture Structure of Din_1_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMCLK: smuxlregsre
-      port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_negedge,
-        SetupLow => tsetup_DI_CLK_noedge_negedge,
-        HoldHigh => thold_DI_CLK_noedge_negedge,
-        HoldLow => thold_DI_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_B";
-
-      tipd_Din0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_Din0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_Din0 	: VitalDelayType := 0 ns;
-      tpw_Din0_posedge	: VitalDelayType := 0 ns;
-      tpw_Din0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; Din0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
-
-  end Din_0_B;
-
-  architecture Structure of Din_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal Din0_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    Din_pad_0: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>Din0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_Din0_Din0          	: x01 := '0';
-    VARIABLE periodcheckinfo_Din0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => Din0_ipd,
-        TestSignalName => "Din0",
-        Period => tperiod_Din0,
-        PulseWidthHigh => tpw_Din0_posedge,
-        PulseWidthLow => tpw_Din0_negedge,
-        PeriodData => periodcheckinfo_Din0,
-        Violation => tviol_Din0_Din0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => Din0_ipd'last_event,
-                           PathDelay => tpd_Din0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity Din_0_MGIOL
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity Din_0_MGIOL is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "Din_0_MGIOL";
-
-      tipd_DI  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CE  	: VitalDelayType01 := (0 ns, 0 ns);
-      tipd_CLK  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CLK_INP	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CLK 	: VitalDelayType := 0 ns;
-      tpw_CLK_posedge	: VitalDelayType := 0 ns;
-      tpw_CLK_negedge	: VitalDelayType := 0 ns;
-      ticd_CLK	: VitalDelayType := 0 ns;
-      tisd_DI_CLK	: VitalDelayType := 0 ns;
-      tsetup_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_DI_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      tisd_CE_CLK	: VitalDelayType := 0 ns;
-      tsetup_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns;
-      thold_CE_CLK_noedge_negedge	: VitalDelayType := 0 ns);
-
-    port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-          INP: out Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE;
-
-  end Din_0_MGIOL;
-
-  architecture Structure of Din_0_MGIOL is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal DI_ipd 	: std_logic := 'X';
-    signal DI_dly 	: std_logic := 'X';
-    signal CE_ipd 	: std_logic := 'X';
-    signal CE_dly 	: std_logic := 'X';
-    signal CLK_ipd 	: std_logic := 'X';
-    signal CLK_dly 	: std_logic := 'X';
-    signal INP_out 	: std_logic := 'X';
-
-    signal CLK_NOTIN: Std_logic;
-    signal GNDI: Std_logic;
-    component gnd
-      port (PWR0: out Std_logic);
-    end component;
-    component inverter
-      port (I: in Std_logic; Z: out Std_logic);
-    end component;
-    component smuxlregsre
-      port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; 
-            LSR: in Std_logic; Q: out Std_logic);
-    end component;
-  begin
-    CmdUFMSDI: smuxlregsre
-      port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out);
-    CLK_INVERTERIN: inverter
-      port map (I=>CLK_dly, Z=>CLK_NOTIN);
-    DRIVEGND: gnd
-      port map (PWR0=>GNDI);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(DI_ipd, DI, tipd_DI);
-      VitalWireDelay(CE_ipd, CE, tipd_CE);
-      VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
-    END BLOCK;
-
-    --  Setup and Hold DELAYs
-    SignalDelay : BLOCK
-    BEGIN
-      VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
-      VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
-      VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out)
-    VARIABLE INP_zd         	: std_logic := 'X';
-    VARIABLE INP_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_DI_CLK       	: x01 := '0';
-    VARIABLE DI_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CE_CLK       	: x01 := '0';
-    VARIABLE CE_CLK_TimingDatash	: VitalTimingDataType;
-    VARIABLE tviol_CLK_CLK          	: x01 := '0';
-    VARIABLE periodcheckinfo_CLK	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalSetupHoldCheck (
-        TestSignal => DI_dly,
-        TestSignalName => "DI",
-        TestDelay => tisd_DI_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_DI_CLK_noedge_negedge,
-        SetupLow => tsetup_DI_CLK_noedge_negedge,
-        HoldHigh => thold_DI_CLK_noedge_negedge,
-        HoldLow => thold_DI_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => DI_CLK_TimingDatash,
-        Violation => tviol_DI_CLK,
-        MsgSeverity => warning);
-      VitalSetupHoldCheck (
-        TestSignal => CE_dly,
-        TestSignalName => "CE",
-        TestDelay => tisd_CE_CLK,
-        RefSignal => CLK_dly,
-        RefSignalName => "CLK",
-        RefDelay => ticd_CLK,
-        SetupHigh => tsetup_CE_CLK_noedge_negedge,
-        SetupLow => tsetup_CE_CLK_noedge_negedge,
-        HoldHigh => thold_CE_CLK_noedge_negedge,
-        HoldLow => thold_CE_CLK_noedge_negedge,
-        CheckEnabled => TRUE,
-        RefTransition => '\',
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        TimingData => CE_CLK_TimingDatash,
-        Violation => tviol_CE_CLK,
-        MsgSeverity => warning);
-      VitalPeriodPulseCheck (
-        TestSignal => CLK_ipd,
-        TestSignalName => "CLK",
-        Period => tperiod_CLK,
-        PulseWidthHigh => tpw_CLK_posedge,
-        PulseWidthLow => tpw_CLK_negedge,
-        PeriodData => periodcheckinfo_CLK,
-        Violation => tviol_CLK_CLK,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    INP_zd 	:= INP_out;
-
-    VitalPathDelay01 (
-      OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
-      Paths      => (0 => (InputChangeTime => CLK_dly'last_event,
-                           PathDelay => tpd_CLK_INP,
-                           PathCondition => TRUE)),
-      GlitchData => INP_GlitchData,
-      Mode       => ondetect, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity CROW_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_1_B";
-
-      tipd_CROW1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW1 	: VitalDelayType := 0 ns;
-      tpw_CROW1_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
-
-  end CROW_1_B;
-
-  architecture Structure of CROW_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW1_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_1: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>CROW1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW1_CROW1          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW1_ipd,
-        TestSignalName => "CROW1",
-        Period => tperiod_CROW1,
-        PulseWidthHigh => tpw_CROW1_posedge,
-        PulseWidthLow => tpw_CROW1_negedge,
-        PeriodData => periodcheckinfo_CROW1,
-        Violation => tviol_CROW1_CROW1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW1_ipd'last_event,
-                           PathDelay => tpd_CROW1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity CROW_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity CROW_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "CROW_0_B";
-
-      tipd_CROW0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_CROW0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_CROW0 	: VitalDelayType := 0 ns;
-      tpw_CROW0_posedge	: VitalDelayType := 0 ns;
-      tpw_CROW0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; CROW0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
-
-  end CROW_0_B;
-
-  architecture Structure of CROW_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal CROW0_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    CROW_pad_0: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>CROW0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_CROW0_CROW0          	: x01 := '0';
-    VARIABLE periodcheckinfo_CROW0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => CROW0_ipd,
-        TestSignalName => "CROW0",
-        Period => tperiod_CROW0,
-        PulseWidthHigh => tpw_CROW0_posedge,
-        PulseWidthLow => tpw_CROW0_negedge,
-        PeriodData => periodcheckinfo_CROW0,
-        Violation => tviol_CROW0_CROW0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => CROW0_ipd'last_event,
-                           PathDelay => tpd_CROW0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_9_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_9_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_9_B";
-
-      tipd_MAin9  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin9_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin9 	: VitalDelayType := 0 ns;
-      tpw_MAin9_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin9_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin9: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
-
-  end MAin_9_B;
-
-  architecture Structure of MAin_9_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin9_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_9: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin9_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin9_MAin9          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin9	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin9_ipd,
-        TestSignalName => "MAin9",
-        Period => tperiod_MAin9,
-        PulseWidthHigh => tpw_MAin9_posedge,
-        PulseWidthLow => tpw_MAin9_negedge,
-        PeriodData => periodcheckinfo_MAin9,
-        Violation => tviol_MAin9_MAin9,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin9_ipd'last_event,
-                           PathDelay => tpd_MAin9_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_8_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_8_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_8_B";
-
-      tipd_MAin8  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin8_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin8 	: VitalDelayType := 0 ns;
-      tpw_MAin8_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin8_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin8: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
-
-  end MAin_8_B;
-
-  architecture Structure of MAin_8_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin8_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_8: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin8_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin8_MAin8          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin8	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin8_ipd,
-        TestSignalName => "MAin8",
-        Period => tperiod_MAin8,
-        PulseWidthHigh => tpw_MAin8_posedge,
-        PulseWidthLow => tpw_MAin8_negedge,
-        PeriodData => periodcheckinfo_MAin8,
-        Violation => tviol_MAin8_MAin8,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin8_ipd'last_event,
-                           PathDelay => tpd_MAin8_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_7_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_7_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_7_B";
-
-      tipd_MAin7  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin7_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin7 	: VitalDelayType := 0 ns;
-      tpw_MAin7_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin7_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin7: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
-
-  end MAin_7_B;
-
-  architecture Structure of MAin_7_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin7_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_7: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin7_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin7_MAin7          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin7	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin7_ipd,
-        TestSignalName => "MAin7",
-        Period => tperiod_MAin7,
-        PulseWidthHigh => tpw_MAin7_posedge,
-        PulseWidthLow => tpw_MAin7_negedge,
-        PeriodData => periodcheckinfo_MAin7,
-        Violation => tviol_MAin7_MAin7,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin7_ipd'last_event,
-                           PathDelay => tpd_MAin7_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_6_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_6_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_6_B";
-
-      tipd_MAin6  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin6_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin6 	: VitalDelayType := 0 ns;
-      tpw_MAin6_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin6_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin6: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
-
-  end MAin_6_B;
-
-  architecture Structure of MAin_6_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin6_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_6: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin6_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin6_MAin6          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin6	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin6_ipd,
-        TestSignalName => "MAin6",
-        Period => tperiod_MAin6,
-        PulseWidthHigh => tpw_MAin6_posedge,
-        PulseWidthLow => tpw_MAin6_negedge,
-        PeriodData => periodcheckinfo_MAin6,
-        Violation => tviol_MAin6_MAin6,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin6_ipd'last_event,
-                           PathDelay => tpd_MAin6_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_5_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_5_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_5_B";
-
-      tipd_MAin5  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin5_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin5 	: VitalDelayType := 0 ns;
-      tpw_MAin5_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin5_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin5: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
-
-  end MAin_5_B;
-
-  architecture Structure of MAin_5_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin5_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_5: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin5_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin5_MAin5          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin5	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin5_ipd,
-        TestSignalName => "MAin5",
-        Period => tperiod_MAin5,
-        PulseWidthHigh => tpw_MAin5_posedge,
-        PulseWidthLow => tpw_MAin5_negedge,
-        PeriodData => periodcheckinfo_MAin5,
-        Violation => tviol_MAin5_MAin5,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin5_ipd'last_event,
-                           PathDelay => tpd_MAin5_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_4_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_4_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_4_B";
-
-      tipd_MAin4  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin4_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin4 	: VitalDelayType := 0 ns;
-      tpw_MAin4_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin4_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin4: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
-
-  end MAin_4_B;
-
-  architecture Structure of MAin_4_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin4_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_4: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin4_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin4_MAin4          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin4	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin4_ipd,
-        TestSignalName => "MAin4",
-        Period => tperiod_MAin4,
-        PulseWidthHigh => tpw_MAin4_posedge,
-        PulseWidthLow => tpw_MAin4_negedge,
-        PeriodData => periodcheckinfo_MAin4,
-        Violation => tviol_MAin4_MAin4,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin4_ipd'last_event,
-                           PathDelay => tpd_MAin4_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_3_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_3_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_3_B";
-
-      tipd_MAin3  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin3_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin3 	: VitalDelayType := 0 ns;
-      tpw_MAin3_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin3_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin3: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
-
-  end MAin_3_B;
-
-  architecture Structure of MAin_3_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin3_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_3: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin3_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin3_MAin3          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin3	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin3_ipd,
-        TestSignalName => "MAin3",
-        Period => tperiod_MAin3,
-        PulseWidthHigh => tpw_MAin3_posedge,
-        PulseWidthLow => tpw_MAin3_negedge,
-        PeriodData => periodcheckinfo_MAin3,
-        Violation => tviol_MAin3_MAin3,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin3_ipd'last_event,
-                           PathDelay => tpd_MAin3_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_2_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_2_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_2_B";
-
-      tipd_MAin2  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin2_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin2 	: VitalDelayType := 0 ns;
-      tpw_MAin2_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin2_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin2: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
-
-  end MAin_2_B;
-
-  architecture Structure of MAin_2_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin2_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_2: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin2_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin2_MAin2          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin2	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin2_ipd,
-        TestSignalName => "MAin2",
-        Period => tperiod_MAin2,
-        PulseWidthHigh => tpw_MAin2_posedge,
-        PulseWidthLow => tpw_MAin2_negedge,
-        PeriodData => periodcheckinfo_MAin2,
-        Violation => tviol_MAin2_MAin2,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin2_ipd'last_event,
-                           PathDelay => tpd_MAin2_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_1_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_1_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_1_B";
-
-      tipd_MAin1  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin1_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin1 	: VitalDelayType := 0 ns;
-      tpw_MAin1_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin1_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin1: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
-
-  end MAin_1_B;
-
-  architecture Structure of MAin_1_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin1_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_1: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin1_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin1_MAin1          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin1	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin1_ipd,
-        TestSignalName => "MAin1",
-        Period => tperiod_MAin1,
-        PulseWidthHigh => tpw_MAin1_posedge,
-        PulseWidthLow => tpw_MAin1_negedge,
-        PeriodData => periodcheckinfo_MAin1,
-        Violation => tviol_MAin1_MAin1,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin1_ipd'last_event,
-                           PathDelay => tpd_MAin1_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity MAin_0_B
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity MAin_0_B is
-    -- miscellaneous vital GENERICs
-    GENERIC (
-      TimingChecksOn	: boolean := TRUE;
-      XOn           	: boolean := FALSE;
-      MsgOn         	: boolean := TRUE;
-      InstancePath  	: string := "MAin_0_B";
-
-      tipd_MAin0  	: VitalDelayType01 := (0 ns, 0 ns);
-      tpd_MAin0_PADDI	 : VitalDelayType01 := (0 ns, 0 ns);
-      tperiod_MAin0 	: VitalDelayType := 0 ns;
-      tpw_MAin0_posedge	: VitalDelayType := 0 ns;
-      tpw_MAin0_negedge	: VitalDelayType := 0 ns);
-
-    port (PADDI: out Std_logic; MAin0: in Std_logic);
-
-    ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
-
-  end MAin_0_B;
-
-  architecture Structure of MAin_0_B is
-    ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
-
-    signal PADDI_out 	: std_logic := 'X';
-    signal MAin0_ipd 	: std_logic := 'X';
-
-    component xo2iobuf0086
-      port (Z: out Std_logic; PAD: in Std_logic);
-    end component;
-  begin
-    MAin_pad_0: xo2iobuf0086
-      port map (Z=>PADDI_out, PAD=>MAin0_ipd);
-
-    --  INPUT PATH DELAYs
-    WireDelay : BLOCK
-    BEGIN
-      VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
-    END BLOCK;
-
-    VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
-    VARIABLE PADDI_zd         	: std_logic := 'X';
-    VARIABLE PADDI_GlitchData 	: VitalGlitchDataType;
-
-    VARIABLE tviol_MAin0_MAin0          	: x01 := '0';
-    VARIABLE periodcheckinfo_MAin0	: VitalPeriodDataType;
-
-    BEGIN
-
-    IF (TimingChecksOn) THEN
-      VitalPeriodPulseCheck (
-        TestSignal => MAin0_ipd,
-        TestSignalName => "MAin0",
-        Period => tperiod_MAin0,
-        PulseWidthHigh => tpw_MAin0_posedge,
-        PulseWidthLow => tpw_MAin0_negedge,
-        PeriodData => periodcheckinfo_MAin0,
-        Violation => tviol_MAin0_MAin0,
-        MsgOn => MsgOn, XOn => XOn,
-        HeaderMsg => InstancePath,
-        CheckEnabled => TRUE,
-        MsgSeverity => warning);
-
-    END IF;
-
-    PADDI_zd 	:= PADDI_out;
-
-    VitalPathDelay01 (
-      OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
-      Paths      => (0 => (InputChangeTime => MAin0_ipd'last_event,
-                           PathDelay => tpd_MAin0_PADDI,
-                           PathCondition => TRUE)),
-      GlitchData => PADDI_GlitchData,
-      Mode       => vitaltransport, XOn => XOn, MsgOn => MsgOn);
-
-    END PROCESS;
-
-  end Structure;
-
--- entity RAM2GS
-  library IEEE, vital2000, MACHXO2;
-  use IEEE.STD_LOGIC_1164.all;
-  use vital2000.vital_timing.all;
-  use MACHXO2.COMPONENTS.ALL;
-
-  entity RAM2GS is
-    port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); 
-          CROW: in Std_logic_vector (1 downto 0); 
-          Din: in Std_logic_vector (7 downto 0); 
-          Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; 
-          nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; 
-          RBA: out Std_logic_vector (1 downto 0); 
-          RA: out Std_logic_vector (11 downto 0); 
-          RD: out Std_logic_vector (7 downto 0); nRCS: out Std_logic; 
-          RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; 
-          nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; 
-          RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; 
-          UFMSDI: out Std_logic; UFMSDO: in Std_logic);
-
-
-
-  end RAM2GS;
-
-  architecture Structure of RAM2GS is
-    signal FS_0: Std_logic;
-    signal FS_s_0: Std_logic;
-    signal RCLK_c: Std_logic;
-    signal FS_cry_0: Std_logic;
-    signal FS_17: Std_logic;
-    signal FS_s_17: Std_logic;
-    signal FS_cry_16: Std_logic;
-    signal FS_16: Std_logic;
-    signal FS_15: Std_logic;
-    signal FS_s_16: Std_logic;
-    signal FS_s_15: Std_logic;
-    signal FS_cry_14: Std_logic;
-    signal FS_14: Std_logic;
-    signal FS_13: Std_logic;
-    signal FS_s_14: Std_logic;
-    signal FS_s_13: Std_logic;
-    signal FS_cry_12: Std_logic;
-    signal FS_12: Std_logic;
-    signal FS_11: Std_logic;
-    signal FS_s_12: Std_logic;
-    signal FS_s_11: Std_logic;
-    signal FS_cry_10: Std_logic;
-    signal FS_10: Std_logic;
-    signal FS_9: Std_logic;
-    signal FS_s_10: Std_logic;
-    signal FS_s_9: Std_logic;
-    signal FS_cry_8: Std_logic;
-    signal FS_8: Std_logic;
-    signal FS_7: Std_logic;
-    signal FS_s_8: Std_logic;
-    signal FS_s_7: Std_logic;
-    signal FS_cry_6: Std_logic;
-    signal FS_6: Std_logic;
-    signal FS_5: Std_logic;
-    signal FS_s_6: Std_logic;
-    signal FS_s_5: Std_logic;
-    signal FS_cry_4: Std_logic;
-    signal FS_4: Std_logic;
-    signal FS_3: Std_logic;
-    signal FS_s_4: Std_logic;
-    signal FS_s_3: Std_logic;
-    signal FS_cry_2: Std_logic;
-    signal FS_2: Std_logic;
-    signal FS_1: Std_logic;
-    signal FS_s_2: Std_logic;
-    signal FS_s_1: Std_logic;
-    signal CmdEnable17_5: Std_logic;
-    signal CmdEnable17_4: Std_logic;
-    signal ADWR: Std_logic;
-    signal CmdEnable16: Std_logic;
-    signal CmdEnable17: Std_logic;
-    signal un1_ADWR: Std_logic;
-    signal ADSubmitted: Std_logic;
-    signal ADSubmitted_r: Std_logic;
-    signal PHI2_c: Std_logic;
-    signal un1_Bank_1: Std_logic;
-    signal MAin_c_2: Std_logic;
-    signal CmdEnable16_5: Std_logic;
-    signal C1WR_3: Std_logic;
-    signal C1Submitted: Std_logic;
-    signal C1Submitted_s: Std_logic;
-    signal nFWE_c: Std_logic;
-    signal nCCAS_c: Std_logic;
-    signal nCCAS_c_i: Std_logic;
-    signal CASr: Std_logic;
-    signal RD_1_i: Std_logic;
-    signal CASr2: Std_logic;
-    signal S_1: Std_logic;
-    signal RASr2: Std_logic;
-    signal IS_3: Std_logic;
-    signal CO0: Std_logic;
-    signal N_166_i: Std_logic;
-    signal Ready_0_sqmuxa_0_a3_2: Std_logic;
-    signal CmdEnable: Std_logic;
-    signal un1_CMDWR: Std_logic;
-    signal CmdEnable_s: Std_logic;
-    signal N_36: Std_logic;
-    signal Din_c_5: Std_logic;
-    signal Din_c_1: Std_logic;
-    signal N_94: Std_logic;
-    signal N_60: Std_logic;
-    signal N_59: Std_logic;
-    signal LEDEN: Std_logic;
-    signal N_14_i: Std_logic;
-    signal XOR8MEG18: Std_logic;
-    signal CmdLEDEN: Std_logic;
-    signal Din_c_3: Std_logic;
-    signal CmdSubmitted: Std_logic;
-    signal CmdSubmitted_1_sqmuxa: Std_logic;
-    signal N_412_0: Std_logic;
-    signal CmdUFMCLK_1_sqmuxa: Std_logic;
-    signal n8MEGEN: Std_logic;
-    signal Cmdn8MEGEN_4_u_i_0: Std_logic;
-    signal N_12_i: Std_logic;
-    signal Cmdn8MEGEN: Std_logic;
-    signal MAin_c_1: Std_logic;
-    signal ADWR_6: Std_logic;
-    signal ADWR_3: Std_logic;
-    signal nFWE_c_i: Std_logic;
-    signal nCRAS_c: Std_logic;
-    signal FWEr: Std_logic;
-    signal CMDWR_2: Std_logic;
-    signal Ready: Std_logic;
-    signal N_151: Std_logic;
-    signal IS_0: Std_logic;
-    signal N_60_i_i: Std_logic;
-    signal RA10s_i: Std_logic;
-    signal IS_2: Std_logic;
-    signal IS_1: Std_logic;
-    signal N_180_i: Std_logic;
-    signal IS_n1_0_x2: Std_logic;
-    signal N_48_i: Std_logic;
-    signal N_58_i_i: Std_logic;
-    signal N_137_5: Std_logic;
-    signal N_137_3: Std_logic;
-    signal InitReady: Std_logic;
-    signal InitReady3: Std_logic;
-    signal N_413_0: Std_logic;
-    signal N_74_i: Std_logic;
-    signal N_28: Std_logic;
-    signal CBR: Std_logic;
-    signal nCRAS_c_i_0: Std_logic;
-    signal RASr: Std_logic;
-    signal LED_c: Std_logic;
-    signal S_0_i_o2_1: Std_logic;
-    signal RCKEEN_8_u_1_0: Std_logic;
-    signal RCKEEN_8_u_0_0: Std_logic;
-    signal RCKEEN_8: Std_logic;
-    signal RCKEEN: Std_logic;
-    signal Ready_fast: Std_logic;
-    signal CROW_c_1: Std_logic;
-    signal RASr3: Std_logic;
-    signal RCKE_2: Std_logic;
-    signal RCKE_c: Std_logic;
-    signal RBAd_0_1: Std_logic;
-    signal N_158: Std_logic;
-    signal N_414_0: Std_logic;
-    signal Ready_0_sqmuxa: Std_logic;
-    signal N_415_0: Std_logic;
-    signal MAin_c_0: Std_logic;
-    signal RowAd_0_1: Std_logic;
-    signal RowAd_0_0: Std_logic;
-    signal RowA_0: Std_logic;
-    signal RowA_1: Std_logic;
-    signal MAin_c_3: Std_logic;
-    signal RowAd_0_3: Std_logic;
-    signal RowAd_0_2: Std_logic;
-    signal RowA_2: Std_logic;
-    signal RowA_3: Std_logic;
-    signal MAin_c_5: Std_logic;
-    signal MAin_c_4: Std_logic;
-    signal RowAd_0_5: Std_logic;
-    signal RowAd_0_4: Std_logic;
-    signal RowA_4: Std_logic;
-    signal RowA_5: Std_logic;
-    signal MAin_c_7: Std_logic;
-    signal MAin_c_6: Std_logic;
-    signal RowAd_0_7: Std_logic;
-    signal RowAd_0_6: Std_logic;
-    signal RowA_6: Std_logic;
-    signal RowA_7: Std_logic;
-    signal MAin_c_9: Std_logic;
-    signal MAin_c_8: Std_logic;
-    signal RowAd_0_9: Std_logic;
-    signal RowAd_0_8: Std_logic;
-    signal RowA_8: Std_logic;
-    signal RowA_9: Std_logic;
-    signal nRCAS_0_sqmuxa_1: Std_logic;
-    signal CmdUFMSDI: Std_logic;
-    signal N_145: Std_logic;
-    signal UFMSDI_ens2_i_a0: Std_logic;
-    signal nUFMCS15: Std_logic;
-    signal UFMSDI_c: Std_logic;
-    signal UFMSDI_RNO: Std_logic;
-    signal N_141_i: Std_logic;
-    signal Din_c_7: Std_logic;
-    signal Din_c_6: Std_logic;
-    signal Din_c_4: Std_logic;
-    signal un1_Din_3: Std_logic;
-    signal XOR8MEG_3_u_1: Std_logic;
-    signal XOR8MEG: Std_logic;
-    signal Din_c_0: Std_logic;
-    signal XOR8MEG_3: Std_logic;
-    signal Bank_4: Std_logic;
-    signal Bank_3: Std_logic;
-    signal Bank_1: Std_logic;
-    signal Bank_0: Std_logic;
-    signal UFMSDO_c: Std_logic;
-    signal N_131: Std_logic;
-    signal N_26: Std_logic;
-    signal un1_Bank_1_4: Std_logic;
-    signal CASr3: Std_logic;
-    signal N_168: Std_logic;
-    signal nRowColSel_0_0: Std_logic;
-    signal nRRAS_0_sqmuxa: Std_logic;
-    signal nRowColSel: Std_logic;
-    signal UFMCLK_r_i_a2_2_2: Std_logic;
-    signal CmdUFMCS: Std_logic;
-    signal nUFMCS_c: Std_logic;
-    signal nUFMCS_s_0_m4_yy: Std_logic;
-    signal nUFMCS_s_0_N_5_i: Std_logic;
-    signal N_129: Std_logic;
-    signal d_m3_0_a2_0: Std_logic;
-    signal CmdUFMCLK: Std_logic;
-    signal i1_i: Std_logic;
-    signal N_50: Std_logic;
-    signal N_154: Std_logic;
-    signal un1_nRCAS_6_sqmuxa_i_0: Std_logic;
-    signal N_45: Std_logic;
-    signal N_146_i_1: Std_logic;
-    signal N_27_i_1: Std_logic;
-    signal N_146_i: Std_logic;
-    signal nRRAS_5_u_i_0: Std_logic;
-    signal N_24_i: Std_logic;
-    signal nRWE_s_i_a3_1_0: Std_logic;
-    signal nRWE_s_i_tz_0: Std_logic;
-    signal PHI2r3: Std_logic;
-    signal PHI2r2: Std_logic;
-    signal un1_PHI2r3_0: Std_logic;
-    signal N_140: Std_logic;
-    signal un1_FS_14_i_a2_0_1: Std_logic;
-    signal N_139_8: Std_logic;
-    signal N_139_6: Std_logic;
-    signal N_139: Std_logic;
-    signal un1_FS_13_i_a2_1: Std_logic;
-    signal UFMSDI_ens2_i_a2_4_2: Std_logic;
-    signal N_34: Std_logic;
-    signal ADWR_2: Std_logic;
-    signal N_24: Std_logic;
-    signal N_27_i_sn: Std_logic;
-    signal N_153: Std_logic;
-    signal C1WR_1: Std_logic;
-    signal UFMSDI_ens2_i_o2_0_3: Std_logic;
-    signal PHI2r: Std_logic;
-    signal i2_i: Std_logic;
-    signal N_27_i: Std_logic;
-    signal Din_c_2: Std_logic;
-    signal CmdEnable16_4: Std_logic;
-    signal CmdEnable16_3: Std_logic;
-    signal Bank_2: Std_logic;
-    signal Bank_7: Std_logic;
-    signal un1_Bank_1_3: Std_logic;
-    signal Bank_6: Std_logic;
-    signal Bank_5: Std_logic;
-    signal nRWE_0io_RNO_1: Std_logic;
-    signal nRWE_0io_RNO_0: Std_logic;
-    signal N_147_i: Std_logic;
-    signal RA_c_9: Std_logic;
-    signal RDQML_c: Std_logic;
-    signal RA_c_8: Std_logic;
-    signal RDQMH_c: Std_logic;
-    signal RA_c_0: Std_logic;
-    signal RA_c_7: Std_logic;
-    signal RA_c_1: Std_logic;
-    signal RA_c_6: Std_logic;
-    signal RA_c_2: Std_logic;
-    signal RA_c_5: Std_logic;
-    signal RA_c_3: Std_logic;
-    signal RA_c_4: Std_logic;
-    signal CROW_c_0: Std_logic;
-    signal RA11d_0: Std_logic;
-    signal RBAd_0_0: Std_logic;
-    signal WRD_0: Std_logic;
-    signal UFMSDI_c_n0: Std_logic;
-    signal UFMCLK_c: Std_logic;
-    signal nUFMCS_c_n1: Std_logic;
-    signal nRCAS_c: Std_logic;
-    signal nRRAS_c: Std_logic;
-    signal nRWE_c: Std_logic;
-    signal RCKE_c_n2: Std_logic;
-    signal nRCS_c: Std_logic;
-    signal WRD_7: Std_logic;
-    signal WRD_6: Std_logic;
-    signal WRD_5: Std_logic;
-    signal WRD_4: Std_logic;
-    signal WRD_3: Std_logic;
-    signal WRD_2: Std_logic;
-    signal WRD_1: Std_logic;
-    signal RA_c_11: Std_logic;
-    signal RA_c_10: Std_logic;
-    signal RBA_c_1: Std_logic;
-    signal RBA_c_0: Std_logic;
-    signal VCCI: Std_logic;
-    component SLICE_0
-      port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_1
-      port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_2
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_3
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_4
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_5
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_6
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_7
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_8
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_9
-      port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic; FCO: out Std_logic);
-    end component;
-    component SLICE_10
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_13
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_14
-      port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_17
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_18
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_19
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_20
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_21
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_22
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_23
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_24
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; 
-            DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_25
-      port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_26
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_27
-      port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic);
-    end component;
-    component SLICE_29
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_31
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_32
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_33
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_34
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_35
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_36
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_37
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_38
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_39
-      port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic; Q1: out Std_logic);
-    end component;
-    component SLICE_40
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_41
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            OFX0: out Std_logic; Q0: out Std_logic);
-    end component;
-    component SLICE_42
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_43
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_44
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_45
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_46
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_47
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_48
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_49
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_50
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_51
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_52
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_53
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_54
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_55
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_56
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_57
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_58
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_59
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_60
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_61
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_62
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_63
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_64
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_65
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; 
-            F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; 
-            Q1: out Std_logic);
-    end component;
-    component SLICE_66
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_67
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_68
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; 
-            Q0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_69
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_70
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_71
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_72
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_73
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_74
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; 
-            CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_75
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_76
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_77
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_78
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; 
-            A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_79
-      port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; 
-            B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; 
-            F1: out Std_logic);
-    end component;
-    component SLICE_80
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_81
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_82
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_83
-      port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_84
-      port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; 
-            C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component SLICE_85
-      port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; 
-            A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; 
-            F0: out Std_logic; F1: out Std_logic);
-    end component;
-    component RD_0_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic);
-    end component;
-    component RD_0_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component Dout_0_B
-      port (PADDO: in Std_logic; Dout0: out Std_logic);
-    end component;
-    component PHI2B
-      port (PADDI: out Std_logic; PHI2S: in Std_logic);
-    end component;
-    component PHI2_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component UFMSDOB
-      port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
-    end component;
-    component UFMSDIB
-      port (IOLDO: in Std_logic; UFMSDIS: out Std_logic);
-    end component;
-    component UFMSDI_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component UFMCLKB
-      port (IOLDO: in Std_logic; UFMCLKS: out Std_logic);
-    end component;
-    component UFMCLK_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; 
-            CLK: in Std_logic);
-    end component;
-    component nUFMCSB
-      port (IOLDO: in Std_logic; nUFMCSS: out Std_logic);
-    end component;
-    component nUFMCS_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RDQMLB
-      port (PADDO: in Std_logic; RDQMLS: out Std_logic);
-    end component;
-    component RDQMHB
-      port (PADDO: in Std_logic; RDQMHS: out Std_logic);
-    end component;
-    component nRCASB
-      port (IOLDO: in Std_logic; nRCASS: out Std_logic);
-    end component;
-    component nRCAS_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component nRRASB
-      port (IOLDO: in Std_logic; nRRASS: out Std_logic);
-    end component;
-    component nRRAS_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component nRWEB
-      port (IOLDO: in Std_logic; nRWES: out Std_logic);
-    end component;
-    component nRWE_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RCKEB
-      port (IOLDO: in Std_logic; RCKES: out Std_logic);
-    end component;
-    component RCKE_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RCLKB
-      port (PADDI: out Std_logic; RCLKS: in Std_logic);
-    end component;
-    component nRCSB
-      port (IOLDO: in Std_logic; nRCSS: out Std_logic);
-    end component;
-    component nRCS_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_7_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic);
-    end component;
-    component RD_7_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_6_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic);
-    end component;
-    component RD_6_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_5_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic);
-    end component;
-    component RD_5_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_4_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic);
-    end component;
-    component RD_4_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_3_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic);
-    end component;
-    component RD_3_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_2_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic);
-    end component;
-    component RD_2_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RD_1_B
-      port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic);
-    end component;
-    component RD_1_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RA_11_B
-      port (IOLDO: in Std_logic; RA11: out Std_logic);
-    end component;
-    component RA_11_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RA_10_B
-      port (IOLDO: in Std_logic; RA10: out Std_logic);
-    end component;
-    component RA_10_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; 
-            CLK: in Std_logic);
-    end component;
-    component RA_9_B
-      port (PADDO: in Std_logic; RA9: out Std_logic);
-    end component;
-    component RA_8_B
-      port (PADDO: in Std_logic; RA8: out Std_logic);
-    end component;
-    component RA_7_B
-      port (PADDO: in Std_logic; RA7: out Std_logic);
-    end component;
-    component RA_6_B
-      port (PADDO: in Std_logic; RA6: out Std_logic);
-    end component;
-    component RA_5_B
-      port (PADDO: in Std_logic; RA5: out Std_logic);
-    end component;
-    component RA_4_B
-      port (PADDO: in Std_logic; RA4: out Std_logic);
-    end component;
-    component RA_3_B
-      port (PADDO: in Std_logic; RA3: out Std_logic);
-    end component;
-    component RA_2_B
-      port (PADDO: in Std_logic; RA2: out Std_logic);
-    end component;
-    component RA_1_B
-      port (PADDO: in Std_logic; RA1: out Std_logic);
-    end component;
-    component RA_0_B
-      port (PADDO: in Std_logic; RA0: out Std_logic);
-    end component;
-    component RBA_1_B
-      port (IOLDO: in Std_logic; RBA1: out Std_logic);
-    end component;
-    component RBA_1_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component RBA_0_B
-      port (IOLDO: in Std_logic; RBA0: out Std_logic);
-    end component;
-    component RBA_0_MGIOL
-      port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
-    end component;
-    component LEDB
-      port (PADDO: in Std_logic; LEDS: out Std_logic);
-    end component;
-    component nFWEB
-      port (PADDI: out Std_logic; nFWES: in Std_logic);
-    end component;
-    component nCRASB
-      port (PADDI: out Std_logic; nCRASS: in Std_logic);
-    end component;
-    component nCCASB
-      port (PADDI: out Std_logic; nCCASS: in Std_logic);
-    end component;
-    component Dout_7_B
-      port (PADDO: in Std_logic; Dout7: out Std_logic);
-    end component;
-    component Dout_6_B
-      port (PADDO: in Std_logic; Dout6: out Std_logic);
-    end component;
-    component Dout_5_B
-      port (PADDO: in Std_logic; Dout5: out Std_logic);
-    end component;
-    component Dout_4_B
-      port (PADDO: in Std_logic; Dout4: out Std_logic);
-    end component;
-    component Dout_3_B
-      port (PADDO: in Std_logic; Dout3: out Std_logic);
-    end component;
-    component Dout_2_B
-      port (PADDO: in Std_logic; Dout2: out Std_logic);
-    end component;
-    component Dout_1_B
-      port (PADDO: in Std_logic; Dout1: out Std_logic);
-    end component;
-    component Din_7_B
-      port (PADDI: out Std_logic; Din7: in Std_logic);
-    end component;
-    component Din_7_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component Din_6_B
-      port (PADDI: out Std_logic; Din6: in Std_logic);
-    end component;
-    component Din_6_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component Din_5_B
-      port (PADDI: out Std_logic; Din5: in Std_logic);
-    end component;
-    component Din_5_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component Din_4_B
-      port (PADDI: out Std_logic; Din4: in Std_logic);
-    end component;
-    component Din_4_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component Din_3_B
-      port (PADDI: out Std_logic; Din3: in Std_logic);
-    end component;
-    component Din_3_MGIOL
-      port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
-    end component;
-    component Din_2_B
-      port (PADDI: out Std_logic; Din2: in Std_logic);
-    end component;
-    component Din_2_MGIOL
-      port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            INP: out Std_logic);
-    end component;
-    component Din_1_B
-      port (PADDI: out Std_logic; Din1: in Std_logic);
-    end component;
-    component Din_1_MGIOL
-      port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            INP: out Std_logic);
-    end component;
-    component Din_0_B
-      port (PADDI: out Std_logic; Din0: in Std_logic);
-    end component;
-    component Din_0_MGIOL
-      port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; 
-            INP: out Std_logic);
-    end component;
-    component CROW_1_B
-      port (PADDI: out Std_logic; CROW1: in Std_logic);
-    end component;
-    component CROW_0_B
-      port (PADDI: out Std_logic; CROW0: in Std_logic);
-    end component;
-    component MAin_9_B
-      port (PADDI: out Std_logic; MAin9: in Std_logic);
-    end component;
-    component MAin_8_B
-      port (PADDI: out Std_logic; MAin8: in Std_logic);
-    end component;
-    component MAin_7_B
-      port (PADDI: out Std_logic; MAin7: in Std_logic);
-    end component;
-    component MAin_6_B
-      port (PADDI: out Std_logic; MAin6: in Std_logic);
-    end component;
-    component MAin_5_B
-      port (PADDI: out Std_logic; MAin5: in Std_logic);
-    end component;
-    component MAin_4_B
-      port (PADDI: out Std_logic; MAin4: in Std_logic);
-    end component;
-    component MAin_3_B
-      port (PADDI: out Std_logic; MAin3: in Std_logic);
-    end component;
-    component MAin_2_B
-      port (PADDI: out Std_logic; MAin2: in Std_logic);
-    end component;
-    component MAin_1_B
-      port (PADDI: out Std_logic; MAin1: in Std_logic);
-    end component;
-    component MAin_0_B
-      port (PADDI: out Std_logic; MAin0: in Std_logic);
-    end component;
-  begin
-    SLICE_0I: SLICE_0
-      port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0, 
-                FCO=>FS_cry_0);
-    SLICE_1I: SLICE_1
-      port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16, 
-                F0=>FS_s_17, Q0=>FS_17);
-    SLICE_2I: SLICE_2
-      port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c, 
-                FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16, 
-                FCO=>FS_cry_16);
-    SLICE_3I: SLICE_3
-      port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c, 
-                FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14, 
-                FCO=>FS_cry_14);
-    SLICE_4I: SLICE_4
-      port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c, 
-                FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12, 
-                FCO=>FS_cry_12);
-    SLICE_5I: SLICE_5
-      port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c, 
-                FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10, 
-                FCO=>FS_cry_10);
-    SLICE_6I: SLICE_6
-      port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c, 
-                FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8, 
-                FCO=>FS_cry_8);
-    SLICE_7I: SLICE_7
-      port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c, 
-                FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6, 
-                FCO=>FS_cry_6);
-    SLICE_8I: SLICE_8
-      port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c, 
-                FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4, 
-                FCO=>FS_cry_4);
-    SLICE_9I: SLICE_9
-      port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c, 
-                FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2, 
-                FCO=>FS_cry_2);
-    SLICE_10I: SLICE_10
-      port map (C1=>CmdEnable17_5, B1=>CmdEnable17_4, A1=>ADWR, 
-                D0=>CmdEnable16, C0=>CmdEnable17, B0=>un1_ADWR, 
-                A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c, 
-                F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
-    SLICE_13I: SLICE_13
-      port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>CmdEnable16_5, A1=>C1WR_3, 
-                C0=>CmdEnable16, B0=>un1_ADWR, A0=>C1Submitted, 
-                DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s, 
-                Q0=>C1Submitted, F1=>CmdEnable16);
-    SLICE_14I: SLICE_14
-      port map (B1=>nFWE_c, A1=>nCCAS_c, A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, 
-                CLK=>RCLK_c, F0=>nCCAS_c_i, Q0=>CASr, F1=>RD_1_i, Q1=>CASr2);
-    SLICE_17I: SLICE_17
-      port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, 
-                DI0=>N_166_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_166_i, Q0=>CO0, 
-                F1=>Ready_0_sqmuxa_0_a3_2);
-    SLICE_18I: SLICE_18
-      port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, 
-                B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, 
-                M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
-    SLICE_19I: SLICE_19
-      port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_1, D0=>N_94, C0=>N_60, 
-                B0=>N_59, A0=>LEDEN, DI0=>N_14_i, CE=>XOR8MEG18, CLK=>PHI2_c, 
-                F0=>N_14_i, Q0=>CmdLEDEN, F1=>N_60);
-    SLICE_20I: SLICE_20
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, 
-                B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_412_0, 
-                CLK=>PHI2_c, F0=>N_412_0, Q0=>CmdSubmitted, 
-                F1=>CmdUFMCLK_1_sqmuxa);
-    SLICE_21I: SLICE_21
-      port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_3, C0=>n8MEGEN, B0=>N_94, 
-                A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_12_i, CE=>XOR8MEG18, 
-                CLK=>PHI2_c, F0=>N_12_i, Q0=>Cmdn8MEGEN, F1=>N_94);
-    SLICE_22I: SLICE_22
-      port map (D1=>nFWE_c, C1=>MAin_c_1, B1=>ADWR_6, A1=>ADWR_3, A0=>nFWE_c, 
-                DI0=>nFWE_c_i, CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, 
-                F1=>CMDWR_2);
-    SLICE_23I: SLICE_23
-      port map (D1=>Ready, C1=>N_151, B1=>IS_3, A1=>IS_0, C0=>Ready, B0=>N_151, 
-                A0=>IS_0, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0, 
-                F1=>RA10s_i);
-    SLICE_24I: SLICE_24
-      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, DI1=>N_180_i, 
-                DI0=>IS_n1_0_x2, CE=>N_48_i, CLK=>RCLK_c, F0=>IS_n1_0_x2, 
-                Q0=>IS_1, F1=>N_180_i, Q1=>IS_2);
-    SLICE_25I: SLICE_25
-      port map (D0=>IS_0, C0=>IS_1, B0=>IS_2, A0=>IS_3, DI0=>N_58_i_i, 
-                CE=>N_48_i, CLK=>RCLK_c, F0=>N_58_i_i, Q0=>IS_3);
-    SLICE_26I: SLICE_26
-      port map (D1=>N_137_5, C1=>N_137_3, B1=>FS_16, A1=>FS_10, B0=>InitReady, 
-                A0=>InitReady3, DI0=>N_413_0, CLK=>RCLK_c, F0=>N_413_0, 
-                Q0=>InitReady, F1=>InitReady3);
-    SLICE_27I: SLICE_27
-      port map (B0=>InitReady, A0=>CmdLEDEN, DI0=>N_74_i, CE=>N_28, 
-                CLK=>RCLK_c, F0=>N_74_i, Q0=>LEDEN);
-    SLICE_29I: SLICE_29
-      port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, A0=>nCRAS_c, DI0=>nCRAS_c_i_0, 
-                M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c, 
-                Q1=>RASr2);
-    SLICE_31I: SLICE_31
-      port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, D0=>Ready, 
-                C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, 
-                CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_0_0);
-    SLICE_32I: SLICE_32
-      port map (B1=>Ready_fast, A1=>CROW_c_1, D0=>RCKEEN, C0=>RASr3, B0=>RASr2, 
-                A0=>RASr, DI0=>RCKE_2, M1=>RASr2, CLK=>RCLK_c, F0=>RCKE_2, 
-                Q0=>RCKE_c, F1=>RBAd_0_1, Q1=>RASr3);
-    SLICE_33I: SLICE_33
-      port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>InitReady, C0=>N_158, 
-                B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_414_0, 
-                CLK=>RCLK_c, F0=>N_414_0, Q0=>Ready, F1=>N_158);
-    SLICE_34I: SLICE_34
-      port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_158, A1=>InitReady, 
-                B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_415_0, CLK=>RCLK_c, 
-                F0=>N_415_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa);
-    SLICE_35I: SLICE_35
-      port map (B1=>Ready_fast, A1=>MAin_c_1, B0=>Ready_fast, A0=>MAin_c_0, 
-                DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0, 
-                Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1);
-    SLICE_36I: SLICE_36
-      port map (B1=>Ready_fast, A1=>MAin_c_3, B0=>Ready_fast, A0=>MAin_c_2, 
-                DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2, 
-                Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3);
-    SLICE_37I: SLICE_37
-      port map (B1=>Ready_fast, A1=>MAin_c_5, B0=>Ready_fast, A0=>MAin_c_4, 
-                DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4, 
-                Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5);
-    SLICE_38I: SLICE_38
-      port map (B1=>Ready_fast, A1=>MAin_c_7, B0=>Ready_fast, A0=>MAin_c_6, 
-                DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6, 
-                Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7);
-    SLICE_39I: SLICE_39
-      port map (B1=>Ready_fast, A1=>MAin_c_9, B0=>Ready_fast, A0=>MAin_c_8, 
-                DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8, 
-                Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9);
-    SLICE_40I: SLICE_40
-      port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR, B0=>S_1, 
-                A0=>CO0, DI0=>S_0_i_o2_1, LSR=>RASr2, CLK=>RCLK_c, 
-                F0=>S_0_i_o2_1, Q0=>S_1, F1=>nRCAS_0_sqmuxa_1);
-    SLICE_41I: SLICE_41
-      port map (D1=>CmdUFMSDI, C1=>N_145, B1=>UFMSDI_ens2_i_a0, A1=>nUFMCS15, 
-                B0=>nUFMCS15, A0=>UFMSDI_c, DI0=>UFMSDI_RNO, M0=>N_141_i, 
-                CLK=>RCLK_c, OFX0=>UFMSDI_RNO, Q0=>UFMSDI_c);
-    SLICE_42I: SLICE_42
-      port map (D1=>Din_c_7, C1=>Din_c_6, B1=>Din_c_5, A1=>Din_c_4, 
-                D0=>un1_Din_3, C0=>XOR8MEG_3_u_1, B0=>XOR8MEG, A0=>Din_c_0, 
-                DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, 
-                Q0=>XOR8MEG, F1=>un1_Din_3);
-    SLICE_43I: SLICE_43
-      port map (D1=>Bank_4, C1=>Bank_3, B1=>Bank_1, A1=>Bank_0, C0=>UFMSDO_c, 
-                B0=>InitReady, A0=>Cmdn8MEGEN, DI0=>N_131, CE=>N_26, 
-                CLK=>RCLK_c, F0=>N_131, Q0=>n8MEGEN, F1=>un1_Bank_1_4);
-    SLICE_44I: SLICE_44
-      port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, 
-                B0=>N_168, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, 
-                CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_168);
-    SLICE_45I: SLICE_45
-      port map (D1=>UFMCLK_r_i_a2_2_2, C1=>nUFMCS15, B1=>InitReady, 
-                A1=>CmdUFMCS, D0=>nUFMCS_c, C0=>nUFMCS_s_0_m4_yy, B0=>nUFMCS15, 
-                A0=>N_141_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, 
-                F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS_s_0_m4_yy);
-    SLICE_46I: SLICE_46
-      port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>C1WR_3, A1=>ADWR, 
-                D0=>un1_ADWR, C0=>un1_Bank_1, B0=>MAin_c_2, A0=>CMDWR_2, 
-                F0=>un1_CMDWR, F1=>un1_ADWR);
-    SLICE_47I: SLICE_47
-      port map (D1=>N_129, C1=>InitReady, B1=>FS_11, A1=>FS_10, 
-                D0=>d_m3_0_a2_0, C0=>nUFMCS15, B0=>InitReady, A0=>CmdUFMCLK, 
-                F0=>i1_i, F1=>nUFMCS15);
-    SLICE_48I: SLICE_48
-      port map (D1=>N_137_5, C1=>N_137_3, B1=>InitReady, A1=>FS_16, 
-                C0=>UFMCLK_r_i_a2_2_2, B0=>N_50, A0=>InitReady, 
-                F0=>d_m3_0_a2_0, F1=>UFMCLK_r_i_a2_2_2);
-    SLICE_49I: SLICE_49
-      port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>Ready, 
-                B0=>N_154, A0=>N_151, F0=>un1_nRCAS_6_sqmuxa_i_0, F1=>N_151);
-    SLICE_50I: SLICE_50
-      port map (D1=>Din_c_0, C1=>Din_c_5, B1=>Cmdn8MEGEN, A1=>N_45, C0=>N_36, 
-                B0=>Din_c_5, A0=>Din_c_3, F0=>N_45, F1=>Cmdn8MEGEN_4_u_i_0);
-    SLICE_51I: SLICE_51
-      port map (C1=>S_1, B1=>un1_nRCAS_6_sqmuxa_i_0, A1=>CBR, D0=>S_1, 
-                C0=>N_146_i_1, B0=>nRCAS_0_sqmuxa_1, A0=>N_27_i_1, F0=>N_146_i, 
-                F1=>N_146_i_1);
-    SLICE_52I: SLICE_52
-      port map (C1=>IS_1, B1=>IS_2, A1=>IS_3, D0=>IS_0, C0=>N_151, B0=>N_154, 
-                A0=>nRRAS_5_u_i_0, F0=>N_24_i, F1=>N_154);
-    SLICE_53I: SLICE_53
-      port map (D1=>nRWE_s_i_a3_1_0, C1=>nRRAS_0_sqmuxa, B1=>RCKE_c, A1=>RASr2, 
-                C0=>CO0, B0=>S_1, A0=>Ready, F0=>nRRAS_0_sqmuxa, 
-                F1=>nRWE_s_i_tz_0);
-    SLICE_54I: SLICE_54
-      port map (B1=>PHI2r3, A1=>PHI2r2, D0=>un1_PHI2r3_0, C0=>N_140, 
-                B0=>InitReady, A0=>CmdSubmitted, F0=>N_28, F1=>un1_PHI2r3_0);
-    SLICE_55I: SLICE_55
-      port map (C1=>un1_FS_14_i_a2_0_1, B1=>N_139_8, A1=>N_139_6, 
-                D0=>un1_PHI2r3_0, C0=>N_139, B0=>InitReady, A0=>CmdSubmitted, 
-                F0=>N_26, F1=>N_139);
-    SLICE_56I: SLICE_56
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>un1_FS_13_i_a2_1, 
-                B0=>N_139_8, A0=>N_139_6, F0=>N_140, F1=>un1_FS_13_i_a2_1);
-    SLICE_57I: SLICE_57
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, 
-                D0=>un1_Bank_1, C0=>MAin_c_2, B0=>CmdEnable, A0=>CMDWR_2, 
-                F0=>XOR8MEG18, F1=>CmdSubmitted_1_sqmuxa);
-    SLICE_58I: SLICE_58
-      port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, 
-                D0=>UFMSDI_ens2_i_a2_4_2, C0=>N_129, B0=>N_34, A0=>InitReady, 
-                F0=>UFMSDI_ens2_i_a0, F1=>UFMSDI_ens2_i_a2_4_2);
-    SLICE_59I: SLICE_59
-      port map (C1=>N_129, B1=>InitReady, A1=>FS_8, D0=>N_145, C0=>FS_11, 
-                B0=>FS_9, A0=>FS_4, F0=>N_139_8, F1=>N_145);
-    SLICE_60I: SLICE_60
-      port map (B1=>MAin_c_0, A1=>MAin_c_7, D0=>un1_Bank_1, C0=>MAin_c_1, 
-                B0=>ADWR_3, A0=>ADWR_2, F0=>ADWR, F1=>ADWR_3);
-    SLICE_61I: SLICE_61
-      port map (C1=>S_1, B1=>N_24, A1=>CBR, D0=>nRRAS_5_u_i_0, C0=>N_154, 
-                B0=>N_151, A0=>IS_0, F0=>N_24, F1=>N_27_i_sn);
-    SLICE_62I: SLICE_62
-      port map (B1=>IS_2, A1=>IS_1, D0=>Ready, C0=>N_153, B0=>N_151, A0=>IS_0, 
-                F0=>nRWE_s_i_a3_1_0, F1=>N_153);
-    SLICE_63I: SLICE_63
-      port map (B1=>nFWE_c, A1=>MAin_c_7, D0=>MAin_c_1, C0=>MAin_c_0, 
-                B0=>C1WR_1, A0=>ADWR_6, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, 
-                F0=>C1WR_3, Q0=>Bank_0, F1=>C1WR_1, Q1=>Bank_1);
-    SLICE_64I: SLICE_64
-      port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_15, D0=>N_129, 
-                C0=>FS_11, B0=>FS_4, A0=>FS_1, F0=>N_50, F1=>N_129);
-    SLICE_65I: SLICE_65
-      port map (B1=>nUFMCS15, A1=>N_141_i, D0=>PHI2r3, C0=>PHI2r2, 
-                B0=>InitReady, A0=>CmdSubmitted, M1=>PHI2r2, M0=>PHI2r, 
-                CLK=>RCLK_c, F0=>N_141_i, Q0=>PHI2r2, F1=>i2_i, Q1=>PHI2r3);
-    SLICE_66I: SLICE_66
-      port map (D1=>Ready, C1=>N_27_i_sn, B1=>N_27_i_1, A1=>N_24_i, D0=>FWEr, 
-                C0=>CO0, B0=>CASr3, A0=>CASr2, F0=>N_27_i_1, F1=>N_27_i);
-    SLICE_67I: SLICE_67
-      port map (D1=>MAin_c_6, C1=>MAin_c_5, B1=>MAin_c_4, A1=>MAin_c_3, 
-                C0=>nFWE_c, B0=>MAin_c_2, A0=>ADWR_6, F0=>ADWR_2, F1=>ADWR_6);
-    SLICE_68I: SLICE_68
-      port map (B1=>Din_c_5, A1=>Din_c_0, D0=>Din_c_6, C0=>Din_c_2, 
-                B0=>CmdEnable16_4, A0=>CmdEnable16_3, M0=>Din_c_2, CLK=>PHI2_c, 
-                F0=>CmdEnable16_5, Q0=>Bank_2, F1=>CmdEnable16_3);
-    SLICE_69I: SLICE_69
-      port map (B1=>Bank_7, A1=>Bank_2, D0=>un1_Bank_1_4, C0=>un1_Bank_1_3, 
-                B0=>Bank_6, A0=>Bank_5, F0=>un1_Bank_1, F1=>un1_Bank_1_3);
-    SLICE_70I: SLICE_70
-      port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>CmdLEDEN, C0=>Din_c_7, 
-                B0=>Din_c_6, A0=>Din_c_4, F0=>N_36, F1=>N_59);
-    SLICE_71I: SLICE_71
-      port map (C1=>CO0, B1=>CASr3, A1=>CASr2, D0=>nRWE_s_i_tz_0, 
-                C0=>nRWE_0io_RNO_1, B0=>nRWE_0io_RNO_0, A0=>nRCAS_0_sqmuxa_1, 
-                F0=>N_147_i, F1=>nRWE_0io_RNO_0);
-    SLICE_72I: SLICE_72
-      port map (D1=>FS_17, C1=>FS_14, B1=>FS_13, A1=>FS_12, D0=>FS_17, 
-                C0=>FS_15, B0=>FS_13, A0=>FS_12, F0=>N_137_5, 
-                F1=>UFMSDI_ens2_i_o2_0_3);
-    SLICE_73I: SLICE_73
-      port map (D1=>Din_c_7, C1=>Din_c_4, B1=>Din_c_3, A1=>Din_c_1, 
-                D0=>Din_c_7, C0=>Din_c_5, B0=>Din_c_4, A0=>Din_c_1, M0=>CASr2, 
-                CLK=>RCLK_c, F0=>CmdEnable17_5, Q0=>CASr3, F1=>CmdEnable16_4);
-    SLICE_74I: SLICE_74
-      port map (D1=>LEDEN, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_1, D0=>Din_c_6, 
-                C0=>Din_c_3, B0=>Din_c_2, A0=>Din_c_0, M0=>nCCAS_c_i, 
-                CLK=>nCRAS_c, F0=>CmdEnable17_4, Q0=>CBR, F1=>XOR8MEG_3_u_1);
-    SLICE_75I: SLICE_75
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, 
-                A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
-    SLICE_76I: SLICE_76
-      port map (D1=>S_1, C1=>Ready, B1=>FWEr, A1=>CBR, D0=>S_1, C0=>FWEr, 
-                B0=>CO0, A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>nRWE_0io_RNO_1);
-    SLICE_77I: SLICE_77
-      port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, B0=>Ready, 
-                A0=>N_151, F0=>N_48_i, F1=>nRRAS_5_u_i_0);
-    SLICE_78I: SLICE_78
-      port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>FS_9, B0=>FS_7, 
-                A0=>FS_5, F0=>N_34, F1=>un1_FS_14_i_a2_0_1);
-    SLICE_79I: SLICE_79
-      port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, 
-                A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
-    SLICE_80I: SLICE_80
-      port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, 
-                B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>RA_c_7);
-    SLICE_81I: SLICE_81
-      port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, 
-                B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_6);
-    SLICE_82I: SLICE_82
-      port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, 
-                B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_5);
-    SLICE_83I: SLICE_83
-      port map (C1=>nRowColSel, B1=>RowA_4, A1=>MAin_c_4, C0=>nRowColSel, 
-                B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_4);
-    SLICE_84I: SLICE_84
-      port map (B1=>Ready_fast, A1=>CROW_c_0, D0=>n8MEGEN, C0=>XOR8MEG, 
-                B0=>Ready_fast, A0=>Din_c_6, F0=>RA11d_0, F1=>RBAd_0_0);
-    SLICE_85I: SLICE_85
-      port map (D1=>FS_10, C1=>FS_7, B1=>FS_6, A1=>FS_1, B0=>FS_14, A0=>FS_11, 
-                F0=>N_137_3, F1=>N_139_6);
-    RD_0_I: RD_0_B
-      port map (IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0));
-    RD_0_MGIOLI: RD_0_MGIOL
-      port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c);
-    Dout_0_I: Dout_0_B
-      port map (PADDO=>MAin_c_3, Dout0=>Dout(0));
-    PHI2I: PHI2B
-      port map (PADDI=>PHI2_c, PHI2S=>PHI2);
-    PHI2_MGIOLI: PHI2_MGIOL
-      port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r);
-    UFMSDOI: UFMSDOB
-      port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
-    UFMSDII: UFMSDIB
-      port map (IOLDO=>UFMSDI_c_n0, UFMSDIS=>UFMSDI);
-    UFMSDI_MGIOLI: UFMSDI_MGIOL
-      port map (IOLDO=>UFMSDI_c_n0, OPOS=>UFMSDI_RNO, CLK=>RCLK_c);
-    UFMCLKI: UFMCLKB
-      port map (IOLDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
-    UFMCLK_MGIOLI: UFMCLK_MGIOL
-      port map (IOLDO=>UFMCLK_c, OPOS=>i1_i, CE=>i2_i, CLK=>RCLK_c);
-    nUFMCSI: nUFMCSB
-      port map (IOLDO=>nUFMCS_c_n1, nUFMCSS=>nUFMCS);
-    nUFMCS_MGIOLI: nUFMCS_MGIOL
-      port map (IOLDO=>nUFMCS_c_n1, OPOS=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c);
-    RDQMLI: RDQMLB
-      port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
-    RDQMHI: RDQMHB
-      port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
-    nRCASI: nRCASB
-      port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS);
-    nRCAS_MGIOLI: nRCAS_MGIOL
-      port map (IOLDO=>nRCAS_c, OPOS=>N_146_i, CLK=>RCLK_c);
-    nRRASI: nRRASB
-      port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS);
-    nRRAS_MGIOLI: nRRAS_MGIOL
-      port map (IOLDO=>nRRAS_c, OPOS=>N_24_i, CLK=>RCLK_c);
-    nRWEI: nRWEB
-      port map (IOLDO=>nRWE_c, nRWES=>nRWE);
-    nRWE_MGIOLI: nRWE_MGIOL
-      port map (IOLDO=>nRWE_c, OPOS=>N_147_i, CLK=>RCLK_c);
-    RCKEI: RCKEB
-      port map (IOLDO=>RCKE_c_n2, RCKES=>RCKE);
-    RCKE_MGIOLI: RCKE_MGIOL
-      port map (IOLDO=>RCKE_c_n2, OPOS=>RCKE_2, CLK=>RCLK_c);
-    RCLKI: RCLKB
-      port map (PADDI=>RCLK_c, RCLKS=>RCLK);
-    nRCSI: nRCSB
-      port map (IOLDO=>nRCS_c, nRCSS=>nRCS);
-    nRCS_MGIOLI: nRCS_MGIOL
-      port map (IOLDO=>nRCS_c, OPOS=>N_27_i, CLK=>RCLK_c);
-    RD_7_I: RD_7_B
-      port map (IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7));
-    RD_7_MGIOLI: RD_7_MGIOL
-      port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c);
-    RD_6_I: RD_6_B
-      port map (IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6));
-    RD_6_MGIOLI: RD_6_MGIOL
-      port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c);
-    RD_5_I: RD_5_B
-      port map (IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5));
-    RD_5_MGIOLI: RD_5_MGIOL
-      port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c);
-    RD_4_I: RD_4_B
-      port map (IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4));
-    RD_4_MGIOLI: RD_4_MGIOL
-      port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c);
-    RD_3_I: RD_3_B
-      port map (IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3));
-    RD_3_MGIOLI: RD_3_MGIOL
-      port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c);
-    RD_2_I: RD_2_B
-      port map (IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2));
-    RD_2_MGIOLI: RD_2_MGIOL
-      port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c);
-    RD_1_I0: RD_1_B
-      port map (IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1));
-    RD_1_MGIOLI: RD_1_MGIOL
-      port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c);
-    RA_11_I: RA_11_B
-      port map (IOLDO=>RA_c_11, RA11=>RA(11));
-    RA_11_MGIOLI: RA_11_MGIOL
-      port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c);
-    RA_10_I: RA_10_B
-      port map (IOLDO=>RA_c_10, RA10=>RA(10));
-    RA_10_MGIOLI: RA_10_MGIOL
-      port map (IOLDO=>RA_c_10, OPOS=>N_153, LSR=>RA10s_i, CLK=>RCLK_c);
-    RA_9_I: RA_9_B
-      port map (PADDO=>RA_c_9, RA9=>RA(9));
-    RA_8_I: RA_8_B
-      port map (PADDO=>RA_c_8, RA8=>RA(8));
-    RA_7_I: RA_7_B
-      port map (PADDO=>RA_c_7, RA7=>RA(7));
-    RA_6_I: RA_6_B
-      port map (PADDO=>RA_c_6, RA6=>RA(6));
-    RA_5_I: RA_5_B
-      port map (PADDO=>RA_c_5, RA5=>RA(5));
-    RA_4_I: RA_4_B
-      port map (PADDO=>RA_c_4, RA4=>RA(4));
-    RA_3_I: RA_3_B
-      port map (PADDO=>RA_c_3, RA3=>RA(3));
-    RA_2_I: RA_2_B
-      port map (PADDO=>RA_c_2, RA2=>RA(2));
-    RA_1_I: RA_1_B
-      port map (PADDO=>RA_c_1, RA1=>RA(1));
-    RA_0_I: RA_0_B
-      port map (PADDO=>RA_c_0, RA0=>RA(0));
-    RBA_1_I: RBA_1_B
-      port map (IOLDO=>RBA_c_1, RBA1=>RBA(1));
-    RBA_1_MGIOLI: RBA_1_MGIOL
-      port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c);
-    RBA_0_I: RBA_0_B
-      port map (IOLDO=>RBA_c_0, RBA0=>RBA(0));
-    RBA_0_MGIOLI: RBA_0_MGIOL
-      port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c);
-    LEDI: LEDB
-      port map (PADDO=>LED_c, LEDS=>LED);
-    nFWEI: nFWEB
-      port map (PADDI=>nFWE_c, nFWES=>nFWE);
-    nCRASI: nCRASB
-      port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
-    nCCASI: nCCASB
-      port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
-    Dout_7_I: Dout_7_B
-      port map (PADDO=>nCRAS_c, Dout7=>Dout(7));
-    Dout_6_I: Dout_6_B
-      port map (PADDO=>MAin_c_9, Dout6=>Dout(6));
-    Dout_5_I: Dout_5_B
-      port map (PADDO=>MAin_c_8, Dout5=>Dout(5));
-    Dout_4_I: Dout_4_B
-      port map (PADDO=>MAin_c_7, Dout4=>Dout(4));
-    Dout_3_I: Dout_3_B
-      port map (PADDO=>MAin_c_6, Dout3=>Dout(3));
-    Dout_2_I: Dout_2_B
-      port map (PADDO=>MAin_c_5, Dout2=>Dout(2));
-    Dout_1_I: Dout_1_B
-      port map (PADDO=>MAin_c_4, Dout1=>Dout(1));
-    Din_7_I: Din_7_B
-      port map (PADDI=>Din_c_7, Din7=>Din(7));
-    Din_7_MGIOLI: Din_7_MGIOL
-      port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7);
-    Din_6_I: Din_6_B
-      port map (PADDI=>Din_c_6, Din6=>Din(6));
-    Din_6_MGIOLI: Din_6_MGIOL
-      port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6);
-    Din_5_I: Din_5_B
-      port map (PADDI=>Din_c_5, Din5=>Din(5));
-    Din_5_MGIOLI: Din_5_MGIOL
-      port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5);
-    Din_4_I: Din_4_B
-      port map (PADDI=>Din_c_4, Din4=>Din(4));
-    Din_4_MGIOLI: Din_4_MGIOL
-      port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4);
-    Din_3_I: Din_3_B
-      port map (PADDI=>Din_c_3, Din3=>Din(3));
-    Din_3_MGIOLI: Din_3_MGIOL
-      port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3);
-    Din_2_I: Din_2_B
-      port map (PADDI=>Din_c_2, Din2=>Din(2));
-    Din_2_MGIOLI: Din_2_MGIOL
-      port map (DI=>Din_c_2, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                INP=>CmdUFMCS);
-    Din_1_I: Din_1_B
-      port map (PADDI=>Din_c_1, Din1=>Din(1));
-    Din_1_MGIOLI: Din_1_MGIOL
-      port map (DI=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                INP=>CmdUFMCLK);
-    Din_0_I: Din_0_B
-      port map (PADDI=>Din_c_0, Din0=>Din(0));
-    Din_0_MGIOLI: Din_0_MGIOL
-      port map (DI=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, 
-                INP=>CmdUFMSDI);
-    CROW_1_I: CROW_1_B
-      port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
-    CROW_0_I: CROW_0_B
-      port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
-    MAin_9_I: MAin_9_B
-      port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
-    MAin_8_I: MAin_8_B
-      port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
-    MAin_7_I: MAin_7_B
-      port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
-    MAin_6_I: MAin_6_B
-      port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
-    MAin_5_I: MAin_5_B
-      port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
-    MAin_4_I: MAin_4_B
-      port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
-    MAin_3_I: MAin_3_B
-      port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
-    MAin_2_I: MAin_2_B
-      port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
-    MAin_1_I: MAin_1_B
-      port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
-    MAin_0_I: MAin_0_B
-      port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
-    VHI_INST: VHI
-      port map (Z=>VCCI);
-    PUR_INST: PUR
-      port map (PUR=>VCCI);
-    GSR_INST: GSR
-      port map (GSR=>VCCI);
-  end Structure;
-
-
-
-  library IEEE, vital2000, MACHXO2;
-  configuration Structure_CON of RAM2GS is
-    for Structure
-    end for;
-  end Structure_CON;
-
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf
deleted file mode 100644
index 593060e..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf
+++ /dev/null
@@ -1,3483 +0,0 @@
-(DELAYFILE
-  (SDFVERSION "3.0")
-  (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 22:56:32 2023")
-  (VENDOR "Lattice")
-  (PROGRAM "ldbanno")
-  (VERSION "Diamond (64-bit) 3.12.1.454")
-  (DIVIDER /)
-  (VOLTAGE 1.26:1.20:1.14)
-  (PROCESS "default")
-  (TEMPERATURE -40:25:85)
-  (TIMESCALE 1ps)
-  (CELL
-    (CELLTYPE "SLICE_0")
-    (INSTANCE SLICE_0)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_1")
-    (INSTANCE SLICE_1)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_2")
-    (INSTANCE SLICE_2)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_3")
-    (INSTANCE SLICE_3)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_4")
-    (INSTANCE SLICE_4)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_5")
-    (INSTANCE SLICE_5)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_6")
-    (INSTANCE SLICE_6)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_7")
-    (INSTANCE SLICE_7)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_8")
-    (INSTANCE SLICE_8)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_9")
-    (INSTANCE SLICE_9)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 FCO (718:803:889)(718:803:889))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F1 (718:803:889)(718:803:889))
-        (IOPATH A0 FCO (827:925:1023)(827:925:1023))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-        (IOPATH FCI F0 (473:529:585)(473:529:585))
-        (IOPATH FCI F1 (519:581:643)(519:581:643))
-        (IOPATH FCI FCO (130:146:162)(130:146:162))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_14")
-    (INSTANCE SLICE_14)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_17")
-    (INSTANCE SLICE_17)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_18")
-    (INSTANCE SLICE_18)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_20")
-    (INSTANCE SLICE_20)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_21")
-    (INSTANCE SLICE_21)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_22")
-    (INSTANCE SLICE_22)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_23")
-    (INSTANCE SLICE_23)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_24")
-    (INSTANCE SLICE_24)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_25")
-    (INSTANCE SLICE_25)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_26")
-    (INSTANCE SLICE_26)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_27")
-    (INSTANCE SLICE_27)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_29")
-    (INSTANCE SLICE_29)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_31")
-    (INSTANCE SLICE_31)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_32")
-    (INSTANCE SLICE_32)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_33")
-    (INSTANCE SLICE_33)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_34")
-    (INSTANCE SLICE_34)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_35")
-    (INSTANCE SLICE_35)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_36")
-    (INSTANCE SLICE_36)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_37")
-    (INSTANCE SLICE_37)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_38")
-    (INSTANCE SLICE_38)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI1 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
-        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
-        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge LSR) (4000:4000:4000))
-      (WIDTH (negedge LSR) (4000:4000:4000))
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37))
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0_")
-    (INSTANCE RD\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RD0 (2927:3031:3136)(2927:3031:3136))
-        (IOPATH PADDT RD0 (2844:3155:3467)(2844:3155:3467)(2844:3155:3467)(2844:3155:3467)
-          (2844:3155:3467)(2844:3155:3467))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RD_0__MGIOL")
-    (INSTANCE RD\[0\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-    )
-  )
-  (CELL
-    (CELLTYPE "Dout_0_")
-    (INSTANCE Dout\[0\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PADDO Dout0 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2")
-    (INSTANCE PHI2_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH PHI2 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge PHI2) (3330:3330:3330))
-      (WIDTH (negedge PHI2) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "PHI2_MGIOL")
-    (INSTANCE PHI2_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDO")
-    (INSTANCE UFMSDO_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH UFMSDO PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge UFMSDO) (3330:3330:3330))
-      (WIDTH (negedge UFMSDO) (3330:3330:3330))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI")
-    (INSTANCE UFMSDI_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO UFMSDI (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMSDI_MGIOL")
-    (INSTANCE UFMSDI_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK")
-    (INSTANCE UFMCLK_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO UFMCLK (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "UFMCLK_MGIOL")
-    (INSTANCE UFMCLK_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
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-    (INSTANCE nUFMCS_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO nUFMCS (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
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-    (INSTANCE nUFMCS_MGIOL)
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-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
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-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
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-  )
-  (CELL
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-      (ABSOLUTE
-        (IOPATH PADDO RDQML (2927:3031:3136)(2927:3031:3136))
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-  )
-  (CELL
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-        (IOPATH PADDO RDQMH (2927:3031:3136)(2927:3031:3136))
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-  (CELL
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-    (TIMINGCHECK
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-      (WIDTH (negedge CLK) (1855:1855:1855))
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-  )
-  (CELL
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-    (TIMINGCHECK
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-      (WIDTH (negedge CLK) (1855:1855:1855))
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-    (TIMINGCHECK
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-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RCKE")
-    (INSTANCE RCKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RCKE (2927:3031:3136)(2927:3031:3136))
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-    )
-  )
-  (CELL
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-    (INSTANCE RCKE_MGIOL)
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-        (IOPATH RCLK PADDI (1007:1069:1132)(1007:1069:1132))
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-      (WIDTH (negedge CLK) (1855:1855:1855))
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-      (WIDTH (negedge CLK) (1855:1855:1855))
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-    (TIMINGCHECK
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-      (WIDTH (negedge CLK) (1855:1855:1855))
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-  (CELL
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-        (IOPATH PADDO LED (2371:2455:2540)(2371:2455:2540))
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-  (CELL
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-      (ABSOLUTE
-        (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din7) (3330:3330:3330))
-      (WIDTH (negedge Din7) (3330:3330:3330))
-    )
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-    (INSTANCE Din\[7\]_MGIOL)
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
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-    (INSTANCE Din\[6\]_I)
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-      (ABSOLUTE
-        (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge Din6) (3330:3330:3330))
-      (WIDTH (negedge Din6) (3330:3330:3330))
-    )
-  )
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-    (CELLTYPE "Din_6__MGIOL")
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "Din_5_")
-    (INSTANCE Din\[5\]_I)
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-      (ABSOLUTE
-        (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge Din5) (3330:3330:3330))
-    )
-  )
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
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-    )
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-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
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-      (ABSOLUTE
-        (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge Din4) (3330:3330:3330))
-    )
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
-      )
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-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
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-      (ABSOLUTE
-        (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge Din3) (3330:3330:3330))
-    )
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
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-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
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-      (ABSOLUTE
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-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge Din2) (3330:3330:3330))
-    )
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-  (CELL
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-    (INSTANCE Din\[2\]_MGIOL)
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
-      )
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-    (TIMINGCHECK
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-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
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-  )
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-      (ABSOLUTE
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-      )
-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge Din1) (3330:3330:3330))
-    )
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-    (INSTANCE Din\[1\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
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-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
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-      (ABSOLUTE
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-      )
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-    (TIMINGCHECK
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-      (WIDTH (negedge Din0) (3330:3330:3330))
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-      (ABSOLUTE
-        (IOPATH CLK IN (577:577:577)(577:577:577))
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-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI (negedge CLK) (595:595:595)(223:223:223))
-      (SETUPHOLD CE (negedge CLK) (63:63:63)(-52:-52:-52))
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-      (ABSOLUTE
-        (IOPATH CROW1 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
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-      (WIDTH (negedge CROW1) (3330:3330:3330))
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-    (TIMINGCHECK
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-    )
-    (TIMINGCHECK
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-    )
-    (TIMINGCHECK
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-    (TIMINGCHECK
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-        (IOPATH MAin6 PADDI (1007:1069:1132)(1007:1069:1132))
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-    )
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-      )
-    )
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-      (WIDTH (negedge MAin3) (3330:3330:3330))
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-      )
-    )
-    (TIMINGCHECK
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-        (IOPATH MAin1 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
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-    )
-  )
-  (CELL
-    (CELLTYPE "RAM2GS")
-    (INSTANCE )
-    (DELAY
-      (ABSOLUTE
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-        (INTERCONNECT SLICE_0/Q1 SLICE_56/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_78/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI SLICE_73/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI PHI2_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI UFMSDI_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI UFMCLK_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI nUFMCS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI nRCAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI nRRAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI RCKE_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI nRCS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT RCLK_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_26/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_48/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_64/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_64/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_72/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_72/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_85/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_72/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_72/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_72/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_72/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_47/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_58/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_59/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q0 SLICE_85/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_26/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_47/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_58/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_85/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_59/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q0 SLICE_78/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_58/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q1 SLICE_59/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_6/Q0 SLICE_78/B0 (0:0:0)(0:0:0))
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-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI Din\[6\]_MGIOL/DI (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_42/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_70/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_73/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_I/PADDI Din\[4\]_MGIOL/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/F1 SLICE_42/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_74/F1 SLICE_42/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 SLICE_42/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 SLICE_84/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_42/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_63/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_68/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_74/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI Din\[0\]_MGIOL/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[4\]_MGIOL/IN SLICE_43/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[3\]_MGIOL/IN SLICE_43/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63/Q1 SLICE_43/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63/Q0 SLICE_43/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT UFMSDO_I/PADDI SLICE_43/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55/F0 SLICE_43/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/F1 SLICE_69/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q0 SLICE_44/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q0 SLICE_66/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/Q0 SLICE_71/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53/F0 SLICE_44/LSR (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53/F0 SLICE_53/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_75/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_75/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_79/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_79/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_80/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_80/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_81/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_81/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_82/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_82/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_83/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_44/Q0 SLICE_83/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48/F1 SLICE_45/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48/F1 SLICE_48/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_MGIOL/IN SLICE_45/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45/Q0 SLICE_45/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45/F1 SLICE_45/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_45/F0 nUFMCS_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F1 SLICE_47/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F1 SLICE_58/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F1 SLICE_59/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_48/F0 SLICE_47/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[1\]_MGIOL/IN SLICE_47/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_47/F0 UFMCLK_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_64/F0 SLICE_48/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F1 SLICE_49/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F1 SLICE_61/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_49/F0 SLICE_51/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_50/F0 SLICE_50/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/F0 SLICE_51/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/F0 SLICE_66/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_51/F0 nRCAS_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F1 SLICE_52/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F1 SLICE_61/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F0 SLICE_66/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F0 nRRAS_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F0 SLICE_53/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53/F1 SLICE_71/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/Q1 SLICE_54/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/Q1 SLICE_65/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/Q0 SLICE_54/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/Q0 SLICE_65/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/Q0 SLICE_65/M1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_54/F1 SLICE_54/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_54/F1 SLICE_55/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56/F0 SLICE_54/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78/F1 SLICE_55/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/F0 SLICE_55/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_59/F0 SLICE_56/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85/F1 SLICE_55/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_85/F1 SLICE_56/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_55/F1 SLICE_55/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_56/F1 SLICE_56/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_58/F1 SLICE_58/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_78/F0 SLICE_58/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F0 SLICE_60/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_61/F1 SLICE_66/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 SLICE_62/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_63/F1 SLICE_63/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_72/F1 SLICE_64/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI2_MGIOL/IN SLICE_65/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_65/F1 UFMCLK_MGIOL/CE (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_66/F1 nRCS_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_68/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_68/M0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_74/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_74/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[2\]_I/PADDI Din\[2\]_MGIOL/DI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_73/F1 SLICE_68/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/F1 SLICE_68/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_68/Q0 SLICE_69/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[7\]_MGIOL/IN SLICE_69/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_69/F1 SLICE_69/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_MGIOL/IN SLICE_69/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[5\]_MGIOL/IN SLICE_69/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_76/F1 SLICE_71/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F1 SLICE_71/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F0 nRWE_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_75/F1 RDQML_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_79/F1 RDQMH_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/F0 RA\[0\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_80/F1 RA\[7\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/F0 RA\[1\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_81/F1 RA\[6\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/F0 RA\[2\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_82/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_83/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0))
-        (INTERCONNECT CROW\[0\]_I/PADDI SLICE_84/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84/F0 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_84/F1 RBA\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[0\]_MGIOL/IOLDO RD\[0\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT UFMSDI_MGIOL/IOLDO UFMSDI_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT UFMCLK_MGIOL/IOLDO UFMCLK_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nUFMCS_MGIOL/IOLDO nUFMCS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRCAS_MGIOL/IOLDO nRCAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRRAS_MGIOL/IOLDO nRRAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RCKE_MGIOL/IOLDO RCKE_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRCS_MGIOL/IOLDO nRCS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_MGIOL/IOLDO RD\[7\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_MGIOL/IOLDO RD\[6\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_MGIOL/IOLDO RD\[5\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_MGIOL/IOLDO RD\[4\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_MGIOL/IOLDO RD\[3\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_MGIOL/IOLDO RD\[2\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_MGIOL/IOLDO RD\[1\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RBA\[1\]_MGIOL/IOLDO RBA\[1\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RBA\[0\]_MGIOL/IOLDO RBA\[0\]_I/IOLDO (0:0:0)(0:0:0))
-      )
-    )
-  )
-)
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo
deleted file mode 100644
index c0bd4e2..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo
+++ /dev/null
@@ -1,4093 +0,0 @@
-
-// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
-
-// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd 
-// Netlist created on Tue Aug 15 22:56:31 2023
-// Netlist written on Tue Aug 15 22:56:32 2023
-// Design is for device LCMXO2-640HC
-// Design is for package TQFP100
-// Design is for performance grade 4
-
-`timescale 1 ns / 1 ps
-
-module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
-                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, 
-                UFMCLK, UFMSDI, UFMSDO );
-  input  PHI2;
-  input  [9:0] MAin;
-  input  [1:0] CROW;
-  input  [7:0] Din;
-  input  nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
-  output [7:0] Dout;
-  output LED;
-  output [1:0] RBA;
-  output [11:0] RA;
-  output [7:0] RD;
-  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
-  wire   \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , 
-         \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , 
-         \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , 
-         \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , 
-         \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
-         \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
-         \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
-         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , 
-         CmdEnable17_5, CmdEnable17_4, ADWR, CmdEnable16, CmdEnable17, 
-         un1_ADWR, ADSubmitted, ADSubmitted_r, PHI2_c, un1_Bank_1, \MAin_c[2] , 
-         CmdEnable16_5, C1WR_3, C1Submitted, C1Submitted_s, nFWE_c, nCCAS_c, 
-         nCCAS_c_i, CASr, RD_1_i, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_166_i, 
-         Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, N_36, 
-         \Din_c[5] , \Din_c[1] , N_94, N_60, N_59, LEDEN, N_14_i, XOR8MEG18, 
-         CmdLEDEN, \Din_c[3] , CmdSubmitted, CmdSubmitted_1_sqmuxa, N_412_0, 
-         CmdUFMCLK_1_sqmuxa, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, Cmdn8MEGEN, 
-         \MAin_c[1] , ADWR_6, ADWR_3, nFWE_c_i, nCRAS_c, FWEr, CMDWR_2, Ready, 
-         N_151, \IS[0] , N_60_i_i, RA10s_i, \IS[2] , \IS[1] , N_180_i, 
-         IS_n1_0_x2, N_48_i, N_58_i_i, N_137_5, N_137_3, InitReady, InitReady3, 
-         N_413_0, N_74_i, N_28, CBR, nCRAS_c_i_0, RASr, LED_c, \S_0_i_o2[1] , 
-         RCKEEN_8_u_1_0, RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, Ready_fast, 
-         \CROW_c[1] , RASr3, RCKE_2, RCKE_c, \RBAd_0[1] , N_158, N_414_0, 
-         Ready_0_sqmuxa, N_415_0, \MAin_c[0] , \RowAd_0[1] , \RowAd_0[0] , 
-         \RowA[0] , \RowA[1] , \MAin_c[3] , \RowAd_0[3] , \RowAd_0[2] , 
-         \RowA[2] , \RowA[3] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] , 
-         \RowAd_0[4] , \RowA[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , 
-         \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , 
-         \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , 
-         nRCAS_0_sqmuxa_1, CmdUFMSDI, N_145, UFMSDI_ens2_i_a0, nUFMCS15, 
-         UFMSDI_c, UFMSDI_RNO, N_141_i, \Din_c[7] , \Din_c[6] , \Din_c[4] , 
-         un1_Din_3, XOR8MEG_3_u_1, XOR8MEG, \Din_c[0] , XOR8MEG_3, \Bank[4] , 
-         \Bank[3] , \Bank[1] , \Bank[0] , UFMSDO_c, N_131, N_26, un1_Bank_1_4, 
-         CASr3, N_168, nRowColSel_0_0, nRRAS_0_sqmuxa, nRowColSel, 
-         UFMCLK_r_i_a2_2_2, CmdUFMCS, nUFMCS_c, nUFMCS_s_0_m4_yy, 
-         nUFMCS_s_0_N_5_i, N_129, d_m3_0_a2_0, CmdUFMCLK, i1_i, N_50, N_154, 
-         un1_nRCAS_6_sqmuxa_i_0, N_45, N_146_i_1, N_27_i_1, N_146_i, 
-         nRRAS_5_u_i_0, N_24_i, nRWE_s_i_a3_1_0, nRWE_s_i_tz_0, PHI2r3, PHI2r2, 
-         un1_PHI2r3_0, N_140, un1_FS_14_i_a2_0_1, N_139_8, N_139_6, N_139, 
-         un1_FS_13_i_a2_1, UFMSDI_ens2_i_a2_4_2, N_34, ADWR_2, N_24, N_27_i_sn, 
-         N_153, C1WR_1, UFMSDI_ens2_i_o2_0_3, PHI2r, i2_i, N_27_i, \Din_c[2] , 
-         CmdEnable16_4, CmdEnable16_3, \Bank[2] , \Bank[7] , un1_Bank_1_3, 
-         \Bank[6] , \Bank[5] , nRWE_0io_RNO_1, nRWE_0io_RNO_0, N_147_i, 
-         \RA_c[9] , RDQML_c, \RA_c[8] , RDQMH_c, \RA_c[0] , \RA_c[7] , 
-         \RA_c[1] , \RA_c[6] , \RA_c[2] , \RA_c[5] , \RA_c[3] , \RA_c[4] , 
-         \CROW_c[0] , RA11d_0, \RBAd_0[0] , \WRD[0] , \UFMSDI_c$n0 , UFMCLK_c, 
-         \nUFMCS_c$n1 , nRCAS_c, nRRAS_c, nRWE_c, \RCKE_c$n2 , nRCS_c, 
-         \WRD[7] , \WRD[6] , \WRD[5] , \WRD[4] , \WRD[3] , \WRD[2] , \WRD[1] , 
-         \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI;
-
-  SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), 
-    .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
-  SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c), 
-    .FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] ));
-  SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ), 
-    .DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), 
-    .Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] ));
-  SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), 
-    .DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), 
-    .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
-  SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), 
-    .DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), 
-    .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
-  SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), 
-    .DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), 
-    .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
-  SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), 
-    .DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), 
-    .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
-  SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), 
-    .DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), 
-    .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
-  SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), 
-    .DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), 
-    .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
-  SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
-    .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
-    .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
-  SLICE_10 SLICE_10( .C1(CmdEnable17_5), .B1(CmdEnable17_4), .A1(ADWR), 
-    .D0(CmdEnable16), .C0(CmdEnable17), .B0(un1_ADWR), .A0(ADSubmitted), 
-    .DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted), 
-    .F1(CmdEnable17));
-  SLICE_13 SLICE_13( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(CmdEnable16_5), 
-    .A1(C1WR_3), .C0(CmdEnable16), .B0(un1_ADWR), .A0(C1Submitted), 
-    .DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted), 
-    .F1(CmdEnable16));
-  SLICE_14 SLICE_14( .B1(nFWE_c), .A1(nCCAS_c), .A0(nCCAS_c), .DI0(nCCAS_c_i), 
-    .M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .F1(RD_1_i), 
-    .Q1(CASr2));
-  SLICE_17 SLICE_17( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
-    .B0(\S[1] ), .A0(CO0), .DI0(N_166_i), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(N_166_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
-  SLICE_18 SLICE_18( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
-    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
-    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
-  SLICE_19 SLICE_19( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[1] ), .D0(N_94), 
-    .C0(N_60), .B0(N_59), .A0(LEDEN), .DI0(N_14_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), .F1(N_60));
-  SLICE_20 SLICE_20( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), 
-    .A1(XOR8MEG18), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa), 
-    .DI0(N_412_0), .CLK(PHI2_c), .F0(N_412_0), .Q0(CmdSubmitted), 
-    .F1(CmdUFMCLK_1_sqmuxa));
-  SLICE_21 SLICE_21( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(n8MEGEN), 
-    .B0(N_94), .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18), 
-    .CLK(PHI2_c), .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(N_94));
-  SLICE_22 SLICE_22( .D1(nFWE_c), .C1(\MAin_c[1] ), .B1(ADWR_6), .A1(ADWR_3), 
-    .A0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), 
-    .F1(CMDWR_2));
-  SLICE_23 SLICE_23( .D1(Ready), .C1(N_151), .B1(\IS[3] ), .A1(\IS[0] ), 
-    .C0(Ready), .B0(N_151), .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), 
-    .F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i));
-  SLICE_24 SLICE_24( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
-    .A0(\IS[0] ), .DI1(N_180_i), .DI0(IS_n1_0_x2), .CE(N_48_i), .CLK(RCLK_c), 
-    .F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_180_i), .Q1(\IS[2] ));
-  SLICE_25 SLICE_25( .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), 
-    .DI0(N_58_i_i), .CE(N_48_i), .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ));
-  SLICE_26 SLICE_26( .D1(N_137_5), .C1(N_137_3), .B1(\FS[16] ), .A1(\FS[10] ), 
-    .B0(InitReady), .A0(InitReady3), .DI0(N_413_0), .CLK(RCLK_c), .F0(N_413_0), 
-    .Q0(InitReady), .F1(InitReady3));
-  SLICE_27 SLICE_27( .B0(InitReady), .A0(CmdLEDEN), .DI0(N_74_i), .CE(N_28), 
-    .CLK(RCLK_c), .F0(N_74_i), .Q0(LEDEN));
-  SLICE_29 SLICE_29( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), 
-    .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), 
-    .F1(LED_c), .Q1(RASr2));
-  SLICE_31 SLICE_31( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2), 
-    .A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
-    .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
-    .F1(RCKEEN_8_u_0_0));
-  SLICE_32 SLICE_32( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(RCKEEN), 
-    .C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(RASr2), .CLK(RCLK_c), 
-    .F0(RCKE_2), .Q0(RCKE_c), .F1(\RBAd_0[1] ), .Q1(RASr3));
-  SLICE_33 SLICE_33( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), 
-    .C0(N_158), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_414_0), 
-    .CLK(RCLK_c), .F0(N_414_0), .Q0(Ready), .F1(N_158));
-  SLICE_34 SLICE_34( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_158), 
-    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_415_0), 
-    .CLK(RCLK_c), .F0(N_415_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
-  SLICE_35 SLICE_35( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), 
-    .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), 
-    .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
-  SLICE_36 SLICE_36( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), 
-    .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), 
-    .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
-  SLICE_37 SLICE_37( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), 
-    .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), 
-    .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
-  SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), 
-    .A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), 
-    .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
-  SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), 
-    .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), 
-    .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
-  SLICE_40 SLICE_40( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR), 
-    .B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), 
-    .F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1));
-  SLICE_41 SLICE_41( .D1(CmdUFMSDI), .C1(N_145), .B1(UFMSDI_ens2_i_a0), 
-    .A1(nUFMCS15), .B0(nUFMCS15), .A0(UFMSDI_c), .DI0(UFMSDI_RNO), 
-    .M0(N_141_i), .CLK(RCLK_c), .OFX0(UFMSDI_RNO), .Q0(UFMSDI_c));
-  SLICE_42 SLICE_42( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), 
-    .A1(\Din_c[4] ), .D0(un1_Din_3), .C0(XOR8MEG_3_u_1), .B0(XOR8MEG), 
-    .A0(\Din_c[0] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
-    .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(un1_Din_3));
-  SLICE_43 SLICE_43( .D1(\Bank[4] ), .C1(\Bank[3] ), .B1(\Bank[1] ), 
-    .A1(\Bank[0] ), .C0(UFMSDO_c), .B0(InitReady), .A0(Cmdn8MEGEN), 
-    .DI0(N_131), .CE(N_26), .CLK(RCLK_c), .F0(N_131), .Q0(n8MEGEN), 
-    .F1(un1_Bank_1_4));
-  SLICE_44 SLICE_44( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
-    .C0(Ready), .B0(N_168), .A0(CO0), .DI0(nRowColSel_0_0), 
-    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
-    .F1(N_168));
-  SLICE_45 SLICE_45( .D1(UFMCLK_r_i_a2_2_2), .C1(nUFMCS15), .B1(InitReady), 
-    .A1(CmdUFMCS), .D0(nUFMCS_c), .C0(nUFMCS_s_0_m4_yy), .B0(nUFMCS15), 
-    .A0(N_141_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), 
-    .Q0(nUFMCS_c), .F1(nUFMCS_s_0_m4_yy));
-  SLICE_46 SLICE_46( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(C1WR_3), .A1(ADWR), 
-    .D0(un1_ADWR), .C0(un1_Bank_1), .B0(\MAin_c[2] ), .A0(CMDWR_2), 
-    .F0(un1_CMDWR), .F1(un1_ADWR));
-  SLICE_47 SLICE_47( .D1(N_129), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ), 
-    .D0(d_m3_0_a2_0), .C0(nUFMCS15), .B0(InitReady), .A0(CmdUFMCLK), .F0(i1_i), 
-    .F1(nUFMCS15));
-  SLICE_48 SLICE_48( .D1(N_137_5), .C1(N_137_3), .B1(InitReady), .A1(\FS[16] ), 
-    .C0(UFMCLK_r_i_a2_2_2), .B0(N_50), .A0(InitReady), .F0(d_m3_0_a2_0), 
-    .F1(UFMCLK_r_i_a2_2_2));
-  SLICE_49 SLICE_49( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
-    .D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_151), 
-    .F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_151));
-  SLICE_50 SLICE_50( .D1(\Din_c[0] ), .C1(\Din_c[5] ), .B1(Cmdn8MEGEN), 
-    .A1(N_45), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), .F0(N_45), 
-    .F1(Cmdn8MEGEN_4_u_i_0));
-  SLICE_51 SLICE_51( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR), 
-    .D0(\S[1] ), .C0(N_146_i_1), .B0(nRCAS_0_sqmuxa_1), .A0(N_27_i_1), 
-    .F0(N_146_i), .F1(N_146_i_1));
-  SLICE_52 SLICE_52( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(\IS[0] ), 
-    .C0(N_151), .B0(N_154), .A0(nRRAS_5_u_i_0), .F0(N_24_i), .F1(N_154));
-  SLICE_53 SLICE_53( .D1(nRWE_s_i_a3_1_0), .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), 
-    .A1(RASr2), .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), 
-    .F1(nRWE_s_i_tz_0));
-  SLICE_54 SLICE_54( .B1(PHI2r3), .A1(PHI2r2), .D0(un1_PHI2r3_0), .C0(N_140), 
-    .B0(InitReady), .A0(CmdSubmitted), .F0(N_28), .F1(un1_PHI2r3_0));
-  SLICE_55 SLICE_55( .C1(un1_FS_14_i_a2_0_1), .B1(N_139_8), .A1(N_139_6), 
-    .D0(un1_PHI2r3_0), .C0(N_139), .B0(InitReady), .A0(CmdSubmitted), 
-    .F0(N_26), .F1(N_139));
-  SLICE_56 SLICE_56( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .C0(un1_FS_13_i_a2_1), .B0(N_139_8), .A0(N_139_6), .F0(N_140), 
-    .F1(un1_FS_13_i_a2_1));
-  SLICE_57 SLICE_57( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), 
-    .A1(XOR8MEG18), .D0(un1_Bank_1), .C0(\MAin_c[2] ), .B0(CmdEnable), 
-    .A0(CMDWR_2), .F0(XOR8MEG18), .F1(CmdSubmitted_1_sqmuxa));
-  SLICE_58 SLICE_58( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ), 
-    .D0(UFMSDI_ens2_i_a2_4_2), .C0(N_129), .B0(N_34), .A0(InitReady), 
-    .F0(UFMSDI_ens2_i_a0), .F1(UFMSDI_ens2_i_a2_4_2));
-  SLICE_59 SLICE_59( .C1(N_129), .B1(InitReady), .A1(\FS[8] ), .D0(N_145), 
-    .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_139_8), .F1(N_145));
-  SLICE_60 SLICE_60( .B1(\MAin_c[0] ), .A1(\MAin_c[7] ), .D0(un1_Bank_1), 
-    .C0(\MAin_c[1] ), .B0(ADWR_3), .A0(ADWR_2), .F0(ADWR), .F1(ADWR_3));
-  SLICE_61 SLICE_61( .C1(\S[1] ), .B1(N_24), .A1(CBR), .D0(nRRAS_5_u_i_0), 
-    .C0(N_154), .B0(N_151), .A0(\IS[0] ), .F0(N_24), .F1(N_27_i_sn));
-  SLICE_62 SLICE_62( .B1(\IS[2] ), .A1(\IS[1] ), .D0(Ready), .C0(N_153), 
-    .B0(N_151), .A0(\IS[0] ), .F0(nRWE_s_i_a3_1_0), .F1(N_153));
-  SLICE_63 SLICE_63( .B1(nFWE_c), .A1(\MAin_c[7] ), .D0(\MAin_c[1] ), 
-    .C0(\MAin_c[0] ), .B0(C1WR_1), .A0(ADWR_6), .M1(\Din_c[1] ), 
-    .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_3), .Q0(\Bank[0] ), .F1(C1WR_1), 
-    .Q1(\Bank[1] ));
-  SLICE_64 SLICE_64( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[15] ), 
-    .D0(N_129), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .F0(N_50), 
-    .F1(N_129));
-  SLICE_65 SLICE_65( .B1(nUFMCS15), .A1(N_141_i), .D0(PHI2r3), .C0(PHI2r2), 
-    .B0(InitReady), .A0(CmdSubmitted), .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c), 
-    .F0(N_141_i), .Q0(PHI2r2), .F1(i2_i), .Q1(PHI2r3));
-  SLICE_66 SLICE_66( .D1(Ready), .C1(N_27_i_sn), .B1(N_27_i_1), .A1(N_24_i), 
-    .D0(FWEr), .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_27_i_1), .F1(N_27_i));
-  SLICE_67 SLICE_67( .D1(\MAin_c[6] ), .C1(\MAin_c[5] ), .B1(\MAin_c[4] ), 
-    .A1(\MAin_c[3] ), .C0(nFWE_c), .B0(\MAin_c[2] ), .A0(ADWR_6), .F0(ADWR_2), 
-    .F1(ADWR_6));
-  SLICE_68 SLICE_68( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\Din_c[6] ), 
-    .C0(\Din_c[2] ), .B0(CmdEnable16_4), .A0(CmdEnable16_3), .M0(\Din_c[2] ), 
-    .CLK(PHI2_c), .F0(CmdEnable16_5), .Q0(\Bank[2] ), .F1(CmdEnable16_3));
-  SLICE_69 SLICE_69( .B1(\Bank[7] ), .A1(\Bank[2] ), .D0(un1_Bank_1_4), 
-    .C0(un1_Bank_1_3), .B0(\Bank[6] ), .A0(\Bank[5] ), .F0(un1_Bank_1), 
-    .F1(un1_Bank_1_3));
-  SLICE_70 SLICE_70( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36), 
-    .A1(CmdLEDEN), .C0(\Din_c[7] ), .B0(\Din_c[6] ), .A0(\Din_c[4] ), 
-    .F0(N_36), .F1(N_59));
-  SLICE_71 SLICE_71( .C1(CO0), .B1(CASr3), .A1(CASr2), .D0(nRWE_s_i_tz_0), 
-    .C0(nRWE_0io_RNO_1), .B0(nRWE_0io_RNO_0), .A0(nRCAS_0_sqmuxa_1), 
-    .F0(N_147_i), .F1(nRWE_0io_RNO_0));
-  SLICE_72 SLICE_72( .D1(\FS[17] ), .C1(\FS[14] ), .B1(\FS[13] ), 
-    .A1(\FS[12] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ), 
-    .F0(N_137_5), .F1(UFMSDI_ens2_i_o2_0_3));
-  SLICE_73 SLICE_73( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), 
-    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[5] ), .B0(\Din_c[4] ), 
-    .A0(\Din_c[1] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdEnable17_5), .Q0(CASr3), 
-    .F1(CmdEnable16_4));
-  SLICE_74 SLICE_74( .D1(LEDEN), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[1] ), .D0(\Din_c[6] ), .C0(\Din_c[3] ), .B0(\Din_c[2] ), 
-    .A0(\Din_c[0] ), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CmdEnable17_4), 
-    .Q0(CBR), .F1(XOR8MEG_3_u_1));
-  SLICE_75 SLICE_75( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
-  SLICE_76 SLICE_76( .D1(\S[1] ), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(\S[1] ), 
-    .C0(FWEr), .B0(CO0), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(nRWE_0io_RNO_1));
-  SLICE_77 SLICE_77( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ), 
-    .B0(Ready), .A0(N_151), .F0(N_48_i), .F1(nRRAS_5_u_i_0));
-  SLICE_78 SLICE_78( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ), 
-    .C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .F0(N_34), 
-    .F1(un1_FS_14_i_a2_0_1));
-  SLICE_79 SLICE_79( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
-    .B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
-  SLICE_80 SLICE_80( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
-    .C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), 
-    .F1(\RA_c[7] ));
-  SLICE_81 SLICE_81( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
-    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
-    .F1(\RA_c[6] ));
-  SLICE_82 SLICE_82( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
-    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
-    .F1(\RA_c[5] ));
-  SLICE_83 SLICE_83( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ), 
-    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
-    .F1(\RA_c[4] ));
-  SLICE_84 SLICE_84( .B1(Ready_fast), .A1(\CROW_c[0] ), .D0(n8MEGEN), 
-    .C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0), 
-    .F1(\RBAd_0[0] ));
-  SLICE_85 SLICE_85( .D1(\FS[10] ), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[1] ), 
-    .B0(\FS[14] ), .A0(\FS[11] ), .F0(N_137_3), .F1(N_139_6));
-  RD_0_ \RD[0]_I ( .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0]));
-  RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), 
-    .CLK(nCCAS_c));
-  Dout_0_ \Dout[0]_I ( .PADDO(\MAin_c[3] ), .Dout0(Dout[0]));
-  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
-  PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r));
-  UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
-  UFMSDI UFMSDI_I( .IOLDO(\UFMSDI_c$n0 ), .UFMSDI(UFMSDI));
-  UFMSDI_MGIOL UFMSDI_MGIOL( .IOLDO(\UFMSDI_c$n0 ), .OPOS(UFMSDI_RNO), 
-    .CLK(RCLK_c));
-  UFMCLK UFMCLK_I( .IOLDO(UFMCLK_c), .UFMCLK(UFMCLK));
-  UFMCLK_MGIOL UFMCLK_MGIOL( .IOLDO(UFMCLK_c), .OPOS(i1_i), .CE(i2_i), 
-    .CLK(RCLK_c));
-  nUFMCS nUFMCS_I( .IOLDO(\nUFMCS_c$n1 ), .nUFMCS(nUFMCS));
-  nUFMCS_MGIOL nUFMCS_MGIOL( .IOLDO(\nUFMCS_c$n1 ), .OPOS(nUFMCS_s_0_N_5_i), 
-    .CLK(RCLK_c));
-  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
-  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
-  nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
-  nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_146_i), .CLK(RCLK_c));
-  nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
-  nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_24_i), .CLK(RCLK_c));
-  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
-  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_147_i), .CLK(RCLK_c));
-  RCKE RCKE_I( .IOLDO(\RCKE_c$n2 ), .RCKE(RCKE));
-  RCKE_MGIOL RCKE_MGIOL( .IOLDO(\RCKE_c$n2 ), .OPOS(RCKE_2), .CLK(RCLK_c));
-  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
-  nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
-  nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_27_i), .CLK(RCLK_c));
-  RD_7_ \RD[7]_I ( .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7]));
-  RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), 
-    .CLK(nCCAS_c));
-  RD_6_ \RD[6]_I ( .IOLDO(\WRD[6] ), .PADDT(RD_1_i), .RD6(RD[6]));
-  RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ), 
-    .CLK(nCCAS_c));
-  RD_5_ \RD[5]_I ( .IOLDO(\WRD[5] ), .PADDT(RD_1_i), .RD5(RD[5]));
-  RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ), 
-    .CLK(nCCAS_c));
-  RD_4_ \RD[4]_I ( .IOLDO(\WRD[4] ), .PADDT(RD_1_i), .RD4(RD[4]));
-  RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ), 
-    .CLK(nCCAS_c));
-  RD_3_ \RD[3]_I ( .IOLDO(\WRD[3] ), .PADDT(RD_1_i), .RD3(RD[3]));
-  RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ), 
-    .CLK(nCCAS_c));
-  RD_2_ \RD[2]_I ( .IOLDO(\WRD[2] ), .PADDT(RD_1_i), .RD2(RD[2]));
-  RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ), 
-    .CLK(nCCAS_c));
-  RD_1_ \RD[1]_I ( .IOLDO(\WRD[1] ), .PADDT(RD_1_i), .RD1(RD[1]));
-  RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ), 
-    .CLK(nCCAS_c));
-  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0), 
-    .CLK(PHI2_c));
-  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_153), .LSR(RA10s_i), 
-    .CLK(RCLK_c));
-  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
-  RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1]));
-  RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ), 
-    .CLK(nCRAS_c));
-  RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0]));
-  RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ), 
-    .CLK(nCRAS_c));
-  LED LED_I( .PADDO(LED_c), .LED(LED));
-  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
-  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
-  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
-  Dout_7_ \Dout[7]_I ( .PADDO(nCRAS_c), .Dout7(Dout[7]));
-  Dout_6_ \Dout[6]_I ( .PADDO(\MAin_c[9] ), .Dout6(Dout[6]));
-  Dout_5_ \Dout[5]_I ( .PADDO(\MAin_c[8] ), .Dout5(Dout[5]));
-  Dout_4_ \Dout[4]_I ( .PADDO(\MAin_c[7] ), .Dout4(Dout[4]));
-  Dout_3_ \Dout[3]_I ( .PADDO(\MAin_c[6] ), .Dout3(Dout[3]));
-  Dout_2_ \Dout[2]_I ( .PADDO(\MAin_c[5] ), .Dout2(Dout[2]));
-  Dout_1_ \Dout[1]_I ( .PADDO(\MAin_c[4] ), .Dout1(Dout[1]));
-  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
-  Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] ));
-  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
-  Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] ));
-  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
-  Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] ));
-  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
-  Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] ));
-  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
-  Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] ));
-  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
-  Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .IN(CmdUFMCS));
-  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
-  Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .IN(CmdUFMCLK));
-  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
-  Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), 
-    .CLK(PHI2_c), .IN(CmdUFMSDI));
-  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
-  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
-  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
-  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
-  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
-  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
-  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
-  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
-  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
-  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
-  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
-  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
-  VHI VHI_INST( .Z(VCCI));
-  PUR PUR_INST( .PUR(VCCI));
-  GSR GSR_INST( .GSR(VCCI));
-endmodule
-
-module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly;
-
-  vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module vcc ( output PWR1 );
-
-  VHI INST1( .Z(PWR1));
-endmodule
-
-module gnd ( output PWR0 );
-
-  VLO INST1( .Z(PWR0));
-endmodule
-
-module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
-
-  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
-  defparam inst1.INIT0 = 16'h000A;
-  defparam inst1.INIT1 = 16'h300A;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());
-
-  specify
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
-
-  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
-  defparam inst1.INIT0 = 16'h5002;
-  defparam inst1.INIT1 = 16'h300A;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
-
-  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
-    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
-  defparam inst1.INIT0 = 16'h300A;
-  defparam inst1.INIT1 = 16'h300A;
-  defparam inst1.INJECT1_0 = "NO";
-  defparam inst1.INJECT1_1 = "NO";
-endmodule
-
-module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
-
-  vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
-    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
-
-  specify
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A1 => FCO) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (A0 => F1) = (0:0:0,0:0:0);
-    (A0 => FCO) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    (FCI => F0) = (0:0:0,0:0:0);
-    (FCI => F1) = (0:0:0,0:0:0);
-    (FCI => FCO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_10 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut4 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40003 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
-module SLICE_13 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40004 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40004 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40005 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_14 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40006 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40007 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40006 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40007 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_17 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40008 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40009 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0010 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_18 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   GNDI, \SLICE_18/SLICE_18_K1_H1 , \SLICE_18/CmdEnable_s/GATE_H0 , VCCI, 
-         CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40011 SLICE_18_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(\SLICE_18/SLICE_18_K1_H1 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(\SLICE_18/CmdEnable_s/GATE_H0 ));
-  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  selmux2 SLICE_18_K0K1MUX( .D0(\SLICE_18/CmdEnable_s/GATE_H0 ), 
-    .D1(\SLICE_18/SLICE_18_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (D0 => OFX0) = (0:0:0,0:0:0);
-    (C0 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40012 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module selmux2 ( input D0, D1, SD, output Z );
-
-  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
-endmodule
-
-module SLICE_19 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40013 CmdLEDEN_4_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40014 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_20 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40015 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
-
-  lut40016 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40017 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40017 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
-
-  lut40018 CMDWR_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40007 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_23 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40019 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40020 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_24 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40021 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40022 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40022 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_25 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40023 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40004 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_27 ( input B0, A0, DI0, CE, CLK, output F0, Q0 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40024 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40025 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40007 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40026 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40026 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40027 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_32 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
-
-  lut40028 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40028 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_33 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40030 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_34 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly;
-
-  lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_35 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
-  lut40028 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
-  lut40028 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module SLICE_37 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
-  lut40024 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
-  lut40028 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
-
-  lut40024 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-  endspecify
-
-endmodule
-
-module SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40015 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40006 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0010 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_41 ( input D1, C1, B1, A1, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
-  wire   \SLICE_41/SLICE_41_K1_H1 , GNDI, \SLICE_41/UFMSDI_RNO/GATE_H0 , VCCI, 
-         DI0_dly, CLK_dly;
-
-  lut40033 SLICE_41_K1( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(\SLICE_41/SLICE_41_K1_H1 ));
-  lut40034 \UFMSDI_RNO/GATE ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
-    .Z(\SLICE_41/UFMSDI_RNO/GATE_H0 ));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  selmux2 SLICE_41_K0K1MUX( .D0(\SLICE_41/UFMSDI_RNO/GATE_H0 ), 
-    .D1(\SLICE_41/SLICE_41_K1_H1 ), .SD(M0), .Z(OFX0));
-
-  specify
-    (D1 => OFX0) = (0:0:0,0:0:0);
-    (C1 => OFX0) = (0:0:0,0:0:0);
-    (B1 => OFX0) = (0:0:0,0:0:0);
-    (A1 => OFX0) = (0:0:0,0:0:0);
-    (B0 => OFX0) = (0:0:0,0:0:0);
-    (A0 => OFX0) = (0:0:0,0:0:0);
-    (M0 => OFX0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40035 un1_Din_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40036 XOR8MEG_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40004 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40038 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0010 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40039 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40040 nUFMCS_s_0_m4_yy( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40041 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0042 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40040 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5F4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module vmuxregsre0042 ( input D0, D1, SD, SP, CK, LSR, output Q );
-
-  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40043 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40044 un1_CMDWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40044 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40035 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40045 UFMCLK_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0B00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_48 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40015 UFMCLK_r_i_a2_2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 UFMCLK_0io_RNO_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40019 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_50 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40048 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40049 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40049 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_51 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40050 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40051 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40050 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_52 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40052 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40053 nRRAS_5_u_i_0_RNILD5I( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40053 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40054 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40055 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40054 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40055 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_54 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40056 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40057 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40056 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_55 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut4 un1_FS_14_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40057 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40058 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 un1_FS_13_i_a2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40059 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40004 XOR8MEG18( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40059 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 UFMSDI_ens2_i_a0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40013 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40015 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_60 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40028 ADWR_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40061 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40062 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40006 RA10_2_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40063 nRWE_s_i_a3_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40064 C1WR_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 C1WR_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank_0io[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \Bank_0io[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40052 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_65 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
-
-  lut40006 UFMCLK_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40066 PHI2r3_RNITCN41( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40066 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40067 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40068 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40067 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40068 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40004 ADWR_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40016 ADWR_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, M0_dly, CLK_dly;
-
-  lut40064 CmdEnable16_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \Bank_0io[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_69 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40056 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40004 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40069 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40070 Cmdn8MEGEN_4_u_i_o2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40071 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40071 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40072 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40073 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40004 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40073 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, M0_dly, CLK_dly;
-
-  lut40058 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40038 CmdEnable17_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, 
-    F1 );
-  wire   VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly;
-
-  lut40074 XOR8MEG_3_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40075 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
-  endspecify
-
-endmodule
-
-module lut40074 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h040C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40075 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_75 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40076 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40076 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40077 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40078 nRWE_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40079 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40078 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40079 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40080 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
-    .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40080 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40081 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40035 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40082 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40082 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40024 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_81 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_82 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_83 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40077 \un9_RA[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40077 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_84 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40028 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40083 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40083 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40058 un1_FS_13_i_a2_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40028 InitReady3_0_a2_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_0_ ( input IOLDO, PADDT, output RD0 );
-
-  xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .PAD(RD0));
-
-  specify
-    (IOLDO => RD0) = (0:0:0,0:0:0);
-    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf ( input I, T, output PAD );
-
-  OBW INST1( .I(I), .T(T), .O(PAD));
-endmodule
-
-module RD_0__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module mfflsre ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module Dout_0_ ( input PADDO, output Dout0 );
-
-  xo2iobuf0084 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
-
-  specify
-    (PADDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf0084 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module PHI2 ( output PADDI, input PHI2 );
-
-  xo2iobuf0085 PHI2_pad( .Z(PADDI), .PAD(PHI2));
-
-  specify
-    (PHI2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge PHI2, 0:0:0);
-    $width (negedge PHI2, 0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf0085 ( output Z, input PAD );
-
-  IBPD INST1( .I(PAD), .O(Z));
-endmodule
-
-module PHI2_MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module smuxlregsre ( input D0, SP, CK, LSR, output Q );
-
-  IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module UFMSDO ( output PADDI, input UFMSDO );
-
-  xo2iobuf0086 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
-
-  specify
-    (UFMSDO => PADDI) = (0:0:0,0:0:0);
-    $width (posedge UFMSDO, 0:0:0);
-    $width (negedge UFMSDO, 0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf0086 ( output Z, input PAD );
-
-  IB INST1( .I(PAD), .O(Z));
-endmodule
-
-module UFMSDI ( input IOLDO, output UFMSDI );
-
-  xo2iobuf0084 UFMSDI_pad( .I(IOLDO), .PAD(UFMSDI));
-
-  specify
-    (IOLDO => UFMSDI) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module UFMSDI_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \UFMSDI$r0 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module UFMCLK ( input IOLDO, output UFMCLK );
-
-  xo2iobuf0084 UFMCLK_pad( .I(IOLDO), .PAD(UFMCLK));
-
-  specify
-    (IOLDO => UFMCLK) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module UFMCLK_MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre UFMCLK_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS ( input IOLDO, output nUFMCS );
-
-  xo2iobuf0084 nUFMCS_pad( .I(IOLDO), .PAD(nUFMCS));
-
-  specify
-    (IOLDO => nUFMCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nUFMCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0087 \nUFMCS$r1 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre0087 ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module RDQML ( input PADDO, output RDQML );
-
-  xo2iobuf0084 RDQML_pad( .I(PADDO), .PAD(RDQML));
-
-  specify
-    (PADDO => RDQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RDQMH ( input PADDO, output RDQMH );
-
-  xo2iobuf0084 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
-
-  specify
-    (PADDO => RDQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS ( input IOLDO, output nRCAS );
-
-  xo2iobuf0084 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
-
-  specify
-    (IOLDO => nRCAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0087 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS ( input IOLDO, output nRRAS );
-
-  xo2iobuf0084 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
-
-  specify
-    (IOLDO => nRRAS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0087 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE ( input IOLDO, output nRWE );
-
-  xo2iobuf0084 nRWE_pad( .I(IOLDO), .PAD(nRWE));
-
-  specify
-    (IOLDO => nRWE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0087 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE ( input IOLDO, output RCKE );
-
-  xo2iobuf0084 RCKE_pad( .I(IOLDO), .PAD(RCKE));
-
-  specify
-    (IOLDO => RCKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RCKE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \RCKE$r2 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module RCLK ( output PADDI, input RCLK );
-
-  xo2iobuf0086 RCLK_pad( .Z(PADDI), .PAD(RCLK));
-
-  specify
-    (RCLK => PADDI) = (0:0:0,0:0:0);
-    $width (posedge RCLK, 0:0:0);
-    $width (negedge RCLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS ( input IOLDO, output nRCS );
-
-  xo2iobuf0084 nRCS_pad( .I(IOLDO), .PAD(nRCS));
-
-  specify
-    (IOLDO => nRCS) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0087 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7_ ( input IOLDO, PADDT, output RD7 );
-
-  xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .PAD(RD7));
-
-  specify
-    (IOLDO => RD7) = (0:0:0,0:0:0);
-    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_7__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_6_ ( input IOLDO, PADDT, output RD6 );
-
-  xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .PAD(RD6));
-
-  specify
-    (IOLDO => RD6) = (0:0:0,0:0:0);
-    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_6__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_5_ ( input IOLDO, PADDT, output RD5 );
-
-  xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .PAD(RD5));
-
-  specify
-    (IOLDO => RD5) = (0:0:0,0:0:0);
-    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_5__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_4_ ( input IOLDO, PADDT, output RD4 );
-
-  xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .PAD(RD4));
-
-  specify
-    (IOLDO => RD4) = (0:0:0,0:0:0);
-    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_4__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_3_ ( input IOLDO, PADDT, output RD3 );
-
-  xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .PAD(RD3));
-
-  specify
-    (IOLDO => RD3) = (0:0:0,0:0:0);
-    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_3__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_2_ ( input IOLDO, PADDT, output RD2 );
-
-  xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .PAD(RD2));
-
-  specify
-    (IOLDO => RD2) = (0:0:0,0:0:0);
-    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_2__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RD_1_ ( input IOLDO, PADDT, output RD1 );
-
-  xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .PAD(RD1));
-
-  specify
-    (IOLDO => RD1) = (0:0:0,0:0:0);
-    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RD_1__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RA_11_ ( input IOLDO, output RA11 );
-
-  xo2iobuf0084 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
-
-  specify
-    (IOLDO => RA11) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10_ ( input IOLDO, output RA10 );
-
-  xo2iobuf0084 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
-
-  specify
-    (IOLDO => RA10) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
-
-  mfflsre0088 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre0088 ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module RA_9_ ( input PADDO, output RA9 );
-
-  xo2iobuf0084 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
-
-  specify
-    (PADDO => RA9) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_8_ ( input PADDO, output RA8 );
-
-  xo2iobuf0084 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
-
-  specify
-    (PADDO => RA8) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_7_ ( input PADDO, output RA7 );
-
-  xo2iobuf0084 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
-
-  specify
-    (PADDO => RA7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_6_ ( input PADDO, output RA6 );
-
-  xo2iobuf0084 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
-
-  specify
-    (PADDO => RA6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_5_ ( input PADDO, output RA5 );
-
-  xo2iobuf0084 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
-
-  specify
-    (PADDO => RA5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_4_ ( input PADDO, output RA4 );
-
-  xo2iobuf0084 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
-
-  specify
-    (PADDO => RA4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_3_ ( input PADDO, output RA3 );
-
-  xo2iobuf0084 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
-
-  specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2_ ( input PADDO, output RA2 );
-
-  xo2iobuf0084 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
-
-  specify
-    (PADDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_1_ ( input PADDO, output RA1 );
-
-  xo2iobuf0084 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
-
-  specify
-    (PADDO => RA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_0_ ( input PADDO, output RA0 );
-
-  xo2iobuf0084 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
-
-  specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1_ ( input IOLDO, output RBA1 );
-
-  xo2iobuf0084 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
-
-  specify
-    (IOLDO => RBA1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module RBA_0_ ( input IOLDO, output RBA0 );
-
-  xo2iobuf0084 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
-
-  specify
-    (IOLDO => RBA0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-  endspecify
-
-endmodule
-
-module LED ( input PADDO, output LED );
-
-  xo2iobuf0089 LED_pad( .I(PADDO), .PAD(LED));
-
-  specify
-    (PADDO => LED) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf0089 ( input I, output PAD );
-
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module nFWE ( output PADDI, input nFWE );
-
-  xo2iobuf0090 nFWE_pad( .Z(PADDI), .PAD(nFWE));
-
-  specify
-    (nFWE => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nFWE, 0:0:0);
-    $width (negedge nFWE, 0:0:0);
-  endspecify
-
-endmodule
-
-module xo2iobuf0090 ( output Z, input PAD );
-
-  IBPU INST1( .I(PAD), .O(Z));
-endmodule
-
-module nCRAS ( output PADDI, input nCRAS );
-
-  xo2iobuf0090 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
-
-  specify
-    (nCRAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCRAS, 0:0:0);
-    $width (negedge nCRAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module nCCAS ( output PADDI, input nCCAS );
-
-  xo2iobuf0090 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
-
-  specify
-    (nCCAS => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nCCAS, 0:0:0);
-    $width (negedge nCCAS, 0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_7_ ( input PADDO, output Dout7 );
-
-  xo2iobuf0084 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
-
-  specify
-    (PADDO => Dout7) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_6_ ( input PADDO, output Dout6 );
-
-  xo2iobuf0084 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
-
-  specify
-    (PADDO => Dout6) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_5_ ( input PADDO, output Dout5 );
-
-  xo2iobuf0084 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
-
-  specify
-    (PADDO => Dout5) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_4_ ( input PADDO, output Dout4 );
-
-  xo2iobuf0084 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
-
-  specify
-    (PADDO => Dout4) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input PADDO, output Dout3 );
-
-  xo2iobuf0084 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
-
-  specify
-    (PADDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input PADDO, output Dout2 );
-
-  xo2iobuf0084 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
-
-  specify
-    (PADDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input PADDO, output Dout1 );
-
-  xo2iobuf0084 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
-
-  specify
-    (PADDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7_ ( output PADDI, input Din7 );
-
-  xo2iobuf0086 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
-
-  specify
-    (Din7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din7, 0:0:0);
-    $width (negedge Din7, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_7__MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6_ ( output PADDI, input Din6 );
-
-  xo2iobuf0086 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
-
-  specify
-    (Din6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din6, 0:0:0);
-    $width (negedge Din6, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_6__MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5_ ( output PADDI, input Din5 );
-
-  xo2iobuf0086 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
-
-  specify
-    (Din5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din5, 0:0:0);
-    $width (negedge Din5, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_5__MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4_ ( output PADDI, input Din4 );
-
-  xo2iobuf0086 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
-
-  specify
-    (Din4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din4, 0:0:0);
-    $width (negedge Din4, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_4__MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3_ ( output PADDI, input Din3 );
-
-  xo2iobuf0086 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
-
-  specify
-    (Din3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din3, 0:0:0);
-    $width (negedge Din3, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_3__MGIOL ( input DI, CLK, output IN );
-  wire   VCCI, GNDI, DI_dly, CLK_dly;
-
-  smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IN));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2_ ( output PADDI, input Din2 );
-
-  xo2iobuf0086 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
-
-  specify
-    (Din2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din2, 0:0:0);
-    $width (negedge Din2, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_2__MGIOL ( input DI, CE, CLK, output IN );
-  wire   CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
-
-  smuxlregsre CmdUFMCS( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IN));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Din_1_ ( output PADDI, input Din1 );
-
-  xo2iobuf0086 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
-
-  specify
-    (Din1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din1, 0:0:0);
-    $width (negedge Din1, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_1__MGIOL ( input DI, CE, CLK, output IN );
-  wire   CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
-
-  smuxlregsre CmdUFMCLK( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IN));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Din_0_ ( output PADDI, input Din0 );
-
-  xo2iobuf0086 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
-
-  specify
-    (Din0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge Din0, 0:0:0);
-    $width (negedge Din0, 0:0:0);
-  endspecify
-
-endmodule
-
-module Din_0__MGIOL ( input DI, CE, CLK, output IN );
-  wire   CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
-
-  smuxlregsre CmdUFMSDI( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), 
-    .Q(IN));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IN) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module CROW_1_ ( output PADDI, input CROW1 );
-
-  xo2iobuf0086 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
-
-  specify
-    (CROW1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW1, 0:0:0);
-    $width (negedge CROW1, 0:0:0);
-  endspecify
-
-endmodule
-
-module CROW_0_ ( output PADDI, input CROW0 );
-
-  xo2iobuf0086 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
-
-  specify
-    (CROW0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge CROW0, 0:0:0);
-    $width (negedge CROW0, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_9_ ( output PADDI, input MAin9 );
-
-  xo2iobuf0086 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
-
-  specify
-    (MAin9 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin9, 0:0:0);
-    $width (negedge MAin9, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_8_ ( output PADDI, input MAin8 );
-
-  xo2iobuf0086 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
-
-  specify
-    (MAin8 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin8, 0:0:0);
-    $width (negedge MAin8, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_7_ ( output PADDI, input MAin7 );
-
-  xo2iobuf0086 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
-
-  specify
-    (MAin7 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin7, 0:0:0);
-    $width (negedge MAin7, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_6_ ( output PADDI, input MAin6 );
-
-  xo2iobuf0086 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
-
-  specify
-    (MAin6 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin6, 0:0:0);
-    $width (negedge MAin6, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_5_ ( output PADDI, input MAin5 );
-
-  xo2iobuf0086 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
-
-  specify
-    (MAin5 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin5, 0:0:0);
-    $width (negedge MAin5, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_4_ ( output PADDI, input MAin4 );
-
-  xo2iobuf0086 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
-
-  specify
-    (MAin4 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin4, 0:0:0);
-    $width (negedge MAin4, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_3_ ( output PADDI, input MAin3 );
-
-  xo2iobuf0086 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
-
-  specify
-    (MAin3 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin3, 0:0:0);
-    $width (negedge MAin3, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_2_ ( output PADDI, input MAin2 );
-
-  xo2iobuf0086 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
-
-  specify
-    (MAin2 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin2, 0:0:0);
-    $width (negedge MAin2, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_1_ ( output PADDI, input MAin1 );
-
-  xo2iobuf0086 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
-
-  specify
-    (MAin1 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin1, 0:0:0);
-    $width (negedge MAin1, 0:0:0);
-  endspecify
-
-endmodule
-
-module MAin_0_ ( output PADDI, input MAin0 );
-
-  xo2iobuf0086 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
-
-  specify
-    (MAin0 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge MAin0, 0:0:0);
-    $width (negedge MAin0, 0:0:0);
-  endspecify
-
-endmodule
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm
deleted file mode 100644
index 8f7f539..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.htm
+++ /dev/null
@@ -1,9 +0,0 @@
-
- 
- syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file
- 
- 
- 
- 				 
-
- 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
deleted file mode 100644
index f197974..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
+++ /dev/null
@@ -1,310 +0,0 @@
-
-Place & Route Report
-
-
-
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 23:30:05 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
-RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
-RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
-D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-
-
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            5.827        0            0.304        0            06           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Tue Aug 15 23:30:05 2023
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)   67+4(JTAG)/80      89% used
-                  67+4(JTAG)/79      90% bonded
-   IOLOGIC           29/80           36% used
-
-   SLICE             81/320          25% used
-
-
-
-Number of Signals: 292
-Number of Connections: 703
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 18)
-
-WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 2 signals are selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
-    nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
-
-WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-...........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-....................
-Placer score = 41844.
-Finished Placer Phase 1.  REAL time: 4 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  41803
-Finished Placer Phase 2.  REAL time: 4 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 4 out of 80 (5%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
-  SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
-
-  PRIMARY  : 2 out of 8 (25%)
-  SECONDARY: 2 out of 8 (25%)
-
-
-
-
-I/O Usage Summary (final):
-   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
-   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
-| 1        | 20 / 20 (100%) | 3.3V       | -         |
-| 2        | 16 / 20 ( 80%) | 3.3V       | -         |
-| 3        | 18 / 20 ( 90%) | 3.3V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 3 secs 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 703 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 23:30:11 08/15/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 23:30:11 08/15/23
-
-Start NBR section for initial routing at 23:30:11 08/15/23
-Level 1, iteration 1
-0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 6.016ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 6.058ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 23:30:11 08/15/23
-Level 4, iteration 1
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23
-
-Start NBR section for re-routing at 23:30:11 08/15/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 5.827ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 23:30:11 08/15/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 5.827ns
-  Timing score<setup> : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  703 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 5.827
-PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
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diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt
deleted file mode 100644
index ac8269d..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_scck.rpt
+++ /dev/null
@@ -1,59 +0,0 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-
-# Written on Tue Aug 15 23:12:43 2023
-
-##### FILES SYNTAX CHECKED ##############################################
-Constraint File(s):      "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
-
-#Run constraint checker to find more issues with constraints.
-#########################################################################
-
-
-
-No issues found in constraint syntax.
-
-
-
-Clock Summary
-*************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-Clock Load Summary
-******************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
deleted file mode 100644
index 0a00dda..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
+++ /dev/null
@@ -1,506 +0,0 @@
-
-Lattice Map TRACE Report
-
-
-
    Map TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:32 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             170 items scored, 0 timing errors detected.
-Report:   47.214MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             590 items scored, 0 timing errors detected.
-Report:   86.296MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:              10.424ns  (36.2% logic, 63.8% route), 7 logic levels.
-
- Constraint Details:
-
-     10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1   e 1.234 *n[3]_MGIOL.IN to    SLICE_43.C1 Bank[3]
-CTOF_DEL    ---     0.495    SLICE_43.C1 to    SLICE_43.F1 SLICE_43
-ROUTE         1   e 1.234    SLICE_43.F1 to    SLICE_69.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495    SLICE_69.D0 to    SLICE_69.F0 SLICE_69
-ROUTE         5   e 1.234    SLICE_69.F0 to    SLICE_60.D0 un1_Bank_1
-CTOF_DEL    ---     0.495    SLICE_60.D0 to    SLICE_60.F0 SLICE_60
-ROUTE         2   e 1.234    SLICE_60.F0 to    SLICE_46.A1 ADWR
-CTOF_DEL    ---     0.495    SLICE_46.A1 to    SLICE_46.F1 SLICE_46
-ROUTE         3   e 0.480    SLICE_46.F1 to    SLICE_46.D0 un1_ADWR
-CTOF_DEL    ---     0.495    SLICE_46.D0 to    SLICE_46.F0 SLICE_46
-ROUTE         1   e 1.234    SLICE_46.F0 to    SLICE_18.C0 un1_CMDWR
-CTOOFX_DEL  ---     0.721    SLICE_18.C0 to  SLICE_18.OFX0 SLICE_18
-ROUTE         1   e 0.001  SLICE_18.OFX0 to   SLICE_18.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                   10.424   (36.2% logic, 63.8% route), 7 logic levels.
-
-Report:   47.214MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 4.412ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
-
- Constraint Details:
-
-     11.306ns physical path delay SLICE_1 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3   e 1.234     SLICE_1.Q0 to    SLICE_72.D1 FS[17]
-CTOF_DEL    ---     0.495    SLICE_72.D1 to    SLICE_72.F1 SLICE_72
-ROUTE         1   e 1.234    SLICE_72.F1 to    SLICE_64.C1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_59.C1 N_129
-CTOF_DEL    ---     0.495    SLICE_59.C1 to    SLICE_59.F1 SLICE_59
-ROUTE         2   e 0.480    SLICE_59.F1 to    SLICE_59.D0 N_145
-CTOF_DEL    ---     0.495    SLICE_59.D0 to    SLICE_59.F0 SLICE_59
-ROUTE         2   e 1.234    SLICE_59.F0 to    SLICE_56.B0 N_139_8
-CTOF_DEL    ---     0.495    SLICE_56.B0 to    SLICE_56.F0 SLICE_56
-ROUTE         1   e 1.234    SLICE_56.F0 to    SLICE_54.C0 N_140
-CTOF_DEL    ---     0.495    SLICE_54.C0 to    SLICE_54.F0 SLICE_54
-ROUTE         1   e 1.234    SLICE_54.F0 to    SLICE_27.CE N_28 (to RCLK_c)
-                  --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
-
-Report:   86.296MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   47.214 MHz|   7  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   86.296 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:32 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             170 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             590 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_10 to SLICE_10 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_10.CLK to    SLICE_10.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2   e 0.199    SLICE_10.Q0 to    SLICE_10.A0 ADSubmitted
-CTOF_DEL    ---     0.101    SLICE_10.A0 to    SLICE_10.F0 SLICE_10
-ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.332ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_14.Q0 to    SLICE_14.M1 CASr (to RCLK_c)
-                  --------
-                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
deleted file mode 100644
index 4a10516..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
+++ /dev/null
@@ -1,2342 +0,0 @@
-
-Lattice TRACE Report
-
-
-
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:39 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             170 items scored, 0 timing errors detected.
-Report:   55.475MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             590 items scored, 0 timing errors detected.
-Report:  101.286MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 163.401ns (weighted slack = 326.802ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.950ns  (28.6% logic, 71.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.950ns physical path delay Din[3]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.401ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.950   (28.6% logic, 71.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.452ns (weighted slack = 326.904ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.899ns  (28.7% logic, 71.3% route), 5 logic levels.
-
- Constraint Details:
-
-      8.899ns physical path delay Din[7]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.452ns
-
- Physical Path Details:
-
-      Data path Din[7]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_L2A.CLK to     IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_L2A.IN to       R3C6A.D1 Bank[7]
-CTOF_DEL    ---     0.495       R3C6A.D1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.899   (28.7% logic, 71.3% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[7]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.522ns (weighted slack = 327.044ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[4]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.829ns  (29.0% logic, 71.0% route), 5 logic levels.
-
- Constraint Details:
-
-      8.829ns physical path delay Din[4]_MGIOL to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.063ns CE_SET requirement (totaling 172.351ns) by 163.522ns
-
- Physical Path Details:
-
-      Data path Din[4]_MGIOL to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6A.CLK to     IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_T6A.IN to       R4C6A.D1 Bank[4]
-CTOF_DEL    ---     0.495       R4C6A.D1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.829   (29.0% logic, 71.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.573ns (weighted slack = 327.146ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.502ns  (44.4% logic, 55.6% route), 7 logic levels.
-
- Constraint Details:
-
-      8.502ns physical path delay Din[3]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.573ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.502   (44.4% logic, 55.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.624ns (weighted slack = 327.248ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.451ns  (44.6% logic, 55.4% route), 7 logic levels.
-
- Constraint Details:
-
-      8.451ns physical path delay Din[7]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.624ns
-
- Physical Path Details:
-
-      Data path Din[7]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_L2A.CLK to     IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_L2A.IN to       R3C6A.D1 Bank[7]
-CTOF_DEL    ---     0.495       R3C6A.D1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.451   (44.6% logic, 55.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[7]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.694ns (weighted slack = 327.388ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[4]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.381ns  (45.0% logic, 55.0% route), 7 logic levels.
-
- Constraint Details:
-
-      8.381ns physical path delay Din[4]_MGIOL to SLICE_18 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 163.694ns
-
- Physical Path Details:
-
-      Data path Din[4]_MGIOL to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6A.CLK to     IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
-ROUTE         1     1.375     IOL_T6A.IN to       R4C6A.D1 Bank[4]
-CTOF_DEL    ---     0.495       R4C6A.D1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.381   (45.0% logic, 55.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6A.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.812ns (weighted slack = 327.624ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.712ns  (27.9% logic, 72.1% route), 5 logic levels.
-
- Constraint Details:
-
-      8.712ns physical path delay SLICE_63 to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-     -0.173ns skew and
-      0.063ns CE_SET requirement (totaling 172.524ns) by 163.812ns
-
- Physical Path Details:
-
-      Data path SLICE_63 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C7A.CLK to       R4C7A.Q0 SLICE_63 (from PHI2_c)
-ROUTE         1     1.383       R4C7A.Q0 to       R4C6A.A1 Bank[0]
-CTOF_DEL    ---     0.495       R4C6A.A1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.712   (27.9% logic, 72.1% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R4C7A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 163.984ns (weighted slack = 327.968ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               8.264ns  (44.1% logic, 55.9% route), 7 logic levels.
-
- Constraint Details:
-
-      8.264ns physical path delay SLICE_63 to SLICE_18 meets
-    172.414ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 172.248ns) by 163.984ns
-
- Physical Path Details:
-
-      Data path SLICE_63 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C7A.CLK to       R4C7A.Q0 SLICE_63 (from PHI2_c)
-ROUTE         1     1.383       R4C7A.Q0 to       R4C6A.A1 Bank[0]
-CTOF_DEL    ---     0.495       R4C6A.A1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8D.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8D.C1 to       R3C8D.F1 SLICE_46
-ROUTE         3     0.445       R3C8D.F1 to       R3C8D.C0 un1_ADWR
-CTOF_DEL    ---     0.495       R3C8D.C0 to       R3C8D.F0 SLICE_46
-ROUTE         1     0.315       R3C8D.F0 to       R3C8C.D0 un1_CMDWR
-CTOOFX_DEL  ---     0.721       R3C8C.D0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    8.264   (44.1% logic, 55.9% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R4C7A.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 164.041ns (weighted slack = 328.082ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[3]  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               8.034ns  (38.0% logic, 62.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.034ns physical path delay Din[3]_MGIOL to SLICE_10 meets
-    172.414ns delay constraint less
-      0.173ns skew and
-      0.166ns DIN_SET requirement (totaling 172.075ns) by 164.041ns
-
- Physical Path Details:
-
-      Data path Din[3]_MGIOL to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-C2INP_DEL   ---     0.577    IOL_T6C.CLK to     IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
-ROUTE         1     1.496     IOL_T6C.IN to       R4C6A.C1 Bank[3]
-CTOF_DEL    ---     0.495       R4C6A.C1 to       R4C6A.F1 SLICE_43
-ROUTE         1     0.623       R4C6A.F1 to       R3C6A.D0 un1_Bank_1_4
-CTOF_DEL    ---     0.495       R3C6A.D0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.092       R3C6A.F0 to       R4C8D.D0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8D.D0 to       R4C8D.F0 SLICE_60
-ROUTE         2     0.758       R4C8D.F0 to       R3C8B.C1 ADWR
-CTOF_DEL    ---     0.495       R3C8B.C1 to       R3C8B.F1 SLICE_10
-ROUTE         2     1.013       R3C8B.F1 to       R3C8B.B0 CmdEnable17
-CTOF_DEL    ---     0.495       R3C8B.B0 to       R3C8B.F0 SLICE_10
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    8.034   (38.0% logic, 62.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to Din[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_T6C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 164.046ns (weighted slack = 328.092ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_0io[2]  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI  (to PHI2_c -)
-
-   Delay:               8.478ns  (28.7% logic, 71.3% route), 5 logic levels.
-
- Constraint Details:
-
-      8.478ns physical path delay SLICE_68 to Din[0]_MGIOL meets
-    172.414ns delay constraint less
-     -0.173ns skew and
-      0.063ns CE_SET requirement (totaling 172.524ns) by 164.046ns
-
- Physical Path Details:
-
-      Data path SLICE_68 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R3C9C.CLK to       R3C9C.Q0 SLICE_68 (from PHI2_c)
-ROUTE         1     1.079       R3C9C.Q0 to       R3C6A.C1 Bank[2]
-CTOF_DEL    ---     0.495       R3C6A.C1 to       R3C6A.F1 SLICE_69
-ROUTE         1     0.693       R3C6A.F1 to       R3C6A.B0 un1_Bank_1_3
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_69
-ROUTE         5     1.213       R3C6A.F0 to       R4C8A.C0 un1_Bank_1
-CTOF_DEL    ---     0.495       R4C8A.C0 to       R4C8A.F0 SLICE_57
-ROUTE         5     0.710       R4C8A.F0 to       R4C8B.B1 XOR8MEG18
-CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_20
-ROUTE         3     2.351       R4C8B.F1 to     IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
-                  --------
-                    8.478   (28.7% logic, 71.3% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_68:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.539        8.PADDI to      R3C9C.CLK PHI2_c
-                  --------
-                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to Din[0]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     3.712        8.PADDI to    IOL_L2C.CLK PHI2_c
-                  --------
-                    3.712   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   55.475MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCCAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 338.168ns
-         The internal maximum frequency of the following component is 150.150 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    PIO        PAD            nCRAS
-
-   Delay:               6.660ns -- based on Minimum Pulse Width
-
-Report:  150.150MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 6.127ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.591ns  (35.7% logic, 64.3% route), 7 logic levels.
-
- Constraint Details:
-
-      9.591ns physical path delay SLICE_4 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.127ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.177       R6C4C.Q1 to       R6C5D.C1 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.C1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.591   (35.7% logic, 64.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.287ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.431ns  (36.3% logic, 63.7% route), 7 logic levels.
-
- Constraint Details:
-
-      9.431ns physical path delay SLICE_1 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.287ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3     1.017       R6C5B.Q0 to       R6C5D.B1 FS[17]
-CTOF_DEL    ---     0.495       R6C5D.B1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.431   (36.3% logic, 63.7% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.319ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.399ns  (36.4% logic, 63.6% route), 7 logic levels.
-
- Constraint Details:
-
-      9.399ns physical path delay SLICE_3 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.319ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.985       R6C4D.Q0 to       R6C5D.A1 FS[13]
-CTOF_DEL    ---     0.495       R6C5D.A1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.399   (36.4% logic, 63.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.646ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[14]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               9.072ns  (37.7% logic, 62.3% route), 7 logic levels.
-
- Constraint Details:
-
-      9.072ns physical path delay SLICE_3 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.646ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q1 SLICE_3 (from RCLK_c)
-ROUTE         3     0.658       R6C4D.Q1 to       R6C5D.D1 FS[14]
-CTOF_DEL    ---     0.495       R6C5D.D1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    9.072   (37.7% logic, 62.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.977ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.741ns  (39.1% logic, 60.9% route), 7 logic levels.
-
- Constraint Details:
-
-      8.741ns physical path delay SLICE_4 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 6.977ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.177       R6C4C.Q1 to       R6C5D.C1 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.C1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.741   (39.1% logic, 60.9% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.097ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[16]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.621ns  (34.0% logic, 66.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.621ns physical path delay SLICE_2 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.097ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q1 SLICE_2 (from RCLK_c)
-ROUTE         4     1.017       R6C5A.Q1 to       R6C5C.B1 FS[16]
-CTOF_DEL    ---     0.495       R6C5C.B1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    8.621   (34.0% logic, 66.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.137ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[17]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.581ns  (39.9% logic, 60.1% route), 7 logic levels.
-
- Constraint Details:
-
-      8.581ns physical path delay SLICE_1 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.137ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5B.CLK to       R6C5B.Q0 SLICE_1 (from RCLK_c)
-ROUTE         3     1.017       R6C5B.Q0 to       R6C5D.B1 FS[17]
-CTOF_DEL    ---     0.495       R6C5D.B1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.581   (39.9% logic, 60.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.169ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)
-
-   Delay:               8.549ns  (40.0% logic, 60.0% route), 7 logic levels.
-
- Constraint Details:
-
-      8.549ns physical path delay SLICE_3 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.169ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.985       R6C4D.Q0 to       R6C5D.A1 FS[13]
-CTOF_DEL    ---     0.495       R6C5D.A1 to       R6C5D.F1 SLICE_72
-ROUTE         1     0.315       R6C5D.F1 to       R6C5C.D1 UFMSDI_ens2_i_o2_0_3
-CTOF_DEL    ---     0.495       R6C5C.D1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.632       R5C4C.F0 to       R4C4A.D1 N_139_8
-CTOF_DEL    ---     0.495       R4C4A.D1 to       R4C4A.F1 SLICE_55
-ROUTE         1     0.693       R4C4A.F1 to       R4C4A.B0 N_139
-CTOF_DEL    ---     0.495       R4C4A.B0 to       R4C4A.F0 SLICE_55
-ROUTE         1     1.069       R4C4A.F0 to       R4C6A.CE N_26 (to RCLK_c)
-                  --------
-                    8.549   (40.0% logic, 60.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R4C6A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.281ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_0io  (to RCLK_c +)
-
-   Delay:               8.739ns  (27.8% logic, 72.2% route), 5 logic levels.
-
- Constraint Details:
-
-      8.739ns physical path delay SLICE_4 to UFMCLK_MGIOL meets
-     16.000ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 16.020ns) by 7.281ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to UFMCLK_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     1.434       R6C4C.Q1 to       R6C5D.B0 FS[12]
-CTOF_DEL    ---     0.495       R6C5D.B0 to       R6C5D.F0 SLICE_72
-ROUTE         2     1.902       R6C5D.F0 to       R5C5C.A1 N_137_5
-CTOF_DEL    ---     0.495       R5C5C.A1 to       R5C5C.F1 SLICE_48
-ROUTE         2     0.982       R5C5C.F1 to       R5C5C.A0 UFMCLK_r_i_a2_2_2
-CTOF_DEL    ---     0.495       R5C5C.A0 to       R5C5C.F0 SLICE_48
-ROUTE         1     0.693       R5C5C.F0 to       R5C5D.B0 d_m3_0_a2_0
-CTOF_DEL    ---     0.495       R5C5D.B0 to       R5C5D.F0 SLICE_47
-ROUTE         1     1.296       R5C5D.F0 to   IOL_B4C.OPOS i1_i (to RCLK_c)
-                  --------
-                    8.739   (27.8% logic, 72.2% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to UFMCLK_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.243       62.PADDI to    IOL_B4C.CLK RCLK_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.354ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN  (to RCLK_c +)
-
-   Delay:               8.364ns  (35.0% logic, 65.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.364ns physical path delay SLICE_2 to SLICE_27 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.282ns CE_SET requirement (totaling 15.718ns) by 7.354ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R6C5A.CLK to       R6C5A.Q0 SLICE_2 (from RCLK_c)
-ROUTE         3     0.760       R6C5A.Q0 to       R6C5C.C1 FS[15]
-CTOF_DEL    ---     0.495       R6C5C.C1 to       R6C5C.F1 SLICE_64
-ROUTE         4     0.988       R6C5C.F1 to       R5C4C.D1 N_129
-CTOF_DEL    ---     0.495       R5C4C.D1 to       R5C4C.F1 SLICE_59
-ROUTE         2     0.445       R5C4C.F1 to       R5C4C.C0 N_145
-CTOF_DEL    ---     0.495       R5C4C.C0 to       R5C4C.F0 SLICE_59
-ROUTE         2     0.753       R5C4C.F0 to       R5C3A.C0 N_139_8
-CTOF_DEL    ---     0.495       R5C3A.C0 to       R5C3A.F0 SLICE_56
-ROUTE         1     1.079       R5C3A.F0 to       R4C4D.C0 N_140
-CTOF_DEL    ---     0.495       R4C4D.C0 to       R4C4D.F0 SLICE_54
-ROUTE         1     1.412       R4C4D.F0 to       R5C7B.CE N_28 (to RCLK_c)
-                  --------
-                    8.364   (35.0% logic, 65.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R6C5A.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_27:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     3.070       62.PADDI to      R5C7B.CLK RCLK_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  101.286MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   55.475 MHz|   5  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  101.286 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 22:56:39 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
-Preference file: ram2gs_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)
    •             170 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)
    •             590 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-            170 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_10 to SLICE_10 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 ADSubmitted
-CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_10
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 ADSubmitted_r (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        C1Submitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_13 to SLICE_13 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_13 (from PHI2_c)
-ROUTE         2     0.132       R3C8A.Q0 to       R3C8A.A0 C1Submitted
-CTOF_DEL    ---     0.101       R3C8A.A0 to       R3C8A.F0 SLICE_13
-ROUTE         1     0.000       R3C8A.F0 to      R3C8A.DI0 C1Submitted_s (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_20 to SLICE_20 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_20 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C8B.CLK to       R4C8B.Q0 SLICE_20 (from PHI2_c)
-ROUTE         4     0.132       R4C8B.Q0 to       R4C8B.A0 CmdSubmitted
-CTOF_DEL    ---     0.101       R4C8B.A0 to       R4C8B.F0 SLICE_20
-ROUTE         1     0.000       R4C8B.F0 to      R4C8B.DI0 N_412_0 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R4C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_20:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R4C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_42 to SLICE_42 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_42 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q0 SLICE_42 (from PHI2_c)
-ROUTE         2     0.132       R5C9B.Q0 to       R5C9B.A0 XOR8MEG
-CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_42
-ROUTE         1     0.000       R5C9B.F0 to      R5C9B.DI0 XOR8MEG_3 (to PHI2_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C9B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.435ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.422ns  (68.5% logic, 31.5% route), 2 logic levels.
-
- Constraint Details:
-
-      0.422ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.435ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8C.CLK to       R3C8C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         3     0.133       R3C8C.Q0 to       R3C8C.A0 CmdEnable
-CTOOFX_DEL  ---     0.156       R3C8C.A0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.422   (68.5% logic, 31.5% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.440ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.427ns  (67.7% logic, 32.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.427ns physical path delay SLICE_10 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.440ns
-
- Physical Path Details:
-
-      Data path SLICE_10 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_10 (from PHI2_c)
-ROUTE         2     0.138       R3C8B.Q0 to       R3C8C.C1 ADSubmitted
-CTOOFX_DEL  ---     0.156       R3C8C.C1 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.427   (67.7% logic, 32.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_10:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.526ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.513ns  (56.3% logic, 43.7% route), 2 logic levels.
-
- Constraint Details:
-
-      0.513ns physical path delay SLICE_13 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.526ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_13 (from PHI2_c)
-ROUTE         2     0.224       R3C8A.Q0 to       R3C8C.B0 C1Submitted
-CTOOFX_DEL  ---     0.156       R3C8C.B0 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.513   (56.3% logic, 43.7% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8A.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.527ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)
-
-   Delay:               0.514ns  (56.2% logic, 43.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.514ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.527ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8C.CLK to       R3C8C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         3     0.225       R3C8C.Q0 to       R3C8C.B1 CmdEnable
-CTOOFX_DEL  ---     0.156       R3C8C.B1 to     R3C8C.OFX0 SLICE_18
-ROUTE         1     0.000     R3C8C.OFX0 to      R3C8C.DI0 CmdEnable_s (to PHI2_c)
-                  --------
-                    0.514   (56.2% logic, 43.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R3C8C.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.616ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDEN  (from PHI2_c -)
-   Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)
-
-   Delay:               0.603ns  (55.6% logic, 44.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.603ns physical path delay SLICE_19 to SLICE_19 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.616ns
-
- Physical Path Details:
-
-      Data path SLICE_19 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C8B.CLK to       R5C8B.Q0 SLICE_19 (from PHI2_c)
-ROUTE         2     0.212       R5C8B.Q0 to       R5C8A.A1 CmdLEDEN
-CTOF_DEL    ---     0.101       R5C8A.A1 to       R5C8A.F1 SLICE_70
-ROUTE         1     0.056       R5C8A.F1 to       R5C8B.C0 N_59
-CTOF_DEL    ---     0.101       R5C8B.C0 to       R5C8B.F0 SLICE_19
-ROUTE         1     0.000       R5C8B.F0 to      R5C8B.DI0 N_14_i (to PHI2_c)
-                  --------
-                    0.603   (55.6% logic, 44.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.702ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Cmdn8MEGEN  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)
-
-   Delay:               0.689ns  (48.6% logic, 51.4% route), 3 logic levels.
-
- Constraint Details:
-
-      0.689ns physical path delay SLICE_21 to SLICE_21 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.702ns
-
- Physical Path Details:
-
-      Data path SLICE_21 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C8D.CLK to       R5C8D.Q0 SLICE_21 (from PHI2_c)
-ROUTE         2     0.224       R5C8D.Q0 to       R5C8C.B1 Cmdn8MEGEN
-CTOF_DEL    ---     0.101       R5C8C.B1 to       R5C8C.F1 SLICE_50
-ROUTE         1     0.130       R5C8C.F1 to       R5C8D.A0 Cmdn8MEGEN_4_u_i_0
-CTOF_DEL    ---     0.101       R5C8D.A0 to       R5C8D.F0 SLICE_21
-ROUTE         1     0.000       R5C8D.F0 to      R5C8D.DI0 N_12_i (to PHI2_c)
-                  --------
-                    0.689   (48.6% logic, 51.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8D.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_21:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        19     1.240        8.PADDI to      R5C8D.CLK PHI2_c
-                  --------
-                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-            590 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.304ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CASr  (from RCLK_c +)
-   Destination:    FF         Data in        CASr2  (to RCLK_c +)
-
-   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.285ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9A.CLK to       R5C9A.Q0 SLICE_14 (from RCLK_c)
-ROUTE         1     0.152       R5C9A.Q0 to       R5C9A.M1 CASr (to RCLK_c)
-                  --------
-                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.309ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr  (from RCLK_c +)
-   Destination:    FF         Data in        RASr2  (to RCLK_c +)
-
-   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.290ns physical path delay SLICE_29 to SLICE_29 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.309ns
-
- Physical Path Details:
-
-      Data path SLICE_29 to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R6C12B.CLK to      R6C12B.Q0 SLICE_29 (from RCLK_c)
-ROUTE         2     0.157      R6C12B.Q0 to      R6C12B.M1 RASr (to RCLK_c)
-                  --------
-                    0.290   (45.9% logic, 54.1% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.311ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr2  (from RCLK_c +)
-   Destination:    FF         Data in        RASr3  (to RCLK_c +)
-
-   Delay:               0.292ns  (45.5% logic, 54.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.292ns physical path delay SLICE_29 to SLICE_32 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.311ns
-
- Physical Path Details:
-
-      Data path SLICE_29 to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R6C12B.CLK to      R6C12B.Q1 SLICE_29 (from RCLK_c)
-ROUTE        10     0.159      R6C12B.Q1 to      R6C12A.M1 RASr2 (to RCLK_c)
-                  --------
-                    0.292   (45.5% logic, 54.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_32:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R6C12A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.311ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r2  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r3  (to RCLK_c +)
-
-   Delay:               0.292ns  (45.5% logic, 54.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.292ns physical path delay SLICE_65 to SLICE_65 meets
-     -0.019ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.019ns) by 0.311ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C4B.CLK to       R4C4B.Q0 SLICE_65 (from RCLK_c)
-ROUTE         3     0.159       R4C4B.Q0 to       R4C4B.M1 PHI2r2 (to RCLK_c)
-                  --------
-                    0.292   (45.5% logic, 54.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R4C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R4C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[0]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[0]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C3A.CLK to       R6C3A.Q1 SLICE_0 (from RCLK_c)
-ROUTE         3     0.132       R6C3A.Q1 to       R6C3A.A1 FS[0]
-CTOF_DEL    ---     0.101       R6C3A.A1 to       R6C3A.F1 SLICE_0
-ROUTE         1     0.000       R6C3A.F1 to      R6C3A.DI1 FS_s[0] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[13]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_3 to SLICE_3 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4D.CLK to       R6C4D.Q0 SLICE_3 (from RCLK_c)
-ROUTE         3     0.132       R6C4D.Q0 to       R6C4D.A0 FS[13]
-CTOF_DEL    ---     0.101       R6C4D.A0 to       R6C4D.F0 SLICE_3
-ROUTE         1     0.000       R6C4D.F0 to      R6C4D.DI0 FS_s[13] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4D.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Ready_fast  (from RCLK_c +)
-   Destination:    FF         Data in        Ready_fast  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_34 to SLICE_34 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C13C.CLK to      R4C13C.Q0 SLICE_34 (from RCLK_c)
-ROUTE        14     0.132      R4C13C.Q0 to      R4C13C.A0 Ready_fast
-CTOF_DEL    ---     0.101      R4C13C.A0 to      R4C13C.F0 SLICE_34
-ROUTE         1     0.000      R4C13C.F0 to     R4C13C.DI0 N_415_0 (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R4C13C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to     R4C13C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[12]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_4 to SLICE_4 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4C.CLK to       R6C4C.Q1 SLICE_4 (from RCLK_c)
-ROUTE         3     0.132       R6C4C.Q1 to       R6C4C.A1 FS[12]
-CTOF_DEL    ---     0.101       R6C4C.A1 to       R6C4C.F1 SLICE_4
-ROUTE         1     0.000       R6C4C.F1 to      R6C4C.DI1 FS_s[12] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4C.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nUFMCS  (from RCLK_c +)
-   Destination:    FF         Data in        nUFMCS  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_45 to SLICE_45 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_45 to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5A.CLK to       R5C5A.Q0 SLICE_45 (from RCLK_c)
-ROUTE         1     0.130       R5C5A.Q0 to       R5C5A.A0 nUFMCS_c
-CTOF_DEL    ---     0.101       R5C5A.A0 to       R5C5A.F0 SLICE_45
-ROUTE         2     0.002       R5C5A.F0 to      R5C5A.DI0 nUFMCS_s_0_N_5_i (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C5A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_45:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R5C5A.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[9]  (from RCLK_c +)
-   Destination:    FF         Data in        FS[9]  (to RCLK_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_5 to SLICE_5 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C4B.CLK to       R6C4B.Q0 SLICE_5 (from RCLK_c)
-ROUTE         3     0.132       R6C4B.Q0 to       R6C4B.A0 FS[9]
-CTOF_DEL    ---     0.101       R6C4B.A0 to       R6C4B.F0 SLICE_5
-ROUTE         1     0.000       R6C4B.F0 to      R6C4B.DI0 FS_s[9] (to RCLK_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.059       62.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
-                                        |             |             |
-FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 19
-   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
-
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log
deleted file mode 100644
index e161627..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log
+++ /dev/null
@@ -1,15 +0,0 @@
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-DRC complete with no errors or warnings
-
-Design Results:
-    309 blocks expanded
-completed the first expansion
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr
deleted file mode 100644
index 4586322..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr
+++ /dev/null
@@ -1,297 +0,0 @@
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Tue Aug 15 05:03:23 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 119 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i1 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i1 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
-Route         1   e 0.941                                  Bank[1]
-LUT4        ---     0.493              D to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i4 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i4 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
-Route         1   e 0.941                                  Bank[4]
-LUT4        ---     0.493              C to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.256ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
-
- Constraint Details:
-
-      9.471ns data_path Bank_i3 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
-
- Path Details: Bank_i3 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
-Route         1   e 0.941                                  Bank[3]
-LUT4        ---     0.493              B to Z              i1989_2_lut
-Route         1   e 0.941                                  n2287
-LUT4        ---     0.493              C to Z              i12_4_lut
-Route         8   e 1.540                                  n26
-LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
-
-Warning: 9.918 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            498 items scored, 186 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i13 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
-Route         3   e 1.315                                  FS[13]
-LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i15 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
-Route         3   e 1.315                                  FS[15]
-LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i16 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
-Route         3   e 1.315                                  FS[16]
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-Warning: 8.319 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n26                                     |       8|      84|     27.54%
-                                        |        |        |
-n1997                                   |       1|      36|     11.80%
-                                        |        |        |
-n1996                                   |       1|      35|     11.48%
-                                        |        |        |
-n1995                                   |       1|      33|     10.82%
-                                        |        |        |
-n10                                     |       5|      32|     10.49%
-                                        |        |        |
-n1998                                   |       1|      32|     10.49%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 305  Score: 1313492
-
-Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
-
-
-Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes
-CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
deleted file mode 100644
index 22e783c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
+++ /dev/null
@@ -1,362 +0,0 @@
-
-Lattice Synthesis Timing Report
-
-
-
    Lattice Synthesis Timing Report
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Tue Aug 15 05:03:23 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 119 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i1 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i1 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
-Route         1   e 0.941                                  Bank[1]
-LUT4        ---     0.493              D to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.418ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      9.633ns data_path Bank_i4 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
-
- Path Details: Bank_i4 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
-Route         1   e 0.941                                  Bank[4]
-LUT4        ---     0.493              C to Z              i8_4_lut
-Route         2   e 1.141                                  n22
-LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
-Route         7   e 1.502                                  n2369
-LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 7.256ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
-
-   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
-
- Constraint Details:
-
-      9.471ns data_path Bank_i3 to CmdEnable_405 violates
-      2.500ns delay constraint less
-      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
-
- Path Details: Bank_i3 to CmdEnable_405
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
-Route         1   e 0.941                                  Bank[3]
-LUT4        ---     0.493              B to Z              i1989_2_lut
-Route         1   e 0.941                                  n2287
-LUT4        ---     0.493              C to Z              i12_4_lut
-Route         8   e 1.540                                  n26
-LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
-Route         1   e 0.941                                  n2362
-LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
-Route         3   e 1.258                                  C1Submitted_N_237
-LUT4        ---     0.493              C to Z              i34_4_lut
-Route         1   e 0.941                                  PHI2_N_120_enable_1
-                  --------
-                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
-
-Warning: 9.918 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            498 items scored, 186 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i13 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
-Route         3   e 1.315                                  FS[13]
-LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i15 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
-Route         3   e 1.315                                  FS[15]
-LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-
-Error:  The following path violates requirements by 3.319ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
-   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
-
-   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
-
- Constraint Details:
-
-      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
-      5.000ns delay constraint less
-      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
-
- Path Details: FS_610__i16 to nUFMCS_415
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
-Route         3   e 1.315                                  FS[16]
-LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
-Route         5   e 1.405                                  n10
-LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
-Route         2   e 1.141                                  n2368
-LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
-Route         1   e 0.941                                  n64
-LUT4        ---     0.493              B to Z              i1448_4_lut
-Route         1   e 0.941                                  nUFMCS_N_199
-                  --------
-                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
-
-Warning: 8.319 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n26                                     |       8|      84|     27.54%
-                                        |        |        |
-n1997                                   |       1|      36|     11.80%
-                                        |        |        |
-n1996                                   |       1|      35|     11.48%
-                                        |        |        |
-n1995                                   |       1|      33|     10.82%
-                                        |        |        |
-n10                                     |       5|      32|     10.49%
-                                        |        |        |
-n1998                                   |       1|      32|     10.49%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 305  Score: 1313492
-
-Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
-
-
-Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes
-CPU_TIME_REPORT: 0 secs 
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diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v
deleted file mode 100644
index c5879ca..0000000
--- a/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v
+++ /dev/null
@@ -1,802 +0,0 @@
-// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
-// Netlist written on Tue Aug 15 05:03:23 2023
-//
-// Verilog Description of module RAM2GS
-//
-
-module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
-            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
-            nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14])
-    input PHI2;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
-    input [9:0]MAin;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    input [1:0]CROW;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
-    input [7:0]Din;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    output [7:0]Dout;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    input nCCAS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
-    input nCRAS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
-    input nFWE;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12])
-    output LED;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12])
-    output [1:0]RBA;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
-    output [11:0]RA;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    inout [7:0]RD;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    output nRCS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17])
-    input RCLK;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
-    output RCKE;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17])
-    output nRWE;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49])
-    output nRRAS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28])
-    output nRCAS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39])
-    output RDQMH;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21])
-    output RDQML;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14])
-    output nUFMCS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19])
-    output UFMCLK;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19])
-    output UFMSDI;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19])
-    input UFMSDO;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14])
-    
-    wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
-    wire nCCAS_c /* synthesis is_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
-    wire nCRAS_c /* synthesis is_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
-    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
-    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13])
-    wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
-    
-    wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, 
-        RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, 
-        Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, 
-        Din_c_0;
-    wire [7:0]Bank;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16])
-    
-    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
-        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
-        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
-        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0;
-    wire [9:0]RowA;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16])
-    
-    wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, 
-        RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c;
-    wire [7:0]WRD;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15])
-    
-    wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, 
-        CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, 
-        CmdUFMCS, InitReady, Ready, n10;
-    wire [17:0]FS;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15])
-    
-    wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, 
-        n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, 
-        nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, 
-        n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, 
-        nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, 
-        n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, 
-        nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, 
-        nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, 
-        CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, 
-        n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, 
-        RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, 
-        UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, 
-        n1999, n2287, n726, n727, n728, n729, n730, n732, n733, 
-        n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, 
-        PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, 
-        PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, 
-        Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, 
-        n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, 
-        RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, 
-        n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, 
-        RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, 
-        n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, 
-        Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, 
-        Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, 
-        n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64;
-    
-    VHI i2 (.Z(VCC_net));
-    INV i2046 (.A(PHI2_c), .Z(PHI2_N_120));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
-    FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam PHI2r2_377.GSR = "ENABLED";
-    LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), 
-         .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7])
-    defparam nRCAS_I_43_4_lut.init = 16'h3afa;
-    LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), 
-         .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
-    defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e;
-    LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), 
-         .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
-    defparam nRWE_I_0_455_4_lut.init = 16'hcfc5;
-    FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam PHI2r3_378.GSR = "ENABLED";
-    FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam RASr_379.GSR = "ENABLED";
-    FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam RASr2_380.GSR = "ENABLED";
-    FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam RASr3_381.GSR = "ENABLED";
-    FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam CASr_382.GSR = "ENABLED";
-    FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam CASr2_383.GSR = "ENABLED";
-    FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam CASr3_384.GSR = "ENABLED";
-    FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam RA11_385.GSR = "ENABLED";
-    CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), 
-          .COUT(n1999), .S0(n82), .S1(n81));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_15.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_15.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_15.INJECT1_0 = "NO";
-    defparam FS_610_add_4_15.INJECT1_1 = "NO";
-    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i0.GSR = "ENABLED";
-    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i0.GSR = "ENABLED";
-    FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam FWEr_389.GSR = "ENABLED";
-    FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam CBR_390.GSR = "ENABLED";
-    FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5])
-    defparam RCKE_395.GSR = "ENABLED";
-    FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
-            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam nRCS_396.GSR = "ENABLED";
-    LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1477_2_lut.init = 16'heeee;
-    FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), 
-            .Q(nRowColSel));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam nRowColSel_402.GSR = "ENABLED";
-    CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), 
-          .COUT(n1998), .S0(n84), .S1(n83));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_13.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_13.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_13.INJECT1_0 = "NO";
-    defparam FS_610_add_4_13.INJECT1_1 = "NO";
-    LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam i2_2_lut.init = 16'h8888;
-    FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), 
-            .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam CmdEnable_405.GSR = "ENABLED";
-    LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), 
-         .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
-    defparam i4_4_lut.init = 16'h4000;
-    FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), 
-            .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam ADSubmitted_407.GSR = "ENABLED";
-    LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;
-    defparam i26_4_lut.init = 16'hc0ca;
-    LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), 
-         .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
-    defparam i1_2_lut_3_lut_4_lut.init = 16'h0020;
-    FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
-            .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam nRRAS_397.GSR = "ENABLED";
-    LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8])
-    defparam nRWE_I_50_1_lut.init = 16'h5555;
-    BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
-            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam nRCAS_398.GSR = "ENABLED";
-    FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), 
-            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam nRWE_399.GSR = "ENABLED";
-    FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam RA10_400.GSR = "ENABLED";
-    FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
-            .Q(RCKEEN));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam RCKEEN_401.GSR = "ENABLED";
-    FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i0.GSR = "ENABLED";
-    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RBA__i1.GSR = "ENABLED";
-    LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), 
-         .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ;
-    defparam i1_4_lut.init = 16'hc444;
-    LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
-    defparam i29_3_lut.init = 16'hcaca;
-    LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), 
-         .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7])
-    defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c;
-    LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1956_2_lut.init = 16'heeee;
-    FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(nRCS_N_139));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i0.GSR = "ENABLED";
-    CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), 
-          .COUT(n1996), .S0(n88), .S1(n87));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_9.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_9.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_9.INJECT1_0 = "NO";
-    defparam FS_610_add_4_9.INJECT1_1 = "NO";
-    FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), 
-            .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam C1Submitted_406.GSR = "ENABLED";
-    FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), 
-            .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
-    defparam nUFMCS_415.GSR = "ENABLED";
-    LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), 
-         .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ;
-    defparam i2_4_lut.init = 16'h8088;
-    FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam S_FSM_i1.GSR = "ENABLED";
-    CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), 
-          .COUT(n1995), .S0(n90), .S1(n89));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_7.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_7.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_7.INJECT1_0 = "NO";
-    defparam FS_610_add_4_7.INJECT1_1 = "NO";
-    LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ;
-    defparam i1_2_lut.init = 16'h2222;
-    LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), 
-         .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
-    defparam i1_2_lut_rep_15_4_lut.init = 16'h0008;
-    CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), 
-          .COUT(n1993), .S0(n94), .S1(n93));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_3.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_3.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_3.INJECT1_0 = "NO";
-    defparam FS_610_add_4_3.INJECT1_1 = "NO";
-    LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51])
-    defparam RA11_I_54_3_lut.init = 16'hc6c6;
-    LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
-    defparam i9_2_lut_3_lut.init = 16'h1f1f;
-    LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1491_2_lut_rep_30.init = 16'heeee;
-    LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), 
-         .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ;
-    defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10;
-    FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), 
-            .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
-    defparam UFMCLK_416.GSR = "ENABLED";
-    LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
-         .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca;
-    LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), 
-         .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
-    defparam i3_4_lut.init = 16'h0800;
-    LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), 
-         .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
-    defparam i1_2_lut_rep_21_3_lut.init = 16'h2020;
-    LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
-         .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca;
-    LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
-         .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca;
-    LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
-         .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca;
-    LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
-         .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca;
-    CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), 
-          .S1(n95));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_1.INIT0 = 16'hF000;
-    defparam FS_610_add_4_1.INIT1 = 16'h0555;
-    defparam FS_610_add_4_1.INJECT1_0 = "NO";
-    defparam FS_610_add_4_1.INJECT1_1 = "NO";
-    LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
-         .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca;
-    FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam PHI2r_376.GSR = "ENABLED";
-    LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), 
-         .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
-    defparam i1962_4_lut.init = 16'hfefa;
-    LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8])
-    defparam i1423_2_lut.init = 16'hdddd;
-    LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
-         .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca;
-    FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam S_FSM_i3.GSR = "ENABLED";
-    FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam S_FSM_i4.GSR = "ENABLED";
-    LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), 
-         .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
-    defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200;
-    LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), 
-         .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
-    defparam MAin_c_0_bdd_4_lut.init = 16'h0200;
-    FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), 
-            .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
-    defparam UFMSDI_417.GSR = "ENABLED";
-    LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
-         .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca;
-    LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
-         .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca;
-    LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), 
-         .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6])
-    defparam i1448_4_lut.init = 16'h3fbb;
-    LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), 
-         .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
-    defparam i2_3_lut_rep_18_4_lut.init = 16'h1000;
-    LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), 
-         .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
-    defparam i3_4_lut_adj_2.init = 16'hbfff;
-    LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
-         .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
-    defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca;
-    LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46])
-    defparam i1416_2_lut.init = 16'hbbbb;
-    LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
-    defparam i2001_2_lut.init = 16'h7777;
-    LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), 
-         .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
-    defparam i2_3_lut_4_lut.init = 16'h4000;
-    LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), 
-         .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
-    defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001;
-    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i0.GSR = "ENABLED";
-    LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), 
-         .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7])
-    defparam i1427_4_lut.init = 16'hfcdd;
-    LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), 
-         .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
-    defparam i3_3_lut_4_lut.init = 16'h0002;
-    LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i1_2_lut_adj_3.init = 16'h8888;
-    LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam i1119_1_lut.init = 16'h5555;
-    LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), 
-         .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
-    defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd;
-    LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ;
-    defparam i11_3_lut_rep_20.init = 16'h8080;
-    LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), 
-         .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
-    defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f;
-    GSR GSR_INST (.GSR(VCC_net));
-    LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
-    defparam i1_4_lut_adj_4.init = 16'h2000;
-    LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i6_4_lut.init = 16'h8000;
-    LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), 
-         .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i8_4_lut.init = 16'h8000;
-    LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), 
-         .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
-    defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff;
-    LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i5_4_lut.init = 16'h8000;
-    LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), 
-         .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
-    defparam i12_4_lut.init = 16'hbfff;
-    LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), 
-         .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
-    defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf;
-    LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam i637_1_lut_rep_31.init = 16'h5555;
-    LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), 
-         .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
-    defparam i1573_4_lut.init = 16'hcac0;
-    LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), 
-         .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i3_4_lut_adj_7.init = 16'hfffe;
-    LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7])
-    defparam i786_2_lut.init = 16'heeee;
-    LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
-    defparam i1_4_lut_adj_8.init = 16'h0002;
-    LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), 
-         .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb;
-    LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), 
-         .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd;
-    CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), 
-          .COUT(n1997), .S0(n86), .S1(n85));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_11.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_11.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_11.INJECT1_0 = "NO";
-    defparam FS_610_add_4_11.INJECT1_1 = "NO";
-    LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
-    defparam i1603_3_lut.init = 16'hcaca;
-    LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), 
-         .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i1979_4_lut.init = 16'h8000;
-    FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(Ready_N_296));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i15.GSR = "ENABLED";
-    LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd;
-    LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), 
-         .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
-    defparam i6_4_lut_adj_9.init = 16'hfffe;
-    LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), 
-         .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15])
-    defparam i1970_4_lut.init = 16'h3a0a;
-    LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam i1_2_lut_2_lut.init = 16'hdddd;
-    PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4));
-    FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n726));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i14.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n727));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i13.GSR = "ENABLED";
-    LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ;
-    defparam i1989_2_lut.init = 16'h8888;
-    LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
-         .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
-    defparam i2_3_lut_rep_32.init = 16'h8080;
-    LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
-         .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
-    defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f;
-    FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n728));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i12.GSR = "ENABLED";
-    FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), 
-            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam XOR8MEG_408.GSR = "ENABLED";
-    FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), 
-            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
-    defparam n8MEGEN_418.GSR = "ENABLED";
-    CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), 
-          .S0(n78));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_19.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_19.INIT1 = 16'h0000;
-    defparam FS_610_add_4_19.INJECT1_0 = "NO";
-    defparam FS_610_add_4_19.INJECT1_1 = "NO";
-    FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), 
-            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
-    defparam LEDEN_419.GSR = "ENABLED";
-    FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam Ready_404.GSR = "ENABLED";
-    FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), 
-            .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam CmdUFMCLK_413.GSR = "ENABLED";
-    FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), 
-            .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam CmdUFMSDI_414.GSR = "ENABLED";
-    FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), 
-            .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam Cmdn8MEGEN_410.GSR = "ENABLED";
-    FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), 
-            .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam CmdSubmitted_411.GSR = "ENABLED";
-    FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), 
-            .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
-    defparam CmdUFMCS_412.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n729));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i11.GSR = "ENABLED";
-    LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), 
-         .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
-    defparam i2008_2_lut_4_lut.init = 16'h0080;
-    LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17])
-    defparam i1404_4_lut.init = 16'hcfc8;
-    LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam i1118_1_lut.init = 16'h5555;
-    FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n730));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i10.GSR = "ENABLED";
-    LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
-    defparam i1_2_lut_adj_10.init = 16'h2222;
-    LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam i1439_2_lut.init = 16'heeee;
-    FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(nRWE_N_177));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i9.GSR = "ENABLED";
-    LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
-    defparam i1432_4_lut.init = 16'h3032;
-    LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ;
-    defparam i1_2_lut_rep_33.init = 16'h8888;
-    LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), 
-         .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31])
-    defparam i1_4_lut_4_lut.init = 16'h5540;
-    LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i4_2_lut.init = 16'heeee;
-    LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), 
-         .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
-    defparam i1589_4_lut.init = 16'hcac0;
-    LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ;
-    defparam i2_1_lut_rep_24.init = 16'h5555;
-    LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), 
-         .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
-    defparam i2_3_lut_4_lut_adj_11.init = 16'h0008;
-    FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n732));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i8.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n733));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i7.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n734));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i6.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n735));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i5.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n736));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i4.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n737));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i3.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(n738));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i2.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), 
-            .Q(nRCAS_N_165));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
-    defparam IS_FSM__i1.GSR = "ENABLED";
-    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RBA__i2.GSR = "ENABLED";
-    FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i17.GSR = "ENABLED";
-    FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i16.GSR = "ENABLED";
-    FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i15.GSR = "ENABLED";
-    FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i14.GSR = "ENABLED";
-    FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i13.GSR = "ENABLED";
-    FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i12.GSR = "ENABLED";
-    FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i11.GSR = "ENABLED";
-    FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i10.GSR = "ENABLED";
-    FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i9.GSR = "ENABLED";
-    FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i8.GSR = "ENABLED";
-    FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i7.GSR = "ENABLED";
-    FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i6.GSR = "ENABLED";
-    FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i5.GSR = "ENABLED";
-    FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i4.GSR = "ENABLED";
-    FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i3.GSR = "ENABLED";
-    FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i2.GSR = "ENABLED";
-    FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610__i1.GSR = "ENABLED";
-    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i7.GSR = "ENABLED";
-    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i6.GSR = "ENABLED";
-    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i5.GSR = "ENABLED";
-    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i4.GSR = "ENABLED";
-    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i3.GSR = "ENABLED";
-    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i2.GSR = "ENABLED";
-    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
-    defparam WRD_i1.GSR = "ENABLED";
-    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i9.GSR = "ENABLED";
-    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i8.GSR = "ENABLED";
-    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i7.GSR = "ENABLED";
-    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i6.GSR = "ENABLED";
-    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i5.GSR = "ENABLED";
-    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i4.GSR = "ENABLED";
-    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i3.GSR = "ENABLED";
-    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i2.GSR = "ENABLED";
-    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam RowA_i1.GSR = "ENABLED";
-    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i7.GSR = "ENABLED";
-    LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
-    defparam i2_3_lut_3_lut.init = 16'h4040;
-    LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31])
-    defparam i1_2_lut_3_lut.init = 16'h1010;
-    LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46])
-    defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555;
-    LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), 
-         .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46])
-    defparam i1_4_lut_4_lut_adj_12.init = 16'hff40;
-    LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), 
-         .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
-    defparam i1_4_lut_adj_13.init = 16'h0004;
-    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i6.GSR = "ENABLED";
-    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i5.GSR = "ENABLED";
-    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i4.GSR = "ENABLED";
-    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i3.GSR = "ENABLED";
-    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i2.GSR = "ENABLED";
-    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
-    defparam Bank_i1.GSR = "ENABLED";
-    CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), 
-          .COUT(n1994), .S0(n92), .S1(n91));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_5.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_5.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_5.INJECT1_0 = "NO";
-    defparam FS_610_add_4_5.INJECT1_1 = "NO";
-    BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), 
-         .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
-    defparam i2_3_lut_4_lut_adj_14.init = 16'h2000;
-    BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
-         .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31])
-    defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe;
-    BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
-    OB Dout_pad_7 (.I(Dout_c), .O(Dout[7]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_6 (.I(Dout_0), .O(Dout[6]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_5 (.I(Dout_1), .O(Dout[5]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_4 (.I(Dout_2), .O(Dout[4]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_3 (.I(Dout_3), .O(Dout[3]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_2 (.I(Dout_4), .O(Dout[2]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_1 (.I(Dout_5), .O(Dout[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB Dout_pad_0 (.I(Dout_6), .O(Dout[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
-    OB LED_pad (.I(LED_c), .O(LED));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12])
-    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
-    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
-    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_10 (.I(RA_0), .O(RA[10]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_9 (.I(RA_1_9), .O(RA[9]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_8 (.I(RA_1_8), .O(RA[8]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_7 (.I(RA_1_7), .O(RA[7]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_6 (.I(RA_1_6), .O(RA[6]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_5 (.I(RA_1_5), .O(RA[5]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_4 (.I(RA_1_4), .O(RA[4]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_3 (.I(RA_1_3), .O(RA[3]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_2 (.I(RA_1_2), .O(RA[2]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_1 (.I(RA_1_1), .O(RA[1]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB RA_pad_0 (.I(RA_1_0), .O(RA[0]));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
-    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17])
-    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17])
-    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49])
-    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28])
-    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39])
-    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21])
-    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14])
-    OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19])
-    OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19])
-    OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19])
-    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
-    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
-    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
-    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
-    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
-    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
-    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
-    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12])
-    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
-    IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14])
-    CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-          .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), 
-          .COUT(n2000), .S0(n80), .S1(n79));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam FS_610_add_4_17.INIT0 = 16'hfaaa;
-    defparam FS_610_add_4_17.INIT1 = 16'hfaaa;
-    defparam FS_610_add_4_17.INJECT1_0 = "NO";
-    defparam FS_610_add_4_17.INJECT1_1 = "NO";
-    LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ;
-    defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd;
-    LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ;
-    defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf;
-    LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23])
-    defparam i2010_3_lut_3_lut.init = 16'hfbfb;
-    LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ;
-    defparam i5_3_lut.init = 16'hfefe;
-    LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), 
-         .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
-    defparam i4_4_lut_adj_16.init = 16'hfffe;
-    LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i4_4_lut_adj_17.init = 16'h0002;
-    LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), 
-         .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;
-    defparam i34_4_lut.init = 16'hc0c5;
-    LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;
-    defparam i13_3_lut.init = 16'hc5c5;
-    LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), 
-         .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
-    defparam i1_2_lut_4_lut.init = 16'hfffe;
-    LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), 
-         .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
-    defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa;
-    LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), 
-         .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
-    defparam i3_4_lut_adj_18.init = 16'h1000;
-    LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1930_2_lut.init = 16'heeee;
-    LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), 
-         .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ;
-    defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0;
-    LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i1_2_lut_adj_19.init = 16'h8888;
-    LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), 
-         .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i2_4_lut_adj_20.init = 16'h1404;
-    LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1417_2_lut.init = 16'heeee;
-    LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), 
-         .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
-    defparam i2_4_lut_adj_21.init = 16'h0004;
-    LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), 
-         .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
-    defparam i3_4_lut_adj_22.init = 16'h0800;
-    LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ;
-    defparam i1_2_lut_adj_23.init = 16'hbbbb;
-    FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), 
-            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5])
-    defparam InitReady_394.GSR = "ENABLED";
-    LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), 
-         .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
-    defparam nRCS_I_0_448_3_lut.init = 16'hcaca;
-    LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), 
-         .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef;
-    LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe;
-    LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), 
-         .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam i2_3_lut_4_lut_adj_24.init = 16'h1000;
-    LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
-    defparam i3_2_lut_rep_26.init = 16'heeee;
-    LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
-    defparam i1_2_lut_rep_27.init = 16'heeee;
-    LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47])
-    defparam i2_3_lut_rep_28.init = 16'h2020;
-    INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
-    FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
-    defparam S_FSM_i2.GSR = "ENABLED";
-    INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3));   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
-    VLO i1 (.Z(GND_net));
-    TSALL TSALL_INST (.TSALL(GND_net));
-    PUR PUR_INST (.PUR(VCC_net));
-    defparam PUR_INST.RST_PULSE = 1;
-    LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), 
-         .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ;   // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47])
-    defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff;
-    LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1_2_lut_rep_29.init = 16'heeee;
-    LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
-    defparam m1_lut.init = 16'hffff;
-    LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), 
-         .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ;
-    defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04;
-    
-endmodule
-//
-// Verilog Description of module TSALL
-// module not written out since it is a black-box. 
-//
-
-//
-// Verilog Description of module PUR
-// module not written out since it is a black-box. 
-//
-
diff --git a/CPLD/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC/impl1/automake.log
index 574ca7b..db8f14d 100644
--- a/CPLD/LCMXO2-640HC/impl1/automake.log
+++ b/CPLD/LCMXO2-640HC/impl1/automake.log
@@ -1,5 +1,1266 @@
 
-map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial  -ioreg b "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf"  -c 0           
+synpwrap -msg -prj "LCMXO2_640HC_impl1_synplify.tcl" -log "LCMXO2_640HC_impl1.srf"
+Copyright (C) 1992-2020 Lattice Semiconductor Corporation. All rights reserved.
+Lattice Diamond Version 3.12.1.454
+    
+
+==contents of LCMXO2_640HC_impl1.srf
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEPC
+
+# Wed Aug 16 20:59:29 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:59:29 2023
+
+###########################################################]
+
+@A: multi_srs_gen output is up to date. No run necessary.
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+@R:"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr"
+Premap Report
+
+# Wed Aug 16 20:59:30 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+
+Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Aug 16 20:59:32 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Aug 16 20:59:32 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+Timing driven replication report
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
+
+   4		0h:00m:01s		    -1.83ns		 210 /       109
+
+
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
+
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
+
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N: MT615 |Found clock RCLK with period 16.00ns 
+@N: MT615 |Found clock PHI2 with period 350.00ns 
+@N: MT615 |Found clock nCRAS with period 350.00ns 
+@N: MT615 |Found clock nCCAS with period 350.00ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Wed Aug 16 20:59:35 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    2.9 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: -1.832
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
+nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
+@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         0.528
+
+    - Propagation time:                      2.361
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     -1.832
+
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
+    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+               Starting                                         Arrival           
+Instance       Reference     Type        Pin     Net            Time        Slack 
+               Clock                                                              
+----------------------------------------------------------------------------------
+Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
+LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
+n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
+==================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required           
+Instance       Reference     Type         Pin     Net            Time         Slack 
+               Clock                                                                
+------------------------------------------------------------------------------------
+RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
+RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
+RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
+RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
+RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
+RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
+RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
+RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
+RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
+RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
+====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[0] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[0]          Net          -        -       -         -           1         
+RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[9] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
+RowAd_0[9]         Net          -        -       -         -           1         
+RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
+=================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[8] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[8]         Net          -        -       -         -           1         
+RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RBA_0io[1] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RBAd[1]            ORCALUT4     B        In      0.000     1.256 r     -         
+RBAd[1]            ORCALUT4     Z        Out     0.617     1.873 r     -         
+RBAd_0[1]          Net          -        -       -         -           1         
+RBA_0io[1]         OFS1P3DX     D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      1.873
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -0.784
+
+    Number of logic level(s):                1
+    Starting point:                          Ready_fast / Q
+    Ending point:                            RowA[6] / D
+    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
+Ready_fast         Net          -        -       -         -           14        
+RowAd[6]           ORCALUT4     B        In      0.000     1.256 r     -         
+RowAd[6]           ORCALUT4     Z        Out     0.617     1.873 r     -         
+RowAd_0[6]         Net          -        -       -         -           1         
+RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: nCRAS
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required           
+Instance       Reference     Type         Pin     Net                Time         Slack 
+               Clock                                                                    
+----------------------------------------------------------------------------------------
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
+========================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
+========================================================================================
+
+
+Path information for path number 2: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.813
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.725
+
+    Number of logic level(s):                2
+    Starting point:                          CBR_fast / Q
+    Ending point:                            nRWE_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                         Pin      Pin               Arrival     No. of    
+Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------------
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
+nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
+========================================================================================
+
+
+Path information for path number 3: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRCAS_0io / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
+
+
+Path information for path number 4: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.781
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.693
+
+    Number of logic level(s):                2
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
+======================================================================================
+
+
+Path information for path number 5: 
+      Requested Period:                      1.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         1.089
+
+    - Propagation time:                      2.741
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 -1.653
+
+    Number of logic level(s):                2
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
+    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
+=================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 109 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
+FD1S3IX:        3
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            8
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       206
+PFUMX:          1
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
+
+###########################################################]
+
+
+Synthesis exit by 0.
+
+edif2ngd  -l "MachXO2" -d LCMXO2-640HC -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" -path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"   "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi" "LCMXO2_640HC_impl1.ngo"   
+edif2ngd:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Writing the design to LCMXO2_640HC_impl1.ngo...
+
+Total CPU Time: 0 secs  
+Total REAL Time: 0 secs  
+Peak Memory Usage: 11 MB
+
+
+ngdbuild  -a "MachXO2" -d LCMXO2-640HC  -p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data"  -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" -p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"  "LCMXO2_640HC_impl1.ngo" "LCMXO2_640HC_impl1.ngd"  	
+ngdbuild:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Reading 'LCMXO2_640HC_impl1.ngo' ...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+
+
+Running DRC...
+
+DRC complete with no errors or warnings
+
+Design Results:
+    403 blocks expanded
+Complete the first expansion.
+Writing 'LCMXO2_640HC_impl1.ngd' ...
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 19 MB
+
+
+map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial   "LCMXO2_640HC_impl1.ngd" -o "LCMXO2_640HC_impl1_map.ncd" -pr "LCMXO2_640HC_impl1.prf" -mp "LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"  -c 0           
 map:  version Diamond (64-bit) 3.12.1.454
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
@@ -7,7 +1268,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-   Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
+   Process the file: LCMXO2_640HC_impl1.ngd
    Picdevice="LCMXO2-640HC"
 
    Pictype="TQFP100"
@@ -31,32 +1292,27 @@ Optimizing...
 
 1 CCU2 constant inputs absorbed.
 
-    
-    
-    
-    
-    
-    
+    
 
 
 
 Design Summary:
-   Number of registers:     93 out of   877 (11%)
-      PFU registers:           64 out of   640 (10%)
-      PIO registers:           29 out of   237 (12%)
-   Number of SLICEs:        81 out of   320 (25%)
-      SLICEs as Logic/ROM:     81 out of   320 (25%)
+   Number of registers:    109 out of   877 (12%)
+      PFU registers:           84 out of   640 (13%)
+      PIO registers:           25 out of   237 (11%)
+   Number of SLICEs:       117 out of   320 (37%)
+      SLICEs as Logic/ROM:    117 out of   320 (37%)
       SLICEs as RAM:            0 out of   240 (0%)
       SLICEs as Carry:         10 out of   320 (3%)
-   Number of LUT4s:        159 out of   640 (25%)
-      Number used as logic LUTs:        139
+   Number of LUT4s:        230 out of   640 (36%)
+      Number used as logic LUTs:        210
       Number used as distributed RAM:     0
       Number used as ripple logic:       20
       Number used as shift registers:     0
-   Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
+   Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
    Number of block RAMs:  0 out of 2 (0%)
    Number of GSRs:        0 out of 1 (0%)
-   EFB used :        No
+   EFB used :        Yes
    JTAG used :       No
    Readback used :   No
    Oscillator used : No
@@ -70,63 +1326,67 @@ Design Summary:
    Notes:-
       1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
       2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
-   Number of clocks:  4
-     Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
+   Number of clocks:  5
+     Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
+     Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
+     Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
+     Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
      Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
-   Number of Clock Enables:  6
+   Number of Clock Enables:  7
+     Net N_245_i: 1 loads, 1 LSLICEs
+     Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
+     Net InitReady: 1 loads, 1 LSLICEs
+     Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
+     Net N_18: 2 loads, 2 LSLICEs
      Net XOR8MEG18: 3 loads, 3 LSLICEs
-     Net i2_i: 1 loads, 0 LSLICEs
-     Net N_26: 1 loads, 1 LSLICEs
-     Net N_28: 1 loads, 1 LSLICEs
-     Net N_188_i: 2 loads, 2 LSLICEs
-     Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
-   Number of LSRs:  3
+     Net N_193_i: 2 loads, 2 LSLICEs
+   Number of LSRs:  5
      Net RA10s_i: 1 loads, 0 LSLICEs
+     Net wb_clk23: 3 loads, 3 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
      Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
      Net RASr2: 2 loads, 2 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net InitReady: 17 loads
+     Net InitReady: 42 loads
+     Net FS[12]: 27 loads
+     Net FS[10]: 25 loads
+     Net FS[11]: 22 loads
+     Net FS[7]: 17 loads
+     Net FS[6]: 16 loads
      Net Ready: 15 loads
      Net Ready_fast: 14 loads
-     Net Din_c[5]: 12 loads
      Net nRowColSel: 12 loads
      Net S[1]: 12 loads
-     Net RASr2: 10 loads
-     Net CO0: 9 loads
-     Net Din_c[3]: 9 loads
-     Net Din_c[4]: 9 loads
  
 
-   Number of warnings:  6
+   Number of warnings:  1
    Number of errors:    0
 
 
 
 Total CPU Time: 0 secs  
 Total REAL Time: 0 secs  
-Peak Memory Usage: 36 MB
+Peak Memory Usage: 37 MB
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Dumping design to file LCMXO2_640HC_impl1_map.ncd.
 
-mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
+mpartrce -p "LCMXO2_640HC_impl1.p2t" -f "LCMXO2_640HC_impl1.p3t" -tf "LCMXO2_640HC_impl1.pt" "LCMXO2_640HC_impl1_map.ncd" "LCMXO2_640HC_impl1.ncd"
 
 ---- MParTrce Tool ----
 Removing old design directory at request of -rem command line option to this program.
 Running par. Please wait . . .
 
-Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
-Tue Aug 15 23:30:05 2023
+Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
+Wed Aug 16 20:59:37 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
-Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
+Preference file: LCMXO2_640HC_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
 
-Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -142,46 +1402,48 @@ License checked out.
 Ignore Preference Error(s):  True
 Device utilization summary:
 
-   PIO (prelim)   67+4(JTAG)/80      89% used
-                  67+4(JTAG)/79      90% bonded
-   IOLOGIC           29/80           36% used
+   PIO (prelim)   63+4(JTAG)/80      84% used
+                  63+4(JTAG)/79      85% bonded
+   IOLOGIC           25/80           31% used
 
-   SLICE             81/320          25% used
+   SLICE            117/320          36% used
+
+   EFB                1/1           100% used
 
 
-
-Number of Signals: 292
-Number of Connections: 703
+Number of Signals: 380
+Number of Connections: 1008
 
 Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
+   63 out of 63 pins locked (100% locked).
 
-The following 2 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 18)
+The following 3 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 46)
+    PHI2_c (driver: PHI2, clk load #: 19)
+    nCRAS_c (driver: nCRAS, clk load #: 10)
 
     
     
+    
 
 The following 2 signals are selected to use the secondary clock routing resources:
-    nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
     nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
+    un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
 
-    
     
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
-...........
+..............
 Finished Placer Phase 0.  REAL time: 0 secs 
 
 Starting Placer Phase 1.
-....................
-Placer score = 41844.
+...................
+Placer score = 55012.
 Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  41803
+Placer score =  54994
 Finished Placer Phase 2.  REAL time: 4 secs 
 
 
@@ -194,21 +1456,22 @@ Global Clock Resources:
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 18
-  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
+  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
   SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
+  SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
 
-  PRIMARY  : 2 out of 8 (25%)
+  PRIMARY  : 3 out of 8 (37%)
   SECONDARY: 2 out of 8 (25%)
 
 --------------- End of Clock Report ---------------
 
 
 I/O Usage Summary (final):
-   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
-   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
+   63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
+   63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
+   Number of PIO comps: 63; differential: 0.
    Number of Vref pins used: 0.
 
 I/O Bank Usage Summary:
@@ -217,21 +1480,24 @@ I/O Bank Usage Summary:
 +----------+----------------+------------+-----------+
 | 0        | 13 / 19 ( 68%) | 3.3V       | -         |
 | 1        | 20 / 20 (100%) | 3.3V       | -         |
-| 2        | 16 / 20 ( 80%) | 3.3V       | -         |
+| 2        | 12 / 20 ( 60%) | 3.3V       | -         |
 | 3        | 18 / 20 ( 90%) | 3.3V       | -         |
 +----------+----------------+------------+-----------+
 
 Total placer CPU time: 3 secs 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 703 unrouted.
+0 connections routed; 1008 unrouted.
 Starting router resource preassignment
     
+    
 
-Completed router resource preassignment. Real time: 6 secs 
+    
 
-Start NBR router at 23:30:11 08/15/23
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 20:59:43 08/16/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -246,41 +1512,54 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 23:30:11 08/15/23
+Start NBR special constraint process at 20:59:43 08/16/23
 
-Start NBR section for initial routing at 23:30:11 08/15/23
+Start NBR section for initial routing at 20:59:43 08/16/23
 Level 1, iteration 1
-0(0.00%) conflict; 529(75.25%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.016ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 2, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.772ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 3, iteration 1
-0(0.00%) conflict; 526(74.82%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 6.058ns/0.000ns; real time: 6 secs 
+0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
-3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
+7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 23:30:11 08/15/23
+Start NBR section for normal routing at 20:59:43 08/16/23
+Level 1, iteration 1
+0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 1
 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 6 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:30:11 08/15/23
-
-Start NBR section for re-routing at 23:30:11 08/15/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
+Level 4, iteration 0
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 5.827ns/0.000ns; real time: 6 secs 
+Estimated worst slack/total negative slack: 0.083ns/0.000ns; real time: 6 secs 
+Level 4, iteration 0
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.902ns/0.000ns; real time: 6 secs 
 
-Start NBR section for post-routing at 23:30:11 08/15/23
+Start NBR section for re-routing at 20:59:44 08/16/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack: 4.922ns/0.000ns; real time: 7 secs 
+
+Start NBR section for post-routing at 20:59:44 08/16/23
 
 End NBR router with 0 unrouted connection
 
@@ -288,35 +1567,37 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 5.827ns
+  Estimated worst slack : 4.922ns
   Timing score : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+    
+
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
 Completely routed.
-End of route.  703 routed (100.00%); 0 unrouted.
+End of route.  1008 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
 Timing score: 0 
 
-Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
 
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 5.827
+PAR_SUMMARY::Worst  slack> = 4.922
 PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.304
+PAR_SUMMARY::Worst  slack> = 0.088
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
 
 par done!
 
@@ -330,9 +1611,9 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 Exiting par with exit code 0
 Exiting mpartrce with exit code 0
 
-tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" 
+tmcheck -par "LCMXO2_640HC_impl1.par" 
 
-bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd"  -jedec "RAM2GS_LCMXO2_640HC_impl1.prf"
+bitgen -f "LCMXO2_640HC_impl1.t2b" -w "LCMXO2_640HC_impl1.ncd"  -jedec "LCMXO2_640HC_impl1.prf"
 
 
 BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
@@ -343,7 +1624,7 @@ Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 
-Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
 Design name: RAM2GS
 NCD version: 3.3
 Vendor:      LATTICE
@@ -356,7 +1637,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 
 Running DRC.
 DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+Reading Preference File from LCMXO2_640HC_impl1.prf.
 
 Preference Summary:
 +---------------------------------+---------------------------------+
@@ -404,7 +1685,7 @@ Creating bit map...
  
 Bitstream Status: Final           Version 1.95.
  
-Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+Saving bit stream in "LCMXO2_640HC_impl1.jed".
  
 ===========
 UFM Summary.
@@ -413,8 +1694,8 @@ UFM Size:        191 Pages (128*191 Bits).
 UFM Utilization: General Purpose Flash Memory.
  
 Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     0 Page.
+Initialized UFM Pages:                     1 Page (Page 190).
  
 Total CPU Time: 1 secs 
 Total REAL Time: 2 secs 
-Peak Memory Usage: 246 MB
+Peak Memory Usage: 245 MB
diff --git a/CPLD/LCMXO2-640HC/impl1/backup/LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/backup/LCMXO2_640HC_impl1.srr
new file mode 100644
index 0000000..0e31ecf
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/backup/LCMXO2_640HC_impl1.srr
@@ -0,0 +1,832 @@
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEPC
+
+# Wed Aug 16 20:35:19 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+Verilog syntax check successful!
+Selecting top level module RAM2GS
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI7 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI6 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI5 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI4 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI3 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI2 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI1 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0DATI0 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL0ACKI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI7 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI6 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI5 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI4 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI3 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI2 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI1 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1DATI0 on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input PLL1ACKI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input I2C1SCLI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input I2C1SDAI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input I2C2SCLI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input I2C2SDAI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input SPISCKI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input SPIMISOI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input SPIMOSII on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input SPISCSN on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input TCCLKI on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input TCRSTN on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input TCIC on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+@W: CG781 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":71:8:71:13|Input UFMSN on instance ufmefb is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
+Running optimization stage 1 on RAM2GS .......
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
+Running optimization stage 2 on RAM2GS .......
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+
+For a summary of runtime and memory usage per design unit, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
+
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 96MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:35:19 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:35:20 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:35:20 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Aug 16 20:35:21 2023
+
+###########################################################]
+Premap Report
+
+# Wed Aug 16 20:35:21 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
+
+@A: MF827 |No constraint file specified.
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+@N: FX493 |Applying initial value "0" on instance InitReady.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance RCKE.
+@N: FX493 |Applying initial value "1" on instance nRCAS.
+@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
+@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRCS.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "0" on instance n8MEGEN.
+@N: FX493 |Applying initial value "1" on instance nRRAS.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
+@N: FX493 |Applying initial value "0" on instance C1Submitted.
+@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
+@N: FX493 |Applying initial value "0" on instance ADSubmitted.
+@N: FX493 |Applying initial value "0" on instance XOR8MEG.
+@N: FX493 |Applying initial value "0" on instance CmdEnable.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+
+
+Clock Summary
+******************
+
+          Start            Requested     Requested     Clock        Clock                   Clock
+Level     Clock            Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------
+0 -       System           100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                 
+0 -       RAM2GS|RCLK      100.0 MHz     10.000        inferred     Inferred_clkgroup_0     65   
+                                                                                                 
+0 -       RAM2GS|PHI2      100.0 MHz     10.000        inferred     Inferred_clkgroup_1     18   
+                                                                                                 
+0 -       RAM2GS|nCRAS     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     14   
+                                                                                                 
+0 -       RAM2GS|nCCAS     100.0 MHz     10.000        inferred     Inferred_clkgroup_3     8    
+=================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                 Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock            Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------------
+System           0         -               -               -                 -                 
+                                                                                               
+RAM2GS|RCLK      65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                               
+RAM2GS|PHI2      18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                               
+RAM2GS|nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                               
+RAM2GS|nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+===============================================================================================
+
+@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":178:4:178:9|Found inferred clock RAM2GS|RCLK which controls 65 sequential elements including nRWE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":319:4:319:9|Found inferred clock RAM2GS|PHI2 which controls 18 sequential elements including CmdEnable. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":136:4:136:9|Found inferred clock RAM2GS|nCRAS which controls 14 sequential elements including RowA[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":154:4:154:9|Found inferred clock RAM2GS|nCCAS which controls 8 sequential elements including WRD[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
+@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
+@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 172MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Aug 16 20:35:23 2023
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Aug 16 20:35:23 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEPC
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":178:4:178:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":165:4:165:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: FX493 |Applying initial value "0" on instance IS[0].
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance IS[1].
+@N: FX493 |Applying initial value "0" on instance IS[2].
+@N: FX493 |Applying initial value "0" on instance IS[3].
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     0.15ns		 204 /       105
+   2		0h:00m:01s		     0.15ns		 208 /       105
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 187MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@A: BN291 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":373:4:373:9|Boundary register wb_clk.fb (in view: work.RAM2GS(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":373:4:373:9|Boundary register wb_cyc_stb.fb (in view: work.RAM2GS(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":373:4:373:9|Boundary register wb_we.fb (in view: work.RAM2GS(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 186MB peak: 187MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 187MB)
+
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 193MB)
+
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":71:8:71:13|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock RAM2GS|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
+@W: MT420 |Found inferred clock RAM2GS|PHI2 with period 10.00ns. Please declare a user-defined clock on port PHI2.
+@W: MT420 |Found inferred clock RAM2GS|nCRAS with period 10.00ns. Please declare a user-defined clock on port nCRAS.
+@W: MT420 |Found inferred clock RAM2GS|nCCAS with period 10.00ns. Please declare a user-defined clock on port nCCAS.
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Wed Aug 16 20:35:26 2023
+#
+
+
+Top view:               RAM2GS
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 0.094
+
+                   Requested     Estimated      Requested     Estimated               Clock        Clock              
+Starting Clock     Frequency     Frequency      Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------
+RAM2GS|PHI2        100.0 MHz     101.9 MHz      10.000        9.812         0.094     inferred     Inferred_clkgroup_1
+RAM2GS|RCLK        100.0 MHz     118.6 MHz      10.000        8.433         1.567     inferred     Inferred_clkgroup_0
+RAM2GS|nCCAS       100.0 MHz     NA             10.000        NA            NA        inferred     Inferred_clkgroup_3
+RAM2GS|nCRAS       100.0 MHz     NA             10.000        NA            NA        inferred     Inferred_clkgroup_2
+System             100.0 MHz     1893.9 MHz     10.000        0.528         9.472     system       system_clkgroup    
+======================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                     |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-----------------------------------------------------------------------------------------------------------------
+Starting      Ending       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+-----------------------------------------------------------------------------------------------------------------
+System        RAM2GS|RCLK  |  10.000      9.472  |  No paths    -      |  No paths    -      |  No paths    -    
+RAM2GS|RCLK   System       |  10.000      8.892  |  No paths    -      |  No paths    -      |  No paths    -    
+RAM2GS|RCLK   RAM2GS|RCLK  |  10.000      1.567  |  No paths    -      |  No paths    -      |  No paths    -    
+RAM2GS|RCLK   RAM2GS|PHI2  |  Diff grp    -      |  No paths    -      |  Diff grp    -      |  No paths    -    
+RAM2GS|PHI2   RAM2GS|RCLK  |  No paths    -      |  No paths    -      |  No paths    -      |  Diff grp    -    
+RAM2GS|PHI2   RAM2GS|PHI2  |  No paths    -      |  10.000      6.099  |  5.000       0.094  |  5.000       3.428
+RAM2GS|nCRAS  RAM2GS|RCLK  |  No paths    -      |  No paths    -      |  No paths    -      |  Diff grp    -    
+=================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: RAM2GS|PHI2
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                Starting                                           Arrival          
+Instance        Reference       Type         Pin     Net           Time        Slack
+                Clock                                                               
+------------------------------------------------------------------------------------
+Bank_0io[7]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[7]       0.972       0.094
+Bank_0io[0]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[0]       0.972       1.111
+Bank_0io[1]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[1]       0.972       1.111
+Bank_0io[2]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[2]       0.972       1.111
+Bank_0io[3]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[3]       0.972       1.111
+Bank_0io[4]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[4]       0.972       1.111
+Bank_0io[5]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[5]       0.972       1.111
+Bank_0io[6]     RAM2GS|PHI2     IFS1P3DX     Q       Bank[6]       0.972       1.111
+XOR8MEG         RAM2GS|PHI2     FD1S3AX      Q       XOR8MEG       1.044       3.428
+CmdEnable       RAM2GS|PHI2     FD1S3AX      Q       CmdEnable     1.204       6.099
+====================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                 Starting                                                 Required          
+Instance         Reference       Type         Pin     Net                 Time         Slack
+                 Clock                                                                      
+--------------------------------------------------------------------------------------------
+ADSubmitted      RAM2GS|PHI2     FD1S3AX      D       ADSubmitted_r_0     5.089        0.094
+C1Submitted      RAM2GS|PHI2     FD1S3AX      D       C1Submitted_s_0     5.089        0.094
+CMDUFMWrite      RAM2GS|PHI2     FD1S3AX      D       CMDUFMWritee_0      5.089        0.166
+CmdEnable        RAM2GS|PHI2     FD1S3AX      D       CmdEnable_s         5.089        0.166
+CmdLEDEN         RAM2GS|PHI2     FD1S3AX      D       CmdLEDENe_0         5.089        0.166
+Cmdn8MEGEN       RAM2GS|PHI2     FD1S3AX      D       Cmdn8MEGENe_0       5.089        0.166
+CmdSubmitted     RAM2GS|PHI2     FD1S3AX      D       N_537_0             5.089        1.183
+CmdUFMData       RAM2GS|PHI2     FD1S3AX      D       CmdUFMDatae_0       5.089        1.183
+XOR8MEG          RAM2GS|PHI2     FD1S3AX      D       XOR8MEGe_0          5.089        1.183
+RA11_0io         RAM2GS|PHI2     OFS1P3IX     D       N_142_i_i           5.089        3.428
+============================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         5.089
+
+    - Propagation time:                      4.995
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     0.094
+
+    Number of logic level(s):                4
+    Starting point:                          Bank_0io[7] / Q
+    Ending point:                            ADSubmitted / D
+    The start point is clocked by            RAM2GS|PHI2 [rising] (rise=0.000 fall=5.000 period=10.000) on pin SCLK
+    The end   point is clocked by            RAM2GS|PHI2 [falling] (rise=0.000 fall=5.000 period=10.000) on pin CK
+
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+Bank_0io[7]              IFS1P3DX     Q        Out     0.972     0.972 r     -         
+Bank[7]                  Net          -        -       -         -           1         
+Bank_0io_RNINMO63[7]     ORCALUT4     A        In      0.000     0.972 r     -         
+Bank_0io_RNINMO63[7]     ORCALUT4     Z        Out     1.017     1.989 r     -         
+m9_e_6                   Net          -        -       -         -           1         
+Bank_0io_RNI5G0O3[2]     ORCALUT4     D        In      0.000     1.989 r     -         
+Bank_0io_RNI5G0O3[2]     ORCALUT4     Z        Out     1.301     3.289 f     -         
+un1_ADWR_i_o4_12         Net          -        -       -         -           14        
+MAin_pad_RNIJ1KC4[1]     ORCALUT4     C        In      0.000     3.289 f     -         
+MAin_pad_RNIJ1KC4[1]     ORCALUT4     Z        Out     1.089     4.378 r     -         
+N_209_i                  Net          -        -       -         -           2         
+ADSubmitted_r_0          ORCALUT4     B        In      0.000     4.378 r     -         
+ADSubmitted_r_0          ORCALUT4     Z        Out     0.617     4.995 f     -         
+ADSubmitted_r_0          Net          -        -       -         -           1         
+ADSubmitted              FD1S3AX      D        In      0.000     4.995 f     -         
+=======================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: RAM2GS|RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                          Arrival          
+Instance      Reference       Type        Pin     Net           Time        Slack
+              Clock                                                              
+---------------------------------------------------------------------------------
+FS[14]        RAM2GS|RCLK     FD1S3AX     Q       FS[14]        1.108       1.567
+FS[16]        RAM2GS|RCLK     FD1S3AX     Q       FS[16]        1.108       1.567
+FS[13]        RAM2GS|RCLK     FD1S3AX     Q       FS[13]        1.108       2.584
+FS[15]        RAM2GS|RCLK     FD1S3AX     Q       FS[15]        1.108       2.584
+FS[17]        RAM2GS|RCLK     FD1S3AX     Q       FS[17]        1.108       2.584
+FS[7]         RAM2GS|RCLK     FD1S3AX     Q       FS[7]         1.280       2.860
+FS[8]         RAM2GS|RCLK     FD1S3AX     Q       FS[8]         1.244       2.896
+FS[9]         RAM2GS|RCLK     FD1S3AX     Q       FS[9]         1.204       2.936
+InitReady     RAM2GS|RCLK     FD1S3AX     Q       InitReady     1.326       3.647
+FS[12]        RAM2GS|RCLK     FD1S3AX     Q       FS[12]        1.309       3.672
+=================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                              Required          
+Instance       Reference       Type        Pin     Net               Time         Slack
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      RAM2GS|RCLK     FD1P3AX     D       wb_adr_10[0]      10.089       1.567
+wb_dati[4]     RAM2GS|RCLK     FD1P3AX     D       wb_dati_10[4]     10.089       1.567
+wb_adr[4]      RAM2GS|RCLK     FD1P3AX     D       N_237             10.089       1.823
+wb_adr[5]      RAM2GS|RCLK     FD1P3AX     D       N_238             10.089       1.823
+wb_adr[6]      RAM2GS|RCLK     FD1P3AX     D       N_239             10.089       1.823
+wb_cyc_stb     RAM2GS|RCLK     FD1P3IX     D       wb_cyc_stb_65     10.089       1.823
+LEDEN          RAM2GS|RCLK     FD1P3AX     SP      N_18              9.528        2.481
+n8MEGEN        RAM2GS|RCLK     FD1P3AX     SP      N_18              9.528        2.481
+wb_dati[0]     RAM2GS|RCLK     FD1P3AX     D       wb_dati_10[0]     10.089       2.496
+wb_dati[3]     RAM2GS|RCLK     FD1P3AX     D       wb_dati_10[3]     10.089       2.496
+=======================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         10.089
+
+    - Propagation time:                      8.521
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 1.567
+
+    Number of logic level(s):                7
+    Starting point:                          FS[14] / Q
+    Ending point:                            wb_adr[0] / D
+    The start point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
+    The end   point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
+
+Instance / Net                       Pin      Pin               Arrival     No. of    
+Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+FS[14]                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+FS[14]                  Net          -        -       -         -           3         
+wb_clk_9_iv_i_o2_1      ORCALUT4     A        In      0.000     1.108 r     -         
+wb_clk_9_iv_i_o2_1      ORCALUT4     Z        Out     1.017     2.125 r     -         
+wb_clk_9_iv_i_o2_1      Net          -        -       -         -           1         
+wb_clk_9_iv_i_o2        ORCALUT4     D        In      0.000     2.125 r     -         
+wb_clk_9_iv_i_o2        ORCALUT4     Z        Out     1.281     3.405 r     -         
+wb_clk_9_iv_i_o2        Net          -        -       -         -           11        
+wb_adr_10_0_a2[0]       ORCALUT4     C        In      0.000     3.405 r     -         
+wb_adr_10_0_a2[0]       ORCALUT4     Z        Out     1.273     4.678 f     -         
+wb_adr_10_0_a2[0]       Net          -        -       -         -           9         
+wb_adr_10_0_a2_7[0]     ORCALUT4     C        In      0.000     4.678 f     -         
+wb_adr_10_0_a2_7[0]     ORCALUT4     Z        Out     1.193     5.871 f     -         
+wb_adr_10_0_a2_7[0]     Net          -        -       -         -           4         
+wb_adr_10_0_4_1[0]      ORCALUT4     D        In      0.000     5.871 f     -         
+wb_adr_10_0_4_1[0]      ORCALUT4     Z        Out     1.017     6.888 f     -         
+wb_adr_10_0_4_1[0]      Net          -        -       -         -           1         
+wb_adr_10_0_4[0]        ORCALUT4     D        In      0.000     6.888 f     -         
+wb_adr_10_0_4[0]        ORCALUT4     Z        Out     1.017     7.905 f     -         
+wb_adr_10_0_4[0]        Net          -        -       -         -           1         
+wb_adr_10_0[0]          ORCALUT4     C        In      0.000     7.905 f     -         
+wb_adr_10_0[0]          ORCALUT4     Z        Out     0.617     8.521 f     -         
+wb_adr_10[0]            Net          -        -       -         -           1         
+wb_adr[0]               FD1P3AX      D        In      0.000     8.521 f     -         
+======================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                          Arrival          
+Instance     Reference     Type     Pin         Net            Time        Slack
+             Clock                                                              
+--------------------------------------------------------------------------------
+ufmefb       System        EFB      WBDATO0     wb_dato[0]     0.000       9.472
+ufmefb       System        EFB      WBDATO1     wb_dato[1]     0.000       9.472
+================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required          
+Instance     Reference     Type        Pin     Net                Time         Slack
+             Clock                                                                  
+------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       10.089       9.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     10.089       9.472
+====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         10.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
+
+Instance / Net                  Pin         Pin               Arrival     No. of    
+Name               Type         Name        Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+ufmefb             EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]         Net          -           -       -         -           1         
+n8MEGEN_6_i_m2     ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2     ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2     Net          -           -       -         -           1         
+n8MEGEN            FD1P3AX      D           In      0.000     0.617 r     -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 105 of 640 (16%)
+PIC Latch:       0
+I/O cells:       63
+
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        22
+FD1P3IX:        3
+FD1S3AX:        42
+FD1S3IX:        3
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+IFS1P3IX:       10
+IFS1P3JX:       2
+INV:            8
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       8
+OFS1P3IX:       1
+OFS1P3JX:       1
+ORCALUT4:       215
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:35:26 2023
+
+###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr
deleted file mode 100644
index 0441a4c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/backup/RAM2GS_LCMXO2_640HC_impl1.srr
+++ /dev/null
@@ -1,911 +0,0 @@
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Tue Aug 15 22:17:22 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:17:22 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:17:22 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:17:23 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:17:24 2023
-
-###########################################################]
-Premap Report
-
-# Tue Aug 15 22:17:24 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB)
-
-@A: MF827 |No constraint file specified.
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start            Requested     Requested     Clock        Clock                   Clock
-Level     Clock            Frequency     Period        Type         Group                   Load 
--------------------------------------------------------------------------------------------------
-0 -       RAM2GS|RCLK      200.0 MHz     5.000         inferred     Inferred_clkgroup_0     48   
-                                                                                                 
-0 -       RAM2GS|PHI2      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     19   
-                                                                                                 
-0 -       RAM2GS|nCRAS     200.0 MHz     5.000         inferred     Inferred_clkgroup_2     14   
-                                                                                                 
-0 -       RAM2GS|nCCAS     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     8    
-=================================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-                 Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock            Load      Pin             Seq Example     Seq Example       Comb Example      
------------------------------------------------------------------------------------------------
-RAM2GS|RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                               
-RAM2GS|PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                               
-RAM2GS|nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                               
-RAM2GS|nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-===============================================================================================
-
-@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found inferred clock RAM2GS|RCLK which controls 48 sequential elements including nRWE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":288:1:288:6|Found inferred clock RAM2GS|PHI2 which controls 19 sequential elements including CmdEnable. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Found inferred clock RAM2GS|nCRAS which controls 14 sequential elements including RowA[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":123:1:123:6|Found inferred clock RAM2GS|nCCAS which controls 8 sequential elements including WRD[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 173MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 22:17:26 2023
-
-###########################################################]
-Map & Optimize Report
-
-# Tue Aug 15 22:17:26 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 129MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 167MB peak: 167MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.87ns		 132 /        89
-   2		0h:00m:01s		    -2.87ns		 142 /        89
-   3		0h:00m:01s		    -2.50ns		 140 /        89
-   4		0h:00m:01s		    -2.50ns		 139 /        89
-   5		0h:00m:01s		    -2.50ns		 139 /        89
-   6		0h:00m:01s		    -2.50ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":98:1:98:6|Replicating instance Bank[5] (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":98:1:98:6|Replicating instance Bank[7] (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
-Timing driven replication report
-Added 2 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   7		0h:00m:01s		    -1.81ns		 164 /        91
-   8		0h:00m:01s		    -1.74ns		 164 /        91
-   9		0h:00m:01s		    -1.71ns		 165 /        91
-  10		0h:00m:01s		    -1.37ns		 167 /        91
-  11		0h:00m:01s		    -2.03ns		 168 /        91
-
-  12		0h:00m:01s		    -1.83ns		 166 /        91
-  13		0h:00m:01s		    -2.00ns		 167 /        91
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 177MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 177MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 184MB)
-
-@W: MT420 |Found inferred clock RAM2GS|RCLK with period 5.00ns. Please declare a user-defined clock on port RCLK.
-@W: MT420 |Found inferred clock RAM2GS|PHI2 with period 5.00ns. Please declare a user-defined clock on port PHI2.
-@W: MT420 |Found inferred clock RAM2GS|nCRAS with period 5.00ns. Please declare a user-defined clock on port nCRAS.
-@W: MT420 |Found inferred clock RAM2GS|nCCAS with period 5.00ns. Please declare a user-defined clock on port nCCAS.
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 22:17:29 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    200.0 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.370
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock              
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
-----------------------------------------------------------------------------------------------------------------------
-RAM2GS|PHI2        200.0 MHz     102.7 MHz     5.000         9.740         -2.370     inferred     Inferred_clkgroup_1
-RAM2GS|RCLK        200.0 MHz     185.7 MHz     5.000         5.385         -0.385     inferred     Inferred_clkgroup_0
-RAM2GS|nCCAS       200.0 MHz     NA            5.000         NA            NA         inferred     Inferred_clkgroup_3
-RAM2GS|nCRAS       200.0 MHz     NA            5.000         NA            NA         inferred     Inferred_clkgroup_2
-======================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks                     |    rise  to  rise    |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------
-Starting      Ending       |  constraint  slack   |  constraint  slack   |  constraint  slack   |  constraint  slack
---------------------------------------------------------------------------------------------------------------------
-RAM2GS|RCLK   RAM2GS|RCLK  |  5.000       -0.385  |  No paths    -       |  No paths    -       |  No paths    -    
-RAM2GS|RCLK   RAM2GS|PHI2  |  Diff grp    -       |  No paths    -       |  Diff grp    -       |  No paths    -    
-RAM2GS|PHI2   RAM2GS|RCLK  |  No paths    -       |  No paths    -       |  No paths    -       |  Diff grp    -    
-RAM2GS|PHI2   RAM2GS|PHI2  |  No paths    -       |  5.000       -0.639  |  2.500       -2.370  |  2.500       0.864
-RAM2GS|nCRAS  RAM2GS|RCLK  |  No paths    -       |  No paths    -       |  No paths    -       |  Diff grp    -    
-====================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: RAM2GS|PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                     Starting                                              Arrival           
-Instance             Reference       Type         Pin     Net              Time        Slack 
-                     Clock                                                                   
----------------------------------------------------------------------------------------------
-Bank_fast_0io[5]     RAM2GS|PHI2     IFS1P3DX     Q       Bank_fast[5]     1.044       -2.370
-Bank_0io[2]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[2]          1.220       -1.457
-Bank_0io[6]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[6]          1.204       -1.441
-Bank_0io[0]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[0]          0.972       -1.429
-Bank_0io[1]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[1]          0.972       -1.429
-Bank_0io[3]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[3]          0.972       -1.429
-Bank_0io[4]          RAM2GS|PHI2     IFS1P3DX     Q       Bank[4]          0.972       -1.429
-Bank_fast_0io[7]     RAM2GS|PHI2     IFS1P3DX     Q       Bank_fast[7]     1.148       -1.385
-Bank[5]              RAM2GS|PHI2     FD1S3AX      Q       Bank[5]          1.148       -1.345
-Bank[7]              RAM2GS|PHI2     FD1S3AX      Q       Bank[7]          1.108       -1.305
-=============================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                              Required           
-Instance         Reference       Type        Pin     Net               Time         Slack 
-                 Clock                                                                    
-------------------------------------------------------------------------------------------
-CmdSubmitted     RAM2GS|PHI2     FD1S3AX     D       N_377_0           2.589        -2.370
-CmdLEDEN         RAM2GS|PHI2     FD1S3AX     D       CmdLEDENe_0       2.589        -1.429
-Cmdn8MEGEN       RAM2GS|PHI2     FD1S3AX     D       Cmdn8MEGENe_0     2.589        -1.429
-XOR8MEG          RAM2GS|PHI2     FD1S3AX     D       XOR8MEGe_0        2.589        -1.429
-ADSubmitted      RAM2GS|PHI2     FD1S3AX     D       ADSubmitted_r     2.589        -1.365
-C1Submitted      RAM2GS|PHI2     FD1S3AX     D       C1Submitted_s     2.589        -1.365
-CmdUFMCLK        RAM2GS|PHI2     FD1S3AX     D       CmdUFMCLKe_0      2.589        -1.365
-CmdUFMCS         RAM2GS|PHI2     FD1S3AX     D       CmdUFMCSe_0       2.589        -1.365
-CmdUFMSDI        RAM2GS|PHI2     FD1S3AX     D       CmdUFMSDIe_0      2.589        -1.353
-CmdEnable        RAM2GS|PHI2     FD1S3AX     D       CmdEnable_s       2.589        -1.337
-==========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      2.500
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.589
-
-    - Propagation time:                      4.959
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.370
-
-    Number of logic level(s):                4
-    Starting point:                          Bank_fast_0io[5] / Q
-    Ending point:                            CmdSubmitted / D
-    The start point is clocked by            RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK
-    The end   point is clocked by            RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                             Pin      Pin               Arrival     No. of    
-Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
-Bank_fast_0io[5]              IFS1P3DX     Q        Out     1.044     1.044 r     -         
-Bank_fast[5]                  Net          -        -       -         -           2         
-Bank_fast_0io_RNI2FJ23[5]     ORCALUT4     A        In      0.000     1.044 r     -         
-Bank_fast_0io_RNI2FJ23[5]     ORCALUT4     Z        Out     1.089     2.133 r     -         
-g0_17_1                       Net          -        -       -         -           2         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     D        In      0.000     2.133 r     -         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     Z        Out     1.193     3.325 f     -         
-un1_ADWR_i_o3_12              Net          -        -       -         -           4         
-CmdSubmitted_1_sqmuxa         ORCALUT4     D        In      0.000     3.325 f     -         
-CmdSubmitted_1_sqmuxa         ORCALUT4     Z        Out     1.017     4.342 r     -         
-CmdSubmitted_1_sqmuxa         Net          -        -       -         -           1         
-CmdSubmitted_RNO              ORCALUT4     A        In      0.000     4.342 r     -         
-CmdSubmitted_RNO              ORCALUT4     Z        Out     0.617     4.959 r     -         
-N_377_0                       Net          -        -       -         -           1         
-CmdSubmitted                  FD1S3AX      D        In      0.000     4.959 r     -         
-============================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      2.500
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.589
-
-    - Propagation time:                      4.046
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.457
-
-    Number of logic level(s):                3
-    Starting point:                          Bank_0io[2] / Q
-    Ending point:                            CmdSubmitted / D
-    The start point is clocked by            RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK
-    The end   point is clocked by            RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                             Pin      Pin               Arrival     No. of    
-Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
-Bank_0io[2]                   IFS1P3DX     Q        Out     1.220     1.220 r     -         
-Bank[2]                       Net          -        -       -         -           8         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     A        In      0.000     1.220 r     -         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     Z        Out     1.193     2.413 r     -         
-un1_ADWR_i_o3_12              Net          -        -       -         -           4         
-CmdSubmitted_1_sqmuxa         ORCALUT4     D        In      0.000     2.413 r     -         
-CmdSubmitted_1_sqmuxa         ORCALUT4     Z        Out     1.017     3.429 f     -         
-CmdSubmitted_1_sqmuxa         Net          -        -       -         -           1         
-CmdSubmitted_RNO              ORCALUT4     A        In      0.000     3.429 f     -         
-CmdSubmitted_RNO              ORCALUT4     Z        Out     0.617     4.046 f     -         
-N_377_0                       Net          -        -       -         -           1         
-CmdSubmitted                  FD1S3AX      D        In      0.000     4.046 f     -         
-============================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      2.500
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.589
-
-    - Propagation time:                      4.030
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.441
-
-    Number of logic level(s):                3
-    Starting point:                          Bank_0io[6] / Q
-    Ending point:                            CmdSubmitted / D
-    The start point is clocked by            RAM2GS|PHI2 [rising] (rise=0.000 fall=2.500 period=5.000) on pin SCLK
-    The end   point is clocked by            RAM2GS|PHI2 [falling] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                             Pin      Pin               Arrival     No. of    
-Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
-Bank_0io[6]                   IFS1P3DX     Q        Out     1.204     1.204 r     -         
-Bank[6]                       Net          -        -       -         -           7         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     B        In      0.000     1.204 r     -         
-Bank_fast_0io_RNIV4MF3[7]     ORCALUT4     Z        Out     1.193     2.397 f     -         
-un1_ADWR_i_o3_12              Net          -        -       -         -           4         
-CmdSubmitted_1_sqmuxa         ORCALUT4     D        In      0.000     2.397 f     -         
-CmdSubmitted_1_sqmuxa         ORCALUT4     Z        Out     1.017     3.413 r     -         
-CmdSubmitted_1_sqmuxa         Net          -        -       -         -           1         
-CmdSubmitted_RNO              ORCALUT4     A        In      0.000     3.413 r     -         
-CmdSubmitted_RNO              ORCALUT4     Z        Out     0.617     4.030 r     -         
-N_377_0                       Net          -        -       -         -           1         
-CmdSubmitted                  FD1S3AX      D        In      0.000     4.030 r     -         
-============================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RAM2GS|RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                          Arrival           
-Instance      Reference       Type        Pin     Net           Time        Slack 
-              Clock                                                               
-----------------------------------------------------------------------------------
-FS[0]         RAM2GS|RCLK     FD1S3AX     Q       FS[0]         1.044       -0.385
-FS[1]         RAM2GS|RCLK     FD1S3AX     Q       FS[1]         1.108       -0.306
-FS[12]        RAM2GS|RCLK     FD1S3AX     Q       FS[12]        1.148       -0.279
-FS[14]        RAM2GS|RCLK     FD1S3AX     Q       FS[14]        1.148       -0.279
-FS[15]        RAM2GS|RCLK     FD1S3AX     Q       FS[15]        1.148       -0.279
-FS[2]         RAM2GS|RCLK     FD1S3AX     Q       FS[2]         1.044       -0.242
-FS[4]         RAM2GS|RCLK     FD1S3AX     Q       FS[4]         1.108       -0.164
-FS[3]         RAM2GS|RCLK     FD1S3AX     Q       FS[3]         1.044       -0.100
-InitReady     RAM2GS|RCLK     FD1S3AX     Q       InitReady     1.272       -0.082
-FS[5]         RAM2GS|RCLK     FD1S3AX     Q       FS[5]         1.108       -0.021
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-             Starting                                           Required           
-Instance     Reference       Type        Pin     Net            Time         Slack 
-             Clock                                                                 
------------------------------------------------------------------------------------
-FS[17]       RAM2GS|RCLK     FD1S3AX     D       FS_s[17]       4.894        -0.385
-UFMSDI       RAM2GS|RCLK     FD1S3AX     D       UFMSDI_RNO     5.462        -0.279
-FS[15]       RAM2GS|RCLK     FD1S3AX     D       FS_s[15]       4.894        -0.242
-FS[16]       RAM2GS|RCLK     FD1S3AX     D       FS_s[16]       4.894        -0.242
-FS[13]       RAM2GS|RCLK     FD1S3AX     D       FS_s[13]       4.894        -0.100
-FS[14]       RAM2GS|RCLK     FD1S3AX     D       FS_s[14]       4.894        -0.100
-UFMCLK       RAM2GS|RCLK     FD1S3AX     D       N_16_i         5.089        -0.082
-nUFMCS       RAM2GS|RCLK     FD1S3AY     D       nUFMCS_s_0     5.089        -0.038
-FS[11]       RAM2GS|RCLK     FD1S3AX     D       FS_s[11]       4.894        0.043 
-FS[12]       RAM2GS|RCLK     FD1S3AX     D       FS_s[12]       4.894        0.043 
-===================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.106
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.894
-
-    - Propagation time:                      5.280
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.385
-
-    Number of logic level(s):                10
-    Starting point:                          FS[0] / Q
-    Ending point:                            FS[17] / D
-    The start point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-    The end   point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                 Pin      Pin               Arrival     No. of    
-Name               Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
-FS[0]              FD1S3AX     Q        Out     1.044     1.044 r     -         
-FS[0]              Net         -        -       -         -           2         
-FS_cry_0[0]        CCU2D       A1       In      0.000     1.044 r     -         
-FS_cry_0[0]        CCU2D       COUT     Out     1.544     2.588 r     -         
-FS_cry[0]          Net         -        -       -         -           1         
-FS_cry_0[1]        CCU2D       CIN      In      0.000     2.588 r     -         
-FS_cry_0[1]        CCU2D       COUT     Out     0.143     2.731 r     -         
-FS_cry[2]          Net         -        -       -         -           1         
-FS_cry_0[3]        CCU2D       CIN      In      0.000     2.731 r     -         
-FS_cry_0[3]        CCU2D       COUT     Out     0.143     2.874 r     -         
-FS_cry[4]          Net         -        -       -         -           1         
-FS_cry_0[5]        CCU2D       CIN      In      0.000     2.874 r     -         
-FS_cry_0[5]        CCU2D       COUT     Out     0.143     3.017 r     -         
-FS_cry[6]          Net         -        -       -         -           1         
-FS_cry_0[7]        CCU2D       CIN      In      0.000     3.017 r     -         
-FS_cry_0[7]        CCU2D       COUT     Out     0.143     3.159 r     -         
-FS_cry[8]          Net         -        -       -         -           1         
-FS_cry_0[9]        CCU2D       CIN      In      0.000     3.159 r     -         
-FS_cry_0[9]        CCU2D       COUT     Out     0.143     3.302 r     -         
-FS_cry[10]         Net         -        -       -         -           1         
-FS_cry_0[11]       CCU2D       CIN      In      0.000     3.302 r     -         
-FS_cry_0[11]       CCU2D       COUT     Out     0.143     3.445 r     -         
-FS_cry[12]         Net         -        -       -         -           1         
-FS_cry_0[13]       CCU2D       CIN      In      0.000     3.445 r     -         
-FS_cry_0[13]       CCU2D       COUT     Out     0.143     3.588 r     -         
-FS_cry[14]         Net         -        -       -         -           1         
-FS_cry_0[15]       CCU2D       CIN      In      0.000     3.588 r     -         
-FS_cry_0[15]       CCU2D       COUT     Out     0.143     3.731 r     -         
-FS_cry[16]         Net         -        -       -         -           1         
-FS_s_0[17]         CCU2D       CIN      In      0.000     3.731 r     -         
-FS_s_0[17]         CCU2D       S0       Out     1.549     5.280 r     -         
-FS_s[17]           Net         -        -       -         -           1         
-FS[17]             FD1S3AX     D        In      0.000     5.280 r     -         
-================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.106
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.894
-
-    - Propagation time:                      5.201
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.306
-
-    Number of logic level(s):                9
-    Starting point:                          FS[1] / Q
-    Ending point:                            FS[17] / D
-    The start point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-    The end   point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                 Pin      Pin               Arrival     No. of    
-Name               Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
-FS[1]              FD1S3AX     Q        Out     1.108     1.108 r     -         
-FS[1]              Net         -        -       -         -           3         
-FS_cry_0[1]        CCU2D       A0       In      0.000     1.108 r     -         
-FS_cry_0[1]        CCU2D       COUT     Out     1.544     2.652 r     -         
-FS_cry[2]          Net         -        -       -         -           1         
-FS_cry_0[3]        CCU2D       CIN      In      0.000     2.652 r     -         
-FS_cry_0[3]        CCU2D       COUT     Out     0.143     2.795 r     -         
-FS_cry[4]          Net         -        -       -         -           1         
-FS_cry_0[5]        CCU2D       CIN      In      0.000     2.795 r     -         
-FS_cry_0[5]        CCU2D       COUT     Out     0.143     2.938 r     -         
-FS_cry[6]          Net         -        -       -         -           1         
-FS_cry_0[7]        CCU2D       CIN      In      0.000     2.938 r     -         
-FS_cry_0[7]        CCU2D       COUT     Out     0.143     3.081 r     -         
-FS_cry[8]          Net         -        -       -         -           1         
-FS_cry_0[9]        CCU2D       CIN      In      0.000     3.081 r     -         
-FS_cry_0[9]        CCU2D       COUT     Out     0.143     3.224 r     -         
-FS_cry[10]         Net         -        -       -         -           1         
-FS_cry_0[11]       CCU2D       CIN      In      0.000     3.224 r     -         
-FS_cry_0[11]       CCU2D       COUT     Out     0.143     3.366 r     -         
-FS_cry[12]         Net         -        -       -         -           1         
-FS_cry_0[13]       CCU2D       CIN      In      0.000     3.366 r     -         
-FS_cry_0[13]       CCU2D       COUT     Out     0.143     3.509 r     -         
-FS_cry[14]         Net         -        -       -         -           1         
-FS_cry_0[15]       CCU2D       CIN      In      0.000     3.509 r     -         
-FS_cry_0[15]       CCU2D       COUT     Out     0.143     3.652 r     -         
-FS_cry[16]         Net         -        -       -         -           1         
-FS_s_0[17]         CCU2D       CIN      In      0.000     3.652 r     -         
-FS_s_0[17]         CCU2D       S0       Out     1.549     5.201 r     -         
-FS_s[17]           Net         -        -       -         -           1         
-FS[17]             FD1S3AX     D        In      0.000     5.201 r     -         
-================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         5.462
-
-    - Propagation time:                      5.741
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.279
-
-    Number of logic level(s):                5
-    Starting point:                          FS[12] / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-    The end   point is clocked by            RAM2GS|RCLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
-
-Instance / Net                          Pin      Pin               Arrival     No. of    
-Name                       Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
-FS[12]                     FD1S3AX      Q        Out     1.148     1.148 r     -         
-FS[12]                     Net          -        -       -         -           4         
-UFMSDI_ens2_i_o4_N_2L1     ORCALUT4     A        In      0.000     1.148 r     -         
-UFMSDI_ens2_i_o4_N_2L1     ORCALUT4     Z        Out     1.017     2.165 f     -         
-UFMSDI_ens2_i_o4_N_2L1     Net          -        -       -         -           1         
-UFMSDI_ens2_i_o4           ORCALUT4     D        In      0.000     2.165 f     -         
-UFMSDI_ens2_i_o4           ORCALUT4     Z        Out     1.153     3.317 r     -         
-N_29                       Net          -        -       -         -           3         
-nUFMCS15_0_a2              ORCALUT4     D        In      0.000     3.317 r     -         
-nUFMCS15_0_a2              ORCALUT4     Z        Out     1.193     4.510 f     -         
-nUFMCS15                   Net          -        -       -         -           4         
-UFMSDI_RNO_0               ORCALUT4     B        In      0.000     4.510 f     -         
-UFMSDI_RNO_0               ORCALUT4     Z        Out     1.017     5.527 r     -         
-UFMSDI_RNO_0               Net          -        -       -         -           1         
-UFMSDI_RNO                 PFUMX        ALUT     In      0.000     5.527 r     -         
-UFMSDI_RNO                 PFUMX        Z        Out     0.214     5.741 r     -         
-UFMSDI_RNO                 Net          -        -       -         -           1         
-UFMSDI                     FD1S3AX      D        In      0.000     5.741 r     -         
-=========================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 91 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        2
-FD1S3AX:        50
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-IFS1P3IX:       10
-IFS1P3JX:       2
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       8
-OFS1P3IX:       1
-OFS1P3JX:       1
-ORCALUT4:       163
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 65MB peak: 184MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Tue Aug 15 22:17:29 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm
index 6eeb0c4..72b5d0e 100644
--- a/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm
+++ b/CPLD/LCMXO2-640HC/impl1/dm/layer0.xdm
@@ -12,7 +12,8 @@ SS
 S"/
 S1S<
+/>S1S"/
+<
 S/k1Fs#OC>S
 
 <-!-R8vFkRDCs0FFR>--
@@ -22,14 +23,175 @@ S/k1Fs#OC>S
 
 <
 S!R--vkF8D7CRCMVHHF0HM-R-><
-S7RCVMI="F3s	).qvtP13CDsHFRo"DP="CDsHF>o"
-SqS"/
-
-
-
-
+S7RCVMI="F3s	e3]QPHCsD"FoR"D=PHCsD"Fo>S
+SS
+S"/
+
+SRSqS
+SR
+SR"/
 /S<7>CV
-]sC
+<
+S!R--vkF8D7CRCMVHHF0HM-R-><
+S7RCVMI="F3s	e3pmPHCsD"FoR"D=PHCsD"Fo>S
+SS
+S"/
+
+SRSqS
+SR
+SR"/
+/S<7>CV
+<
+S!R--vkF8D7CRCMVHHF0HM-R-><
+S7RCVMI="F3s	 3wAPHCsD"FoR"D=PHCsD"Fo>S
+SS
+S"/
+
+SR"/
+S
+S
+SR
+SRS
+SSuS
+SR
+SR
+SR
+SRS
+SSuS
+SR
+SR
+SR
+SRSuS"/
+
+SR"/
+
+SR"/
+"/
+"/
+SuS"/
+
+SR
+SR"/
+"/
+SuS
+SRS
+S"/
+SuSSuSS
+S
+SRS
+SS
+SS
+S
+SRSuSS
+S
+SR"/
+
+SR
+SR
+SR"/
+
+SRSqS
+SR
+SR"/
+/S<7>CV
+<
+S!R--vkF8D7CRCMVHHF0HM-R-><
+S7RCVMI="F3s	)A w3sPCHoDF"=RD"sPCHoDF"S>
+SRS
+S
+SRS
+S
+
+SC<)V=RM"sIF	]3eQC3PsFHDoH"R=O"#k_LNP_EHH0M#"S>
+SWSR/
+S
+SS
+SSRS/S<)>CV
+SS
+SSR
+SqS"/
+SSSS
+SSRSS
+SqSSS
+SSR
+SqS"/
+SSSS
+SSR"/
+SSSS"/
+SSSS
+SSRS
+SSRS
+SqSS
+SqSSSSSSSS
+SqSS
+SSR
+SqS"/
+SSS"/
+SSSS
+SSR
+SqS
+SqSS
+SSRS
+SqSS
+SSR
+SqSSS"/
+SSSS
+SSRS
+SSRSS
+SSR"/
+SSS"/
+SSSS
+S
+
+S-SC<7V=RM"sIF	q3)v1.t3sPCHoDF"=RD"sPCHoDF"S>
+SRS
+S
+SR
+
+SC<)V=RM"sIF	 3)wPA3CDsHFRo"Hk="VVlCL
+">SS
+S
+
+/p]71k0sOs0kC@>
+ 
+
+
 
-@ 
diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
index 659885d..4ce8f81 100644
--- a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
@@ -1,9 +1,14 @@
          	                                   	                                                	                                                 	                                                  	
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-735,10) (VERI-9000) elaborating module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
 Done: design load finished with (0) errors, and (0) warnings
 
 
    
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/impl1.areasrr
deleted file mode 100644
index 41b5352..0000000
--- a/CPLD/LCMXO2-640HC/impl1/impl1.areasrr
+++ /dev/null
@@ -1,29 +0,0 @@
-----------------------------------------------------------------------
-Report for cell RAM2GS.verilog
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-                                          Cell usage:
-                               cell       count    Res Usage(%)
-                                 BB        8       100.0
-                              CCU2D       10       100.0
-                            FD1P3AX       11       100.0
-                            FD1S3AX       49       100.0
-                            FD1S3AY        1       100.0
-                            FD1S3IX        3       100.0
-                                GSR        1       100.0
-                                 IB       26       100.0
-                           IFS1P3DX        9       100.0
-                                INV        7       100.0
-                                 OB       33       100.0
-                           OFS1P3BX        4       100.0
-                           OFS1P3DX       12       100.0
-                           OFS1P3JX        1       100.0
-                           ORCALUT4      135       100.0
-                              PFUMX        1       100.0
-                                PUR        1       100.0
-                                VHI        1       100.0
-                                VLO        1       100.0
-                            
-                         TOTAL           314           
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.htm b/CPLD/LCMXO2-640HC/impl1/impl1.htm
deleted file mode 100644
index 5cabe18..0000000
--- a/CPLD/LCMXO2-640HC/impl1/impl1.htm
+++ /dev/null
@@ -1,9 +0,0 @@
-
- 
- syntmp/impl1_srr.htm log file
- 
- 
- 
- 				 
-
- 
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srd b/CPLD/LCMXO2-640HC/impl1/impl1.srd
deleted file mode 100644
index 956725b..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/impl1.srd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srm b/CPLD/LCMXO2-640HC/impl1/impl1.srm
deleted file mode 100644
index b4d59f5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/impl1.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srr.db b/CPLD/LCMXO2-640HC/impl1/impl1.srr.db
deleted file mode 100644
index 3e9605b..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/impl1.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.srs b/CPLD/LCMXO2-640HC/impl1/impl1.srs
deleted file mode 100644
index 0afd997..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/impl1.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.xcf b/CPLD/LCMXO2-640HC/impl1/impl1.xcf
deleted file mode 100644
index bb517c2..0000000
--- a/CPLD/LCMXO2-640HC/impl1/impl1.xcf
+++ /dev/null
@@ -1,52 +0,0 @@
-
-
-
-	
-	
-		JTAG
-		
-			
-			1
-			Lattice
-			MachXO2
-			LCMXO2-640HC
-			0x012b9043
-			All
-			LCMXO2-640HC
-			
-				8
-				11111111
-				1
-				0
-			
-			D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
-			08/15/23 23:30:13
-			0x812F
-			FLASH Erase,Program,Verify
-			
-		
-	
-	
-		SEQUENTIAL
-		ENTIRED CHAIN
-		No Override
-		TLR
-		TLR
-		
-		1
-	
-	
-		USB
-		EzUSB-0
-		\\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13#
-	
-
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt.db b/CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt.db
deleted file mode 100644
index 5e85483..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/impl1_cck.rpt.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_syn.prj b/CPLD/LCMXO2-640HC/impl1/impl1_syn.prj
deleted file mode 100644
index e8f3855..0000000
--- a/CPLD/LCMXO2-640HC/impl1/impl1_syn.prj
+++ /dev/null
@@ -1,76 +0,0 @@
-#--  Synopsys, Inc.
-#--  Version R-2021.03L-SP1
-#--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_syn.prj
-#--  Written on Tue Aug 15 22:34:07 2023
-
-
-#project files
-add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-
-
-#implementation: "impl1"
-impl -add impl1 -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std sysv
-set_option -project_relative_includes 1
-set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_640HC
-set_option -package TG100C
-set_option -speed_grade -4
-set_option -part_companion ""
-
-#compilation/mapping options
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-set_option -hdl_strict_syntax 0
-
-# mapper_without_write_options
-set_option -frequency auto
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 0
-set_option -write_structural_verilog 0
-set_option -write_vhdl 0
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr no
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-set_option -seqshift_no_replicate 0
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./impl1.edi"
-impl -active "impl1"
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_synplify.lpf b/CPLD/LCMXO2-640HC/impl1/impl1_synplify.lpf
deleted file mode 100644
index 2b0f89b..0000000
--- a/CPLD/LCMXO2-640HC/impl1/impl1_synplify.lpf
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
-#
-
-# Period Constraints 
-FREQUENCY PORT "PHI2" 2.9 MHz;
-FREQUENCY PORT "nCCAS" 2.9 MHz;
-FREQUENCY PORT "nCRAS" 2.9 MHz;
-FREQUENCY PORT "RCLK" 62.5 MHz;
-
-
-# Output Constraints 
-
-# Input Constraints 
-
-# Point-to-point Delay Constraints 
-
-
-
-# Block Path Constraints 
-
-BLOCK ASYNCPATHS;
-
-# End of generated Logical Preferences.
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp8.lpf b/CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp8.lpf
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/launch_synplify.tcl b/CPLD/LCMXO2-640HC/impl1/launch_synplify.tcl
deleted file mode 100644
index 80e7f2f..0000000
--- a/CPLD/LCMXO2-640HC/impl1/launch_synplify.tcl
+++ /dev/null
@@ -1,55 +0,0 @@
-#-- Lattice Semiconductor Corporation Ltd.
-#-- Synplify OEM project file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/launch_synplify.tcl
-#-- Written on Tue Aug 15 22:33:53 2023
-
-project -close
-set filename "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1_syn.prj"
-if ([file exists "$filename"]) {
-	project -load "$filename"
-	project_file -remove *
-} else {
-	project -new "$filename"
-}
-set create_new 0
-
-#device options
-set_option -technology MACHXO2
-set_option -part LCMXO2_640HC
-set_option -package TG100C
-set_option -speed_grade -4
-
-if {$create_new == 1} {
-#-- add synthesis options
-	set_option -symbolic_fsm_compiler true
-	set_option -resource_sharing true
-	set_option -vlog_std v2001
-	set_option -frequency 200
-	set_option -maxfan 1000
-	set_option -auto_constrain_io 0
-	set_option -disable_io_insertion false
-	set_option -retiming false; set_option -pipe true
-	set_option -force_gsr auto
-	set_option -compiler_compatible 0
-	set_option -dup false
-	
-	set_option -default_enum_encoding default
-	
-	set_option -num_critical_paths 3
-	
-	set_option -write_apr_constraint 1
-	set_option -fix_gated_and_generated_clocks 1
-	set_option -update_models_cp 0
-	set_option -resolve_multiple_driver 0
-	
-	
-	set_option -seqshift_no_replicate 0
-	
-}
-#-- add_file options
-add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc}
-set_option -include_path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
-#-- top module name
-set_option -top_module {}
-project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.edi}
-project -save "$filename"
diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
deleted file mode 100644
index c5a0d71..0000000
--- a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
+++ /dev/null
@@ -1,138 +0,0 @@
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 22:56:41 2023
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     3.268      4      -0.395     M
-CROW[1] nCRAS F     1.999      4      -0.040     M
-Din[0]  PHI2  F     4.389      4       3.636     4
-Din[0]  nCCAS F     0.646      4       0.538     4
-Din[1]  PHI2  F     4.456      4       3.516     4
-Din[1]  nCCAS F     1.108      4       0.143     4
-Din[2]  PHI2  F     4.106      4       3.516     4
-Din[2]  nCCAS F     1.315      4       0.036     M
-Din[3]  PHI2  F     4.427      4       3.516     4
-Din[3]  nCCAS F     1.893      4      -0.089     M
-Din[4]  PHI2  F     4.612      4       3.516     4
-Din[4]  nCCAS F     0.714      4       0.460     4
-Din[5]  PHI2  F     4.805      4       3.516     4
-Din[5]  nCCAS F     1.636      4      -0.054     M
-Din[6]  PHI2  F     4.266      4       3.636     4
-Din[6]  nCCAS F     1.078      4       0.185     4
-Din[7]  PHI2  F     5.607      4       3.636     4
-Din[7]  nCCAS F     2.050      4      -0.188     M
-MAin[0] PHI2  F     6.493      4      -0.289     M
-MAin[0] nCRAS F     0.832      4       0.632     4
-MAin[1] PHI2  F     5.109      4       0.055     M
-MAin[1] nCRAS F     1.627      4       0.047     M
-MAin[2] PHI2  F     5.349      4       0.695     4
-MAin[2] nCRAS F     1.684      4       0.048     M
-MAin[3] PHI2  F     7.301      4      -0.533     M
-MAin[3] nCRAS F     1.660      4       0.035     M
-MAin[4] PHI2  F     6.167      4      -0.223     M
-MAin[4] nCRAS F     1.339      4       0.181     4
-MAin[5] PHI2  F     6.923      4      -0.449     M
-MAin[5] nCRAS F     1.082      4       0.412     4
-MAin[6] PHI2  F     6.784      4      -0.408     M
-MAin[6] nCRAS F     0.961      4       0.423     4
-MAin[7] PHI2  F     6.547      4      -0.171     M
-MAin[7] nCRAS F     1.331      4       0.186     4
-MAin[8] nCRAS F     0.454      4       0.874     4
-MAin[9] nCRAS F     0.782      4       0.684     4
-PHI2    RCLK  R    -0.312      M       3.167     4
-UFMSDO  RCLK  R     0.397      4       0.958     4
-nCCAS   RCLK  R     2.272      4      -0.095     M
-nCCAS   nCRAS F     3.094      4      -0.308     M
-nCRAS   RCLK  R     1.843      4       0.009     M
-nFWE    PHI2  F     5.987      4      -0.179     M
-nFWE    nCRAS F     0.594      4       0.839     4
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.623         4        3.337          M
-LED    nCRAS F    10.867         4        3.086          M
-RA[0]  RCLK  R    10.387         4        3.085          M
-RA[0]  nCRAS F    10.473         4        3.018          M
-RA[10] RCLK  R     8.141         4        2.620          M
-RA[11] PHI2  R     8.610         4        2.756          M
-RA[1]  RCLK  R    11.208         4        3.281          M
-RA[1]  nCRAS F    10.655         4        3.096          M
-RA[2]  RCLK  R    11.477         4        3.355          M
-RA[2]  nCRAS F    10.655         4        3.096          M
-RA[3]  RCLK  R    10.954         4        3.201          M
-RA[3]  nCRAS F    10.693         4        3.092          M
-RA[4]  RCLK  R    12.338         4        3.584          M
-RA[4]  nCRAS F    10.776         4        3.099          M
-RA[5]  RCLK  R    11.516         4        3.347          M
-RA[5]  nCRAS F    11.072         4        3.177          M
-RA[6]  RCLK  R    11.068         4        3.255          M
-RA[6]  nCRAS F    10.655         4        3.096          M
-RA[7]  RCLK  R    10.823         4        3.207          M
-RA[7]  nCRAS F    11.129         4        3.214          M
-RA[8]  RCLK  R    11.034         4        3.275          M
-RA[8]  nCRAS F    10.664         4        3.099          M
-RA[9]  RCLK  R    10.925         4        3.239          M
-RA[9]  nCRAS F    10.710         4        3.093          M
-RBA[0] nCRAS F     8.157         4        2.563          M
-RBA[1] nCRAS F     8.157         4        2.563          M
-RCKE   RCLK  R     8.141         4        2.620          M
-RDQMH  RCLK  R    11.337         4        3.355          M
-RDQML  RCLK  R    10.800         4        3.223          M
-RD[0]  nCCAS F     7.888         4        2.510          M
-RD[1]  nCCAS F     7.888         4        2.510          M
-RD[2]  nCCAS F     7.888         4        2.510          M
-RD[3]  nCCAS F     7.888         4        2.510          M
-RD[4]  nCCAS F     7.888         4        2.510          M
-RD[5]  nCCAS F     7.888         4        2.510          M
-RD[6]  nCCAS F     7.888         4        2.510          M
-RD[7]  nCCAS F     7.888         4        2.510          M
-UFMCLK RCLK  R     8.121         4        2.627          M
-UFMSDI RCLK  R     8.121         4        2.627          M
-nRCAS  RCLK  R     8.141         4        2.620          M
-nRCS   RCLK  R     8.141         4        2.620          M
-nRRAS  RCLK  R     8.141         4        2.620          M
-nRWE   RCLK  R     8.121         4        2.627          M
-nUFMCS RCLK  R     8.121         4        2.627          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
deleted file mode 100644
index 4b4d1c0..0000000
--- a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
+++ /dev/null
@@ -1,17 +0,0 @@
-[ActiveSupport TRCE]
-; Setup Analysis
-Fmax_0 = 55.475 MHz (2.900 MHz);
-Fmax_1 = 150.150 MHz (2.900 MHz);
-Fmax_2 = 150.150 MHz (2.900 MHz);
-Fmax_3 = 101.286 MHz (62.500 MHz);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
-; Hold Analysis
-Fmax_0 = - (-);
-Fmax_1 = - (-);
-Fmax_2 = - (-);
-Fmax_3 = - (-);
-Failed = 0 (Total 4);
-Clock_ports = 4;
-Clock_nets = 4;
diff --git a/CPLD/LCMXO2-640HC/impl1/run_options.txt b/CPLD/LCMXO2-640HC/impl1/run_options.txt
index 9458d4f..fa2c1d6 100644
--- a/CPLD/LCMXO2-640HC/impl1/run_options.txt
+++ b/CPLD/LCMXO2-640HC/impl1/run_options.txt
@@ -1,12 +1,13 @@
 #--  Synopsys, Inc.
 #--  Version R-2021.03L-SP1
 #--  Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
-#--  Written on Tue Aug 15 23:12:41 2023
+#--  Written on Wed Aug 16 20:59:29 2023
 
 
 #project files
 add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
+add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
 
 
 #implementation: "impl1"
@@ -16,7 +17,6 @@ impl -add impl1 -type fpga
 #implementation attributes
 
 set_option -vlog_std v2001
-set_option -num_critical_paths 3
 set_option -project_relative_includes 1
 set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
 
@@ -35,7 +35,7 @@ set_option -distributed_compile 0
 set_option -hdl_strict_syntax 0
 
 # mapper_without_write_options
-set_option -frequency 70
+set_option -frequency 100
 set_option -srs_instrumentation 1
 
 # mapper_options
@@ -47,8 +47,8 @@ set_option -write_vhdl 0
 set_option -maxfan 1000
 set_option -disable_io_insertion 0
 set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
+set_option -pipe 1
+set_option -forcegsr false
 set_option -fix_gated_and_generated_clocks 1
 set_option -rw_check_on_ram 1
 set_option -update_models_cp 0
@@ -74,8 +74,8 @@ set_option -auto_infer_blackbox 0
 set_option -write_apr_constraint 1
 
 #set result format/file last
-project -result_file "./RAM2GS_LCMXO2_640HC_impl1.edi"
+project -result_file "./LCMXO2_640HC_impl1.edi"
 
 #set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf" 
+set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
 impl -active "impl1"
diff --git a/CPLD/LCMXO2-640HC/impl1/scratchproject.prs b/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
index 9d7c42b..8d7cd5a 100644
--- a/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
+++ b/CPLD/LCMXO2-640HC/impl1/scratchproject.prs
@@ -4,7 +4,8 @@
 
 #project files
 add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
-add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
+add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
+add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
 
 
 #implementation: "impl1"
@@ -14,7 +15,6 @@ impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
 #implementation attributes
 
 set_option -vlog_std v2001
-set_option -num_critical_paths 3
 set_option -project_relative_includes 1
 set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
 set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
@@ -34,7 +34,7 @@ set_option -distributed_compile 0
 set_option -hdl_strict_syntax 0
 
 # mapper_without_write_options
-set_option -frequency 70
+set_option -frequency 100
 set_option -srs_instrumentation 1
 
 # mapper_options
@@ -46,8 +46,8 @@ set_option -write_vhdl 0
 set_option -maxfan 1000
 set_option -disable_io_insertion 0
 set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr auto
+set_option -pipe 1
+set_option -forcegsr false
 set_option -fix_gated_and_generated_clocks 1
 set_option -rw_check_on_ram 1
 set_option -update_models_cp 0
@@ -73,8 +73,8 @@ set_option -auto_infer_blackbox 0
 set_option -write_apr_constraint 1
 
 #set result format/file last
-project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.edi"
+project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
 
 #set log file 
-set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.srf" 
+set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" 
 impl -active "impl1"
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log b/CPLD/LCMXO2-640HC/impl1/stdout.log
index 8a13efe..61eeca9 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log
@@ -13,75 +13,68 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 23:12:40 2023
+Date:        Wed Aug 16 20:59:29 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 23:12:41 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
+# Wed Aug 16 20:59:29 2023
 
 compiler completed
-# Tue Aug 15 23:12:42 2023
+# Wed Aug 16 20:59:30 2023
 
 Return Code: 0
 Run Time:00h:00m:01s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 23:12:42 2023
-
-multi_srs_gen completed
-# Tue Aug 15 23:12:42 2023
-
-Return Code: 0
-Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+# Wed Aug 16 20:59:30 2023
+Up-To-Date: multi_srs_gen. No run necessary
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 23:12:42 2023
+# Wed Aug 16 20:59:30 2023
 
 premap completed with warnings
-# Tue Aug 15 23:12:44 2023
+# Wed Aug 16 20:59:32 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 23:12:44 2023
+# Wed Aug 16 20:59:32 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 23:12:44 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
+# Wed Aug 16 20:59:32 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
 
 fpga_mapper completed with warnings
-# Tue Aug 15 23:12:47 2023
+# Wed Aug 16 20:59:35 2023
 
 Return Code: 1
 Run Time:00h:00m:03s
 Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
 exit status=0
 exit status=0
 Save changes for project:
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
index 36117a5..0e70380 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
@@ -13,75 +13,75 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 23:05:00 2023
+Date:        Wed Aug 16 20:57:40 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 23:05:00 2023
+# Wed Aug 16 20:57:40 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 23:05:00 2023
+# Wed Aug 16 20:57:40 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 23:05:00 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
+# Wed Aug 16 20:57:40 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
 
 compiler completed
-# Tue Aug 15 23:05:02 2023
+# Wed Aug 16 20:57:43 2023
 
 Return Code: 0
-Run Time:00h:00m:02s
+Run Time:00h:00m:03s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 23:05:02 2023
+# Wed Aug 16 20:57:43 2023
 
 multi_srs_gen completed
-# Tue Aug 15 23:05:02 2023
+# Wed Aug 16 20:57:43 2023
 
 Return Code: 0
 Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 23:05:02 2023
+# Wed Aug 16 20:57:43 2023
 
 premap completed with warnings
-# Tue Aug 15 23:05:04 2023
+# Wed Aug 16 20:57:45 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 23:05:04 2023
+# Wed Aug 16 20:57:45 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 23:05:04 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
+# Wed Aug 16 20:57:45 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
 
 fpga_mapper completed with warnings
-# Tue Aug 15 23:05:07 2023
+# Wed Aug 16 20:57:49 2023
 
 Return Code: 1
-Run Time:00h:00m:03s
+Run Time:00h:00m:04s
 Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
 exit status=0
 exit status=0
 Save changes for project:
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
index 7dbdadd..01eeeba 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
@@ -13,77 +13,47 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 23:03:21 2023
+Date:        Wed Aug 16 20:52:48 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 23:03:21 2023
+# Wed Aug 16 20:52:48 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 23:03:21 2023
+# Wed Aug 16 20:52:48 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 23:03:21 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
+# Wed Aug 16 20:52:48 2023
+compiler exited with errors
+Job failed on: proj_1|impl1
 
-compiler completed
-# Tue Aug 15 23:03:23 2023
+Job: "compiler" terminated with error status: 2
+See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
+# Wed Aug 16 20:52:49 2023
 
-Return Code: 0
-Run Time:00h:00m:02s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 23:03:23 2023
-
-multi_srs_gen completed
-# Tue Aug 15 23:03:23 2023
-
-Return Code: 0
-Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Return Code: 2
+Run Time:00h:00m:01s
 Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 23:03:23 2023
-
-premap completed with warnings
-# Tue Aug 15 23:03:25 2023
-
-Return Code: 1
-Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 23:03:25 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 23:03:25 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Tue Aug 15 23:03:28 2023
-
-Return Code: 1
-Run Time:00h:00m:03s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Error: At line 65 while processing "LCMXO2_640HC_impl1_synplify.tcl"
+2
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=9
+exit status=9
 Save changes for project:
 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
 batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
index b8d632b..71d9674 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.3
@@ -13,77 +13,47 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 23:00:01 2023
+Date:        Wed Aug 16 20:52:31 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 23:00:02 2023
+# Wed Aug 16 20:52:32 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 23:00:02 2023
+# Wed Aug 16 20:52:32 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 23:00:02 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
+# Wed Aug 16 20:52:32 2023
+compiler exited with errors
+Job failed on: proj_1|impl1
 
-compiler completed
-# Tue Aug 15 23:00:03 2023
+Job: "compiler" terminated with error status: 2
+See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
+# Wed Aug 16 20:52:32 2023
 
-Return Code: 0
-Run Time:00h:00m:01s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 23:00:03 2023
-
-multi_srs_gen completed
-# Tue Aug 15 23:00:04 2023
-
-Return Code: 0
-Run Time:00h:00m:01s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Return Code: 2
+Run Time:00h:00m:00s
 Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 23:00:04 2023
-
-premap completed with warnings
-# Tue Aug 15 23:00:05 2023
-
-Return Code: 1
-Run Time:00h:00m:01s
 Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 23:00:05 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 23:00:05 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Tue Aug 15 23:00:08 2023
-
-Return Code: 1
-Run Time:00h:00m:03s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
+2
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=9
+exit status=9
 Save changes for project:
 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
 batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
index 2f995a3..5c65ff4 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.4
@@ -13,75 +13,75 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 22:59:06 2023
+Date:        Wed Aug 16 20:44:48 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 22:59:06 2023
+# Wed Aug 16 20:44:49 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 22:59:06 2023
+# Wed Aug 16 20:44:49 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 22:59:06 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
+# Wed Aug 16 20:44:49 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
 
 compiler completed
-# Tue Aug 15 22:59:08 2023
+# Wed Aug 16 20:44:51 2023
 
 Return Code: 0
 Run Time:00h:00m:02s
 
 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 22:59:08 2023
+# Wed Aug 16 20:44:51 2023
 
 multi_srs_gen completed
-# Tue Aug 15 22:59:08 2023
+# Wed Aug 16 20:44:52 2023
 
 Return Code: 0
-Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Run Time:00h:00m:01s
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Compile Process on proj_1|impl1
 
 Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 22:59:08 2023
+# Wed Aug 16 20:44:52 2023
 
 premap completed with warnings
-# Tue Aug 15 22:59:10 2023
+# Wed Aug 16 20:44:54 2023
 
 Return Code: 1
 Run Time:00h:00m:02s
 Complete: Compile on proj_1|impl1
 
 Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 22:59:10 2023
+# Wed Aug 16 20:44:54 2023
 License granted for 4 parallel jobs
 
 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 22:59:10 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
+# Wed Aug 16 20:44:54 2023
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
 
 fpga_mapper completed with warnings
-# Tue Aug 15 22:59:13 2023
+# Wed Aug 16 20:44:57 2023
 
 Return Code: 1
 Run Time:00h:00m:03s
 Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
 exit status=0
 exit status=0
 Save changes for project:
diff --git a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5 b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
index 06b517d..1110f0a 100644
--- a/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
+++ b/CPLD/LCMXO2-640HC/impl1/stdout.log.bak.5
@@ -13,76 +13,47 @@ Running in Lattice mode
 Starting:    C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
 Install:     C:\lscc\diamond\3.12\synpbase
 Hostname:    ZANEPC
-Date:        Tue Aug 15 22:58:25 2023
+Date:        Wed Aug 16 20:41:46 2023
 Version:     R-2021.03L-SP1
 
-Arguments:   -product synplify_pro -batch RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+Arguments:   -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
 ProductType: synplify_pro
 
 
 
 
-log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr"
+log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
 Running: impl1 in foreground
 
 Running proj_1|impl1
 
 Running Flow: compile (Compile) on proj_1|impl1
-# Tue Aug 15 22:58:25 2023
+# Wed Aug 16 20:41:47 2023
 
 Running Flow: compile_flow (Compile Process) on proj_1|impl1
-# Tue Aug 15 22:58:25 2023
+# Wed Aug 16 20:41:47 2023
 
 Running: compiler (Compile Input) on proj_1|impl1
-# Tue Aug 15 22:58:25 2023
+# Wed Aug 16 20:41:47 2023
+compiler exited with errors
+Job failed on: proj_1|impl1
 
-compiler completed
-# Tue Aug 15 22:58:26 2023
+Job: "compiler" terminated with error status: 2
+See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
+# Wed Aug 16 20:41:47 2023
 
-Return Code: 0
-Run Time:00h:00m:01s
-
-Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
-# Tue Aug 15 22:58:26 2023
-
-multi_srs_gen completed
-# Tue Aug 15 22:58:26 2023
-
-Return Code: 0
+Return Code: 2
 Run Time:00h:00m:00s
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srs
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
 Complete: Compile Process on proj_1|impl1
-
-Running: premap (Premap) on proj_1|impl1
-# Tue Aug 15 22:58:26 2023
-
-premap completed with warnings
-# Tue Aug 15 22:58:27 2023
-
-Return Code: 1
-Run Time:00h:00m:01s
 Complete: Compile on proj_1|impl1
-
-Running Flow: map (Map) on proj_1|impl1
-# Tue Aug 15 22:58:27 2023
-License granted for 4 parallel jobs
-
-Running: fpga_mapper (Map & Optimize) on proj_1|impl1
-# Tue Aug 15 22:58:27 2023
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm
-
-fpga_mapper completed with warnings
-# Tue Aug 15 22:58:30 2023
-
-Return Code: 1
-Run Time:00h:00m:03s
-Complete: Map on proj_1|impl1
-Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srf
 Complete: Logic Synthesis on proj_1|impl1
-TCL script complete: "RAM2GS_LCMXO2_640HC_impl1_synplify.tcl"
-exit status=0
-exit status=0
+Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
+Error: At line 64 while processing "LCMXO2_640HC_impl1_synplify.tcl"
+2
+TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
+TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
+exit status=9
+exit status=9
 Save changes for project:
 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
 batch mode default:no
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog.tcl b/CPLD/LCMXO2-640HC/impl1/synlog.tcl
index 0ad1811..08b4740 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog.tcl
+++ b/CPLD/LCMXO2-640HC/impl1/synlog.tcl
@@ -1 +1 @@
-run_tcl -fg RAM2GS_LCMXO2_640HC_impl1_synplify.tcl
+run_tcl -fg LCMXO2_640HC_impl1_synplify.tcl
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap
new file mode 100644
index 0000000..ac358a3
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_comp.rt.csv.rptmap
@@ -0,0 +1 @@
+./synwork/LCMXO2_640HC_impl1_comp.rt.csv,LCMXO2_640HC_impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
similarity index 64%
rename from CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
index 11e3045..c6bd2e5 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr
@@ -39,17 +39,38 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
 
 Compiler output is up to date.  No re-compile necessary
 
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
@@ -61,7 +82,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 ###########################################################[
@@ -83,18 +104,21 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.rt.csv
 
 @END
 
@@ -103,6 +127,6 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:41 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db
similarity index 90%
rename from CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.db
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db
index 3f6f00c..4c6c160 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.db and b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.rptmap
new file mode 100644
index 0000000..5e69042
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/LCMXO2_640HC_impl1_compiler.srr,LCMXO2_640HC_impl1_compiler.srr,Compile Log
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr
similarity index 57%
rename from CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr
index 7e06b9b..2b3abf7 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr
@@ -1,4 +1,4 @@
-# Tue Aug 15 22:34:22 2023
+# Wed Aug 16 20:59:32 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -17,7 +17,7 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
@@ -38,95 +38,90 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 
 Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
 
-@N: MT204 |Auto Constrain mode is disabled because the following clocks are already defined:
-
-            RCLK
-            PHI2
-            nCRAS
-            nCCAS
-
 
 Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
 
-   4		0h:00m:01s		    -2.04ns		 140 /        90
+   4		0h:00m:01s		    -1.83ns		 210 /       109
 
 
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 177MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_m.srm
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
 
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
 @N: MT615 |Found clock nCRAS with period 350.00ns 
@@ -134,7 +129,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:0
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 22:34:24 2023
+# Timing report written on Wed Aug 16 20:59:35 2023
 #
 
 
@@ -154,21 +149,22 @@ Performance Summary
 *******************
 
 
-Worst slack in design: -2.389
+Worst slack in design: -1.832
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
 nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
 
 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
@@ -178,17 +174,19 @@ Estimated period and frequency reported as NA means no slack depends directly on
 Clock Relationships
 *******************
 
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
@@ -210,41 +208,41 @@ Detailed Report for Clock: PHI2
 Starting Points with Worst Slack
 ********************************
 
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
 
 
 
@@ -258,122 +256,110 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 2: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
 
 
 Path information for path number 3: 
       Requested Period:                      1.000
-    - Setup time:                            -0.462
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
+    = Required time:                         0.528
 
-    - Propagation time:                      3.214
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 4: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.605
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.517
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdUFMCS / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdUFMCS             FD1P3AX      Q        Out     0.972     0.972 r     -         
-CmdUFMCS             Net          -        -       -         -           1         
-nUFMCS_s_0_m4_yy     ORCALUT4     A        In      0.000     0.972 r     -         
-nUFMCS_s_0_m4_yy     ORCALUT4     Z        Out     1.017     1.989 r     -         
-nUFMCS_s_0_m4_yy     Net          -        -       -         -           1         
-nUFMCS_s_0_N_5_i     ORCALUT4     C        In      0.000     1.989 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.605 f     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.605 f     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 5: 
@@ -382,26 +368,26 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      1.765
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.236
+    = Slack (critical) :                     -1.832
 
     Number of logic level(s):                1
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            LEDEN / SP
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CmdSubmitted       FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted       Net          -        -       -         -           4         
-un1_FS_13_i_0      ORCALUT4     A        In      0.000     1.148 r     -         
-un1_FS_13_i_0      ORCALUT4     Z        Out     0.617     1.765 r     -         
-N_28               Net          -        -       -         -           1         
-LEDEN              FD1P3AX      SP       In      0.000     1.765 r     -         
-=================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 
@@ -422,13 +408,13 @@ Instance       Reference     Type        Pin     Net            Time        Slac
 Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
 LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
 n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
 ==================================================================================
 
 
@@ -608,13 +594,15 @@ Detailed Report for Clock: nCRAS
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
 
 
 Ending Points with Worst Slack
@@ -624,11 +612,11 @@ Ending Points with Worst Slack
 Instance       Reference     Type         Pin     Net                Time         Slack 
                Clock                                                                    
 ----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
 ========================================================================================
 
 
@@ -643,12 +631,12 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -656,15 +644,15 @@ Path information for path number 1:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
 ========================================================================================
 
 
@@ -674,12 +662,12 @@ Path information for path number 2:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRWE_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -687,15 +675,15 @@ Path information for path number 2:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
 ========================================================================================
 
 
@@ -705,29 +693,29 @@ Path information for path number 3:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
+    Starting point:                          CBR / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
 
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
 
 
 Path information for path number 4: 
@@ -736,28 +724,28 @@ Path information for path number 4:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                       Pin      Pin               Arrival     No. of    
 Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
 --------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCS_0io_RNO            ORCALUT4     B        In      0.000     2.237 r     -         
-nRCS_0io_RNO            ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_27_i                  Net          -        -       -         -           1         
-nRCS_0io                OFS1P3BX     D        In      0.000     2.853 f     -         
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
 ======================================================================================
 
 
@@ -767,75 +755,142 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.837
+    - Propagation time:                      2.741
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.749
+    = Slack (non-critical) :                 -1.653
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                  Pin      Pin               Arrival     No. of    
 Name               Type         Name     Dir     Delay     Time        Fan Out(s)
 ---------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                Net          -        -       -         -           7         
-nRCS_0io_RNO_0     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.221 f     -         
-N_27_i_sn          Net          -        -       -         -           1         
-nRCS_0io_RNO       ORCALUT4     C        In      0.000     2.221 f     -         
-nRCS_0io_RNO       ORCALUT4     Z        Out     0.617     2.837 r     -         
-N_27_i             Net          -        -       -         -           1         
-nRCS_0io           OFS1P3BX     D        In      0.000     2.837 r     -         
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
 =================================================================================
 
 
 
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
 ##### END OF TIMING REPORT #####]
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 90 of 640 (14%)
+Register bits: 109 of 640 (17%)
 PIC Latch:       0
-I/O cells:       67
+I/O cells:       63
 
 
 Details:
 BB:             8
 CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
 FD1S3IX:        3
 GSR:            1
-IB:             26
+IB:             25
 IFS1P3DX:       9
-INV:            7
-OB:             33
+INV:            8
+OB:             30
 OFS1P3BX:       4
-OFS1P3DX:       12
+OFS1P3DX:       11
 OFS1P3JX:       1
-ORCALUT4:       135
+ORCALUT4:       206
 PFUMX:          1
 PUR:            1
-VHI:            1
-VLO:            1
+VHI:            2
+VLO:            2
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 22:34:24 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr.db
similarity index 61%
rename from CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr.db
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr.db
index 29d1798..1fafb7e 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr.db and b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.srr.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.szr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.szr
new file mode 100644
index 0000000..f71e97c
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_fpga_mapper.szr differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
similarity index 87%
rename from CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
index ec10a55..3622db3 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr
@@ -16,13 +16,13 @@ Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
 @N|Running in 64-bit mode
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 23:12:42 2023
+# Wed Aug 16 20:58:39 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_scck.rpt.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr.db
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/impl1_scck.rpt.db
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_multi_srs_gen.srr.db
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
similarity index 70%
rename from CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
index a6d05c0..c10e02c 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr
@@ -1,4 +1,4 @@
-# Tue Aug 15 22:34:20 2023
+# Wed Aug 16 20:59:30 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -20,11 +20,11 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
 
 Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt"
+@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@@ -35,7 +35,7 @@ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s
 Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
 
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
@@ -51,68 +51,67 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 @N: FX493 |Applying initial value "0" on instance LEDEN.
 @N: FX493 |Applying initial value "0" on instance n8MEGEN.
 @N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
 @N: FX493 |Applying initial value "0" on instance C1Submitted.
 @N: FX493 |Applying initial value "0" on instance CmdSubmitted.
 @N: FX493 |Applying initial value "0" on instance ADSubmitted.
 @N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 
-
 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
 
 Clock Summary
 ******************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 
 Clock Load Summary
 ***********************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
 
 ICG Latch Removal Summary:
 Number of ICG latches removed: 0
@@ -126,15 +125,15 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
 @KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
 @KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
@@ -145,19 +144,19 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 22:34:21 2023
+# Wed Aug 16 20:59:32 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db
similarity index 76%
rename from CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr.db
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db
index 2b0c182..9da85ab 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr.db and b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.srr.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr
new file mode 100644
index 0000000..efea1da
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.szr differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.xck b/CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.xck
rename to CPLD/LCMXO2-640HC/impl1/synlog/LCMXO2_640HC_impl1_premap.xck
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv.rptmap
deleted file mode 100644
index e89a2e5..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv.rptmap
+++ /dev/null
@@ -1 +0,0 @@
-./synwork/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv,RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.rptmap
deleted file mode 100644
index 83b0421..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr.rptmap
+++ /dev/null
@@ -1 +0,0 @@
-./synlog/RAM2GS_LCMXO2_640HC_impl1_compiler.srr,RAM2GS_LCMXO2_640HC_impl1_compiler.srr,Compile Log
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr
deleted file mode 100644
index 0e83cb2..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr
+++ /dev/null
@@ -1,657 +0,0 @@
-# Tue Aug 15 23:12:44 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -2.04ns		 140 /        90
-
-
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
-
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.389
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
-
-    - Propagation time:                      3.214
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
-========================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.853
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.szr b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.szr
deleted file mode 100644
index 10c6f70..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.szr and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr.db
deleted file mode 100644
index 33612a2..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr
deleted file mode 100644
index a0083f3..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr
+++ /dev/null
@@ -1,162 +0,0 @@
-# Tue Aug 15 23:12:42 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr.db
deleted file mode 100644
index ea25651..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.szr b/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.szr
deleted file mode 100644
index a17b0bf..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/RAM2GS_LCMXO2_640HC_impl1_premap.szr and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_comp.rt.csv.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_comp.rt.csv.rptmap
deleted file mode 100644
index 38b18f8..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_comp.rt.csv.rptmap
+++ /dev/null
@@ -1 +0,0 @@
-./synwork/impl1_comp.rt.csv,impl1_comp.rt.csv,Module Runtime Summary
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr
deleted file mode 100644
index 9dfedb6..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr
+++ /dev/null
@@ -1,112 +0,0 @@
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
-
-@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
-
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-Options changed - recompiling
-Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:18 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:18 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:18 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.db
deleted file mode 100644
index 75e3067..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.rptmap
deleted file mode 100644
index a67038c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_compiler.srr.rptmap
+++ /dev/null
@@ -1 +0,0 @@
-./synlog/impl1_compiler.srr,impl1_compiler.srr,Compile Log
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr.db
deleted file mode 100644
index 2f4fc14..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.szr b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.szr
deleted file mode 100644
index 8654366..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_fpga_mapper.szr and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr
deleted file mode 100644
index 1c2ca5c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_multi_srs_gen.srr
+++ /dev/null
@@ -1,29 +0,0 @@
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:19 2023
-
-###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr.db b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr.db
deleted file mode 100644
index 664c090..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.srr.db and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.szr b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.szr
deleted file mode 100644
index c43a832..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.szr and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.xck b/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.xck
deleted file mode 100644
index 465056f..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/impl1_premap.xck
+++ /dev/null
@@ -1,4 +0,0 @@
-ckid0_0:@|S:RCLK@|E:nRWE@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0
-ckid0_1:@|S:PHI2@|E:RA11@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1
-ckid0_2:@|S:nCCAS@|E:WRD[7:0]@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2
-ckid0_3:@|S:nCRAS@|E:RowA[9:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
new file mode 100644
index 0000000..05efd23
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_errors.txt
@@ -0,0 +1,2 @@
+@E: CS168 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":72:15:72:15|Port WBCLKI does not exist
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt
new file mode 100644
index 0000000..a4cc1cf
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_notes.txt
@@ -0,0 +1,9 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N|Running in 64-bit mode
+
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_warnings.txt
new file mode 100644
index 0000000..2448168
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_compiler_warnings.txt
@@ -0,0 +1,2 @@
+@W: CG360 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":72:6:72:12|Removing wire ufm_irq, as there is no assignment to it.
+
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.fse b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_errors.txt
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/impl1.fse
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_errors.txt
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
similarity index 51%
rename from CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_notes.txt
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
index 1da1bf7..76f0d50 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_notes.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_notes.txt
@@ -1,15 +1,18 @@
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":148:4:148:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
 @N: FX493 |Applying initial value "0" on instance IS[0].
 @N: FX493 |Applying initial value "0" on instance IS[1].
 @N: FX493 |Applying initial value "0" on instance IS[2].
 @N: FX493 |Applying initial value "0" on instance IS[3].
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":302:4:302:9|Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":161:4:161:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-lcmxo2.v":119:4:119:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
+@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 @N: MT615 |Found clock RCLK with period 16.00ns 
 @N: MT615 |Found clock PHI2 with period 350.00ns 
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
new file mode 100644
index 0000000..be4701a
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
@@ -0,0 +1,28 @@
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 109 of 640 (17%)
+PIC Latch:       0
+I/O cells:       63
+
+Details:
+BB:             8
+CCU2D:          10
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
+FD1S3IX:        3
+GSR:            1
+IB:             25
+IFS1P3DX:       9
+INV:            8
+OB:             30
+OFS1P3BX:       4
+OFS1P3DX:       11
+OFS1P3JX:       1
+ORCALUT4:       206
+PFUMX:          1
+PUR:            1
+VHI:            2
+VLO:            2
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
similarity index 77%
rename from CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
index b7e853c..d66136f 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_fpga_mapper_warnings.txt
@@ -1,6 +1,7 @@
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT246 :"d:\onedrive\documents\github\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
+@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
 @W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
 @W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_combined_clk.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
similarity index 80%
rename from CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_combined_clk.rpt
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
index 7fbc557..19787e5 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_combined_clk.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_combined_clk.rpt
@@ -6,15 +6,15 @@
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
+@KP:ckid0_0       RCLK                port                   65         nRWE           
+@KP:ckid0_1       PHI2                port                   18         RA11           
 @KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
 @KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp2.lpf b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_errors.txt
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp2.lpf
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_errors.txt
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
similarity index 79%
rename from CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_notes.txt
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
index d90f08b..dad55c4 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_notes.txt
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_notes.txt
@@ -11,16 +11,12 @@
 @N: FX493 |Applying initial value "0" on instance LEDEN.
 @N: FX493 |Applying initial value "0" on instance n8MEGEN.
 @N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
+@N: FX493 |Applying initial value "0" on instance CMDUFMWrite.
+@N: FX493 |Applying initial value "0" on instance CmdUFMData.
 @N: FX493 |Applying initial value "0" on instance C1Submitted.
 @N: FX493 |Applying initial value "0" on instance CmdSubmitted.
 @N: FX493 |Applying initial value "0" on instance ADSubmitted.
 @N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
 @N: FX493 |Applying initial value "0" on instance CmdEnable.
 @N: FX493 |Applying initial value "1" on instance nRWE.
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_warnings.txt
rename to CPLD/LCMXO2-640HC/impl1/synlog/report/LCMXO2_640HC_impl1_premap_warnings.txt
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_compiler_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_compiler_notes.txt
deleted file mode 100644
index 434a18f..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_compiler_notes.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-@N|Running in 64-bit mode
-
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_errors.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
deleted file mode 100644
index 12a0407..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_fpga_mapper_resourceusage.rpt
+++ /dev/null
@@ -1,27 +0,0 @@
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/RAM2GS_LCMXO2_640HC_impl1_premap_errors.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_compiler_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_compiler_notes.txt
deleted file mode 100644
index 89868fe..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_compiler_notes.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
-@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
-@N|Running in 64-bit mode
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
-
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_errors.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_notes.txt
deleted file mode 100644
index 6dc71d8..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_notes.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MT204 |Auto Constrain mode is disabled because the following clocks are already defined:
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N: FX493 |Applying initial value "0" on instance IS[0].
-@N: FX493 |Applying initial value "0" on instance IS[1].
-@N: FX493 |Applying initial value "0" on instance IS[2].
-@N: FX493 |Applying initial value "0" on instance IS[3].
-@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-@N: MT615 |Found clock RCLK with period 16.00ns 
-@N: MT615 |Found clock PHI2 with period 350.00ns 
-@N: MT615 |Found clock nCRAS with period 350.00ns 
-@N: MT615 |Found clock nCCAS with period 350.00ns 
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt
deleted file mode 100644
index 12a0407..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_resourceusage.rpt
+++ /dev/null
@@ -1,27 +0,0 @@
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_warnings.txt
deleted file mode 100644
index b7e853c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_fpga_mapper_warnings.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
-@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
-@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_combined_clk.rpt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_combined_clk.rpt
deleted file mode 100644
index 7fbc557..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_combined_clk.rpt
+++ /dev/null
@@ -1,24 +0,0 @@
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       RCLK                port                   48         nRWE           
-@KP:ckid0_1       PHI2                port                   19         RA11           
-@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
-@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_errors.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_errors.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_notes.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_notes.txt
deleted file mode 100644
index d90f08b..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_notes.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX493 |Applying initial value "0" on instance InitReady.
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "0" on instance RCKE.
-@N: FX493 |Applying initial value "1" on instance nRCAS.
-@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
-@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRCS.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "0" on instance n8MEGEN.
-@N: FX493 |Applying initial value "1" on instance nRRAS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
-@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
-@N: FX493 |Applying initial value "0" on instance C1Submitted.
-@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
-@N: FX493 |Applying initial value "0" on instance ADSubmitted.
-@N: FX493 |Applying initial value "0" on instance XOR8MEG.
-@N: FX493 |Applying initial value "1" on instance nUFMCS.
-@N: FX493 |Applying initial value "0" on instance UFMSDI.
-@N: FX493 |Applying initial value "0" on instance UFMCLK.
-@N: FX493 |Applying initial value "0" on instance CmdEnable.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_warnings.txt b/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_warnings.txt
deleted file mode 100644
index 81e8ed8..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synlog/report/impl1_premap_warnings.txt
+++ /dev/null
@@ -1 +0,0 @@
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db b/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db
index d36c7c6..4c61203 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db and b/CPLD/LCMXO2-640HC/impl1/synlog/report/metrics.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap b/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
index 58034cf..4359284 100644
--- a/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
+++ b/CPLD/LCMXO2-640HC/impl1/synlog/syntax_constraint_check.rpt.rptmap
@@ -1 +1 @@
-./RAM2GS_LCMXO2_640HC_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+./LCMXO2_640HC_impl1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2-640HC/impl1/synthesis.log
deleted file mode 100644
index c8e59c3..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synthesis.log
+++ /dev/null
@@ -1,237 +0,0 @@
-synthesis:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:22 2023
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
-
-Synthesis options:
-The -a option is MachXO2.
-The -s option is 4.
-The -t option is TQFP100.
-The -d option is LCMXO2-640HC.
-Using package TQFP100.
-Using performance grade 4.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO2
-
-### Device  : LCMXO2-640HC
-
-### Package : TQFP100
-
-### Speed   : 4
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
-Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
-NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 877 (11 % )
-BB => 8
-CCU2D => 10
-FD1P3AX => 29
-FD1P3AY => 5
-FD1P3IX => 3
-FD1S3AX => 47
-FD1S3IX => 14
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-LUT4 => 122
-OB => 33
-PFUMX => 1
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 14
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : RCLK_c_enable_6, loads : 4
-  Net : PHI2_N_120_enable_8, loads : 3
-  Net : RCLK_c_enable_10, loads : 3
-  Net : RCLK_c_enable_5, loads : 2
-  Net : PHI2_N_120_enable_3, loads : 1
-  Net : Ready_N_292, loads : 1
-  Net : PHI2_N_120_enable_2, loads : 1
-  Net : RCLK_c_enable_15, loads : 1
-  Net : PHI2_N_120_enable_6, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : InitReady, loads : 15
-  Net : nCRAS_c__inv, loads : 15
-  Net : RASr2, loads : 14
-  Net : nRowColSel_N_35, loads : 13
-  Net : n2380, loads : 13
-  Net : nRowColSel, loads : 12
-  Net : Ready, loads : 12
-  Net : Din_c_4, loads : 10
-  Net : MAin_c_1, loads : 10
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 53.555  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.828  secs
---------------------------------------------------------------
diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html
deleted file mode 100644
index c8b6b6a..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html
+++ /dev/null
@@ -1,302 +0,0 @@
-
-Synthesis and Ngdbuild Report
-
-
-
    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:22 2023
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
-
-Synthesis options:
-The -a option is MachXO2.
-The -s option is 4.
-The -t option is TQFP100.
-The -d option is LCMXO2-640HC.
-Using package TQFP100.
-Using performance grade 4.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO2
-
-### Device  : LCMXO2-640HC
-
-### Package : TQFP100
-
-### Speed   : 4
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
-Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
-NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 877 (11 % )
-BB => 8
-CCU2D => 10
-FD1P3AX => 29
-FD1P3AY => 5
-FD1P3IX => 3
-FD1S3AX => 47
-FD1S3IX => 14
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-LUT4 => 122
-OB => 33
-PFUMX => 1
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 14
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : RCLK_c_enable_6, loads : 4
-  Net : PHI2_N_120_enable_8, loads : 3
-  Net : RCLK_c_enable_10, loads : 3
-  Net : RCLK_c_enable_5, loads : 2
-  Net : PHI2_N_120_enable_3, loads : 1
-  Net : Ready_N_292, loads : 1
-  Net : PHI2_N_120_enable_2, loads : 1
-  Net : RCLK_c_enable_15, loads : 1
-  Net : PHI2_N_120_enable_6, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : InitReady, loads : 15
-  Net : nCRAS_c__inv, loads : 15
-  Net : RASr2, loads : 14
-  Net : nRowColSel_N_35, loads : 13
-  Net : n2380, loads : 13
-  Net : nRowColSel, loads : 12
-  Net : Ready, loads : 12
-  Net : Din_c_4, loads : 10
-  Net : MAin_c_1, loads : 10
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 53.555  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.828  secs
---------------------------------------------------------------
-
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-
    
-
-
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg
new file mode 100644
index 0000000..591b2fe
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1.plg
@@ -0,0 +1,29 @@
+@P:  Worst Slack : -1.832
+@P:  PHI2 - Estimated Frequency : 1.0 MHz
+@P:  PHI2 - Requested Frequency : 2.9 MHz
+@P:  PHI2 - Estimated Period : 991.270
+@P:  PHI2 - Requested Period : 350.000
+@P:  PHI2 - Slack : -1.832
+@P:  RCLK - Estimated Frequency : 22.1 MHz
+@P:  RCLK - Requested Frequency : 62.5 MHz
+@P:  RCLK - Estimated Period : 45.315
+@P:  RCLK - Requested Period : 16.000
+@P:  RCLK - Slack : -0.784
+@P:  nCCAS - Estimated Frequency : NA
+@P:  nCCAS - Requested Frequency : 2.9 MHz
+@P:  nCCAS - Estimated Period : NA
+@P:  nCCAS - Requested Period : 350.000
+@P:  nCCAS - Slack : NA
+@P:  nCRAS - Estimated Frequency : 1.0 MHz
+@P:  nCRAS - Requested Frequency : 2.9 MHz
+@P:  nCRAS - Estimated Period : 953.610
+@P:  nCRAS - Requested Period : 350.000
+@P:  nCRAS - Slack : -1.725
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : NA
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 15.472
+@P:  Total Area : 214.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
similarity index 82%
rename from CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
rename to CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
index ba0d843..6e98078 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm
@@ -1,5 +1,5 @@
 
    -
+
 ###########################################################[
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -17,15 +17,15 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+@N: :  | Running in 64-bit mode 
+File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs changed - recompiling
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:24:08 2023
+# Wed Aug 16 20:58:39 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
similarity index 64%
rename from CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
rename to CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
index d69e3c9..f7a9a65 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm
@@ -12,12 +12,9 @@
 
 
  • Synthesis -   
 
    • 
-
  • Place and Route -   
-
    • 
-
  • Session Log (22:31 15-Aug)  
+
  • Compiler Constraint Applicator  
    • 
+
  • Constraint Checker Report (20:58 16-Aug)  
    • 
+
  • Session Log (20:59 16-Aug)  
 
      •          
         
    
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
similarity index 55%
rename from CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm
rename to CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
index 7408ad9..741590b 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm
@@ -1,11 +1,11 @@
 
      -
+
 #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
 #install: C:\lscc\diamond\3.12\synpbase
 #OS: Windows 8 6.2
 #Hostname: ZANEPC
 
-# Tue Aug 15 22:34:17 2023
+# Wed Aug 16 20:59:29 2023
 
 #Implementation: impl1
 
@@ -25,7 +25,7 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 ###########################################################[
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -43,38 +43,57 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
-@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 
-
-@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 
-
+@N: :  | Running in 64-bit mode 
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
-Options changed - recompiling
+
+Compiler output is up to date.  No re-compile necessary
+
 Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
+@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : machxo2.v(1124) | Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : machxo2.v(1800) | Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : REFB.v(8) | Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : RAM2GS-LCMXO2.v(1) | Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
 Linked File:  layer0.rt.csv
 
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 ###########################################################[
@@ -94,22 +113,23 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
+@N: :  | Running in 64-bit mode 
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-Linked File:  impl1_comp.rt.csv
+Linked File:  LCMXO2_640HC_impl1_comp.rt.csv
 
 @END
 
@@ -118,53 +138,30 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 
      
 
      -
-###########################################################[
+
 
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:19 2023
-
-###########################################################]
+@A: :  | multi_srs_gen output is up to date. No run necessary. 
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+Linked File:  LCMXO2_640HC_impl1_multi_srs_gen.srr
 
 
      
 
      -
+
 Premap Report
 
 
 
      
 
      -
-# Tue Aug 15 22:34:20 2023
+
+# Wed Aug 16 20:59:30 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -186,14 +183,14 @@ Implementation : impl1
 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
 
 Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+Linked File:  LCMXO2_640HC_impl1_scck.rpt
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
 
 Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
@@ -201,84 +198,83 @@ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s
 Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
 
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CMDUFMWrite. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMData. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
 
 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
 
 Clock Summary
 ******************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 
 Clock Load Summary
 ***********************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
 
 ICG Latch Removal Summary:
 Number of ICG latches removed: 0
@@ -292,52 +288,52 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+ClockId_0_0       RCLK                port                   65         nRWE           
+ClockId_0_1       PHI2                port                   18         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
 
 
 ##### END OF CLOCK OPTIMIZATION REPORT ######
 
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 22:34:21 2023
+# Wed Aug 16 20:59:32 2023
 
 ###########################################################]
 
 
      
 
      -
+
 Map & Optimize Report
 
 
 
      
 
      -
-# Tue Aug 15 22:34:22 2023
+
+# Wed Aug 16 20:59:32 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -356,11 +352,11 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
 
 Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
 
@@ -377,103 +373,98 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 
 Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
 
-@N:MT204 :  | Auto Constrain mode is disabled because the following clocks are already defined: 
-
-            RCLK
-            PHI2
-            nCRAS
-            nCCAS
-
 
 Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+@N:MO231 : ram2gs-lcmxo2.v(161) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-lcmxo2.v(148) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N:FX271 : ram2gs-lcmxo2.v(302) | Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(161) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
 
-   4		0h:00m:01s		    -2.04ns		 140 /        90
+   4		0h:00m:01s		    -1.83ns		 210 /       109
 
 
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 177MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_m.srm
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
 
 Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
 
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+@W:MT246 : refb.v(78) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 22:34:24 2023
+# Timing report written on Wed Aug 16 20:59:35 2023
 #
 
 
@@ -483,9 +474,9 @@ Wire load mode:         top
 Paths requested:        5
 Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
                        
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
 
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
 
 
 
@@ -493,41 +484,44 @@ Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
 *******************
 
 
-Worst slack in design: -2.389
+Worst slack in design: -1.832
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
 nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
 
 
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
 
 
 
 Clock Relationships
 *******************
 
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
@@ -549,46 +543,46 @@ No IO constraint found
 Starting Points with Worst Slack
 ********************************
 
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
 
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -598,122 +592,110 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 2: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
 
 
 Path information for path number 3: 
       Requested Period:                      1.000
-    - Setup time:                            -0.462
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
+    = Required time:                         0.528
 
-    - Propagation time:                      3.214
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 4: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.605
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.517
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdUFMCS / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdUFMCS             FD1P3AX      Q        Out     0.972     0.972 r     -         
-CmdUFMCS             Net          -        -       -         -           1         
-nUFMCS_s_0_m4_yy     ORCALUT4     A        In      0.000     0.972 r     -         
-nUFMCS_s_0_m4_yy     ORCALUT4     Z        Out     1.017     1.989 r     -         
-nUFMCS_s_0_m4_yy     Net          -        -       -         -           1         
-nUFMCS_s_0_N_5_i     ORCALUT4     C        In      0.000     1.989 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.605 f     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.605 f     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 5: 
@@ -722,26 +704,26 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      1.765
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.236
+    = Slack (critical) :                     -1.832
 
     Number of logic level(s):                1
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            LEDEN / SP
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CmdSubmitted       FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted       Net          -        -       -         -           4         
-un1_FS_13_i_0      ORCALUT4     A        In      0.000     1.148 r     -         
-un1_FS_13_i_0      ORCALUT4     Z        Out     0.617     1.765 r     -         
-N_28               Net          -        -       -         -           1         
-LEDEN              FD1P3AX      SP       In      0.000     1.765 r     -         
-=================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 
@@ -762,13 +744,13 @@ Instance       Reference     Type        Pin     Net            Time        Slac
 Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
 LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
 n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
 ==================================================================================
 
 
@@ -794,7 +776,7 @@ RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -949,13 +931,15 @@ RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
 
 
 Ending Points with Worst Slack
@@ -965,17 +949,17 @@ FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
 Instance       Reference     Type         Pin     Net                Time         Slack 
                Clock                                                                    
 ----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
 ========================================================================================
 
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -985,12 +969,12 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -998,15 +982,15 @@ Path information for path number 1:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
 ========================================================================================
 
 
@@ -1016,12 +1000,12 @@ Path information for path number 2:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRWE_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -1029,15 +1013,15 @@ Path information for path number 2:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
 ========================================================================================
 
 
@@ -1047,29 +1031,29 @@ Path information for path number 3:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
+    Starting point:                          CBR / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
 
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
 
 
 Path information for path number 4: 
@@ -1078,28 +1062,28 @@ Path information for path number 4:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                       Pin      Pin               Arrival     No. of    
 Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
 --------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCS_0io_RNO            ORCALUT4     B        In      0.000     2.237 r     -         
-nRCS_0io_RNO            ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_27_i                  Net          -        -       -         -           1         
-nRCS_0io                OFS1P3BX     D        In      0.000     2.853 f     -         
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
 ======================================================================================
 
 
@@ -1109,76 +1093,144 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.837
+    - Propagation time:                      2.741
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.749
+    = Slack (non-critical) :                 -1.653
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                  Pin      Pin               Arrival     No. of    
 Name               Type         Name     Dir     Delay     Time        Fan Out(s)
 ---------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                Net          -        -       -         -           7         
-nRCS_0io_RNO_0     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.221 f     -         
-N_27_i_sn          Net          -        -       -         -           1         
-nRCS_0io_RNO       ORCALUT4     C        In      0.000     2.221 f     -         
-nRCS_0io_RNO       ORCALUT4     Z        Out     0.617     2.837 r     -         
-N_27_i             Net          -        -       -         -           1         
-nRCS_0io           OFS1P3BX     D        In      0.000     2.837 r     -         
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
 =================================================================================
 
 
 
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
 ##### END OF TIMING REPORT #####]
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
 
 ---------------------------------------
-Resource Usage Report
+Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 90 of 640 (14%)
+Register bits: 109 of 640 (17%)
 PIC Latch:       0
-I/O cells:       67
+I/O cells:       63
 
 
 Details:
 BB:             8
 CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
 FD1S3IX:        3
 GSR:            1
-IB:             26
+IB:             25
 IFS1P3DX:       9
-INV:            7
-OB:             33
+INV:            8
+OB:             30
 OFS1P3BX:       4
-OFS1P3DX:       12
+OFS1P3DX:       11
 OFS1P3JX:       1
-ORCALUT4:       135
+ORCALUT4:       206
 PFUMX:          1
 PUR:            1
-VHI:            1
-VLO:            1
+VHI:            2
+VLO:            2
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 22:34:24 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
new file mode 100644
index 0000000..d3b0487
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
@@ -0,0 +1,60 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg
deleted file mode 100644
index 3b8cd49..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg
+++ /dev/null
@@ -1,23 +0,0 @@
-@P:  Worst Slack : -2.389
-@P:  PHI2 - Estimated Frequency : 0.8 MHz
-@P:  PHI2 - Requested Frequency : 2.9 MHz
-@P:  PHI2 - Estimated Period : 1186.150
-@P:  PHI2 - Requested Period : 350.000
-@P:  PHI2 - Slack : -2.389
-@P:  RCLK - Estimated Frequency : 18.4 MHz
-@P:  RCLK - Requested Frequency : 62.5 MHz
-@P:  RCLK - Estimated Period : 54.224
-@P:  RCLK - Requested Period : 16.000
-@P:  RCLK - Slack : -0.784
-@P:  nCCAS - Estimated Frequency : NA
-@P:  nCCAS - Requested Frequency : 2.9 MHz
-@P:  nCCAS - Estimated Period : NA
-@P:  nCCAS - Requested Period : 350.000
-@P:  nCCAS - Slack : NA
-@P:  nCRAS - Estimated Frequency : 1.0 MHz
-@P:  nCRAS - Requested Frequency : 2.9 MHz
-@P:  nCRAS - Estimated Period : 987.210
-@P:  nCRAS - Requested Period : 350.000
-@P:  nCRAS - Slack : -1.821
-@P:  Total Area : 142.0
-@P:  CPU Time : 0h:00m:02s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm
deleted file mode 100644
index cf508f4..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm
+++ /dev/null
@@ -1,983 +0,0 @@
-
      -
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Tue Aug 15 23:12:41 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-Linked File:  layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-Linked File:  RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-
      
-
      -
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:42 2023
-
-###########################################################]
-
-
      
-
      -
-# Tue Aug 15 23:12:42 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  RAM2GS_LCMXO2_640HC_impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
-
-###########################################################]
-
-
      
-
      -
-# Tue Aug 15 23:12:44 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -2.04ns		 140 /        90
-
-
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
-
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.389
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
-
-    - Propagation time:                      3.214
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
-========================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.853
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
-
-###########################################################]
-
-
      
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm
deleted file mode 100644
index dd30c89..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm
+++ /dev/null
@@ -1,58 +0,0 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
- 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
index 67c8bf4..b95cb8d 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
@@ -1,10 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
+C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v  -jobname  "compiler" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-LCMXO2.v -lib work -fv2001 ..\..\REFB.v -jobname "compiler"
 rc:0 success:1 runtime:1
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs|io:o|time:1692155561|size:10463|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692155561|size:4591|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:o|time:1692233918|size:21157|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692233969|size:6365|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
 file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\..\RAM2GS-SPI.v|io:i|time:1692155394|size:11758|exec:0|csum:1D033D06BAC573F583D1480CDDD96F81
+file:..\..\..\RAM2GS-LCMXO2.v|io:i|time:1692233914|size:28573|exec:0|csum:28E8FB7DCCB7771914C4CAAAD23A3A6B
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\REFB.v|io:i|time:1692233522|size:5624|exec:0|csum:AE22D4C116724FF57C15D0DA14242382
 file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
index 9cc96e0..77a28d0 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\RAM2GS_LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO2_640HC_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO2_640HC_impl1.plg -osyn ..\RAM2GS_LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -oedif ..\LCMXO2_640HC_impl1.edi -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
 rc:1 success:1 runtime:3
-file:..\RAM2GS_LCMXO2_640HC_impl1.edi|io:o|time:1692155566|size:135533|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233975|size:204145|exec:0|csum:
 file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:i|time:1692155563|size:16785|exec:0|csum:E0DA21F06B7F0F84BB4B88EF6879699C
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:i|time:1692233971|size:28839|exec:0|csum:6AF572CB579AF7B57405A148BF7BEB9E
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO2_640HC_impl1.plg|io:o|time:1692155567|size:853|exec:0|csum:
-file:..\RAM2GS_LCMXO2_640HC_impl1.srm|io:o|time:1692155566|size:30417|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692155567|size:35619|exec:0|csum:
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692233975|size:1070|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.srm|io:o|time:1692233974|size:38081|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692233975|size:50128|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
index b38047b..cf97934 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -1,7 +1,7 @@
-C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr
+C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\LCMXO2_640HC_impl1_mult.srs -log ..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr
 rc:0 success:1 runtime:0
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs|io:i|time:1692155561|size:10463|exec:0|csum:43BAA23EACACCD6D11E31E1651718DD7
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs|io:o|time:1692155562|size:10332|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692155562|size:1163|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:i|time:1692233918|size:21157|exec:0|csum:BB526DCCC65867AFD6AA24AF2B7D8510
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:o|time:1692233919|size:13269|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692233919|size:1156|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
index 3ea9f3a..736b297 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
@@ -1,14 +1,14 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\RAM2GS_LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_cck.rpt   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\RAM2GS_LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO2_640HC_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO2_640HC_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO2_640HC_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_cck.rpt   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -oedif ..\LCMXO2_640HC_impl1.edi -conchk_prepass ..\LCMXO2_640HC_impl1_cck.rpt -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\synwork\LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
 rc:1 success:1 runtime:2
-file:..\RAM2GS_LCMXO2_640HC_impl1.edi|io:o|time:1692155404|size:135532|exec:0|csum:
-file:..\RAM2GS_LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692155564|size:4751|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233923|size:210943|exec:0|csum:
+file:..\LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692233972|size:4979|exec:0|csum:
 file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs|io:i|time:1692155562|size:10332|exec:0|csum:0BE029DC3BEEF698461F9E379A2ED022
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:o|time:1692155563|size:16785|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:i|time:1692233919|size:13269|exec:0|csum:9E33176D7D9CB39EFA557E27492465CA
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO2_640HC_impl1.plg|io:o|time:1692155563|size:0|exec:0|csum:
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:o|time:1692155563|size:16785|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr|io:o|time:1692155564|size:8429|exec:0|csum:
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692233970|size:0|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_premap.srr|io:o|time:1692233972|size:8565|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg
deleted file mode 100644
index 3b8cd49..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg
+++ /dev/null
@@ -1,23 +0,0 @@
-@P:  Worst Slack : -2.389
-@P:  PHI2 - Estimated Frequency : 0.8 MHz
-@P:  PHI2 - Requested Frequency : 2.9 MHz
-@P:  PHI2 - Estimated Period : 1186.150
-@P:  PHI2 - Requested Period : 350.000
-@P:  PHI2 - Slack : -2.389
-@P:  RCLK - Estimated Frequency : 18.4 MHz
-@P:  RCLK - Requested Frequency : 62.5 MHz
-@P:  RCLK - Estimated Period : 54.224
-@P:  RCLK - Requested Period : 16.000
-@P:  RCLK - Slack : -0.784
-@P:  nCCAS - Estimated Frequency : NA
-@P:  nCCAS - Requested Frequency : 2.9 MHz
-@P:  nCCAS - Estimated Period : NA
-@P:  nCCAS - Requested Period : 350.000
-@P:  nCCAS - Slack : NA
-@P:  nCRAS - Estimated Frequency : 1.0 MHz
-@P:  nCRAS - Requested Frequency : 2.9 MHz
-@P:  nCRAS - Estimated Period : 987.210
-@P:  nCRAS - Requested Period : 350.000
-@P:  nCRAS - Slack : -1.821
-@P:  Total Area : 142.0
-@P:  CPU Time : 0h:00m:02s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm
deleted file mode 100644
index b6ef59b..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm
+++ /dev/null
@@ -1,55 +0,0 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
- 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
index 5f88a13..9175808 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
@@ -12,7 +12,7 @@
    Project Name  proj_1  Device Name  impl1: Lattice MachXO2 : LCMXO2_640HC 
   Implementation Name  impl1  Top Module  RAM2GS 
  		  
-		    Pipelining  0  Retiming  0 
+		    Pipelining  1  Retiming  0 
   Resource Sharing  1  Fanout Guide  1000 
   Disable I/O Insertion  0  Disable Sequential Optimizations  0 
   Clock Conversion  1  FSM Compiler  1 
@@ -34,40 +34,38 @@
          
   
    (compiler)Complete
- 4
+ 8
 0
 0
 -
 00m:00s
 -
-8/15/2023
      11:12:41 PM
+8/16/2023
      8:59:29 PM
  
 
  
    (premap)Complete
- 27
+ 23
  1
 0
 0m:01s
 0m:01s
-174MB
-8/15/2023
      11:12:44 PM
+175MB
+8/16/2023
      8:59:32 PM
  
 
  
    (fpga_mapper)Complete
- 19
- 6
+ 22
+ 7
 0
-0m:02s
-0m:02s
-184MB
-8/15/2023
      11:12:47 PM
+0m:03s
+0m:03s
+193MB
+8/16/2023
      8:59:35 PM
  
 
-
-  Multi-srs Generator
-  Complete8/15/2023
      11:12:42 PM 		
+ 		
      
  
       
  
@@ -75,8 +73,8 @@
  
-
-
+
+
+(total_luts)
       
       
       
         
   
      Register bits 90I/O cells 67Register bits 109I/O cells 63
 
      
 
       
 Block RAMs
@@ -86,7 +84,7 @@
 
      
 
       
 ORCA LUTs
-(total_luts) 135 206
 
       
       
     

      
@@ -96,10 +94,11 @@
   
  
    Clock NameReq FreqEst FreqSlack 
- PHI22.9 MHz0.8 MHz-2.389 
- RCLK62.5 MHz18.4 MHz-0.784 
+ PHI22.9 MHz1.0 MHz-1.832 
+ RCLK62.5 MHz22.1 MHz-0.784 
  nCCAS2.9 MHzNANA 
- nCRAS2.9 MHz1.0 MHz-1.821 
+ nCRAS2.9 MHz1.0 MHz-1.725 
+ System100.0 MHzNA15.472 
  
  
 
      
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer b/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer
index 5aa3ef0..5be0367 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer and b/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
new file mode 100644
index 0000000..68dc0e5
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
+0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work REFB 1
+module work RAM2GS 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
rename to CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs
new file mode 100644
index 0000000..c9a54d2
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m.srm
new file mode 100644
index 0000000..b926cbb
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/1.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/1.srm
new file mode 100644
index 0000000..15c11ca
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/1.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/fileinfo.srm
new file mode 100644
index 0000000..f43e3da
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/fileinfo.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
similarity index 97%
rename from CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr
rename to CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
index 4fc0177..bf5564a 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
@@ -1,12 +1,12 @@
 i RCLK
 m 0 0
-u 27 48
+u 30 65
 p {p:RCLK}{t:nRWE.C}
 e ckid0_0 {t:nRWE.C} dffs
 c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
 i PHI2
 m 0 0
-u 12 19
+u 11 18
 p {p:PHI2}{t:RA11.C}
 e ckid0_1 {t:RA11.C} sdffr
 c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs
new file mode 100644
index 0000000..e927913
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/1.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/1.srs
new file mode 100644
index 0000000..ea524b7
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/1.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/fileinfo.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/fileinfo.srs
new file mode 100644
index 0000000..bdbde5a
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/fileinfo.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/skeleton.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/skeleton.srs
new file mode 100644
index 0000000..9928be5
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/skeleton.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp4.lpf b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.fse
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/impl1_synplify_tmp4.lpf
rename to CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.fse
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srd b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srd
new file mode 100644
index 0000000..9c5ca3a
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srd differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srm
new file mode 100644
index 0000000..08c6830
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm
new file mode 100644
index 0000000..bfcc1db
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/fileinfo.srm
new file mode 100644
index 0000000..30acc28
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/fileinfo.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm
new file mode 100644
index 0000000..c919829
Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.fdep
deleted file mode 100644
index 75f8841..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.fdep
+++ /dev/null
@@ -1,16 +0,0 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\RAM2GS_LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692155394
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work RAM2GS 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.srs
deleted file mode 100644
index 28fd0b9..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m.srm
deleted file mode 100644
index 33a15e2..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/1.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/1.srm
deleted file mode 100644
index 3aed49f..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/1.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/fileinfo.srm
deleted file mode 100644
index 6bacc31..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/fileinfo.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.srs
deleted file mode 100644
index 2e048d5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/fileinfo.srs b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/fileinfo.srs
deleted file mode 100644
index 8d3d803..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/fileinfo.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/skeleton.srs b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/skeleton.srs
deleted file mode 100644
index ab3d38f..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult_srs/skeleton.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.fse b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.fse
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srd b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srd
deleted file mode 100644
index 0514ab5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srm
deleted file mode 100644
index b51d8b9..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/fileinfo.srm
deleted file mode 100644
index 77da4e0..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/fileinfo.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/skeleton.srm b/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/skeleton.srm
deleted file mode 100644
index 122ae4d..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_prem_srm/skeleton.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep
deleted file mode 100644
index 841c519..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep
+++ /dev/null
@@ -1,16 +0,0 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\impl1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-sysv|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692152477
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work RAM2GS 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.rt.csv
deleted file mode 100644
index 915b7cd..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.rt.csv
+++ /dev/null
@@ -1 +0,0 @@
-Library, Design Unit, compile Time, Peak Mem Usage
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs
deleted file mode 100644
index cf3e2d6..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m.srm
deleted file mode 100644
index b4d59f5..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/1.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/1.srm
deleted file mode 100644
index 0bac0a3..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/1.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/fileinfo.srm
deleted file mode 100644
index 6bacc31..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/fileinfo.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr
deleted file mode 100644
index 4fc0177..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr
+++ /dev/null
@@ -1,26 +0,0 @@
-i RCLK
-m 0 0
-u 27 48
-p {p:RCLK}{t:nRWE.C}
-e ckid0_0 {t:nRWE.C} dffs
-c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
-i PHI2
-m 0 0
-u 12 19
-p {p:PHI2}{t:RA11.C}
-e ckid0_1 {t:RA11.C} sdffr
-c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
-i nCCAS
-m 0 0
-u 1 8
-p {p:nCCAS}{t:CASr_2.I[0]}{t:CASr_2.OUT[0]}{t:WRD[7:0].C}
-e ckid0_2 {t:WRD[7:0].C} dff
-c ckid0_2 {p:nCCAS} port Unsupported/too complex instance on clock path
-i nCRAS
-m 0 0
-u 4 14
-p {p:nCRAS}{t:RASr_2.I[0]}{t:RASr_2.OUT[0]}{t:RowA[9:0].C}
-e ckid0_3 {t:RowA[9:0].C} sdffpatr
-c ckid0_3 {p:nCRAS} port Unsupported/too complex instance on clock path
-l 0 0 0 0 0 0
-r 0 0 0 0 0 0 0 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs
deleted file mode 100644
index 0afd997..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/fileinfo.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/fileinfo.srs
deleted file mode 100644
index 8d3d803..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/fileinfo.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/skeleton.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/skeleton.srs
deleted file mode 100644
index 601afd8..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/skeleton.srs and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.fse b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.fse
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srd b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srd
deleted file mode 100644
index c8bbb4f..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srd and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srm
deleted file mode 100644
index 3c33024..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm
deleted file mode 100644
index 77da4e0..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm
deleted file mode 100644
index da1f86c..0000000
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm and /dev/null differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
index 1b93d00..1a088e6 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
@@ -22,7 +22,7 @@ Modules that may have changed as a result of file changes: 0
 MID:  lib.cell.view
 
 *******************************************************************
-Unmodified files: 7
+Unmodified files: 8
 FID:  path (timestamp)
 0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v (2021-08-10 09:11:08)
 1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
@@ -30,9 +30,11 @@ FID:  path (timestamp)
 3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
 4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
 5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
-6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v (2023-08-15 23:09:54)
+7        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v (2023-08-16 20:52:02)
+6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v (2023-08-16 20:58:34)
 
 *******************************************************************
-Unchanged modules: 1
+Unchanged modules: 2
 MID:  lib.cell.view
 0        work.RAM2GS.verilog
+1        work.REFB.verilog
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
index 77735f2..b5d3d64 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
@@ -1,4 +1,4 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\RAM2GS_LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
+#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
@@ -6,13 +6,18 @@
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692155394
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
 #numinternalfiles:6
 #defaultlanguage:verilog
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
+0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
 #Dependency Lists(Uses List)
-0 -1
+0 1
+1 -1
 #Dependency Lists(Users Of)
 0 -1
+1 0
 #Design Unit to File Association
 module work RAM2GS 0
+module work REFB 1
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs
index e58feb9..8b59e6d 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs and b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
index 0cb1c41..1f02696 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg
@@ -1,9 +1,29 @@
 Selecting top level module RAM2GS
-@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db
index 3f6f00c..4c6c160 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db and b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.tlg.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/modulechange.db b/CPLD/LCMXO2-640HC/impl1/synwork/modulechange.db
index 6fcbcc8..3e1a35f 100644
Binary files a/CPLD/LCMXO2-640HC/impl1/synwork/modulechange.db and b/CPLD/LCMXO2-640HC/impl1/synwork/modulechange.db differ
diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
deleted file mode 100644
index 1c1a02c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
+++ /dev/null
@@ -1,250 +0,0 @@
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
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diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file
deleted file mode 100644
index 7e27975..0000000
--- a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file
+++ /dev/null
@@ -1,250 +0,0 @@
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-LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]"
-LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
-LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
-LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]"
-LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
-LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
-LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
-LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
-LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]"
-LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
-LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]"
-LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
diff --git a/CPLD/LCMXO2-640HC-old/msg_file.log b/CPLD/LCMXO2-640HC/msg_file.log
similarity index 69%
rename from CPLD/LCMXO2-640HC-old/msg_file.log
rename to CPLD/LCMXO2-640HC/msg_file.log
index e93ec92..6f835a7 100644
--- a/CPLD/LCMXO2-640HC-old/msg_file.log
+++ b/CPLD/LCMXO2-640HC/msg_file.log
@@ -1,5 +1,5 @@
-SCUBA, Version Diamond (64-bit) 3.12.0.240.2
-Tue Aug 17 05:48:29 2021
+SCUBA, Version Diamond (64-bit) 3.12.1.454
+Wed Aug 16 20:52:02 2023
   
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -9,20 +9,20 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
   
 BEGIN SCUBA Module Synthesis
   
-    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
-    Circuit name     : EFB
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : REFB
     Module type      : efb
     Module Version   : 1.2
     Ports            : 
     Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
     Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
     I/O buffer       : not inserted
-    EDIF output      : EFB.edn
-    Verilog output   : EFB.v
-    Verilog template : EFB_tmpl.v
+    EDIF output      : REFB.edn
+    Verilog output   : REFB.v
+    Verilog template : REFB_tmpl.v
     Verilog purpose  : for synthesis and simulation
     Bus notation     : big endian
-    Report output    : EFB.srp
+    Report output    : REFB.srp
     Estimated Resource Usage:
   
 END   SCUBA Module Synthesis
diff --git a/CPLD/RAM2GS-AGM.v b/CPLD/RAM2GS-AGM.v
new file mode 100644
index 0000000..0dc7503
--- /dev/null
+++ b/CPLD/RAM2GS-AGM.v
@@ -0,0 +1,425 @@
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML,
+              nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
+
+    /* 65816 Phase 2 Clock */
+    input PHI2;
+
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
+
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
+
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
+
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
+
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
+
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+
+    /* UFM Interface */
+    reg nUFMCS = 1;
+    reg UFMCLK = 0;
+    reg UFMSDI = 0;
+    wire UFMSDO;
+    wire UFMOsc;
+    alta_ufms u_alta_ufms (
+        .i_ufm_set (1'b1), 
+        .i_osc_ena (1'b1), 
+        .i_ufm_flash_csn (nUFMCS), 
+        .i_ufm_flash_sclk (UFMCLK), 
+        .i_ufm_flash_sdi (UFMSDI), 
+        .o_ufm_flash_sdo (UFMSDO), 
+        .o_osc (UFMOsc) 
+    );
+
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMCLK = 0;
+    reg CmdUFMSDI = 0;
+    reg CmdUFMCS = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
+
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
+
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
+
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
+
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
+
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // SPI (LCMXO, iCE40, AGM) commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMCS <= Din[2];
+                CmdUFMCLK <= Din[1];
+                CmdUFMSDI <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
+
+    /* UFM Control */
+    output nUFMCSout = nUFMCS;
+    output UFMCLKout = UFMCLK;
+    output UFMSDIout = UFMSDI;
+    output UFMSDOout = UFMSDO;
+    input [3:0] In;
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            case (FS[9:5]) // Shift out read data command (0x03)
+                5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
+                5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
+                5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
+                5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
+                5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
+                5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
+                5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
+                5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
+                5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
+                5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
+                5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
+                5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
+                5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
+                5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
+                5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
+                5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
+                5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
+                5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
+                5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
+                5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
+                5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
+                5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
+                5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
+                5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
+                5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
+                5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
+                5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
+                5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
+                5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
+                5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
+                5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
+                5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            UFMSDI <= 1'b0;
+            // Latch n8MEGEN and LEDEN
+            if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
+            if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
+        end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[1];
+            UFMSDI <= 1'b0;
+        end else if (~InitReady) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            nUFMCS <= ~CmdUFMCS;
+            UFMCLK <= CmdUFMCLK;
+            UFMSDI <= CmdUFMSDI;
+        end
+    end
+endmodule
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/RAM2GS-LCMXO2.lpf
similarity index 93%
rename from CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
rename to CPLD/RAM2GS-LCMXO2.lpf
index dbcda5a..2e973f9 100644
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
+++ b/CPLD/RAM2GS-LCMXO2.lpf
@@ -24,7 +24,6 @@ LOCATE COMP "MAin[6]" SITE "24" ;
 LOCATE COMP "MAin[7]" SITE "18" ;
 LOCATE COMP "MAin[8]" SITE "25" ;
 LOCATE COMP "MAin[9]" SITE "32" ;
-LOCATE COMP "UFMSDO" SITE "27" ;
 LOCATE COMP "nFWE" SITE "15" ;
 LOCATE COMP "Dout[0]" SITE "76" ;
 LOCATE COMP "Dout[1]" SITE "86" ;
@@ -52,8 +51,6 @@ LOCATE COMP "RBA[1]" SITE "60" ;
 LOCATE COMP "RCKE" SITE "53" ;
 LOCATE COMP "RDQMH" SITE "51" ;
 LOCATE COMP "RDQML" SITE "48" ;
-LOCATE COMP "UFMCLK" SITE "28" ;
-LOCATE COMP "UFMSDI" SITE "29" ;
 LOCATE COMP "nRCAS" SITE "52" ;
 LOCATE COMP "nRCS" SITE "57" ;
 LOCATE COMP "nRRAS" SITE "54" ;
@@ -90,7 +87,6 @@ IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
-IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "nFWE" IO_TYPE=LVCMOS33 PULLMODE=UP ;
 IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ;
 IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ;
@@ -118,13 +114,10 @@ IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RCKE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RDQMH" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RDQML" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRCAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRRAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
@@ -133,4 +126,3 @@ IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-LOCATE COMP "nUFMCS" SITE "30" ;
diff --git a/CPLD/RAM2GS-LCMXO2.v b/CPLD/RAM2GS-LCMXO2.v
index 48ace8c..e7f3953 100644
--- a/CPLD/RAM2GS-LCMXO2.v
+++ b/CPLD/RAM2GS-LCMXO2.v
@@ -1,731 +1,735 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = ~(~nCRAS &&  LEDEN);
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg CmdLEDEN = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdUFMData = 0;
-	reg CmdUFMShift = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	reg WriteDone;
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* UFM Interface */
+    reg wb_clk;
+    reg wb_rst;
+    reg wb_cyc_stb;
+    reg wb_we;
+    reg [7:0] wb_adr;
+    reg [7:0] wb_dati;
+	wire wb_ack;
+    wire [7:0] wb_dato;
+	wire ufm_irq;
+    REFB ufmefb (
+        .wb_clk_i(wb_clk),
+        .wb_rst_i(wb_rst),
+        .wb_cyc_i(wb_cyc_stb),
+        .wb_stb_i(wb_cyc_stb),
+        .wb_we_i(wb_we),
+        .wb_adr_i(wb_adr),
+        .wb_dat_i(wb_dati),
+        .wb_dat_o(wb_dato),
+        .wb_ack_o(wb_ack),
+		.wbc_ufm_irq(ufm_irq));
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMData = 0;
+    reg CMDUFMWrite = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0) begin
-				XOR8MEG <= Din[0];
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= ~Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-			end else if (Din[7:4]==4'h3 && Din[3]) begin
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMShift <= Din[1];
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
+
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // Reserved for SPI (LCMXO, iCE40) commands
+                // Din[2] - CS
+                // Din[1] - SCK
+                // Din[0] - SDI
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // LCMXO2 commands
+                // Din[1] - Shift when low, execute when high
+                // Din[0] - Shift data
+				CMDUFMWrite <= Din[1];
 				CmdUFMData <= Din[0];
-			end
-			CmdSubmitted <= 1;
-		end else CmdSubmitted <= 0;
-	end
-	
-	reg wb_clk;
-	reg wb_rst;
-	reg wb_cyc_stb;
-	reg wb_we;
-	reg [7:0] wb_adr;
-	reg [7:0] wb_dati;
-	wire [1:0] wb_dato;
-	
-	EFB ufmefb (
-		.WBCLKI(wb_clk),
-		.WBRSTI(wb_rst),
-		.WBCYCI(wb_cyc_stb),
-		.WBSTBI(wb_cyc_stb), 
-		.WBWEI(wb_we),
-		.WBADRI7(wb_adr[7]),
-		.WBADRI6(wb_adr[6]),
-		.WBADRI5(wb_adr[5]),
-		.WBADRI4(wb_adr[4]),
-		.WBADRI3(wb_adr[3]),
-		.WBADRI2(wb_adr[2]),
-		.WBADRI1(wb_adr[1]),
-		.WBADRI0(wb_adr[0]),
-		.WBDATI7(wb_dati[7]),
-		.WBDATI6(wb_dati[6]),
-		.WBDATI5(wb_dati[5]),
-		.WBDATI4(wb_dati[4]),
-		.WBDATI3(wb_dati[3]),
-		.WBDATI2(wb_dati[2]),
-		.WBDATI1(wb_dati[1]),
-		.WBDATI0(wb_dati[0]),
-		.WBDATO1(wb_dato[1]),
-		.WBDATO0(wb_dato[0]));
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdSubmitted <= 1'b1;
+            end
+        end
+    end
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			wb_clk <= 1'b0;
-			wb_rst <= ~FS[9];
-			wb_cyc_stb <= 1'b0;
-			wb_we <= 1'b0;
-			wb_adr[7:0] <= 8'h00;
-			wb_dati[7:0] <= 8'h00;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Enable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h74;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Enable configuration interface - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h08;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Enable configuration interface - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Enable configuration interface - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Poll status register - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h3C;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Poll status register - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Poll status register - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Poll status register - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Read status register 1/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h3C;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h06: begin // Read status register 2/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Read status register 3/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Read status register 4/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Set UFM address - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hB4;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Set UFM address - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Set UFM address - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Set UFM address - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Set UFM address - data 1/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h40;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h06: begin // Set UFM address - data 2/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Set UFM address - data 3/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Set UFM address - data 4/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h01;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h04) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Read UFM page - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hCA;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Read UFM page - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h10;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Read UFM page - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Read UFM page - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h01;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Read UFM page - data 1/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-					
-					if (FS[4:0]==5'h0C) begin
-						LEDEN <= wb_dato[1];
-						n8MEGEN <= wb_dato[0];
-					end
-				end 5'h06: begin // Read UFM page - data 2/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Read UFM page - data 3/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Read UFM page - data 4/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h09: begin // Read UFM page - data 5/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0A: begin // Read UFM page - data 6/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0B: begin // Read UFM page - data 7/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0C: begin // Read UFM page - data 8/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0D: begin // Read UFM page - data 9/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0E: begin // Read UFM page - data 10/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0F: begin // Read UFM page - data 11/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h10: begin // Read UFM page - data 12/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h11: begin // Read UFM page - data 13/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h12: begin // Read UFM page - data 14/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h13: begin // Read UFM page - data 15/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h14: begin // Read UFM page - data 16/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h05) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Disable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h26;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Disable configuration interface - operand 1/2
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Disable configuration interface - operand 2/2
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h06) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Disable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hFF;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady) begin
-			wb_clk <= 1'b0;
-			wb_rst <= 1'b0;
-			wb_cyc_stb <= 1'b0;
-			wb_we <= 1'b0;
-			wb_adr[7:0] <= 8'h00;
-			wb_dati[7:0] <= 8'h00;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMShift, CmdUFMData
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			if (CmdUFMShift) begin
-				wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
-				wb_dati[7:0] <= { wb_dati[6:0], wb_we };
-				wb_we <= wb_cyc_stb;
-				wb_cyc_stb <= CmdUFMData;
-				wb_clk <= 1'b0;
-			end else wb_clk <= 1'b1;
-		end
-	end
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            wb_clk <= 1'b0;
+            wb_rst <= ~FS[9];
+            wb_cyc_stb <= 1'b0;
+            wb_we <= 1'b0;
+            wb_adr[7:0] <= 8'h00;
+            wb_dati[7:0] <= 8'h00;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Enable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h74;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Enable configuration interface - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h08;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Enable configuration interface - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Enable configuration interface - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Poll status register - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h3C;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Poll status register - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Poll status register - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Poll status register - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Read status register 1/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h3C;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h06: begin // Read status register 2/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Read status register 3/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Read status register 4/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Set UFM address - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hB4;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Set UFM address - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Set UFM address - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Set UFM address - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Set UFM address - data 1/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h40;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h06: begin // Set UFM address - data 2/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Set UFM address - data 3/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Set UFM address - data 4/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h01;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h04) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Read UFM page - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hCA;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Read UFM page - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h10;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Read UFM page - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Read UFM page - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h01;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Read UFM page - data 1/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                    
+                    if (FS[4:0]==5'h0C) begin
+                        LEDEN <= wb_dato[1];
+                        n8MEGEN <= wb_dato[0];
+                    end
+                end 5'h06: begin // Read UFM page - data 2/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Read UFM page - data 3/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Read UFM page - data 4/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h09: begin // Read UFM page - data 5/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0A: begin // Read UFM page - data 6/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0B: begin // Read UFM page - data 7/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0C: begin // Read UFM page - data 8/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0D: begin // Read UFM page - data 9/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0E: begin // Read UFM page - data 10/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0F: begin // Read UFM page - data 11/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h10: begin // Read UFM page - data 12/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h11: begin // Read UFM page - data 13/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h12: begin // Read UFM page - data 14/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h13: begin // Read UFM page - data 15/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h14: begin // Read UFM page - data 16/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h05) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Disable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h26;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Disable configuration interface - operand 1/2
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Disable configuration interface - operand 2/2
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h06) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Disable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hFF;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady) begin
+            wb_clk <= 1'b0;
+            wb_rst <= 1'b0;
+            wb_cyc_stb <= 1'b0;
+            wb_we <= 1'b0;
+            wb_adr[7:0] <= 8'h00;
+            wb_dati[7:0] <= 8'h00;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            if (!CMDUFMWrite) begin
+                wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
+                wb_dati[7:0] <= { wb_dati[6:0], wb_we };
+                wb_we <= wb_cyc_stb;
+                wb_cyc_stb <= CmdUFMData;
+                wb_clk <= 1'b0;
+            end else wb_clk <= 1'b1;
+        end
+    end
 endmodule
diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v
index 6e97a29..c8693fb 100644
--- a/CPLD/RAM2GS-MAX.v
+++ b/CPLD/RAM2GS-MAX.v
@@ -1,470 +1,471 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* UFM Interface */
-	reg UFMD = 0; // UFM data register bit 15
-	reg ARCLK = 0; // UFM address register clock
-	// UFM address register data input tied to 0
-	reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
-	reg DRCLK = 0; // UFM data register clock
-	reg DRDIn = 0; // UFM data register input
-	reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
-	reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
-	reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
-	reg UFMOscEN = 0; // UFM oscillator enable
-	wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
-	wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
-	wire DRDOut; // UFM data output
-	// UFM oscillator always enabled
-	wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
-	UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
-		.arclk (ARCLK),
-		.ardin (1'b0),
-		.arshft (ARShift),
-		.drclk (DRCLK),
-		.drdin (DRDIn),
-		.drshft (DRShift),
-		.erase (UFMErase),
-		.oscena (UFMOscEN),
-		.program (UFMProgram),
-		.busy (UFMBusy),
-		.drdout (DRDOut),
-		.osc (UFMOsc),
-		.rtpbusy (RTPBusy));
-	reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
-	reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* UFM State */
-	reg UFMInitDone = 0; // 1 if UFM initialization finished
-	reg UFMReqErase = 0; // 1 if UFM requires erase
+    /* UFM Interface */
+    reg UFMD = 0; // UFM data register bit 15
+    reg ARCLK = 0; // UFM address register clock
+    // UFM address register data input tied to 0
+    reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
+    reg DRCLK = 0; // UFM data register clock
+    reg DRDIn = 0; // UFM data register input
+    reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
+    reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
+    reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
+    reg UFMOscEN = 0; // UFM oscillator enable
+    wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
+    wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
+    wire DRDOut; // UFM data output
+    // UFM oscillator always enabled
+    wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
+    UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
+        .arclk (ARCLK),
+        .ardin (1'b0),
+        .arshft (ARShift),
+        .drclk (DRCLK),
+        .drdin (DRDIn),
+        .drshft (DRShift),
+        .erase (UFMErase),
+        .oscena (UFMOscEN),
+        .program (UFMProgram),
+        .busy (UFMBusy),
+        .drdout (DRDOut),
+        .osc (UFMOsc),
+        .rtpbusy (RTPBusy));
+    reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
+    reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdDRCLK = 0;
-	reg CmdDRDIn = 0;
-	reg CmdUFMErase = 0; // Set by user command. Programs UFM
-	reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* UFM State */
+    reg UFMInitDone = 0; // 1 if UFM initialization finished
+    reg UFMReqErase = 0; // 1 if UFM requires erase
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdDRCLK = 0;
+    reg CmdDRDIn = 0;
+    reg CmdUFMErase = 0; // Set by user command. Programs UFM
+    reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// MAX commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMErase <= Din[3];
-				CmdUFMPrgm <= Din[2];
-				CmdDRCLK <= Din[1];
-				CmdDRDIn <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// Reserved for SPI (LCMXO, iCE40) commands
-				// Din[2] - CS
-				// Din[1] - SCK
-				// Din[0] - SDI
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+                UFMOscEN <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+                UFMOscEN <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~Ready) begin
-			if (~UFMInitDone & FS[17:16]==2'b00) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
-				// Parallel transfer UFM data to shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // Parallel transfer to data register
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// Capture bit 15 of this UFM word in UFMD register
-				if (FS[3:0]==4'h7) UFMD <= DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// If valid setting here, set capacity setting to UFMD[14]
-				if (FS[3:0]==4'h7 && ~UFMD) n8MEGEN <= ~DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
-				if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
-				else begin // If valid setting here
-					LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
-					// If last byte in sector, mark need to erase
-					if (FS[15:8]==8'hFF) begin
-						UFMReqErase <= 1'b1; // Mark need to wrap around
-						UFMInitDone <= 1'b1; // Quit iterating
-					end
-				end
-				
-				// Increment UFM address
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b0; // Increment UFM address
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (FS[17:16]==2'b10 & UFMReqErase) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else begin
-				// Don't do anything with UFM
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // MAX commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMErase <= Din[3];
+                CmdUFMPrgm <= Din[2];
+                CmdDRCLK <= Din[1];
+                CmdDRDIn <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // Reserved for SPI (LCMXO, iCE40) commands
+                // Din[2] - CS
+                // Din[1] - SCK
+                // Din[0] - SDI
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
 
-			// Don't erase or program UFM during initialization 
-			UFMErase <= 1'b0;
-			UFMProgram <= 1'b0;
-		end else begin
-			// Can only shift UFM data register now
-			ARCLK <= 1'b0;
-			ARShift <= 1'b0;
-			DRShift <= 1'b1;
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~Ready) begin
+            if (~UFMInitDone & FS[17:16]==2'b00) begin
+                // Shift 0 into address register
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b1; // Shift 0 into address register
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
+                // Parallel transfer UFM data to shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // Parallel transfer to data register
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
+                // Shift UFM data shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b1; // Shift data register
+                // Capture bit 15 of this UFM word in UFMD register
+                if (FS[3:0]==4'h7) UFMD <= DRDOut;
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
+                // Shift UFM data shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b1; // Shift data register
+                // If valid setting here, set capacity setting to UFMD[14]
+                if (FS[3:0]==4'h7 && ~UFMD) n8MEGEN <= ~DRDOut;
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
+                if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
+                else begin // If valid setting here
+                    LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
+                    // If last byte in sector, mark need to erase
+                    if (FS[15:8]==8'hFF) begin
+                        UFMReqErase <= 1'b1; // Mark need to wrap around
+                        UFMInitDone <= 1'b1; // Quit iterating
+                    end
+                end
+                
+                // Increment UFM address
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b0; // Increment UFM address
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else if (FS[17:16]==2'b10 & UFMReqErase) begin
+                // Shift 0 into address register
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b1; // Shift 0 into address register
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else begin
+                // Don't do anything with UFM
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end
 
-			// Set user command signals after PHI2 falls
-			if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-				LEDEN <= CmdLEDEN;
-				n8MEGEN <= Cmdn8MEGEN;
-				DRCLK <= CmdDRCLK;
-				DRDIn <= CmdDRDIn;
-			end
+            // Don't erase or program UFM during initialization 
+            UFMErase <= 1'b0;
+            UFMProgram <= 1'b0;
+        end else begin
+            // Can only shift UFM data register now
+            ARCLK <= 1'b0;
+            ARShift <= 1'b0;
+            DRShift <= 1'b1;
 
-			// UFM programming sequence
-			if (CmdUFMPrgm | CmdUFMErase) begin
-				if (~UFMBusyReg & ~RTPBusyReg) begin
-					if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
-					else if (CmdUFMPrgm) UFMProgram <= 1'b1;
-				end else if (UFMBusyReg) UFMReqErase <= 1'b0;
-			end
-		end
-	end
+            // Set user command signals after PHI2 falls
+            if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+                LEDEN <= CmdLEDEN;
+                n8MEGEN <= Cmdn8MEGEN;
+                DRCLK <= CmdDRCLK;
+                DRDIn <= CmdDRDIn;
+            end
+
+            // UFM programming sequence
+            if (CmdUFMPrgm | CmdUFMErase) begin
+                if (~UFMBusyReg & ~RTPBusyReg) begin
+                    if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
+                    else if (CmdUFMPrgm) UFMProgram <= 1'b1;
+                end else if (UFMBusyReg) UFMReqErase <= 1'b0;
+            end
+        end
+    end
 endmodule
diff --git a/CPLD/RAM2GS-SPI.v b/CPLD/RAM2GS-SPI.v
index d885e6d..1aa4a9f 100644
--- a/CPLD/RAM2GS-SPI.v
+++ b/CPLD/RAM2GS-SPI.v
@@ -1,411 +1,410 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCS, UFMCLK, UFMSDI, UFMSDO);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML,
+              nUFMCS, UFMCLK, UFMSDI, UFMSDO);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* UFM Interface */
-	output reg nUFMCS = 1;
-	output reg UFMCLK = 0;
-	output reg UFMSDI = 0;
-	input UFMSDO;
+    /* UFM Interface */
+    output reg nUFMCS = 1;
+    output reg UFMCLK = 0;
+    output reg UFMSDI = 0;
+    input UFMSDO;
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMCLK = 0;
+    reg CmdUFMSDI = 0;
+    reg CmdUFMCS = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// Reserved for MAX commands
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// SPI (LCMXO, iCE40, AGM) commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // SPI (LCMXO, iCE40, AGM) commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMCS <= Din[2];
+                CmdUFMCLK <= Din[1];
+                CmdUFMSDI <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN and LEDEN
-			if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
-			if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            case (FS[9:5]) // Shift out read data command (0x03)
+                5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
+                5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
+                5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
+                5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
+                5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
+                5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
+                5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
+                5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
+                5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
+                5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
+                5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
+                5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
+                5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
+                5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
+                5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
+                5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
+                5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
+                5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
+                5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
+                5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
+                5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
+                5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
+                5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
+                5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
+                5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
+                5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
+                5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
+                5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
+                5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
+                5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
+                5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
+                5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            UFMSDI <= 1'b0;
+            // Latch n8MEGEN and LEDEN
+            if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
+            if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
+        end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[1];
+            UFMSDI <= 1'b0;
+        end else if (~InitReady) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            nUFMCS <= ~CmdUFMCS;
+            UFMCLK <= CmdUFMCLK;
+            UFMSDI <= CmdUFMSDI;
+        end
+    end
 endmodule
diff --git a/CPLD/RAM4GS-AGM.v b/CPLD/RAM4GS-AGM.v
deleted file mode 100644
index 19ba8e5..0000000
--- a/CPLD/RAM4GS-AGM.v
+++ /dev/null
@@ -1,426 +0,0 @@
-module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
-
-	/* 65816 Phase 2 Clock */
-	input PHI2;
-
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
-
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
-
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
-
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
-
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
-
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
-
-	/* UFM Interface */
-	reg nUFMCS = 1;
-	reg UFMCLK = 0;
-	reg UFMSDI = 0;
-	wire UFMSDO;
-	wire UFMOsc;
-	alta_ufms u_alta_ufms (
-		.i_ufm_set (1'b1), 
-		.i_osc_ena (1'b1), 
-		.i_ufm_flash_csn (nUFMCS), 
-		.i_ufm_flash_sclk (UFMCLK), 
-		.i_ufm_flash_sdi (UFMSDI), 
-		.o_ufm_flash_sdo (UFMSDO), 
-		.o_osc (UFMOsc) 
-	);
-
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
-
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
-
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
-
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
-
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
-
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// Reserved for MAX commands
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// SPI (LCMXO, iCE40, AGM) commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
-
-	/* UFM Control */
-	output nUFMCSout = nUFMCS;
-	output UFMCLKout = UFMCLK;
-	output UFMSDIout = UFMSDI;
-	output UFMSDOout = UFMSDO;
-	input [3:0] In;
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN and LEDEN
-			if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
-			if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
-endmodule