From 8e3c43b7fc76ee67f446019d881738e97528e72d Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 16 Aug 2023 21:04:05 -0400 Subject: [PATCH] MachXO2 stuff --- CPLD/LCMXO2-640HC-old/.run_manager.ini | 9 - CPLD/LCMXO2-640HC-old/.setting.ini | 4 - CPLD/LCMXO2-640HC-old/EFB.ipx | 8 - CPLD/LCMXO2-640HC-old/EFB.sort | 1 - CPLD/LCMXO2-640HC-old/EFB.sym | Bin 464 -> 0 bytes CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf | 14 - CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf | 215 - .../RAM2GS_LCMXO2_640HC_tcl.html | 112 - .../pn210817003052.tcr | 6 - .../pn210817054927.tcr | 9 - .../pn210817062320.tcr | 24 - .../pn211010064144.tcr | 6 - CPLD/LCMXO2-640HC-old/impl1/.build_status | 46 - .../.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb | Bin 91027 -> 0 bytes .../impl1/.vdbs/RAM2GS_rtl.vdb | Bin 147042 -> 0 bytes .../impl1/.vdbs/RAM2GS_tech.vdb | Bin 116485 -> 0 bytes CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt | 1 - .../impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs | 2837 -- .../impl1/RAM2GS_LCMXO2_640HC_impl1.arearep | 22 - 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bytes .../LCMXO2_640HC_impl1_m_srm/fileinfo.srm | Bin 0 -> 328 bytes ...1_mult.gcr => LCMXO2_640HC_impl1_mult.gcr} | 4 +- .../impl1/synwork/LCMXO2_640HC_impl1_mult.srs | Bin 0 -> 13269 bytes .../synwork/LCMXO2_640HC_impl1_mult_srs/1.srs | Bin 0 -> 4774 bytes .../LCMXO2_640HC_impl1_mult_srs/fileinfo.srs | Bin 0 -> 273 bytes .../LCMXO2_640HC_impl1_mult_srs/skeleton.srs | Bin 0 -> 1329 bytes .../LCMXO2_640HC_impl1_prem.fse} | 0 .../impl1/synwork/LCMXO2_640HC_impl1_prem.srd | Bin 0 -> 28839 bytes .../impl1/synwork/LCMXO2_640HC_impl1_prem.srm | Bin 0 -> 16330 bytes .../synwork/LCMXO2_640HC_impl1_prem_srm/1.srm | Bin 0 -> 7771 bytes .../LCMXO2_640HC_impl1_prem_srm/fileinfo.srm | Bin 0 -> 330 bytes .../LCMXO2_640HC_impl1_prem_srm/skeleton.srm | Bin 0 -> 1459 bytes .../RAM2GS_LCMXO2_640HC_impl1_comp.fdep | 16 - .../RAM2GS_LCMXO2_640HC_impl1_comp.srs | Bin 10463 -> 0 bytes .../synwork/RAM2GS_LCMXO2_640HC_impl1_m.srm | Bin 30417 -> 0 bytes .../RAM2GS_LCMXO2_640HC_impl1_m_srm/1.srm | Bin 1712 -> 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create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult_srs/skeleton.srs rename CPLD/LCMXO2-640HC/impl1/{impl1_synplify_tmp4.lpf => synwork/LCMXO2_640HC_impl1_prem.fse} (100%) create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srd create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem.srm create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/fileinfo.srm create mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/skeleton.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.fdep delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.srs delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_m_srm/1.srm delete mode 100644 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CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_m.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/1.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_m_srm/fileinfo.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/fileinfo.srs delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult_srs/skeleton.srs delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.fse delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srd delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm delete mode 100644 CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list delete mode 100644 CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file rename CPLD/{LCMXO2-640HC-old => LCMXO2-640HC}/msg_file.log (69%) create mode 100644 CPLD/RAM2GS-AGM.v rename CPLD/{LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf => RAM2GS-LCMXO2.lpf} (93%) delete mode 100644 CPLD/RAM4GS-AGM.v diff --git a/CPLD/LCMXO2-640HC-old/.run_manager.ini b/CPLD/LCMXO2-640HC-old/.run_manager.ini deleted file mode 100644 index 8c0aa7b..0000000 --- a/CPLD/LCMXO2-640HC-old/.run_manager.ini +++ /dev/null @@ -1,9 +0,0 @@ -[Runmanager] -Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) -windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) -headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) - -[impl1%3CStrategy1%3E] -isChecked=false -isHidden=false -isExpanded=false diff --git a/CPLD/LCMXO2-640HC-old/.setting.ini b/CPLD/LCMXO2-640HC-old/.setting.ini deleted file mode 100644 index 449a648..0000000 --- a/CPLD/LCMXO2-640HC-old/.setting.ini +++ /dev/null @@ -1,4 +0,0 @@ -[General] -Map.auto_tasks=MapTrace -Export.auto_tasks=IBIS, Bitgen, Jedecgen -PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO2-640HC-old/EFB.ipx b/CPLD/LCMXO2-640HC-old/EFB.ipx deleted file mode 100644 index 0954007..0000000 --- a/CPLD/LCMXO2-640HC-old/EFB.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/EFB.sort b/CPLD/LCMXO2-640HC-old/EFB.sort deleted file mode 100644 index 8437cdd..0000000 --- a/CPLD/LCMXO2-640HC-old/EFB.sort +++ /dev/null @@ -1 +0,0 @@ -EFB.v diff --git a/CPLD/LCMXO2-640HC-old/EFB.sym b/CPLD/LCMXO2-640HC-old/EFB.sym deleted file mode 100644 index 98635d35b1f64bfccca3395cd1f2b9bd133a0e8b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 464 zcmYk2F-yZx5Xb-52x>(r;?Th%Lnm=~gCIyJX)_6Cs3?fOwuwS$r7^7r!4J?eh##P{ zba3og#9162J2^T#`hTy~7&!9dckk}qz3~b7IgAfkG6+>@ii@fo3a~3xni;lHsS(!G zwr+)qj?VV>)j1ke3f?@o!d%ep=m_Z2$GG_C?*rq9^se0Hy~5UD(QCwaQC6BX|ZFcYUCvD=sl zdh=}-XUq%Cuq735N3fQ*1ATjSt)t}TuM4p0)V%}Lq%6MF>B~|=T~0+%Vy&qUEl=${ zv8>W( - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf deleted file mode 100644 index 746bae4..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf +++ /dev/null @@ -1,215 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "62" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ; -IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -USE PRIMARY NET "PHI2_c" ; -USE PRIMARY NET "RCLK_c" ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 16.000000 ns ; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -USE PRIMARY NET "nCCAS_c" ; -USE PRIMARY NET "nCRAS_c" ; diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html deleted file mode 100644 index ee9c39f..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html +++ /dev/null @@ -1,112 +0,0 @@ - -Lattice TCL Log - - -
pn210817003052
-#Start recording tcl command: 8/16/2021 23:26:11
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
-prj_project save
-#Stop recording: 8/17/2021 00:30:52
-
-
-
-pn210817054927
-#Start recording tcl command: 8/17/2021 00:30:55
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/17/2021 05:49:27
-
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-pn210817062320
-#Start recording tcl command: 8/17/2021 05:49:30
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Synthesis -impl impl1
-prj_run Synthesis -impl impl1 -forceOne
-prj_run Map -impl impl1 -forceOne
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceOne
-#Stop recording: 8/17/2021 06:23:20
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- - diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr deleted file mode 100644 index ffbaf5f..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817003052.tcr +++ /dev/null @@ -1,6 +0,0 @@ -#Start recording tcl command: 8/16/2021 23:26:11 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse" -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v" -prj_project save -#Stop recording: 8/17/2021 00:30:52 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr deleted file mode 100644 index 76d8b28..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817054927.tcr +++ /dev/null @@ -1,9 +0,0 @@ -#Start recording tcl command: 8/17/2021 00:30:55 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -#Stop recording: 8/17/2021 05:49:27 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr deleted file mode 100644 index 9f6f1a8..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn210817062320.tcr +++ /dev/null @@ -1,24 +0,0 @@ -#Start recording tcl command: 8/17/2021 05:49:30 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -prj_run Synthesis -impl impl1 -prj_run Synthesis -impl impl1 -forceOne -prj_run Map -impl impl1 -forceOne -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceOne -#Stop recording: 8/17/2021 06:23:20 diff --git a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr deleted file mode 100644 index 21e57a4..0000000 --- a/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr +++ /dev/null @@ -1,6 +0,0 @@ -#Start recording tcl command: 10/9/2021 01:18:46 -#Project Location: C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC -prj_project open "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" -prj_run Map -impl impl1 -forceAll -prj_run PAR -impl impl1 -forceAll -#Stop recording: 10/10/2021 06:41:44 diff --git a/CPLD/LCMXO2-640HC-old/impl1/.build_status b/CPLD/LCMXO2-640HC-old/impl1/.build_status deleted file mode 100644 index 9e3c1d3..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/.build_status +++ /dev/null @@ -1,46 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb deleted file mode 100644 index 7051715d6931cca081a4521d0e85c1db6d1c5dc8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 91027 zcmd7537A~RbspN7>7EUk?itKL7=i?Fdl|aBCvh|b!jH7sFU?2OCMl83_FlZ35+#eI z|G>%dsZ{FK6#nYJ|KXG4=|6e%WVbG@ zU#VZ-x^VT<<;z=}>8l&p)@AtzQYlLC75%vR|G-pzckiY8rOmn~97qL(c%kEKtGDb| z=2(iks+a?*@gqm)nLLnw;N9K#W&DIlp+z z@uSBV_Y+_?l{vnEd{xO9kW&I#Tv(Vpsd5ga(ibjV*)UvV8y76~rL8MhZF=wOHJcvW zyKbmsTbm|@mL9dqp)DQr6 z>NDprT;IE}wWo0O2Oc#^TlY+TYjflBo~%7air1f6nqNG+x}OA<)L6qRaI9g~GuAk7 zL>gu>H635m@ii^qc(k}+9vRQMXCVs42|&r zLobdm&f6N&&Cg!c7BQ9@YhF|}F!j1kH5{#BY3YW4CX+k9FsB6@OQo9^*55EfW+Iu< z5E%uT(GnSXnbGkX>E_i7x>)pmZo#S{-4Nu+lUtsg?)dchantBAB_aMhaImI~;F$D2 zaa!DNCX}IF+|O`s`QOfP{{OLyA=;j*!*$CM8W7@o9>=t>pOU9j8SnQ3k9a`(N+73% zdxRJDzH;oPYsOI17j}(PJCHhZYVG*R+NnEFo>;8SFCJT5Tl)Ii@l%HJZP$0NUaMb! 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U-1xKKKClZCQ&c^h9X>Pqf0mWHTmS$7 diff --git a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt deleted file mode 100644 index 0a575a4..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/.vdbs/dbStat.txt +++ /dev/null @@ -1 +0,0 @@ -RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs b/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs deleted file mode 100644 index 4b06874..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/IBIS/RAM2GS_LCMXO2_640HC~.ibs +++ /dev/null @@ -1,2837 +0,0 @@ -|************************************************************************ -| IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2 -| Generate date: Tue Aug 17 06:21:03 2021 -|************************************************************************ -| IBIS File LibisMaker.ibs -| LibisGen v2.0.1.0, 02/25/2008, Lattice Semiconductor Corporation -| Modified by LibisMaker v2.0.1.0, 02/25/2008, Lattice Semiconductor -| North Carolina State University, ERL, 2006 -|************************************************************************ -[IBIS ver] 3.2 -[File Name] RAM2GS_LCMXO2_640HC~.ibs -[File Rev] 3.5 -[Date] Thu Sep 10 07:33:23 PDT 2020 -[Source] Lattice Semiconductor cs200fl Process - LCMXO2-640HC FINAL - Lattice Semiconductor has worked hard to ensure the - models below are accurate and complete. However, the - data below was generated using simulation of the - input/output model files for the silicon. Therefore, - the data below is for reference and initial design - purposes only. -| - Lattice Semiconductor grants permission to use this - data for use in printed circuit design using this - Lattice programmable logic device. Other use of this - code, including the selling or duplication of any - portion is strictly prohibited. -| -| NAMING CONVENTION -| - The IBIS [Model] header is limited by the specification to a - total of characters. With such a set of characters available - for naming models it becomes important to attempt to - meaningfully encode the IO standards so they fit within the - twenty character limit. It would seem that twenty characters - would provide room enough for describing IO's. However, the - PLD IO structure continues to grow more and more complex. The - complexity is making the twenty characters insuffiently - descriptive. In order to overcome this issue the naming - convention described below is implemented to resolve the issue. -| -The twenty character space is managed as follows: - bbbvvvsdddprugtcoixx -| - b = standard - v = voltage (x.xx V) - s = slew code - d = drive (xx.x ma) - p = pullup code - r = series resistance or bank_vccio code - u = terminate to vcc code - g = terminate to gnd code - t = terminate to vtt code - c = common mode termination mode - o = diff resistor code - i = diff resistor current code - x = reserved -| -| - standard -| - lvcmos lvc - lvcmosd lvd - lvcmosr lvr - lvds25e lve - lvttl lvt - lvttld ltd - pci pci - sstl_I ss1 - sstl_II ss2 - sstld_I s1d - sstld_II s2d - hstl_i hs1 - hstl_ii hs2 - hstld_i h1d - hstld_ii h2d - lvds25 lvs - blvds25 blv - blvds25e blv - mlvds25 mlv - mlvds25e mlv - lvpecl33 lvp - lvpecl33e lvp - rsds25 rsd - rsds25e rse - mipi mip - mipi_lp mip - vref1 vr1 - vref2 vr2 - ref_res rer -| -| - slew - na a - fast f - slow s -| - pullmode - off a - pullup b - pulldown c - bushold d - clamp e - up_clamp f - down_clamp g - keeper_clamp h -| - impedance or Bank_vccio - off a - 25 b - 33 c - 50 d - 100 e - 3.3 f - 2.5 g - 1.8 h - 1.5 i - 1.2 j -| - termVCC - off a - 50 b - 100 c - 120 d -| - termGND - off a - 50 b - 100 c - 120 d -| - termVTT - off a - 60 b - 75 c - 120 d - 150 e - 210 f -| - VCMT - off a - VCMT b - VTT c - DDR-2 d -| - differential resistor - off a - 100 b -| - diff drive - NA a - 2.0 b - 3.5 c - 1.25 f - 2.5 g -| - Reserved IO type - in input only - ou output - io I/O - od Open drain - on Inverting differential I/O - (signal name only) - op Non-Inverting differential I/O - (signal name only) -| - Lattice Semiconductor Corporation - 5555 NE Moore Court - Hillsboro, OR 97214 - U.S.A -| - TEL: 1-800-Lattice (USA and Canada) - 408-826-6000 (other locations) -| - web: http://www.latticesemi.com/ - email: techsupport@latticesemi.com -| -| -| -[Disclaimer] This IBIS source code is intended as a design reference - which illustrates how the Lattice Semiconductor device operates. - It is the user's responsibility to verify their design for - consistency and functionality through the use of formal - verification methods. Lattice Semiconductor provides no warranty - regarding the use or functionality of this data. -| -[Copyright] Copyright 2007 by Lattice Semiconductor Corporation -| -| -|************************************************************************ -| Component XO2 -|************************************************************************ -| -[Component] XO2 -[Manufacturer] Lattice Semiconductor Corp. -[Package] -|TQFP100 -| variable typ min max -R_pkg 150.5m 124.0m 187.0m -L_pkg 6.27nH 5.50nH 7.16nH -C_pkg 0.95pF 0.87pF 1.07pF -| -[Pin] signal_name model_name R_pin L_pin C_pin -10 CROW[0] lvt330axxxefaaaaaain -16 CROW[1] lvt330axxxefaaaaaain -3 Din[0] lvt330axxxefaaaaaain -96 Din[1] lvt330axxxefaaaaaain -88 Din[2] lvt330axxxefaaaaaain -97 Din[3] lvt330axxxefaaaaaain -99 Din[4] lvt330axxxefaaaaaain -98 Din[5] lvt330axxxefaaaaaain -2 Din[6] lvt330axxxefaaaaaain -1 Din[7] lvt330axxxefaaaaaain -76 Dout[0] lvt330s040aaaaaaaaou -86 Dout[1] lvt330s040aaaaaaaaou -87 Dout[2] lvt330s040aaaaaaaaou -85 Dout[3] lvt330s040aaaaaaaaou -83 Dout[4] lvt330s040aaaaaaaaou -84 Dout[5] lvt330s040aaaaaaaaou -78 Dout[6] lvt330s040aaaaaaaaou -82 Dout[7] lvt330s040aaaaaaaaou -34 LED lvt330s160aaaaaaaaou -14 MAin[0] lvt330axxxefaaaaaain -12 MAin[1] lvt330axxxefaaaaaain -13 MAin[2] lvt330axxxefaaaaaain -21 MAin[3] lvt330axxxefaaaaaain -20 MAin[4] lvt330axxxefaaaaaain -19 MAin[5] lvt330axxxefaaaaaain -24 MAin[6] lvt330axxxefaaaaaain -18 MAin[7] lvt330axxxefaaaaaain -25 MAin[8] lvt330axxxefaaaaaain -32 MAin[9] lvt330axxxefaaaaaain -8 PHI2 lvt330axxxefaaaaaain -66 RA[0] lvt330s040aaaaaaaaou -64 RA[10] lvt330s040aaaaaaaaou -59 RA[11] lvt330s040aaaaaaaaou -67 RA[1] lvt330s040aaaaaaaaou -69 RA[2] lvt330s040aaaaaaaaou -71 RA[3] lvt330s040aaaaaaaaou -74 RA[4] lvt330s040aaaaaaaaou -70 RA[5] lvt330s040aaaaaaaaou -68 RA[6] lvt330s040aaaaaaaaou -75 RA[7] lvt330s040aaaaaaaaou -65 RA[8] lvt330s040aaaaaaaaou -62 RA[9] lvt330s040aaaaaaaaou -58 RBA[0] lvt330s040aaaaaaaaou -60 RBA[1] lvt330s040aaaaaaaaou -53 RCKE lvt330s040aaaaaaaaou -63 RCLK lvt330axxxefaaaaaain -51 RDQMH lvt330s040aaaaaaaaou -48 RDQML lvt330s040aaaaaaaaou -36 RD[0] lvt330s040haaaaaaaio -37 RD[1] lvt330s040haaaaaaaio -38 RD[2] lvt330s040haaaaaaaio -39 RD[3] lvt330s040haaaaaaaio -40 RD[4] lvt330s040haaaaaaaio -41 RD[5] lvt330s040haaaaaaaio -42 RD[6] lvt330s040haaaaaaaio -43 RD[7] lvt330s040haaaaaaaio -9 nCCAS lvt330axxxefaaaaaain -17 nCRAS lvt330axxxefaaaaaain -15 nFWE lvt330axxxefaaaaaain -52 nRCAS lvt330s040aaaaaaaaou -57 nRCS lvt330s040aaaaaaaaou -54 nRRAS lvt330s040aaaaaaaaou -49 nRWE lvt330s040aaaaaaaaou -|************************************************************************ -[Model] lvt330axxxefaaaaaain -Model_type Input -Polarity Non-Inverting -Enable Active-Low -Vinl = 0.8000V -Vinh = 2.0000V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A -0.9287A - -3.15 -0.8816A -0.8571A -0.9041A - -3.10 -0.8571A -0.8328A -0.8794A - -3.05 -0.8326A -0.8084A -0.8548A - -3.00 -0.8081A -0.7841A -0.8302A - -2.95 -0.7837A -0.7598A -0.8056A - -2.90 -0.7592A -0.7356A -0.781A - -2.85 -0.7348A -0.7113A -0.7565A - -2.80 -0.7104A -0.6872A -0.7319A - -2.75 -0.686A -0.663A -0.7074A - -2.70 -0.6617A -0.6389A -0.6829A - -2.65 -0.6374A -0.6149A -0.6584A - -2.60 -0.6131A -0.5909A -0.634A - -2.55 -0.5889A -0.5669A -0.6096A - -2.50 -0.5647A -0.5431A -0.5852A - -2.45 -0.5406A -0.5193A -0.5609A - -2.40 -0.5166A -0.4956A -0.5366A - -2.35 -0.4926A -0.472A -0.5124A - -2.30 -0.4687A -0.4485A -0.4882A - -2.25 -0.4449A -0.4251A -0.4641A - -2.20 -0.4211A -0.4019A -0.44A - -2.15 -0.3976A -0.3789A -0.4161A - -2.10 -0.3741A -0.3562A -0.3923A - -2.05 -0.3509A -0.3337A -0.3686A - -2.00 -0.3279A -0.3116A -0.3451A - -1.95 -0.3052A -0.2899A -0.3218A - -1.90 -0.283A -0.2689A -0.2988A - -1.85 -0.2612A -0.2486A -0.2762A - -1.80 -0.2402A -0.2294A -0.2543A - -1.75 -0.2204A -0.2116A -0.2332A - -1.70 -0.202A -0.1954A -0.2135A - -1.65 -0.1857A -0.181A -0.1959A - -1.60 -0.1717A -0.1682A -0.181A - -1.55 -0.1594A -0.1563A -0.1685A - -1.50 -0.1481A -0.1452A -0.1571A - -1.45 -0.1372A -0.1343A -0.1462A - -1.40 -0.1266A -0.1237A -0.1355A - -1.35 -0.1162A -0.1132A -0.125A - -1.30 -0.106A -0.1029A -0.1146A - -1.25 -95.9599mA -92.8329mA -0.1046A - -1.20 -86.1849mA -82.9339mA -94.9069mA - -1.15 -76.7349mA -73.2869mA -85.7379mA - -1.10 -67.7089mA -63.9519mA -77.2789mA - -1.05 -59.2439mA -55.0099mA -69.7479mA - -1.00 -51.5159mA -46.5729mA -63.2139mA - -0.95 -44.7119mA -38.7979mA -57.3089mA - -0.90 -38.8659mA -31.8819mA -51.2599mA - -0.85 -33.5299mA -25.9129mA -44.7209mA - -0.80 -28.2499mA -20.5839mA -37.9699mA - -0.75 -23.0669mA -15.7839mA -31.2789mA - -0.70 -18.0989mA -11.6329mA -24.8089mA - -0.65 -13.4569mA -8.1389mA -18.6889mA - -0.60 -9.2667mA -5.2646mA -13.0589mA - -0.55 -5.6915mA -3.0244mA -8.1194mA - -0.50 -2.937mA -1.4709mA -4.1747mA - -0.45 -1.1814mA -0.5866mA -1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.1216A 0.1237A 0.1238A - -3.15 0.1196A 0.1223A 0.1209A - -3.05 0.1173A 0.1206A 0.1178A - -2.95 0.1149A 0.1187A 0.1145A - -2.85 0.1124A 0.1167A 0.1111A - -2.75 0.1096A 0.1144A 0.1076A - -2.65 0.1067A 0.1119A 0.1038A - -2.55 0.1036A 0.1092A 99.9050mA - -2.45 0.1003A 0.1063A 95.7580mA - -2.35 96.7690mA 0.1032A 91.3580mA - -2.25 92.9860mA 99.8100mA 86.6530mA - -2.15 88.9230mA 96.2310mA 81.5730mA - -2.05 84.5480mA 92.4190mA 76.0140mA - -1.95 79.8300mA 88.3720mA 69.8490mA - -1.85 74.7460mA 84.0930mA 62.9770mA - -1.75 69.2870mA 79.5850mA 55.3980mA - -1.65 63.4650mA 74.8610mA 47.2410mA - -1.55 57.3080mA 69.9360mA 38.7130mA - -1.45 50.8520mA 64.8290mA 30.0630mA - -1.35 44.1410mA 59.5630mA 21.7860mA - -1.25 37.2260mA 54.1610mA 15.4630mA - -1.15 30.1740mA 48.6420mA 11.3590mA - -1.05 23.0900mA 43.0210mA 6.9249mA - -0.95 16.2170mA 37.3010mA 3.1428mA - -0.85 10.2220mA 31.4860mA 0.8130mA - -0.75 6.0667mA 25.5900mA 0.1206mA - -0.65 3.1215mA 19.6580mA 19.6640uA - -0.55 1.0958mA 13.7970mA 3.9127uA - -0.45 0.2189mA 8.2788mA 1.9769uA - -0.35 37.5650uA 3.8148mA 1.5352uA - -0.25 5.9156uA 1.3265mA 1.2603uA - -0.15 0.9342uA 0.3367mA 1.0262uA - -0.05 0.2497uA 63.0770uA 0.8243uA - 0.00 0.1905uA 26.3140uA 0.7347uA - 0.05 0.1661uA 10.7330uA 0.6522uA - 0.15 0.1377uA 1.6689uA 0.5077uA - 0.25 0.1149uA 0.2675uA 0.3882uA - 0.35 95.5840nA 94.4800nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2001nA 17.4270nA -0.8025nA - 1.55 4.6215nA 13.7460nA -4.4469nA - 1.65 1.0974nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8986nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2566nA -22.2600nA - 2.15 -16.3730nA -7.8413nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -| End [Model] lvt330axxxefaaaaaain -|************************************************************************ -[Model] lvt330s040aaaaaaaaou -Model_type Output -Polarity Non-Inverting -Enable Active-Low -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -11.9500mA -8.6650mA -15.6420mA - -3.20 -11.9500mA -8.6650mA -15.6420mA - -3.10 -11.9500mA -8.6650mA -15.6420mA - -3.00 -11.9500mA -8.6650mA -15.6420mA - -2.90 -11.9500mA -8.6650mA -15.6420mA - -2.80 -11.9500mA -8.6650mA -15.6420mA - -2.70 -11.9500mA -8.6650mA -15.6420mA - -2.60 -11.9500mA -8.6650mA -15.6420mA - -2.50 -11.9500mA -8.6650mA -15.6420mA - -2.40 -11.9500mA -8.6650mA -15.6420mA - -2.30 -11.9500mA -8.6650mA -15.6420mA - -2.20 -11.9500mA -8.6650mA -15.6420mA - -2.10 -11.9500mA -8.6650mA -15.6420mA - -2.00 -11.9500mA -8.6650mA -15.6420mA - -1.90 -11.9500mA -8.6650mA -15.6420mA - -1.80 -11.9500mA -8.6650mA -15.6420mA - -1.70 -11.9500mA -8.6650mA -15.6420mA - -1.60 -11.9500mA -8.6650mA -15.6420mA - -1.50 -11.9500mA -8.6650mA -15.6420mA - -1.40 -11.9500mA -8.6650mA -15.6420mA - -1.30 -11.9500mA -8.6650mA -15.6420mA - -1.20 -11.9500mA -8.6650mA -15.6420mA - -1.10 -11.9500mA -8.6650mA -15.6420mA - -1.00 -11.9500mA -8.6650mA -15.6420mA - -0.90 -11.9260mA -8.6650mA -14.3050mA - -0.80 -11.2400mA -8.5300mA -13.3800mA - -0.70 -10.7050mA -8.3490mA -12.9130mA - -0.60 -10.2262mA -7.9463mA -12.5750mA - -0.50 -9.6879mA -7.2722mA -12.3552mA - -0.40 -8.5353mA -6.1307mA -11.3241mA - -0.30 -6.5715mA -4.6600mA -8.7716mA - -0.20 -4.4298mA -3.1245mA -5.9312mA - -0.10 -2.2389mA -1.5709mA -3.0077mA - 0.00 2.6070nA 1.8160nA 4.3450nA - 0.10 2.2086mA 1.5382mA 2.9824mA - 0.20 4.3047mA 2.9922mA 5.8245mA - 0.30 6.2890mA 4.3627mA 8.5260mA - 0.40 8.1616mA 5.6502mA 11.0870mA - 0.50 9.9232mA 6.8553mA 13.5060mA - 0.60 11.5740mA 7.9787mA 15.7840mA - 0.70 13.1130mA 9.0208mA 17.9190mA - 0.80 14.5410mA 9.9819mA 19.9070mA - 0.90 15.8560mA 10.8620mA 21.7440mA - 1.00 17.0540mA 11.6600mA 23.4200mA - 1.10 18.1290mA 12.3750mA 24.9200mA - 1.20 19.0710mA 13.0030mA 26.2250mA - 1.30 19.8710mA 13.5400mA 27.3150mA - 1.40 20.5280mA 13.9880mA 28.1920mA - 1.50 21.0520mA 14.3520mA 28.8770mA - 1.60 21.4690mA 14.6450mA 29.4110mA - 1.70 21.8020mA 14.8830mA 29.8330mA - 1.80 22.0750mA 15.0800mA 30.1740mA - 1.90 22.3020mA 15.2450mA 30.4550mA - 2.00 22.4950mA 15.3870mA 30.6940mA - 2.10 22.6630mA 15.5110mA 30.8990mA - 2.20 22.8110mA 15.6210mA 31.0780mA - 2.30 22.9430mA 15.7190mA 31.2379mA - 2.40 23.0630mA 15.8080mA 31.3819mA - 2.50 23.1710mA 15.8900mA 31.5119mA - 2.60 23.2710mA 15.9650mA 31.6318mA - 2.70 23.3639mA 16.0350mA 31.7418mA - 2.80 23.4499mA 16.0999mA 31.8447mA - 2.90 23.5309mA 16.1609mA 31.9406mA - 3.00 23.6069mA 16.2189mA 32.0305mA - 3.10 23.6789mA 16.2739mA 32.1163mA - 3.20 23.7478mA 16.3258mA 32.1981mA - 3.30 23.8138mA 16.3756mA 32.2769mA - 3.40 23.8786mA 16.4213mA 32.3557mA - 3.50 23.9417mA 16.4526mA 32.4354mA - 3.60 24.0002mA 16.6876mA 32.5189mA - 3.70 24.0309mA 17.3426mA 32.6070mA - 3.80 24.3774mA 19.1285mA 32.6921mA - 3.90 25.3543mA 22.9154mA 32.7222mA - 4.00 27.4942mA 28.3023mA 33.3062mA - 4.10 30.5709mA 34.3240mA 34.9817mA - 4.20 34.9446mA 40.5557mA 38.3579mA - 4.30 41.2761mA 46.8344mA 42.8549mA - 4.40 48.5706mA 53.0950mA 47.3478mA - 4.50 56.1500mA 59.3125mA 52.6274mA - 4.60 63.7762mA 65.4900mA 60.8279mA - 4.70 71.3464mA 71.6374mA 70.1182mA - 4.80 78.8056mA 77.7568mA 79.6014mA - 4.90 86.1136mA 83.8381mA 88.9754mA - 5.00 93.2445mA 89.8594mA 98.0452mA - 5.10 0.1002A 95.7986mA 0.1067A - 5.20 0.1069A 0.1016A 0.1148A - 5.30 0.1134A 0.1074A 0.1224A - 5.40 0.1197A 0.1130A 0.1298A - 5.50 0.1258A 0.1184A 0.1369A - 5.60 0.1318A 0.1237A 0.1439A - 5.70 0.1376A 0.1289A 0.1508A - 5.80 0.1432A 0.1340A 0.1576A - 5.90 0.1488A 0.1390A 0.1644A - 6.00 0.1544A 0.1438A 0.1712A - 6.10 0.1598A 0.1485A 0.1780A - 6.20 0.1652A 0.1530A 0.1848A - 6.30 0.1706A 0.1575A 0.1916A - 6.40 0.1760A 0.1620A 0.1984A - 6.50 0.1813A 0.1663A 0.2053A - 6.60 0.1867A 0.1705A 0.2122A -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| --3.30 0.1819A 0.1298A 0.2190A --3.20 0.1819A 0.1298A 0.2177A --3.10 0.1819A 0.1298A 0.2139A --3.00 0.1785A 0.1298A 0.2092A --2.90 0.1743A 0.1298A 0.2039A --2.80 0.1697A 0.1298A 0.1982A --2.70 0.1647A 0.1298A 0.1922A --2.60 0.1594A 0.1298A 0.1860A --2.50 0.1538A 0.1298A 0.1795A --2.40 0.1479A 0.1298A 0.1728A --2.30 0.1418A 0.1259A 0.1658A --2.20 0.1353A 0.1198A 0.1586A --2.10 0.1286A 0.1135A 0.1512A --2.00 0.1216A 0.1069A 0.1435A --1.90 0.1142A 0.1002A 0.1355A --1.80 0.1066A 93.3488mA 0.1271A --1.70 93.5831mA 86.3555mA 0.1182A --1.60 85.8190mA 79.2592mA 0.1088A --1.50 77.8471mA 72.0828mA 98.7659mA --1.40 69.6957mA 64.8453mA 88.3330mA --1.30 61.4020mA 57.5538mA 77.6100mA --1.20 53.0124mA 50.2142mA 66.7828mA --1.10 44.6065mA 42.8446mA 56.1774mA --1.00 36.3505mA 35.4829mA 46.7939mA --0.90 28.6912mA 28.2232mA 39.5361mA --0.80 22.4746mA 21.3014mA 32.3042mA --0.70 17.6024mA 15.3245mA 25.5251mA --0.60 13.5809mA 11.1535mA 19.7918mA --0.50 10.4816mA 8.4310mA 14.7443mA --0.40 8.0206mA 6.4251mA 11.9096mA --0.30 5.9614mA 4.6861mA 8.8891mA --0.20 3.9365mA 3.0816mA 5.8934mA --0.10 1.9506mA 1.5203mA 2.9319mA -0.00 -7.7700nA -3.4200nA -87.8000nA -0.10 -1.8904mA -1.4640mA -2.8585mA -0.20 -3.6938mA -2.8556mA -5.5960mA -0.30 -5.4106mA -4.1752mA -8.2131mA -0.40 -7.0415mA -5.4235mA -10.7106mA -0.50 -8.5871mA -6.6009mA -13.0875mA -0.60 -10.0478mA -7.7082mA -15.3464mA -0.70 -11.4233mA -8.7458mA -17.4873mA -0.80 -12.7164mA -9.7144mA -19.5102mA -0.90 -13.9250mA -10.6140mA -21.4151mA -1.00 -15.0511mA -11.4460mA -23.2041mA -1.10 -16.0947mA -12.2110mA -24.8771mA -1.20 -17.0567mA -12.9090mA -26.4350mA -1.30 -17.9380mA -13.5400mA -27.8770mA -1.40 -18.7378mA -14.1060mA -29.2060mA -1.50 -19.4578mA -14.6060mA -30.4200mA -1.60 -20.0982mA -15.0420mA -31.5220mA -1.70 -20.6608mA -15.4150mA -32.5110mA -1.80 -21.1446mA -15.7260mA -33.3890mA -1.90 -21.5526mA -15.9770mA -34.1570mA -2.00 -21.8875mA -16.1730mA -34.8170mA -2.10 -22.1540mA -16.3230mA -35.3710mA -2.20 -22.3628mA -16.4420mA -35.8270mA -2.30 -22.5316mA -16.5430mA -36.1970mA -2.40 -22.6758mA -16.6340mA -36.5020mA -2.50 -22.8058mA -16.7200mA -36.7650mA -2.60 -22.9282mA -16.8010mA -37.0040mA -2.70 -23.0458mA -16.8800mA -37.2270mA -2.80 -23.1578mA -16.9560mA -37.4390mA -2.90 -23.2659mA -17.0290mA -37.6420mA -3.00 -23.3712mA -17.1009mA -37.8370mA -3.10 -23.4737mA -17.1709mA -38.0259mA -3.20 -23.5732mA -17.2379mA -38.2079mA -3.30 -23.6690mA -17.3046mA -38.3849mA -3.40 -23.7639mA -17.3656mA -38.5569mA -3.50 -23.8544mA -17.3881mA -38.7229mA -3.60 -23.9301mA -17.3881mA -38.8849mA -3.70 -23.9301mA -17.3881mA -39.0415mA -3.80 -23.9301mA -17.3881mA -39.1532mA -3.90 -23.9301mA -17.3881mA -39.1532mA -4.00 -23.9301mA -17.3881mA -39.1532mA -4.10 -23.9301mA -17.3881mA -39.1532mA -4.20 -23.9301mA -17.3881mA -39.1532mA -4.30 -23.9301mA -17.3881mA -39.1532mA -4.40 -23.9301mA -17.3881mA -39.1532mA -4.50 -23.9301mA -17.3881mA -39.1532mA -4.60 -23.9301mA -17.3881mA -39.1532mA -4.70 -23.9301mA -17.3881mA -39.1532mA -4.80 -23.9301mA -17.3881mA -39.1532mA -4.90 -23.9301mA -17.3881mA -39.1532mA -5.00 -23.9301mA -17.3881mA -39.1532mA -5.10 -23.9301mA -17.3881mA -39.1532mA -5.20 -23.9301mA -17.3881mA -39.1532mA -5.30 -23.9301mA -17.3881mA -39.1532mA -5.40 -23.9301mA -17.3881mA -39.1532mA -5.50 -23.9301mA -17.3881mA -39.1532mA -5.60 -23.9301mA -17.3881mA -39.1532mA -5.70 -23.9301mA -17.3881mA -39.1532mA -5.80 -23.9301mA -17.3881mA -39.1532mA -5.90 -23.9301mA -17.3881mA -39.1532mA -6.00 -23.9301mA -17.3881mA -39.1532mA -6.10 -23.9301mA -17.3881mA -39.1532mA -6.20 -23.9301mA -17.3881mA -39.1532mA -6.30 -23.9301mA -17.3881mA -39.1532mA -6.40 -23.9301mA -17.3881mA -39.1532mA -6.50 -23.9301mA -17.3881mA -39.1532mA -6.55 -23.9301mA -17.3881mA -39.1532mA -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A -0.9287A - -3.15 -0.8816A -0.8571A -0.9041A - -3.10 -0.8571A -0.8328A -0.8794A - -3.05 -0.8326A -0.8084A -0.8548A - -3.00 -0.8081A -0.7841A -0.8302A - -2.95 -0.7837A -0.7598A -0.8056A - -2.90 -0.7592A -0.7356A -0.781A - -2.85 -0.7348A -0.7113A -0.7565A - -2.80 -0.7104A -0.6872A -0.7319A - -2.75 -0.686A -0.663A -0.7074A - -2.70 -0.6617A -0.6389A -0.6829A - -2.65 -0.6374A -0.6149A -0.6584A - -2.60 -0.6131A -0.5909A -0.634A - -2.55 -0.5889A -0.5669A -0.6096A - -2.50 -0.5647A -0.5431A -0.5852A - -2.45 -0.5406A -0.5193A -0.5609A - -2.40 -0.5166A -0.4956A -0.5366A - -2.35 -0.4926A -0.472A -0.5124A - -2.30 -0.4687A -0.4485A -0.4882A - -2.25 -0.4449A -0.4251A -0.4641A - -2.20 -0.4211A -0.4019A -0.44A - -2.15 -0.3976A -0.3789A -0.4161A - -2.10 -0.3741A -0.3562A -0.3923A - -2.05 -0.3509A -0.3337A -0.3686A - -2.00 -0.3279A -0.3116A -0.3451A - -1.95 -0.3052A -0.2899A -0.3218A - -1.90 -0.283A -0.2689A -0.2988A - -1.85 -0.2612A -0.2486A -0.2762A - -1.80 -0.2402A -0.2294A -0.2543A - -1.75 -0.2204A -0.2116A -0.2332A - -1.70 -0.202A -0.1954A -0.2135A - -1.65 -0.1857A -0.181A -0.1959A - -1.60 -0.1717A -0.1682A -0.181A - -1.55 -0.1594A -0.1563A -0.1685A - -1.50 -0.1481A -0.1452A -0.1571A - -1.45 -0.1372A -0.1343A -0.1462A - -1.40 -0.1266A -0.1237A -0.1355A - -1.35 -0.1162A -0.1132A -0.125A - -1.30 -0.106A -0.1029A -0.1146A - -1.25 -95.9599mA -92.8329mA -0.1046A - -1.20 -86.1849mA -82.9339mA -94.9069mA - -1.15 -76.7349mA -73.2869mA -85.7379mA - -1.10 -67.7089mA -63.9519mA -77.2789mA - -1.05 -59.2439mA -55.0099mA -69.7479mA - -1.00 -51.5159mA -46.5729mA -63.2139mA - -0.95 -44.7119mA -38.7979mA -57.3089mA - -0.90 -38.8659mA -31.8819mA -51.2599mA - -0.85 -33.5299mA -25.9129mA -44.7209mA - -0.80 -28.2499mA -20.5839mA -37.9699mA - -0.75 -23.0669mA -15.7839mA -31.2789mA - -0.70 -18.0989mA -11.6329mA -24.8089mA - -0.65 -13.4569mA -8.1389mA -18.6889mA - -0.60 -9.2667mA -5.2646mA -13.0589mA - -0.55 -5.6915mA -3.0244mA -8.1194mA - -0.50 -2.937mA -1.4709mA -4.1747mA - -0.45 -1.1814mA -0.5866mA -1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.6648mA 0.7494mA 0.5971mA - -3.15 0.5464mA 0.6392mA 0.4620mA - -3.05 0.4320mA 0.5325mA 0.3346mA - -2.95 0.3223mA 0.4288mA 0.2203mA - -2.85 0.2202mA 0.3288mA 0.1294mA - -2.75 0.1318mA 0.2341mA 72.8310uA - -2.65 67.1930uA 0.1484mA 47.8290uA - -2.55 33.3830uA 79.2120uA 38.1420uA - -2.45 21.1010uA 36.2260uA 33.4220uA - -2.35 16.7340uA 18.9530uA 30.1320uA - -2.25 14.6010uA 13.5620uA 27.2560uA - -2.15 13.0520uA 11.4690uA 24.5640uA - -2.05 11.6720uA 10.2210uA 22.0120uA - -1.95 10.3780uA 9.1893uA 19.5960uA - -1.85 9.1543uA 8.2396uA 17.3210uA - -1.75 8.0014uA 7.3461uA 15.1920uA - -1.65 6.9210uA 6.5045uA 13.2170uA - -1.55 5.9158uA 5.7141uA 11.4020uA - -1.45 4.9887uA 4.9753uA 9.7529uA - -1.35 4.1426uA 4.2887uA 8.2767uA - -1.25 3.3804uA 3.6548uA 6.9786uA - -1.15 2.7049uA 3.0746uA 5.8648uA - -1.05 2.1189uA 2.5487uA 4.9428uA - -0.95 1.6251uA 2.0780uA 4.2177uA - -0.85 1.2274uA 1.6631uA 3.6560uA - -0.75 0.9313uA 1.3051uA 3.6560uA - -0.65 0.7398uA 1.0056uA 3.6560uA - -0.55 0.6327uA 0.7679uA 3.6560uA - -0.45 0.5649uA 0.5968uA 1.9769uA - -0.35 0.5649uA 0.4927uA 1.5352uA - -0.25 0.5649uA 0.4380uA 1.2603uA - -0.15 0.5649uA 0.4056uA 1.0262uA - -0.05 0.2497uA 0.3924uA 0.8243uA - 0.00 0.1905uA 0.3924uA 0.7347uA - 0.05 0.1661uA 0.3924uA 0.6522uA - 0.15 0.1377uA 0.3924uA 0.5077uA - 0.25 0.1149uA 0.2673uA 0.3882uA - 0.35 95.5840nA 94.4790nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2001nA 17.4270nA -0.8025nA - 1.55 4.6216nA 13.7460nA -4.4469nA - 1.65 1.0975nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8985nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2565nA -22.2600nA - 2.15 -16.3730nA -7.8414nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -[Ramp] -| variable typ min max -dV/dt_r 0.7026/0.4330n 0.4966/0.5731n 1.0018/0.3242n -dV/dt_f 0.6827/0.4387n 0.4730/0.5599n 0.9168/0.3576n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 2.1621V 2.3517V 1.9420V -0.1010nS 2.1621V 2.3517V 1.9420V -0.2020nS 2.1621V 2.3517V 1.9420V -0.3030nS 2.1621V 2.3517V 1.9420V -0.4040nS 2.1621V 2.3517V 1.9420V -0.5051nS 2.1622V 2.3517V 2.2421V -0.6061nS 2.1615V 2.3517V 2.8060V -0.7071nS 2.2762V 2.3517V 3.1342V -0.8081nS 2.7361V 2.3522V 3.3164V -0.9091nS 2.9561V 2.3515V 3.3898V -1.0101nS 3.0907V 2.3704V 3.4244V -1.1111nS 3.1772V 2.6051V 3.4432V -1.2121nS 3.2242V 2.8360V 3.4539V -1.3131nS 3.2509V 2.9413V 3.4602V -1.4141nS 3.2670V 3.0020V 3.4639V -1.5152nS 3.2775V 3.0439V 3.4662V -1.6162nS 3.2845V 3.0714V 3.4676V -1.7172nS 3.2892V 3.0897V 3.4685V -1.8182nS 3.2924V 3.1025V 3.4690V -1.9192nS 3.2946V 3.1117V 3.4694V -2.0202nS 3.2961V 3.1186V 3.4696V -2.1212nS 3.2972V 3.1237V 3.4697V -2.2222nS 3.2980V 3.1276V 3.4698V -2.3232nS 3.2986V 3.1305V 3.4699V -2.4242nS 3.2989V 3.1327V 3.4699V -2.5253nS 3.2992V 3.1344V 3.4699V -2.6263nS 3.2994V 3.1356V 3.4699V -2.7273nS 3.2996V 3.1366V 3.4699V -2.8283nS 3.2997V 3.1373V 3.4699V -2.9293nS 3.2998V 3.1379V 3.4700V -3.0303nS 3.2998V 3.1383V 3.4699V -3.1313nS 3.2999V 3.1387V 3.4700V -3.2323nS 3.2999V 3.1390V 3.4699V -3.3333nS 3.2999V 3.1392V 3.4700V -3.4343nS 3.2999V 3.1393V 3.4699V -3.5354nS 3.2999V 3.1395V 3.4700V -3.6364nS 3.3000V 3.1396V 3.4699V -3.7374nS 3.3000V 3.1397V 3.4700V -3.8384nS 3.3000V 3.1397V 3.4700V -3.9394nS 3.3000V 3.1398V 3.4700V -4.0404nS 3.3000V 3.1398V 3.4700V -4.1414nS 3.3000V 3.1399V 3.4700V -4.2424nS 3.3000V 3.1399V 3.4700V -4.3434nS 3.3000V 3.1399V 3.4700V -4.4444nS 3.3000V 3.1400V 3.4700V -4.5455nS 3.3000V 3.1400V 3.4700V -4.6465nS 3.3000V 3.1399V 3.4700V -4.7475nS 3.3000V 3.1400V 3.4700V -4.8485nS 3.3000V 3.1400V 3.4700V -4.9495nS 3.3000V 3.1400V 3.4700V -5.0505nS 3.3000V 3.1400V 3.4700V -5.1515nS 3.3000V 3.1400V 3.4699V -5.2525nS 3.3000V 3.1400V 3.4700V -5.3535nS 3.3000V 3.1400V 3.4700V -5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4699V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4699V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4699V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4699V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4699V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 3.3000V 3.1400V 3.4700V -8.4848nS 3.3000V 3.1400V 3.4700V -8.5859nS 3.3000V 3.1400V 3.4700V -8.6869nS 3.3000V 3.1400V 3.4700V -8.7879nS 3.3000V 3.1400V 3.4700V -8.8889nS 3.3000V 3.1400V 3.4700V -8.9899nS 3.3000V 3.1400V 3.4700V -9.0909nS 3.3000V 3.1400V 3.4700V -9.1919nS 3.3000V 3.1400V 3.4700V -9.2929nS 3.3000V 3.1400V 3.4700V -9.3939nS 3.3000V 3.1400V 3.4700V -9.4949nS 3.3000V 3.1400V 3.4700V -9.5960nS 3.3000V 3.1400V 3.4700V -9.6970nS 3.3000V 3.1400V 3.4700V -9.7980nS 3.3000V 3.1400V 3.4700V -9.8990nS 3.3000V 3.1400V 3.4700V -10.0000nS 3.3000V 3.1400V 3.4700V -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 1.2884uV 1.5543uV 1.3225uV -0.1010nS 0.5355uV 0.8430uV 0.6254uV -0.2020nS -3.0614uV 0.1113uV 0.5701uV -0.3030nS 0.6806uV -1.9546uV 10.3860uV -0.4040nS 3.2624uV 1.2769uV -0.2118mV -0.5051nS 32.7230uV 1.5286uV -24.1640mV -0.6061nS -0.3955mV 2.8080uV -9.9395mV -0.7071nS -15.7200mV 17.6660uV 0.1561V -0.8081nS -19.9850mV 99.9200uV 0.5397V -0.9091nS -0.4586mV -0.2072mV 0.9226V -1.0101nS 88.3420mV -6.1838mV 1.2091V -1.1111nS 0.2478V -18.1000mV 1.3886V -1.2121nS 0.4471V -16.0430mV 1.4951V -1.3131nS 0.6318V -10.1180mV 1.5589V -1.4141nS 0.7749V 8.8815mV 1.5984V -1.5152nS 0.8766V 55.5920mV 1.6234V -1.6162nS 0.9465V 0.1340V 1.6394V -1.7172nS 0.9942V 0.2360V 1.6498V -1.8182nS 1.0272V 0.3461V 1.6566V -1.9192nS 1.0502V 0.4492V 1.6613V -2.0202nS 1.0667V 0.5367V 1.6638V -2.1212nS 1.0785V 0.6066V 1.6656V -2.2222nS 1.0871V 0.6605V 1.6667V -2.3232nS 1.0934V 0.7013V 1.6675V -2.4242nS 1.0979V 0.7318V 1.6680V -2.5253nS 1.1013V 0.7546V 1.6684V -2.6263nS 1.1038V 0.7716V 1.6687V -2.7273nS 1.1056V 0.7845V 1.6689V -2.8283nS 1.1069V 0.7942V 1.6691V -2.9293nS 1.1080V 0.8016V 1.6693V -3.0303nS 1.1087V 0.8073V 1.6693V -3.1313nS 1.1093V 0.8118V 1.6694V -3.2323nS 1.1097V 0.8152V 1.6695V -3.3333nS 1.1100V 0.8178V 1.6695V -3.4343nS 1.1103V 0.8199V 1.6695V -3.5354nS 1.1104V 0.8215V 1.6696V -3.6364nS 1.1105V 0.8228V 1.6695V -3.7374nS 1.1106V 0.8238V 1.6696V -3.8384nS 1.1107V 0.8246V 1.6696V -3.9394nS 1.1107V 0.8252V 1.6696V -4.0404nS 1.1108V 0.8257V 1.6696V -4.1414nS 1.1108V 0.8261V 1.6696V -4.2424nS 1.1108V 0.8265V 1.6696V -4.3434nS 1.1109V 0.8267V 1.6696V -4.4444nS 1.1109V 0.8269V 1.6696V -4.5455nS 1.1109V 0.8271V 1.6696V -4.6465nS 1.1109V 0.8272V 1.6696V -4.7475nS 1.1109V 0.8273V 1.6696V -4.8485nS 1.1109V 0.8274V 1.6696V -4.9495nS 1.1109V 0.8274V 1.6696V -5.0505nS 1.1109V 0.8276V 1.6696V -5.1515nS 1.1109V 0.8276V 1.6696V -5.2525nS 1.1109V 0.8276V 1.6696V -5.3535nS 1.1109V 0.8276V 1.6696V -5.4545nS 1.1109V 0.8276V 1.6696V -5.5556nS 1.1109V 0.8276V 1.6696V -5.6566nS 1.1109V 0.8276V 1.6696V -5.7576nS 1.1109V 0.8277V 1.6696V -5.8586nS 1.1109V 0.8277V 1.6696V -5.9596nS 1.1109V 0.8277V 1.6696V -6.0606nS 1.1109V 0.8277V 1.6696V -6.1616nS 1.1109V 0.8277V 1.6696V -6.2626nS 1.1109V 0.8277V 1.6696V -6.3636nS 1.1109V 0.8277V 1.6696V -6.4646nS 1.1109V 0.8277V 1.6696V -6.5657nS 1.1109V 0.8277V 1.6696V -6.6667nS 1.1110V 0.8277V 1.6696V -6.7677nS 1.1109V 0.8277V 1.6696V -6.8687nS 1.1109V 0.8277V 1.6696V -6.9697nS 1.1109V 0.8277V 1.6696V -7.0707nS 1.1110V 0.8277V 1.6696V -7.1717nS 1.1109V 0.8277V 1.6696V -7.2727nS 1.1110V 0.8277V 1.6696V -7.3737nS 1.1110V 0.8277V 1.6696V -7.4747nS 1.1110V 0.8277V 1.6696V -7.5758nS 1.1110V 0.8277V 1.6696V -7.6768nS 1.1110V 0.8277V 1.6696V -7.7778nS 1.1109V 0.8277V 1.6696V -7.8788nS 1.1110V 0.8277V 1.6696V -7.9798nS 1.1110V 0.8277V 1.6696V -8.0808nS 1.1110V 0.8277V 1.6696V -8.1818nS 1.1109V 0.8277V 1.6696V -8.2828nS 1.1110V 0.8277V 1.6696V -8.3838nS 1.1110V 0.8277V 1.6696V -8.4848nS 1.1110V 0.8277V 1.6696V -8.5859nS 1.1110V 0.8277V 1.6696V -8.6869nS 1.1110V 0.8277V 1.6696V -8.7879nS 1.1109V 0.8277V 1.6696V -8.8889nS 1.1109V 0.8277V 1.6696V -8.9899nS 1.1109V 0.8277V 1.6696V -9.0909nS 1.1109V 0.8277V 1.6696V -9.1919nS 1.1109V 0.8277V 1.6696V -9.2929nS 1.1109V 0.8277V 1.6696V -9.3939nS 1.1109V 0.8277V 1.6696V -9.4949nS 1.1109V 0.8277V 1.6696V -9.5960nS 1.1109V 0.8277V 1.6696V -9.6970nS 1.1110V 0.8277V 1.6696V -9.7980nS 1.1110V 0.8277V 1.6696V -9.8990nS 1.1110V 0.8277V 1.6696V -10.0000nS 1.1109V 0.8277V 1.6696V -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 1.1109V 0.8277V 1.6696V -0.1010nS 1.1109V 0.8277V 1.6696V -0.2020nS 1.1109V 0.8277V 1.6696V -0.3030nS 1.1110V 0.8277V 1.6696V -0.4040nS 1.1110V 0.8277V 1.6696V -0.5051nS 1.1109V 0.8277V 1.6644V -0.6061nS 1.1110V 0.8277V 1.0431V -0.7071nS 1.1113V 0.8277V 0.4157V -0.8081nS 0.9851V 0.8277V 0.1612V -0.9091nS 0.5727V 0.8276V 77.0900mV -1.0101nS 0.2814V 0.8282V 40.8740mV -1.1111nS 0.1329V 0.8285V 22.9430mV -1.2121nS 73.6840mV 0.7997V 12.4510mV -1.3131nS 43.0370mV 0.5895V 6.8313mV -1.4141nS 26.7550mV 0.3604V 3.7992mV -1.5152nS 17.0970mV 0.2116V 2.1510mV -1.6162nS 11.1140mV 0.1248V 1.2529mV -1.7172nS 7.2776mV 75.3210mV 0.7544mV -1.8182nS 4.8176mV 47.2290mV 0.4826mV -1.9192nS 3.1888mV 31.3570mV 0.3253mV -2.0202nS 2.1519mV 21.8020mV 0.2392mV -2.1212nS 1.4430mV 15.5850mV 0.1806mV -2.2222nS 1.0065mV 11.3310mV 0.1485mV -2.3232nS 0.6888mV 8.3187mV 0.1251mV -2.4242nS 0.5069mV 6.1527mV 0.1108mV -2.5253nS 0.3566mV 4.5704mV 0.1026mV -2.6263nS 0.2717mV 3.4134mV 96.2470uV -2.7273nS 0.1995mV 2.5569mV 87.3860uV -2.8283nS 0.1853mV 1.9272mV 82.9260uV -2.9293nS 0.1277mV 1.4565mV 68.6140uV -3.0303nS 0.1252mV 1.1098mV 60.2230uV -3.1313nS 89.5590uV 0.8485mV 49.7170uV -3.2323nS 94.4160uV 0.6561mV 56.7570uV -3.3333nS 49.7470uV 0.5093mV 54.1530uV -3.4343nS 57.0870uV 0.3863mV 49.3370uV -3.5354nS 52.4280uV 0.3073mV 42.7020uV -3.6364nS 77.0030uV 0.2451mV 40.7070uV -3.7374nS 46.1550uV 0.1875mV 33.9890uV -3.8384nS 63.3650uV 0.1621mV 34.0740uV -3.9394nS 31.9750uV 0.1378mV 27.5110uV -4.0404nS 46.0820uV 0.1176mV 33.5240uV -4.1414nS 14.0450uV 0.1002mV 26.4520uV -4.2424nS 30.8440uV 91.6770uV 22.6270uV -4.3434nS 23.9580uV 76.4830uV 15.2880uV -4.4444nS 37.9550uV 66.7720uV 22.2140uV -4.5455nS 20.1420uV 54.3060uV 29.8260uV -4.6465nS 38.7320uV 46.2710uV 31.2670uV -4.7475nS 7.9010uV 34.7060uV 23.8310uV -4.8485nS 28.9680uV 27.4260uV 23.1060uV -4.9495nS 3.7079uV 16.8370uV 10.7150uV -5.0505nS 4.6522uV 25.8205uV 14.7445uV -5.1515nS 12.5270uV 19.1810uV 11.7510uV -5.2525nS 10.5410uV 17.0160uV 5.4213uV -5.3535nS 42.1190uV 11.8180uV 8.5329uV -5.4545nS 11.4930uV 19.2340uV 13.1240uV -5.5556nS 38.3480uV 27.0890uV 18.1120uV -5.6566nS 1.7742uV 38.8120uV 11.7850uV -5.7576nS 22.6050uV 31.4050uV 7.1004uV -5.8586nS -3.9145uV 19.9240uV -7.3305uV -5.9596nS 13.3160uV 7.4008uV 0.4354uV -6.0606nS 7.3534uV -0.9538uV 7.7540uV -6.1616nS 33.4920uV -8.2614uV 8.9420uV -6.2626nS 9.8852uV 1.6769uV 5.0332uV -6.3636nS 25.5040uV 16.3790uV 2.4944uV -6.4646nS -2.5946uV 32.5920uV -5.3283uV -6.5657nS 4.1073uV 30.8730uV 6.9637uV -6.6667nS 2.1062uV 21.8930uV 7.5789uV -6.7677nS 10.6270uV 5.1201uV 6.5788uV -6.8687nS -19.4020uV -8.0928uV 0.9709uV -6.9697nS 3.6023uV 5.3486uV -0.4159uV -7.0707nS -20.2800uV 10.3380uV -4.1503uV -7.1717nS 19.4790uV 23.0950uV -4.9697uV -7.2727nS -10.7860uV 7.5118uV -8.6698uV -7.3737nS 21.7550uV 9.0311uV -7.4803uV -7.4747nS 12.4390uV -5.6908uV -10.4050uV -7.5758nS 18.3510uV -4.5175uV -8.2164uV -7.6768nS -7.8114uV 1.1510uV -10.8020uV -7.7778nS 2.0275uV 12.3600uV -1.5528uV -7.8788nS -76.1190nV 12.0690uV 6.6952uV -7.9798nS 4.0097uV 8.9861uV 10.0890uV -8.0808nS 0.4972uV -1.8875uV 0.6130uV -8.1818nS 0.5840uV -11.3150uV -1.5820uV -8.2828nS -12.7280uV -15.9390uV -8.5048uV -8.3838nS 3.4867uV -5.2058uV -1.9719uV -8.4848nS -4.5739uV 2.6217uV 0.5424uV -8.5859nS 4.1249uV 2.6585uV 4.0878uV -8.6869nS -12.0140uV -0.6919uV 6.4732uV -8.7879nS -3.8915uV -10.4690uV 7.0541uV -8.8889nS -10.5260uV -22.7580uV 2.8919uV -8.9899nS 2.5661uV -25.3070uV -3.3709uV -9.0909nS -2.9240uV -11.4390uV -5.9996uV -9.1919nS -3.0241uV -1.1643uV 0.8082uV -9.2929nS -7.9366uV 5.3328uV 0.4492uV -9.3939nS -2.3621uV 8.5118uV 5.8039uV -9.4949nS -9.1146uV -8.6006uV -2.4704uV -9.5960nS -3.7574uV -19.3450uV -0.8494uV -9.6970nS -16.6030uV -15.4900uV -2.2380uV -9.7980nS -2.4824uV -3.6242uV 4.0030uV -9.8990nS -18.6820uV 15.5490uV 1.5950uV -10.0000nS -1.0707uV 8.4164uV -6.6712uV -| -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 3.3000V 3.1400V 3.4700V -0.1010nS 3.3000V 3.1400V 3.4700V -0.2020nS 3.3000V 3.1400V 3.4700V -0.3030nS 3.3000V 3.1400V 3.4700V -0.4040nS 3.3000V 3.1400V 3.4700V -0.5051nS 3.3000V 3.1400V 3.4758V -0.6061nS 3.3001V 3.1400V 3.4570V -0.7071nS 3.2983V 3.1400V 3.0951V -0.8081nS 3.3299V 3.1400V 2.7403V -0.9091nS 3.2987V 3.1398V 2.4747V -1.0101nS 3.1080V 3.1409V 2.2935V -1.1111nS 2.8866V 3.1388V 2.1742V -1.2121nS 2.6919V 3.1507V 2.0966V -1.3131nS 2.5414V 3.1748V 2.0453V -1.4141nS 2.4321V 3.1565V 2.0112V -1.5152nS 2.3547V 3.0752V 1.9884V -1.6162nS 2.3001V 2.9642V 1.9732V -1.7172nS 2.2616V 2.8458V 1.9629V -1.8182nS 2.2341V 2.7389V 1.9561V -1.9192nS 2.2145V 2.6506V 1.9515V -2.0202nS 2.2003V 2.5809V 1.9484V -2.1212nS 2.1900V 2.5272V 1.9463V -2.2222nS 2.1826V 2.4862V 1.9450V -2.3232nS 2.1771V 2.4551V 1.9440V -2.4242nS 2.1731V 2.4314V 1.9434V -2.5253nS 2.1702V 2.4134V 1.9430V -2.6263nS 2.1681V 2.3996V 1.9427V -2.7273nS 2.1665V 2.3890V 1.9425V -2.8283nS 2.1654V 2.3808V 1.9424V -2.9293nS 2.1646V 2.3745V 1.9423V -3.0303nS 2.1639V 2.3696V 1.9422V -3.1313nS 2.1635V 2.3658V 1.9422V -3.2323nS 2.1631V 2.3628V 1.9421V -3.3333nS 2.1629V 2.3604V 1.9421V -3.4343nS 2.1627V 2.3586V 1.9421V -3.5354nS 2.1626V 2.3572V 1.9420V -3.6364nS 2.1625V 2.3560V 1.9421V -3.7374nS 2.1624V 2.3551V 1.9421V -3.8384nS 2.1623V 2.3544V 1.9421V -3.9394nS 2.1623V 2.3539V 1.9420V -4.0404nS 2.1622V 2.3534V 1.9420V -4.1414nS 2.1622V 2.3531V 1.9420V -4.2424nS 2.1622V 2.3528V 1.9420V -4.3434nS 2.1622V 2.3526V 1.9420V -4.4444nS 2.1622V 2.3524V 1.9420V -4.5455nS 2.1622V 2.3523V 1.9420V -4.6465nS 2.1622V 2.3522V 1.9420V -4.7475nS 2.1622V 2.3521V 1.9420V -4.8485nS 2.1622V 2.3520V 1.9420V -4.9495nS 2.1622V 2.3519V 1.9420V -5.0505nS 2.1622V 2.3519V 1.9420V -5.1515nS 2.1622V 2.3518V 1.9420V -5.2525nS 2.1622V 2.3518V 1.9420V -5.3535nS 2.1622V 2.3518V 1.9420V -5.4545nS 2.1622V 2.3518V 1.9420V -5.5556nS 2.1622V 2.3518V 1.9420V -5.6566nS 2.1622V 2.3517V 1.9420V -5.7576nS 2.1621V 2.3517V 1.9420V -5.8586nS 2.1621V 2.3517V 1.9420V -5.9596nS 2.1621V 2.3517V 1.9420V -6.0606nS 2.1621V 2.3517V 1.9420V -6.1616nS 2.1621V 2.3517V 1.9420V -6.2626nS 2.1621V 2.3517V 1.9420V -6.3636nS 2.1621V 2.3517V 1.9420V -6.4646nS 2.1621V 2.3517V 1.9420V -6.5657nS 2.1621V 2.3517V 1.9420V -6.6667nS 2.1622V 2.3517V 1.9420V -6.7677nS 2.1621V 2.3517V 1.9420V -6.8687nS 2.1621V 2.3517V 1.9420V -6.9697nS 2.1621V 2.3517V 1.9420V -7.0707nS 2.1621V 2.3517V 1.9420V -7.1717nS 2.1621V 2.3517V 1.9420V -7.2727nS 2.1621V 2.3517V 1.9420V -7.3737nS 2.1621V 2.3517V 1.9420V -7.4747nS 2.1621V 2.3517V 1.9420V -7.5758nS 2.1621V 2.3517V 1.9420V -7.6768nS 2.1621V 2.3517V 1.9420V -7.7778nS 2.1621V 2.3517V 1.9420V -7.8788nS 2.1621V 2.3517V 1.9420V -7.9798nS 2.1621V 2.3517V 1.9420V -8.0808nS 2.1621V 2.3517V 1.9420V -8.1818nS 2.1621V 2.3517V 1.9420V -8.2828nS 2.1621V 2.3517V 1.9420V -8.3838nS 2.1621V 2.3517V 1.9420V -8.4848nS 2.1621V 2.3517V 1.9420V -8.5859nS 2.1621V 2.3517V 1.9420V -8.6869nS 2.1621V 2.3517V 1.9420V -8.7879nS 2.1621V 2.3517V 1.9420V -8.8889nS 2.1621V 2.3517V 1.9420V -8.9899nS 2.1621V 2.3517V 1.9420V -9.0909nS 2.1621V 2.3517V 1.9420V -9.1919nS 2.1621V 2.3517V 1.9420V -9.2929nS 2.1621V 2.3517V 1.9420V -9.3939nS 2.1621V 2.3517V 1.9420V -9.4949nS 2.1621V 2.3517V 1.9420V -9.5960nS 2.1621V 2.3517V 1.9420V -9.6970nS 2.1621V 2.3517V 1.9420V -9.7980nS 2.1621V 2.3517V 1.9420V -9.8990nS 2.1621V 2.3517V 1.9420V -10.0000nS 2.1621V 2.3517V 1.9420V -| -| End [Model] lvt330s040aaaaaaaaou -|************************************************************************ -[Model] lvt330s040haaaaaaaio -Model_type I/O -Polarity Non-Inverting -Enable Active-Low -Vinl = 0.8000V -Vinh = 2.0000V -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -13.0175mA -9.4589mA -17.0245mA - -3.20 -12.9707mA -9.4248mA -16.9624mA - -3.10 -12.9240mA -9.3908mA -16.9003mA - -3.00 -12.8773mA -9.3568mA -16.8383mA - -2.90 -12.8305mA -9.3227mA -16.7762mA - -2.80 -12.7838mA -9.2887mA -16.7142mA - -2.70 -12.7370mA -9.2546mA -16.6521mA - -2.60 -12.6903mA -9.2206mA -16.5900mA - -2.50 -12.6435mA -9.1866mA -16.5280mA - -2.40 -12.5968mA -9.1525mA -16.4659mA - -2.30 -12.5500mA -9.1185mA -16.4038mA - -2.20 -12.5033mA -9.0845mA -16.3418mA - -2.10 -12.4566mA -9.0504mA -16.2797mA - -2.00 -12.4098mA -9.0164mA -16.2176mA - -1.90 -12.3631mA -8.9824mA -16.1556mA - -1.80 -12.3163mA -8.9483mA -16.0935mA - -1.70 -12.2696mA -8.9143mA -16.0314mA - -1.60 -12.2228mA -8.8803mA -15.9694mA - -1.50 -12.1761mA -8.8462mA -15.9073mA - -1.40 -12.1293mA -8.8122mA -15.8453mA - -1.30 -12.0826mA -8.7781mA -15.7832mA - -1.20 -12.0359mA -8.7441mA -15.7211mA - -1.10 -11.9891mA -8.7101mA -15.6591mA - -1.00 -11.9424mA -8.6760mA -15.5970mA - -0.90 -11.8920mA -8.6420mA -14.2580mA - -0.80 -11.2030mA -8.5040mA -13.3310mA - -0.70 -10.6640mA -8.3180mA -12.8580mA - -0.60 -10.1775mA -7.9085mA -12.5090mA - -0.50 -9.6242mA -7.2249mA -12.2652mA - -0.40 -8.4558mA -6.0810mA -11.1990mA - -0.30 -6.5017mA -4.6206mA -8.6527mA - -0.20 -4.3829mA -3.0989mA -5.8476mA - -0.10 -2.2159mA -1.5586mA -2.9656mA - 0.00 1.3970nA 1.1420nA 1.8430nA - 0.10 2.1875mA 1.5273mA 2.9429mA - 0.20 4.2657mA 2.9723mA 5.7511mA - 0.30 6.2349mA 4.3353mA 8.4238mA - 0.40 8.0952mA 5.6169mA 10.9612mA - 0.50 9.8472mA 6.8175mA 13.3613mA - 0.60 11.4909mA 7.9379mA 15.6250mA - 0.70 13.0251mA 8.9781mA 17.7500mA - 0.80 14.4502mA 9.9381mA 19.7321mA - 0.90 15.7635mA 10.8176mA 21.5658mA - 1.00 16.9605mA 11.6151mA 23.2399mA - 1.10 18.0347mA 12.3297mA 24.7385mA - 1.20 18.9760mA 12.9574mA 26.0423mA - 1.30 19.7754mA 13.4941mA 27.1313mA - 1.40 20.4319mA 13.9418mA 28.0074mA - 1.50 21.1825mA 14.4344mA 28.6916mA - 1.60 21.5959mA 14.7249mA 29.6115mA - 1.70 21.9250mA 14.9601mA 30.0279mA - 1.80 22.1935mA 15.1539mA 30.3626mA - 1.90 22.4157mA 15.3154mA 30.6368mA - 2.00 22.6034mA 15.4536mA 30.8683mA - 2.10 22.7656mA 15.5735mA 31.0653mA - 2.20 22.9074mA 15.6790mA 31.2357mA - 2.30 23.0328mA 15.7722mA 31.3865mA - 2.40 23.1458mA 15.8561mA 31.5207mA - 2.50 23.2463mA 15.9326mA 31.6404mA - 2.60 23.3383mA 16.0018mA 31.7495mA - 2.70 23.4230mA 16.0657mA 31.8480mA - 2.80 23.5002mA 16.1243mA 31.9389mA - 2.90 23.5720mA 16.1785mA 32.0223mA - 3.00 23.6383mA 16.2294mA 32.0991mA - 3.10 23.7003mA 16.2770mA 32.1714mA - 3.20 23.7588mA 16.3211mA 32.2390mA - 3.30 23.8138mA 16.3630mA 32.3031mA - 3.40 23.8674mA 16.4006mA 32.3667mA - 3.50 23.9193mA 16.4233mA 32.4306mA - 3.60 23.9674mA 16.4889mA 32.4982mA - 3.70 23.9882mA 16.5546mA 32.5708mA - 3.80 24.0840mA 16.6202mA 32.6441mA - 3.90 24.1798mA 16.6859mA 32.7359mA - 4.00 24.2756mA 16.7515mA 32.8665mA - 4.10 24.3714mA 16.8172mA 32.9972mA - 4.20 24.4672mA 16.8828mA 33.1278mA - 4.30 24.5630mA 16.9485mA 33.2584mA - 4.40 24.6588mA 17.0142mA 33.3891mA - 4.50 24.7546mA 17.0798mA 33.5197mA - 4.60 24.8504mA 17.1455mA 33.6503mA - 4.70 24.9462mA 17.2111mA 33.7810mA - 4.80 25.0420mA 17.2768mA 33.9116mA - 4.90 25.1378mA 17.3424mA 34.0423mA - 5.00 25.2336mA 17.4081mA 34.1729mA - 5.10 25.3294mA 17.4737mA 34.3035mA - 5.20 25.4252mA 17.5394mA 34.4342mA - 5.30 25.5210mA 17.6051mA 34.5648mA - 5.40 25.6168mA 17.6707mA 34.6955mA - 5.50 25.7126mA 17.7364mA 34.8261mA - 5.60 25.8084mA 17.8020mA 34.9567mA - 5.70 25.9042mA 17.8677mA 35.0874mA - 5.80 25.9999mA 17.9333mA 35.2180mA - 5.90 26.0957mA 17.9990mA 35.3486mA - 6.00 26.1915mA 18.0647mA 35.4793mA - 6.10 26.2873mA 18.1303mA 35.6099mA - 6.20 26.3831mA 18.1960mA 35.7406mA - 6.30 26.4789mA 18.2616mA 35.8712mA - 6.40 26.5747mA 18.3273mA 36.0018mA - 6.50 26.6705mA 18.3929mA 36.1325mA - 6.60 26.7663mA 18.4586mA 36.2631mA -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| --3.30 60.9662mA 46.6308mA 87.0217mA --3.20 60.7240mA 46.4472mA 86.7600mA --3.10 60.2994mA 46.2636mA 85.3500mA --3.00 59.0755mA 46.0800mA 83.1700mA --2.90 57.3963mA 45.5300mA 80.5900mA --2.80 55.4705mA 44.3800mA 77.7700mA --2.70 53.3739mA 42.9200mA 74.8000mA --2.60 51.1729mA 41.2800mA 71.7300mA --2.50 48.8960mA 39.5320mA 68.6000mA --2.40 46.5650mA 37.7130mA 65.4100mA --2.30 44.2113mA 35.8570mA 62.2000mA --2.20 41.8320mA 33.9950mA 58.9610mA --2.10 39.4555mA 32.1310mA 55.7110mA --2.00 37.1056mA 30.2880mA 52.4470mA --1.90 34.7793mA 28.4710mA 49.1720mA --1.80 32.5319mA 26.6850mA 45.8900mA --1.70 30.3631mA 24.9360mA 42.6060mA --1.60 28.2959mA 23.2280mA 39.3910mA --1.50 26.3236mA 21.5600mA 36.3540mA --1.40 24.4385mA 19.9360mA 33.5720mA --1.30 22.6312mA 18.3560mA 31.0630mA --1.20 20.8932mA 16.8240mA 28.8020mA --1.10 19.2273mA 15.3490mA 26.8550mA --1.00 17.6525mA 13.9360mA 25.6750mA --0.90 16.2417mA 12.5950mA 24.4660mA --0.80 14.9068mA 11.3600mA 21.3180mA --0.70 13.2931mA 10.2971mA 18.9703mA --0.60 11.6685mA 9.2483mA 16.9105mA --0.50 9.9513mA 7.8709mA 14.6683mA --0.40 7.9801mA 6.2914mA 11.8564mA --0.30 5.9303mA 4.6622mA 8.8439mA --0.20 3.9153mA 3.0657mA 5.8617mA --0.10 1.9400mA 1.5124mA 2.9160mA -0.00 -6.9700nA -2.5700nA -86.5000nA -0.10 -1.8799mA -1.4564mA -2.8429mA -0.20 -3.6735mA -2.8408mA -5.5653mA -0.30 -5.3808mA -4.1535mA -8.1679mA -0.40 -7.0025mA -5.3952mA -10.6515mA -0.50 -8.5393mA -6.5665mA -13.0149mA -0.60 -9.9917mA -7.6679mA -15.2608mA -0.70 -11.3594mA -8.6999mA -17.3894mA -0.80 -12.6449mA -9.6632mA -19.4005mA -0.90 -13.8465mA -10.5579mA -21.2942mA -1.00 -14.9659mA -11.3853mA -23.0724mA -1.10 -16.0032mA -12.1460mA -24.7353mA -1.20 -16.9593mA -12.8401mA -26.2837mA -1.30 -17.8352mA -13.4675mA -27.7167mA -1.40 -18.6299mA -14.0302mA -29.0372mA -1.50 -19.3454mA -14.5272mA -30.2434mA -1.60 -19.9815mA -14.9606mA -31.3381mA -1.70 -20.5404mA -15.3313mA -32.3204mA -1.80 -21.0208mA -15.7720mA -33.1924mA -1.90 -21.6437mA -16.0228mA -34.3429mA -2.00 -21.9782mA -16.2184mA -35.0021mA -2.10 -22.2442mA -16.3681mA -35.5553mA -2.20 -22.4522mA -16.4866mA -36.0104mA -2.30 -22.6203mA -16.5871mA -36.3794mA -2.40 -22.7636mA -16.6772mA -36.6831mA -2.50 -22.8919mA -16.7617mA -36.9446mA -2.60 -23.0116mA -16.8402mA -37.1814mA -2.70 -23.1247mA -16.9153mA -37.4005mA -2.80 -23.2299mA -16.9860mA -37.6054mA -2.90 -23.3289mA -17.0521mA -37.7972mA -3.00 -23.4225mA -17.1156mA -37.9765mA -3.10 -23.5107mA -17.1755mA -38.1452mA -3.20 -23.5932mA -17.2307mA -38.3020mA -3.30 -23.6690mA -17.2845mA -38.4487mA -3.40 -23.7421mA -17.3317mA -38.5851mA -3.50 -23.8099mA -17.3821mA -38.7103mA -3.60 -23.8639mA -17.4515mA -38.8302mA -3.70 -23.9593mA -17.5209mA -38.9459mA -3.80 -24.0548mA -17.5902mA -39.0277mA -3.90 -24.1501mA -17.6596mA -39.1834mA -4.00 -24.2455mA -17.7290mA -39.3392mA -4.10 -24.3409mA -17.7983mA -39.4949mA -4.20 -24.4363mA -17.8677mA -39.6506mA -4.30 -24.5317mA -17.9371mA -39.8063mA -4.40 -24.6271mA -18.0064mA -39.9620mA -4.50 -24.7225mA -18.0758mA -40.1178mA -4.60 -24.8179mA -18.1452mA -40.2735mA -4.70 -24.9133mA -18.2145mA -40.4292mA -4.80 -25.0087mA -18.2839mA -40.5849mA -4.90 -25.1041mA -18.3532mA -40.7406mA -5.00 -25.1995mA -18.4226mA -40.8964mA -5.10 -25.2949mA -18.4920mA -41.0521mA -5.20 -25.3902mA -18.5613mA -41.2078mA -5.30 -25.4857mA -18.6307mA -41.3635mA -5.40 -25.5810mA -18.7001mA -41.5192mA -5.50 -25.6765mA -18.7694mA -41.6750mA -5.60 -25.7719mA -18.8388mA -41.8307mA -5.70 -25.8673mA -18.9082mA -41.9864mA -5.80 -25.9627mA -18.9775mA -42.1421mA -5.90 -26.0580mA -19.0469mA -42.2978mA -6.00 -26.1535mA -19.1163mA -42.4536mA -6.10 -26.2488mA -19.1856mA -42.6093mA -6.20 -26.3443mA -19.2550mA -42.7650mA -6.30 -26.4396mA -19.3244mA -42.9207mA -6.40 -26.5350mA -19.3937mA -43.0764mA -6.50 -26.6305mA -19.4631mA -43.2322mA -6.55 -26.6781mA -19.4978mA -43.3100mA -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9552A -0.9302A -0.9778A - -3.25 -0.9306A -0.9058A -0.9532A - -3.20 -0.9061A -0.8814A -0.9285A - -3.15 -0.8815A -0.857A -0.9039A - -3.10 -0.857A -0.8327A -0.8792A - -3.05 -0.8325A -0.8083A -0.8546A - -3.00 -0.808A -0.784A -0.83A - -2.95 -0.7836A -0.7597A -0.8054A - -2.90 -0.7591A -0.7355A -0.7808A - -2.85 -0.7347A -0.7112A -0.7563A - -2.80 -0.7103A -0.6871A -0.7317A - -2.75 -0.6859A -0.6629A -0.7072A - -2.70 -0.6616A -0.6388A -0.6827A - -2.65 -0.6373A -0.6148A -0.6582A - -2.60 -0.613A -0.5908A -0.6338A - -2.55 -0.5888A -0.5668A -0.6094A - -2.50 -0.5646A -0.543A -0.585A - -2.45 -0.5405A -0.5192A -0.5607A - -2.40 -0.5165A -0.4955A -0.5364A - -2.35 -0.4925A -0.4719A -0.5122A - -2.30 -0.4686A -0.4484A -0.488A - -2.25 -0.4448A -0.425A -0.4639A - -2.20 -0.421A -0.4018A -0.4398A - -2.15 -0.3975A -0.3788A -0.4159A - -2.10 -0.374A -0.3561A -0.3921A - -2.05 -0.3508A -0.3336A -0.3684A - -2.00 -0.3278A -0.3115A -0.3449A - -1.95 -0.3051A -0.2898A -0.3216A - -1.90 -0.2829A -0.2688A -0.2986A - -1.85 -0.2611A -0.2485A -0.276A - -1.80 -0.2402A -0.2293A -0.2541A - -1.75 -0.2203A -0.2115A -0.233A - -1.70 -0.2019A -0.1953A -0.2133A - -1.65 -0.1856A -0.1809A -0.1957A - -1.60 -0.1716A -0.1681A -0.1809A - -1.55 -0.1593A -0.1563A -0.1683A - -1.50 -0.148A -0.1451A -0.157A - -1.45 -0.1371A -0.1342A -0.146A - -1.40 -0.1266A -0.1236A -0.1353A - -1.35 -0.1161A -0.1131A -0.1248A - -1.30 -0.1059A -0.1029A -0.1145A - -1.25 -95.8525mA -92.7685mA -0.1044A - -1.20 -86.0775mA -82.8695mA -94.7415mA - -1.15 -76.6285mA -73.2225mA -85.5735mA - -1.10 -67.6045mA -63.8875mA -77.1175mA - -1.05 -59.1405mA -54.9455mA -69.5895mA - -1.00 -51.4145mA -46.5095mA -63.0585mA - -0.95 -44.6125mA -38.7355mA -57.1555mA - -0.90 -38.7695mA -31.8215mA -51.1065mA - -0.85 -33.4345mA -25.8545mA -44.5675mA - -0.80 -28.1565mA -20.5265mA -37.8185mA - -0.75 -22.9755mA -15.7285mA -31.1295mA - -0.70 -18.0095mA -11.5805mA -24.6635mA - -0.65 -13.3705mA -8.0894mA -18.5475mA - -0.60 -9.185mA -5.219mA -12.9245mA - -0.55 -5.6163mA -2.9834mA -7.9946mA - -0.50 -2.8703mA -1.4348mA -4.0643mA - -0.45 -1.1245mA -0.5536mA -1.5008mA - -0.40 -0.308mA -0.1624mA -0.3485mA - -0.35 -35.6uA -20.3890uA -16.0uA - -0.30 0.0A 0.0A 0.0A - -0.25 0.0A 0.0A 0.0A - -0.20 0.0A 0.0A 0.0A - -0.15 0.0A 0.0A 0.0A - -0.10 0.0A 0.0A 0.0A - -0.05 0.0A 0.0A 0.0A - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.1221A 0.1248A 0.1242A - -3.15 0.1200A 0.1232A 0.1212A - -3.05 0.1178A 0.1215A 0.1181A - -2.95 0.1153A 0.1196A 0.1148A - -2.85 0.1128A 0.1174A 0.1114A - -2.75 0.1100A 0.1151A 0.1078A - -2.65 0.1071A 0.1126A 0.1041A - -2.55 0.1039A 0.1098A 0.1001A - -2.45 0.1006A 0.1069A 95.9680mA - -2.35 97.0630mA 0.1037A 91.5590mA - -2.25 93.2670mA 0.1003A 86.8480mA - -2.15 89.1920mA 96.7010mA 81.7630mA - -2.05 84.8070mA 92.8600mA 76.2010mA - -1.95 80.0800mA 88.7860mA 70.0340mA - -1.85 74.9870mA 84.4790mA 63.1570mA - -1.75 69.5180mA 79.9450mA 55.5700mA - -1.65 63.6850mA 75.1950mA 47.4010mA - -1.55 57.5160mA 70.2440mA 38.8580mA - -1.45 51.0440mA 65.1120mA 30.1910mA - -1.35 44.3150mA 59.8210mA 21.8920mA - -1.25 37.3820mA 54.3940mA 15.5340mA - -1.15 30.3110mA 48.8520mA 11.4230mA - -1.05 23.2090mA 43.2090mA 6.9858mA - -0.95 16.3160mA 37.4680mA 3.1948mA - -0.85 10.2960mA 31.6320mA 0.8600mA - -0.75 6.1213mA 25.7150mA 0.1694mA - -0.65 3.1679mA 19.7630mA 65.5350uA - -0.55 1.1362mA 13.8830mA 37.1010uA - -0.45 0.2574mA 8.3464mA 19.4580uA - -0.35 73.3430uA 3.8624mA 3.1206uA - -0.25 33.6580uA 1.3608mA -12.8040uA - -0.15 17.7650uA 0.3668mA -28.1570uA - -0.05 5.8276uA 90.2420uA -42.9420uA - 0.00 0.1897uA 50.8660uA -50.1210uA - 0.05 -5.3380uA 31.9340uA -57.1590uA - 0.15 -16.0560uA 15.1110uA -70.8070uA - 0.25 -26.3450uA 5.7330uA -83.8870uA - 0.35 -36.2070uA -2.2074uA -96.3970uA - 0.45 -45.6400uA -9.6847uA -0.1083mA - 0.55 -54.6440uA -16.8200uA -0.1197mA - 0.65 -63.2180uA -23.6240uA -0.1305mA - 0.75 -71.3610uA -30.0980uA -0.1407mA - 0.85 -79.0710uA -36.2430uA -0.1504mA - 0.95 -86.3480uA -42.0600uA -0.1594mA - 1.05 -93.1890uA -47.5470uA -0.1679mA - 1.15 -99.5930uA -52.7050uA -0.1758mA - 1.25 -0.1056mA -57.5350uA -0.1832mA - 1.35 -0.1111mA -62.0370uA -0.1899mA - 1.45 -0.1162mA -66.2090uA -0.1961mA - 1.55 -0.1208mA -70.0530uA -0.2016mA - 1.65 -0.1250mA -73.5690uA -0.2016mA - 1.75 -0.1287mA -76.7560uA -0.2016mA - 1.85 -0.1305mA -79.6150uA -0.2016mA - 1.95 -0.1305mA -82.1480uA -0.2016mA - 2.05 -0.1305mA -83.2920uA -0.2016mA - 2.15 -0.1305mA -83.2920uA -0.2016mA - 2.25 -0.1305mA -83.2920uA -0.2016mA - 2.35 -0.1305mA -83.2920uA -0.2016mA - 2.45 -0.1305mA -83.2920uA -0.2016mA - 2.55 -0.1305mA -83.2920uA -0.2016mA - 2.65 -0.1305mA -83.2920uA -0.2016mA - 2.75 -0.1305mA -83.2920uA -0.2016mA - 2.85 -0.1305mA -83.2920uA -0.2016mA - 2.95 -0.1305mA -83.2920uA -0.2016mA - 3.05 -0.1305mA -83.2920uA -0.2016mA - 3.15 -0.1305mA -83.2920uA -0.2016mA - 3.25 -0.1305mA -83.2920uA -0.2016mA - 6.60 -0.1305mA -83.292uA -0.2016mA -| -[Ramp] -| variable typ min max -dV/dt_r 0.7026/0.4330n 0.4966/0.5731n 1.0018/0.3242n -dV/dt_f 0.6827/0.4387n 0.4730/0.5599n 0.9168/0.3576n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 2.1621V 2.3517V 1.9420V -0.1010nS 2.1621V 2.3517V 1.9420V -0.2020nS 2.1621V 2.3517V 1.9420V -0.3030nS 2.1621V 2.3517V 1.9420V -0.4040nS 2.1621V 2.3517V 1.9420V -0.5051nS 2.1622V 2.3517V 2.2421V -0.6061nS 2.1615V 2.3517V 2.8060V -0.7071nS 2.2762V 2.3517V 3.1342V -0.8081nS 2.7361V 2.3522V 3.3164V -0.9091nS 2.9561V 2.3515V 3.3898V -1.0101nS 3.0907V 2.3704V 3.4244V -1.1111nS 3.1772V 2.6051V 3.4432V -1.2121nS 3.2242V 2.8360V 3.4539V -1.3131nS 3.2509V 2.9413V 3.4602V -1.4141nS 3.2670V 3.0020V 3.4639V -1.5152nS 3.2775V 3.0439V 3.4662V -1.6162nS 3.2845V 3.0714V 3.4676V -1.7172nS 3.2892V 3.0897V 3.4685V -1.8182nS 3.2924V 3.1025V 3.4690V -1.9192nS 3.2946V 3.1117V 3.4694V -2.0202nS 3.2961V 3.1186V 3.4696V -2.1212nS 3.2972V 3.1237V 3.4697V -2.2222nS 3.2980V 3.1276V 3.4698V -2.3232nS 3.2986V 3.1305V 3.4699V -2.4242nS 3.2989V 3.1327V 3.4699V -2.5253nS 3.2992V 3.1344V 3.4699V -2.6263nS 3.2994V 3.1356V 3.4699V -2.7273nS 3.2996V 3.1366V 3.4699V -2.8283nS 3.2997V 3.1373V 3.4699V -2.9293nS 3.2998V 3.1379V 3.4700V -3.0303nS 3.2998V 3.1383V 3.4699V -3.1313nS 3.2999V 3.1387V 3.4700V -3.2323nS 3.2999V 3.1390V 3.4699V -3.3333nS 3.2999V 3.1392V 3.4700V -3.4343nS 3.2999V 3.1393V 3.4699V -3.5354nS 3.2999V 3.1395V 3.4700V -3.6364nS 3.3000V 3.1396V 3.4699V -3.7374nS 3.3000V 3.1397V 3.4700V -3.8384nS 3.3000V 3.1397V 3.4700V -3.9394nS 3.3000V 3.1398V 3.4700V -4.0404nS 3.3000V 3.1398V 3.4700V -4.1414nS 3.3000V 3.1399V 3.4700V -4.2424nS 3.3000V 3.1399V 3.4700V -4.3434nS 3.3000V 3.1399V 3.4700V -4.4444nS 3.3000V 3.1400V 3.4700V -4.5455nS 3.3000V 3.1400V 3.4700V -4.6465nS 3.3000V 3.1399V 3.4700V -4.7475nS 3.3000V 3.1400V 3.4700V -4.8485nS 3.3000V 3.1400V 3.4700V -4.9495nS 3.3000V 3.1400V 3.4700V -5.0505nS 3.3000V 3.1400V 3.4700V -5.1515nS 3.3000V 3.1400V 3.4699V -5.2525nS 3.3000V 3.1400V 3.4700V -5.3535nS 3.3000V 3.1400V 3.4700V -5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4699V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4699V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4699V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4699V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4699V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 3.3000V 3.1400V 3.4700V -8.4848nS 3.3000V 3.1400V 3.4700V -8.5859nS 3.3000V 3.1400V 3.4700V -8.6869nS 3.3000V 3.1400V 3.4700V -8.7879nS 3.3000V 3.1400V 3.4700V -8.8889nS 3.3000V 3.1400V 3.4700V -8.9899nS 3.3000V 3.1400V 3.4700V -9.0909nS 3.3000V 3.1400V 3.4700V -9.1919nS 3.3000V 3.1400V 3.4700V -9.2929nS 3.3000V 3.1400V 3.4700V -9.3939nS 3.3000V 3.1400V 3.4700V -9.4949nS 3.3000V 3.1400V 3.4700V -9.5960nS 3.3000V 3.1400V 3.4700V -9.6970nS 3.3000V 3.1400V 3.4700V -9.7980nS 3.3000V 3.1400V 3.4700V -9.8990nS 3.3000V 3.1400V 3.4700V -10.0000nS 3.3000V 3.1400V 3.4700V -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 1.2884uV 1.5543uV 1.3225uV -0.1010nS 0.5355uV 0.8430uV 0.6254uV -0.2020nS -3.0614uV 0.1113uV 0.5701uV -0.3030nS 0.6806uV -1.9546uV 10.3860uV -0.4040nS 3.2624uV 1.2769uV -0.2118mV -0.5051nS 32.7230uV 1.5286uV -24.1640mV -0.6061nS -0.3955mV 2.8080uV -9.9395mV -0.7071nS -15.7200mV 17.6660uV 0.1561V -0.8081nS -19.9850mV 99.9200uV 0.5397V -0.9091nS -0.4586mV -0.2072mV 0.9226V -1.0101nS 88.3420mV -6.1838mV 1.2091V -1.1111nS 0.2478V -18.1000mV 1.3886V -1.2121nS 0.4471V -16.0430mV 1.4951V -1.3131nS 0.6318V -10.1180mV 1.5589V -1.4141nS 0.7749V 8.8815mV 1.5984V -1.5152nS 0.8766V 55.5920mV 1.6234V -1.6162nS 0.9465V 0.1340V 1.6394V -1.7172nS 0.9942V 0.2360V 1.6498V -1.8182nS 1.0272V 0.3461V 1.6566V -1.9192nS 1.0502V 0.4492V 1.6613V -2.0202nS 1.0667V 0.5367V 1.6638V -2.1212nS 1.0785V 0.6066V 1.6656V -2.2222nS 1.0871V 0.6605V 1.6667V -2.3232nS 1.0934V 0.7013V 1.6675V -2.4242nS 1.0979V 0.7318V 1.6680V -2.5253nS 1.1013V 0.7546V 1.6684V -2.6263nS 1.1038V 0.7716V 1.6687V -2.7273nS 1.1056V 0.7845V 1.6689V -2.8283nS 1.1069V 0.7942V 1.6691V -2.9293nS 1.1080V 0.8016V 1.6693V -3.0303nS 1.1087V 0.8073V 1.6693V -3.1313nS 1.1093V 0.8118V 1.6694V -3.2323nS 1.1097V 0.8152V 1.6695V -3.3333nS 1.1100V 0.8178V 1.6695V -3.4343nS 1.1103V 0.8199V 1.6695V -3.5354nS 1.1104V 0.8215V 1.6696V -3.6364nS 1.1105V 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0.3253mV -2.0202nS 2.1519mV 21.8020mV 0.2392mV -2.1212nS 1.4430mV 15.5850mV 0.1806mV -2.2222nS 1.0065mV 11.3310mV 0.1485mV -2.3232nS 0.6888mV 8.3187mV 0.1251mV -2.4242nS 0.5069mV 6.1527mV 0.1108mV -2.5253nS 0.3566mV 4.5704mV 0.1026mV -2.6263nS 0.2717mV 3.4134mV 96.2470uV -2.7273nS 0.1995mV 2.5569mV 87.3860uV -2.8283nS 0.1853mV 1.9272mV 82.9260uV -2.9293nS 0.1277mV 1.4565mV 68.6140uV -3.0303nS 0.1252mV 1.1098mV 60.2230uV -3.1313nS 89.5590uV 0.8485mV 49.7170uV -3.2323nS 94.4160uV 0.6561mV 56.7570uV -3.3333nS 49.7470uV 0.5093mV 54.1530uV -3.4343nS 57.0870uV 0.3863mV 49.3370uV -3.5354nS 52.4280uV 0.3073mV 42.7020uV -3.6364nS 77.0030uV 0.2451mV 40.7070uV -3.7374nS 46.1550uV 0.1875mV 33.9890uV -3.8384nS 63.3650uV 0.1621mV 34.0740uV -3.9394nS 31.9750uV 0.1378mV 27.5110uV -4.0404nS 46.0820uV 0.1176mV 33.5240uV -4.1414nS 14.0450uV 0.1002mV 26.4520uV -4.2424nS 30.8440uV 91.6770uV 22.6270uV -4.3434nS 23.9580uV 76.4830uV 15.2880uV -4.4444nS 37.9550uV 66.7720uV 22.2140uV -4.5455nS 20.1420uV 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-16.6030uV -15.4900uV -2.2380uV -9.7980nS -2.4824uV -3.6242uV 4.0030uV -9.8990nS -18.6820uV 15.5490uV 1.5950uV -10.0000nS -1.0707uV 8.4164uV -6.6712uV -| -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 3.3000V 3.1400V 3.4700V -0.1010nS 3.3000V 3.1400V 3.4700V -0.2020nS 3.3000V 3.1400V 3.4700V -0.3030nS 3.3000V 3.1400V 3.4700V -0.4040nS 3.3000V 3.1400V 3.4700V -0.5051nS 3.3000V 3.1400V 3.4758V -0.6061nS 3.3001V 3.1400V 3.4570V -0.7071nS 3.2983V 3.1400V 3.0951V -0.8081nS 3.3299V 3.1400V 2.7403V -0.9091nS 3.2987V 3.1398V 2.4747V -1.0101nS 3.1080V 3.1409V 2.2935V -1.1111nS 2.8866V 3.1388V 2.1742V -1.2121nS 2.6919V 3.1507V 2.0966V -1.3131nS 2.5414V 3.1748V 2.0453V -1.4141nS 2.4321V 3.1565V 2.0112V -1.5152nS 2.3547V 3.0752V 1.9884V -1.6162nS 2.3001V 2.9642V 1.9732V -1.7172nS 2.2616V 2.8458V 1.9629V -1.8182nS 2.2341V 2.7389V 1.9561V -1.9192nS 2.2145V 2.6506V 1.9515V -2.0202nS 2.2003V 2.5809V 1.9484V -2.1212nS 2.1900V 2.5272V 1.9463V -2.2222nS 2.1826V 2.4862V 1.9450V -2.3232nS 2.1771V 2.4551V 1.9440V -2.4242nS 2.1731V 2.4314V 1.9434V -2.5253nS 2.1702V 2.4134V 1.9430V -2.6263nS 2.1681V 2.3996V 1.9427V -2.7273nS 2.1665V 2.3890V 1.9425V -2.8283nS 2.1654V 2.3808V 1.9424V -2.9293nS 2.1646V 2.3745V 1.9423V -3.0303nS 2.1639V 2.3696V 1.9422V -3.1313nS 2.1635V 2.3658V 1.9422V -3.2323nS 2.1631V 2.3628V 1.9421V -3.3333nS 2.1629V 2.3604V 1.9421V -3.4343nS 2.1627V 2.3586V 1.9421V -3.5354nS 2.1626V 2.3572V 1.9420V -3.6364nS 2.1625V 2.3560V 1.9421V -3.7374nS 2.1624V 2.3551V 1.9421V -3.8384nS 2.1623V 2.3544V 1.9421V -3.9394nS 2.1623V 2.3539V 1.9420V -4.0404nS 2.1622V 2.3534V 1.9420V -4.1414nS 2.1622V 2.3531V 1.9420V -4.2424nS 2.1622V 2.3528V 1.9420V -4.3434nS 2.1622V 2.3526V 1.9420V -4.4444nS 2.1622V 2.3524V 1.9420V -4.5455nS 2.1622V 2.3523V 1.9420V -4.6465nS 2.1622V 2.3522V 1.9420V -4.7475nS 2.1622V 2.3521V 1.9420V -4.8485nS 2.1622V 2.3520V 1.9420V -4.9495nS 2.1622V 2.3519V 1.9420V -5.0505nS 2.1622V 2.3519V 1.9420V -5.1515nS 2.1622V 2.3518V 1.9420V -5.2525nS 2.1622V 2.3518V 1.9420V -5.3535nS 2.1622V 2.3518V 1.9420V -5.4545nS 2.1622V 2.3518V 1.9420V -5.5556nS 2.1622V 2.3518V 1.9420V -5.6566nS 2.1622V 2.3517V 1.9420V -5.7576nS 2.1621V 2.3517V 1.9420V -5.8586nS 2.1621V 2.3517V 1.9420V -5.9596nS 2.1621V 2.3517V 1.9420V -6.0606nS 2.1621V 2.3517V 1.9420V -6.1616nS 2.1621V 2.3517V 1.9420V -6.2626nS 2.1621V 2.3517V 1.9420V -6.3636nS 2.1621V 2.3517V 1.9420V -6.4646nS 2.1621V 2.3517V 1.9420V -6.5657nS 2.1621V 2.3517V 1.9420V -6.6667nS 2.1622V 2.3517V 1.9420V -6.7677nS 2.1621V 2.3517V 1.9420V -6.8687nS 2.1621V 2.3517V 1.9420V -6.9697nS 2.1621V 2.3517V 1.9420V -7.0707nS 2.1621V 2.3517V 1.9420V -7.1717nS 2.1621V 2.3517V 1.9420V -7.2727nS 2.1621V 2.3517V 1.9420V -7.3737nS 2.1621V 2.3517V 1.9420V -7.4747nS 2.1621V 2.3517V 1.9420V -7.5758nS 2.1621V 2.3517V 1.9420V -7.6768nS 2.1621V 2.3517V 1.9420V -7.7778nS 2.1621V 2.3517V 1.9420V -7.8788nS 2.1621V 2.3517V 1.9420V -7.9798nS 2.1621V 2.3517V 1.9420V -8.0808nS 2.1621V 2.3517V 1.9420V -8.1818nS 2.1621V 2.3517V 1.9420V -8.2828nS 2.1621V 2.3517V 1.9420V -8.3838nS 2.1621V 2.3517V 1.9420V -8.4848nS 2.1621V 2.3517V 1.9420V -8.5859nS 2.1621V 2.3517V 1.9420V -8.6869nS 2.1621V 2.3517V 1.9420V -8.7879nS 2.1621V 2.3517V 1.9420V -8.8889nS 2.1621V 2.3517V 1.9420V -8.9899nS 2.1621V 2.3517V 1.9420V -9.0909nS 2.1621V 2.3517V 1.9420V -9.1919nS 2.1621V 2.3517V 1.9420V -9.2929nS 2.1621V 2.3517V 1.9420V -9.3939nS 2.1621V 2.3517V 1.9420V -9.4949nS 2.1621V 2.3517V 1.9420V -9.5960nS 2.1621V 2.3517V 1.9420V -9.6970nS 2.1621V 2.3517V 1.9420V -9.7980nS 2.1621V 2.3517V 1.9420V -9.8990nS 2.1621V 2.3517V 1.9420V -10.0000nS 2.1621V 2.3517V 1.9420V -| -| End [Model] lvt330s040haaaaaaaio -|************************************************************************ -[Model] lvt330s160aaaaaaaaou -Model_type Output -Polarity Non-Inverting -Enable Active-Low -Vmeas = 1.500000V -Cref = 0.0F -Rref = 1.0000M -Vref = 0.0V -C_comp 4.2000pF 3.8000pF 7.5000pF -| -| -[Temperature Range] 25.0000 0.1050k -40.0000 -[Voltage Range] 3.3000V 3.1400V 3.4700V -[Pulldown] -|Voltage I(typ) I(min) I(max) -| - -3.30 -46.0510mA -33.7410mA -59.5510mA - -3.20 -46.0510mA -33.7410mA -59.5510mA - -3.10 -46.0510mA -33.7410mA -59.5510mA - -3.00 -46.0510mA -33.7410mA -59.5510mA - -2.90 -46.0510mA -33.7410mA -59.5510mA - -2.80 -46.0510mA -33.7410mA -59.5510mA - -2.70 -46.0510mA -33.7410mA -59.5510mA - -2.60 -46.0510mA -33.7410mA -59.5510mA - -2.50 -46.0510mA -33.7410mA -59.5510mA - -2.40 -46.0510mA -33.7410mA -59.5510mA - -2.30 -46.0510mA -33.7410mA -59.5510mA - -2.20 -46.0510mA -33.7410mA -59.5510mA - -2.10 -46.0510mA -33.7410mA -59.5510mA - -2.00 -46.0510mA -33.7410mA -59.5510mA - -1.90 -46.0510mA -33.7410mA -59.5510mA - -1.80 -46.0510mA -33.7410mA -59.5510mA - -1.70 -46.0510mA -33.7410mA -59.5510mA - -1.60 -46.0510mA -33.7410mA -59.5510mA - -1.50 -46.0510mA -33.7410mA -59.5510mA - -1.40 -46.0510mA -33.7410mA -59.5510mA - -1.30 -46.0510mA -33.7410mA -59.5510mA - -1.20 -46.0510mA -33.7410mA -59.5510mA - -1.10 -46.0510mA -33.7410mA -59.5510mA - -1.00 -46.0510mA -33.7410mA -57.7460mA - -0.90 -45.1960mA -33.7410mA -53.3800mA - -0.80 -42.7900mA -33.0880mA -50.7690mA - -0.70 -40.7010mA -32.1190mA -48.9510mA - -0.60 -38.5892mA -30.1763mA -47.3570mA - -0.50 -35.7989mA -27.1490mA -45.2332mA - -0.40 -30.5530mA -22.5448mA -39.2561mA - -0.30 -23.3101mA -17.0730mA -30.0082mA - -0.20 -15.6753mA -11.4360mA -20.2124mA - -0.10 -7.9044mA -5.7449mA -10.2109mA - 0.00 9.1810nA 6.6370nA 14.6880nA - 0.10 7.8212mA 5.6449mA 10.1501mA - 0.20 15.3310mA 11.0300mA 19.9541mA - 0.30 22.5240mA 16.1530mA 29.4071mA - 0.40 29.3980mA 21.0130mA 38.5000mA - 0.50 35.9480mA 25.6080mA 47.2270mA - 0.60 42.1700mA 29.9370mA 55.5800mA - 0.70 48.0590mA 33.9980mA 63.5490mA - 0.80 53.6080mA 37.7880mA 71.1220mA - 0.90 58.8090mA 41.3050mA 78.2850mA - 1.00 63.6510mA 44.5440mA 85.0150mA - 1.10 68.1160mA 47.4970mA 91.2820mA - 1.20 72.1780mA 50.1540mA 97.0390mA - 1.30 75.8000mA 52.4980mA 0.1022A - 1.40 78.9390mA 54.5150mA 0.1067A - 1.50 81.5710mA 56.2010mA 0.1106A - 1.60 83.7180mA 57.5820mA 0.1137A - 1.70 85.4430mA 58.7040mA 0.1161A - 1.80 86.8340mA 59.6220mA 0.1181A - 1.90 87.9720mA 60.3850mA 0.1196A - 2.00 88.9210mA 61.0310mA 0.1209A - 2.10 89.7270mA 61.5880mA 0.1220A - 2.20 90.4240mA 62.0750mA 0.1229A - 2.30 91.0370mA 62.5080mA 0.1237A - 2.40 91.5820mA 62.8970mA 0.1244A - 2.50 92.0740mA 63.2500mA 0.1250A - 2.60 92.5210mA 63.5730mA 0.1256A - 2.70 92.9309mA 63.8720mA 0.1261A - 2.80 93.3099mA 64.1499mA 0.1266A - 2.90 93.6629mA 64.4089mA 0.1270A - 3.00 93.9929mA 64.6529mA 0.1274A - 3.10 94.3029mA 64.8829mA 0.1278A - 3.20 94.5958mA 65.1008mA 0.1281A - 3.30 94.8758mA 65.3076mA 0.1285A - 3.40 95.1436mA 65.5013mA 0.1288A - 3.50 95.4017mA 65.6576mA 0.1291A - 3.60 95.6462mA 65.9236mA 0.1294A - 3.70 95.8369mA 66.2546mA 0.1298A - 3.80 96.2034mA 67.0655mA 0.1301A - 3.90 96.5733mA 69.0584mA 0.1303A - 4.00 97.3652mA 73.2123mA 0.1309A - 4.10 99.2509mA 79.1820mA 0.1314A - 4.20 0.1022A 85.9597mA 0.1322A - 4.30 0.1063A 93.0914mA 0.1344A - 4.40 0.1126A 0.1004A 0.1384A - 4.50 0.1206A 0.1078A 0.1435A - 4.60 0.1294A 0.1153A 0.1489A - 4.70 0.1385A 0.1229A 0.1551A - 4.80 0.1479A 0.1307A 0.1648A - 4.90 0.1573A 0.1386A 0.1760A - 5.00 0.1669A 0.1467A 0.1878A - 5.10 0.1765A 0.1550A 0.1999A - 5.20 0.1863A 0.1634A 0.2120A - 5.30 0.1961A 0.1719A 0.2241A - 5.40 0.2062A 0.1805A 0.2362A - 5.50 0.2163A 0.1892A 0.2482A - 5.60 0.2265A 0.1980A 0.2603A - 5.70 0.2369A 0.2068A 0.2726A - 5.80 0.2473A 0.2158A 0.2851A - 5.90 0.2579A 0.2248A 0.2978A - 6.00 0.2687A 0.2339A 0.3108A - 6.10 0.2796A 0.2431A 0.3240A - 6.20 0.2907A 0.2524A 0.3374A - 6.30 0.3021A 0.2618A 0.3511A - 6.40 0.3136A 0.2714A 0.3652A - 6.50 0.3254A 0.2811A 0.3794A - 6.60 0.3374A 0.2909A 0.3940A -| -[Pullup] -|Voltage I(typ) I(min) I(max) -| - -3.30 0.3688A 0.3085A 0.4482A - -3.20 0.3595A 0.3039A 0.4356A - -3.10 0.3495A 0.2972A 0.4227A - -3.00 0.3390A 0.2892A 0.4094A - -2.90 0.3282A 0.2805A 0.3959A - -2.80 0.3171A 0.2712A 0.3822A - -2.70 0.3056A 0.2615A 0.3683A - -2.60 0.2939A 0.2514A 0.3543A - -2.50 0.2819A 0.2409A 0.3400A - -2.40 0.2697A 0.2303A 0.3256A - -2.30 0.2573A 0.2194A 0.3110A - -2.20 0.2447A 0.2084A 0.2962A - -2.10 0.2318A 0.1972A 0.2811A - -2.00 0.2189A 0.1859A 0.2659A - -1.90 0.2058A 0.1745A 0.2504A - -1.80 0.1927A 0.1631A 0.2346A - -1.70 0.1795A 0.1517A 0.2186A - -1.60 0.1662A 0.1402A 0.2025A - -1.50 0.1528A 0.1288A 0.1863A - -1.40 0.1394A 0.1175A 0.1702A - -1.30 0.1260A 0.1062A 0.1543A - -1.20 0.1126A 94.9202mA 0.1391A - -1.10 99.3436mA 83.7786mA 0.1252A - -1.00 86.4581mA 72.7899mA 0.1110A - -0.90 74.6466mA 62.0952mA 97.2911mA - -0.80 64.2979mA 52.0534mA 84.6162mA - -0.70 54.8762mA 43.3265mA 72.7261mA - -0.60 46.1133mA 35.9755mA 61.5078mA - -0.50 37.8734mA 29.3476mA 50.1553mA - -0.40 29.8849mA 23.1046mA 40.2866mA - -0.30 22.2622mA 17.0802mA 30.1199mA - -0.20 14.7337mA 11.2591mA 20.0045mA - -0.10 7.3149mA 5.5671mA 9.9673mA - 0.00 -27.6800nA -12.5600nA -0.2990uA - 0.10 -7.1350mA -5.3932mA -9.7862mA - 0.20 -14.0071mA -10.5601mA -19.2690mA - 0.30 -20.6131mA -15.4991mA -28.4448mA - 0.40 -26.9531mA -20.2101mA -37.3096mA - 0.50 -33.0231mA -24.6920mA -45.8605mA - 0.60 -38.8211mA -28.9440mA -54.0924mA - 0.70 -44.3460mA -32.9660mA -62.0013mA - 0.80 -49.5950mA -36.7560mA -69.5842mA - 0.90 -54.5660mA -40.3130mA -76.8361mA - 1.00 -59.2570mA -43.6380mA -83.7531mA - 1.10 -63.6650mA -46.7280mA -90.3311mA - 1.20 -67.7890mA -49.5840mA -96.5660mA - 1.30 -71.6270mA -52.2040mA -0.1025A - 1.40 -75.1760mA -54.5890mA -0.1080A - 1.50 -78.4330mA -56.7370mA -0.1132A - 1.60 -81.3980mA -58.6480mA -0.1180A - 1.70 -84.0680mA -60.3220mA -0.1224A - 1.80 -86.4420mA -61.7600mA -0.1265A - 1.90 -88.5180mA -62.9650mA -0.1302A - 2.00 -90.2990mA -63.9430mA -0.1335A - 2.10 -91.7860mA -64.7110mA -0.1365A - 2.20 -92.9940mA -65.3040mA -0.1391A - 2.30 -93.9530mA -65.7740mA -0.1412A - 2.40 -94.7160mA -66.1750mA -0.1431A - 2.50 -95.3540mA -66.5370mA -0.1446A - 2.60 -95.9200mA -66.8780mA -0.1458A - 2.70 -96.4460mA -67.2020mA -0.1469A - 2.80 -96.9450mA -67.5150mA -0.1478A - 2.90 -97.4230mA -67.8180mA -0.1487A - 3.00 -97.8850mA -68.1109mA -0.1495A - 3.10 -98.3320mA -68.3969mA -0.1504A - 3.20 -98.7659mA -68.6739mA -0.1511A - 3.30 -99.1879mA -68.9436mA -0.1519A - 3.40 -99.5979mA -69.2026mA -0.1526A - 3.50 -99.9963mA -69.3920mA -0.1533A - 3.60 -0.1004A -69.3920mA -0.1540A - 3.70 -0.1005A -69.3920mA -0.1547A - 3.80 -0.1005A -69.3920mA -0.1553A - 3.90 -0.1005A -69.3920mA -0.1554A - 4.00 -0.1005A -69.3920mA -0.1554A - 4.10 -0.1005A -69.3920mA -0.1554A - 4.20 -0.1005A -69.3920mA -0.1554A - 4.30 -0.1005A -69.3920mA -0.1554A - 4.40 -0.1005A -69.3920mA -0.1554A - 4.50 -0.1005A -69.3920mA -0.1554A - 4.60 -0.1005A -69.3920mA -0.1554A - 4.70 -0.1005A -69.3920mA -0.1554A - 4.80 -0.1005A -69.3920mA -0.1554A - 4.90 -0.1005A -69.3920mA -0.1554A - 5.00 -0.1005A -69.3920mA -0.1554A - 5.10 -0.1005A -69.3920mA -0.1554A - 5.20 -0.1005A -69.3920mA -0.1554A - 5.30 -0.1005A -69.3920mA -0.1554A - 5.40 -0.1005A -69.3920mA -0.1554A - 5.50 -0.1005A -69.3920mA -0.1554A - 5.60 -0.1005A -69.3920mA -0.1554A - 5.70 -0.1005A -69.3920mA -0.1554A - 5.80 -0.1005A -69.3920mA -0.1554A - 5.90 -0.1005A -69.3920mA -0.1554A - 6.00 -0.1005A -69.3920mA -0.1554A - 6.10 -0.1005A -69.3920mA -0.1554A - 6.20 -0.1005A -69.3920mA -0.1554A - 6.30 -0.1005A -69.3920mA -0.1554A - 6.40 -0.1005A -69.3920mA -0.1554A - 6.50 -0.1005A -69.3920mA -0.1554A - 6.55 -0.1005A -69.3920mA -0.1554A -| -[GND_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.30 -0.9553A -0.9303A -0.978A - -3.25 -0.9307A -0.9059A -0.9534A - -3.20 -0.9062A -0.8815A -0.9287A - -3.15 -0.8816A -0.8571A -0.9041A - -3.10 -0.8571A -0.8328A -0.8794A - -3.05 -0.8326A -0.8084A -0.8548A - -3.00 -0.8081A -0.7841A -0.8302A - -2.95 -0.7837A -0.7598A -0.8056A - -2.90 -0.7592A -0.7356A -0.781A - -2.85 -0.7348A -0.7113A -0.7565A - -2.80 -0.7104A -0.6872A -0.7319A - -2.75 -0.686A -0.663A -0.7074A - -2.70 -0.6617A -0.6389A -0.6829A - -2.65 -0.6374A -0.6149A -0.6584A - -2.60 -0.6131A -0.5909A -0.634A - -2.55 -0.5889A -0.5669A -0.6096A - -2.50 -0.5647A -0.5431A -0.5852A - -2.45 -0.5406A -0.5193A -0.5609A - -2.40 -0.5166A -0.4956A -0.5366A - -2.35 -0.4926A -0.472A -0.5124A - -2.30 -0.4687A -0.4485A -0.4882A - -2.25 -0.4449A -0.4251A -0.4641A - -2.20 -0.4211A -0.4019A -0.44A - -2.15 -0.3976A -0.3789A -0.4161A - -2.10 -0.3741A -0.3562A -0.3923A - -2.05 -0.3509A -0.3337A -0.3686A - -2.00 -0.3279A -0.3116A -0.3451A - -1.95 -0.3052A -0.2899A -0.3218A - -1.90 -0.283A -0.2689A -0.2988A - -1.85 -0.2612A -0.2486A -0.2762A - -1.80 -0.2402A -0.2294A -0.2543A - -1.75 -0.2204A -0.2116A -0.2332A - -1.70 -0.202A -0.1954A -0.2135A - -1.65 -0.1857A -0.181A -0.1959A - -1.60 -0.1717A -0.1682A -0.181A - -1.55 -0.1594A -0.1563A -0.1685A - -1.50 -0.1481A -0.1452A -0.1571A - -1.45 -0.1372A -0.1343A -0.1462A - -1.40 -0.1266A -0.1237A -0.1355A - -1.35 -0.1162A -0.1132A -0.125A - -1.30 -0.106A -0.1029A -0.1146A - -1.25 -95.9599mA -92.8329mA -0.1046A - -1.20 -86.1849mA -82.9339mA -94.9069mA - -1.15 -76.7349mA -73.2869mA -85.7379mA - -1.10 -67.7089mA -63.9519mA -77.2789mA - -1.05 -59.2439mA -55.0099mA -69.7479mA - -1.00 -51.5159mA -46.5729mA -63.2139mA - -0.95 -44.7119mA -38.7979mA -57.3089mA - -0.90 -38.8659mA -31.8819mA -51.2599mA - -0.85 -33.5299mA -25.9129mA -44.7209mA - -0.80 -28.2499mA -20.5839mA -37.9699mA - -0.75 -23.0669mA -15.7839mA -31.2789mA - -0.70 -18.0989mA -11.6329mA -24.8089mA - -0.65 -13.4569mA -8.1389mA -18.6889mA - -0.60 -9.2667mA -5.2646mA -13.0589mA - -0.55 -5.6915mA -3.0244mA -8.1194mA - -0.50 -2.937mA -1.4709mA -4.1747mA - -0.45 -1.1814mA -0.5866mA -1.592mA - -0.40 -0.3589mA -0.1961mA -0.4238mA - -0.35 -88.3674uA -58.3595uA -88.5118uA - -0.30 -18.8304uA -15.9765uA -16.7268uA - -0.25 -3.5316uA -4.0546uA -3.0027uA - -0.20 -0.6045uA -0.9665uA -0.4941uA - -0.15 -99.742nA -0.2204uA -76.537nA - -0.10 -17.537nA -48.631nA -14.0860nA - -0.05 -3.547nA -9.5380nA -3.817nA - 0.00 0.0A 0.0A 0.0A - 6.60 0.0A 0.0A 0.0A -| -[POWER_clamp] -|Voltage I(typ) I(min) I(max) -| - -3.25 0.6648mA 0.7494mA 0.5971mA - -3.15 0.5464mA 0.6392mA 0.4620mA - -3.05 0.4320mA 0.5325mA 0.3346mA - -2.95 0.3223mA 0.4288mA 0.2203mA - -2.85 0.2202mA 0.3288mA 0.1294mA - -2.75 0.1318mA 0.2341mA 72.8320uA - -2.65 67.1940uA 0.1484mA 47.8300uA - -2.55 33.3840uA 79.2130uA 38.1430uA - -2.45 21.1020uA 36.2270uA 33.4230uA - -2.35 16.7350uA 18.9540uA 30.1320uA - -2.25 14.6020uA 13.5630uA 27.2570uA - -2.15 13.0530uA 11.4700uA 24.5650uA - -2.05 11.6730uA 10.2220uA 22.0130uA - -1.95 10.3790uA 9.1903uA 19.5970uA - -1.85 9.1554uA 8.2406uA 17.3220uA - -1.75 8.0024uA 7.3472uA 15.1930uA - -1.65 6.9220uA 6.5055uA 13.2180uA - -1.55 5.9168uA 5.7151uA 11.4030uA - -1.45 4.9897uA 4.9762uA 9.7538uA - -1.35 4.1435uA 4.2896uA 8.2775uA - -1.25 3.3813uA 3.6558uA 6.9794uA - -1.15 2.7058uA 3.0755uA 5.8656uA - -1.05 2.1197uA 2.5496uA 4.9436uA - -0.95 1.6260uA 2.0788uA 4.2185uA - -0.85 1.2282uA 1.6639uA 3.6568uA - -0.75 0.9321uA 1.3059uA 3.6568uA - -0.65 0.7406uA 1.0064uA 3.6568uA - -0.55 0.6334uA 0.7687uA 3.6568uA - -0.45 0.5657uA 0.5976uA 1.9769uA - -0.35 0.5657uA 0.4934uA 1.5352uA - -0.25 0.5657uA 0.4388uA 1.2603uA - -0.15 0.5657uA 0.4063uA 1.0262uA - -0.05 0.2497uA 0.3931uA 0.8243uA - 0.00 0.1905uA 0.3931uA 0.7347uA - 0.05 0.1661uA 0.3931uA 0.6522uA - 0.15 0.1377uA 0.3931uA 0.5077uA - 0.25 0.1149uA 0.2673uA 0.3882uA - 0.35 95.5840nA 94.4790nA 0.2911uA - 0.45 79.2300nA 72.9410nA 0.2139uA - 0.55 65.5240nA 63.7780nA 0.1539uA - 0.65 54.1200nA 56.2440nA 0.1084uA - 0.75 44.6720nA 49.6060nA 74.7270nA - 0.85 36.8450nA 43.7060nA 50.5340nA - 0.95 30.3210nA 38.4180nA 33.5490nA - 1.05 24.8050nA 33.6240nA 21.8000nA - 1.15 20.0360nA 29.2180nA 13.6290nA - 1.25 15.7920nA 25.1030nA 7.7259nA - 1.35 11.8920nA 21.1950nA 3.1291nA - 1.45 8.2000nA 17.4270nA -0.8025nA - 1.55 4.6215nA 13.7460nA -4.4469nA - 1.65 1.0974nA 10.1160nA -7.9944nA - 1.75 -2.4045nA 6.5107nA -11.5260nA - 1.85 -5.8986nA 2.9177nA -15.0700nA - 1.95 -9.3903nA -0.6705nA -18.6430nA - 2.05 -12.8810nA -4.2566nA -22.2600nA - 2.15 -16.3730nA -7.8413nA -25.9390nA - 2.25 -19.8660nA -11.4260nA -29.7010nA - 2.35 -23.3620nA -15.0100nA -33.5700nA - 2.45 -26.8630nA -18.5940nA -37.5740nA - 2.55 -30.3710nA -22.1800nA -41.7450nA - 2.65 -33.8890nA -25.7670nA -46.1170nA - 2.75 -37.4190nA -29.3570nA -50.7240nA - 2.85 -40.9640nA -32.9520nA -55.6060nA - 2.95 -44.5300nA -36.5540nA -60.8020nA - 3.05 -48.1210nA -40.1670nA -66.3570nA - 3.15 -51.7470nA -43.7980nA -72.4990nA - 3.25 -55.4690nA -47.4690nA -97.5860nA - 6.60 -57.5580nA -49.34nA -0.2325uA -| -[Ramp] -| variable typ min max -dV/dt_r 1.4966/0.2592n 1.2936/0.4087n 1.7021/0.1678n -dV/dt_f 1.5290/0.2281n 1.3043/0.3741n 1.7112/0.1501n -R_load = 50.0000 -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 3.3000 -V_fixture_min= 3.1400 -V_fixture_max= 3.4700 -|time V(typ) V(min) V(max) -| -0.0S 0.7516V 0.9661V 0.6180V -0.1010nS 0.7516V 0.9661V 0.6180V -0.2020nS 0.7516V 0.9661V 0.6180V -0.3030nS 0.7516V 0.9661V 0.6180V -0.4040nS 0.7516V 0.9661V 0.6171V -0.5051nS 0.7517V 0.9661V 0.7829V -0.6061nS 0.7505V 0.9661V 2.0255V -0.7071nS 0.7950V 0.9661V 2.8797V -0.8081nS 1.7861V 0.9664V 3.3462V -0.9091nS 2.4193V 0.9655V 3.4176V -1.0101nS 2.8512V 0.9681V 3.4439V -1.1111nS 3.1357V 1.3754V 3.4564V -1.2121nS 3.2249V 2.1421V 3.4627V -1.3131nS 3.2565V 2.5293V 3.4661V -1.4141nS 3.2737V 2.7345V 3.4678V -1.5152nS 3.2838V 2.8969V 3.4688V -1.6162nS 3.2896V 3.0120V 3.4693V -1.7172nS 3.2934V 3.0632V 3.4696V -1.8182nS 3.2957V 3.0894V 3.4697V -1.9192nS 3.2972V 3.1045V 3.4698V -2.0202nS 3.2981V 3.1151V 3.4699V -2.1212nS 3.2987V 3.1221V 3.4699V -2.2222nS 3.2991V 3.1274V 3.4699V -2.3232nS 3.2994V 3.1308V 3.4699V -2.4242nS 3.2996V 3.1334V 3.4700V -2.5253nS 3.2997V 3.1352V 3.4700V -2.6263nS 3.2998V 3.1365V 3.4700V -2.7273nS 3.2998V 3.1374V 3.4700V -2.8283nS 3.2999V 3.1380V 3.4700V -2.9293nS 3.2999V 3.1385V 3.4700V -3.0303nS 3.2999V 3.1389V 3.4700V -3.1313nS 3.2999V 3.1391V 3.4700V -3.2323nS 3.3000V 3.1393V 3.4700V -3.3333nS 3.3000V 3.1395V 3.4700V -3.4343nS 3.3000V 3.1396V 3.4700V -3.5354nS 3.3000V 3.1397V 3.4700V -3.6364nS 3.3000V 3.1398V 3.4700V -3.7374nS 3.3000V 3.1398V 3.4700V -3.8384nS 3.3000V 3.1398V 3.4700V -3.9394nS 3.3000V 3.1399V 3.4700V -4.0404nS 3.3000V 3.1399V 3.4700V -4.1414nS 3.3000V 3.1399V 3.4700V -4.2424nS 3.3000V 3.1399V 3.4700V -4.3434nS 3.3000V 3.1399V 3.4700V -4.4444nS 3.3000V 3.1399V 3.4700V -4.5455nS 3.3000V 3.1400V 3.4700V -4.6465nS 3.3000V 3.1400V 3.4700V -4.7475nS 3.3000V 3.1400V 3.4700V -4.8485nS 3.3000V 3.1400V 3.4700V -4.9495nS 3.3000V 3.1400V 3.4700V -5.0505nS 3.3000V 3.1400V 3.4700V -5.1515nS 3.3000V 3.1400V 3.4700V -5.2525nS 3.3000V 3.1400V 3.4700V -5.3535nS 3.3000V 3.1400V 3.4700V -5.4545nS 3.3000V 3.1400V 3.4700V -5.5556nS 3.3000V 3.1400V 3.4700V -5.6566nS 3.3000V 3.1400V 3.4700V -5.7576nS 3.3000V 3.1400V 3.4700V -5.8586nS 3.3000V 3.1400V 3.4700V -5.9596nS 3.3000V 3.1400V 3.4700V -6.0606nS 3.3000V 3.1400V 3.4700V -6.1616nS 3.3000V 3.1400V 3.4700V -6.2626nS 3.3000V 3.1400V 3.4700V -6.3636nS 3.3000V 3.1400V 3.4700V -6.4646nS 3.3000V 3.1400V 3.4700V -6.5657nS 3.3000V 3.1400V 3.4700V -6.6667nS 3.3000V 3.1400V 3.4700V -6.7677nS 3.3000V 3.1400V 3.4700V -6.8687nS 3.3000V 3.1400V 3.4700V -6.9697nS 3.3000V 3.1400V 3.4700V -7.0707nS 3.3000V 3.1400V 3.4700V -7.1717nS 3.3000V 3.1400V 3.4700V -7.2727nS 3.3000V 3.1400V 3.4700V -7.3737nS 3.3000V 3.1400V 3.4700V -7.4747nS 3.3000V 3.1400V 3.4700V -7.5758nS 3.3000V 3.1400V 3.4700V -7.6768nS 3.3000V 3.1400V 3.4700V -7.7778nS 3.3000V 3.1400V 3.4700V -7.8788nS 3.3000V 3.1400V 3.4700V -7.9798nS 3.3000V 3.1400V 3.4700V -8.0808nS 3.3000V 3.1400V 3.4700V -8.1818nS 3.3000V 3.1400V 3.4700V -8.2828nS 3.3000V 3.1400V 3.4700V -8.3838nS 3.3000V 3.1400V 3.4700V -8.4848nS 3.3000V 3.1400V 3.4700V -8.5859nS 3.3000V 3.1400V 3.4700V -8.6869nS 3.3000V 3.1400V 3.4700V -8.7879nS 3.3000V 3.1400V 3.4700V -8.8889nS 3.3000V 3.1400V 3.4700V -8.9899nS 3.3000V 3.1400V 3.4700V -9.0909nS 3.3000V 3.1400V 3.4700V -9.1919nS 3.3000V 3.1400V 3.4700V -9.2929nS 3.3000V 3.1400V 3.4700V -9.3939nS 3.3000V 3.1400V 3.4700V -9.4949nS 3.3000V 3.1400V 3.4700V -9.5960nS 3.3000V 3.1400V 3.4700V -9.6970nS 3.3000V 3.1400V 3.4700V -9.7980nS 3.3000V 3.1400V 3.4700V -9.8990nS 3.3000V 3.1400V 3.4700V -10.0000nS 3.3000V 3.1400V 3.4700V -| -[Rising Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 0.4849uV 0.6538uV 0.4584uV -0.1010nS -91.8400nV 63.2160nV -25.7920nV -0.2020nS -2.6993uV -0.4530uV -0.2185uV -0.3030nS -0.1263uV -1.9171uV 9.8177uV -0.4040nS 2.2148uV 0.3884uV -0.7508mV -0.5051nS 17.9080uV 0.4320uV -54.9180mV -0.6061nS -0.9283mV 2.0154uV -38.8140mV -0.7071nS -36.0310mV 19.4020uV 0.5590V -0.8081nS -59.6090mV 49.7370uV 1.7463V -0.9091nS -7.5013mV -0.5918mV 2.5098V -1.0101nS 0.3035V -13.7970mV 2.7118V -1.1111nS 0.8765V -46.7140mV 2.7764V -1.2121nS 1.5353V -51.2590mV 2.8047V -1.3131nS 2.0287V -34.8250mV 2.8192V -1.4141nS 2.2720V 25.7290mV 2.8271V -1.5152nS 2.3732V 0.1849V 2.8315V -1.6162nS 2.4197V 0.4573V 2.8339V -1.7172nS 2.4473V 0.8065V 2.8353V -1.8182nS 2.4633V 1.1645V 2.8360V -1.9192nS 2.4738V 1.4818V 2.8364V -2.0202nS 2.4810V 1.7269V 2.8366V -2.1212nS 2.4853V 1.8846V 2.8368V -2.2222nS 2.4883V 1.9770V 2.8368V -2.3232nS 2.4902V 2.0335V 2.8369V -2.4242nS 2.4916V 2.0698V 2.8369V -2.5253nS 2.4924V 2.0942V 2.8369V -2.6263nS 2.4930V 2.1112V 2.8369V -2.7273nS 2.4934V 2.1231V 2.8370V -2.8283nS 2.4937V 2.1316V 2.8369V -2.9293nS 2.4938V 2.1374V 2.8370V -3.0303nS 2.4940V 2.1420V 2.8369V -3.1313nS 2.4940V 2.1455V 2.8370V -3.2323nS 2.4942V 2.1480V 2.8369V -3.3333nS 2.4941V 2.1499V 2.8370V -3.4343nS 2.4942V 2.1514V 2.8369V -3.5354nS 2.4942V 2.1525V 2.8370V -3.6364nS 2.4943V 2.1533V 2.8369V -3.7374nS 2.4942V 2.1539V 2.8370V -3.8384nS 2.4943V 2.1544V 2.8369V -3.9394nS 2.4942V 2.1548V 2.8370V -4.0404nS 2.4943V 2.1551V 2.8369V -4.1414nS 2.4942V 2.1553V 2.8370V -4.2424nS 2.4943V 2.1554V 2.8369V -4.3434nS 2.4942V 2.1556V 2.8370V -4.4444nS 2.4943V 2.1557V 2.8369V -4.5455nS 2.4942V 2.1557V 2.8370V -4.6465nS 2.4943V 2.1558V 2.8369V -4.7475nS 2.4942V 2.1558V 2.8370V -4.8485nS 2.4943V 2.1559V 2.8369V -4.9495nS 2.4942V 2.1559V 2.8370V -5.0505nS 2.4942V 2.1559V 2.8369V -5.1515nS 2.4943V 2.1560V 2.8369V -5.2525nS 2.4943V 2.1560V 2.8370V -5.3535nS 2.4943V 2.1560V 2.8369V -5.4545nS 2.4943V 2.1560V 2.8370V -5.5556nS 2.4943V 2.1560V 2.8369V -5.6566nS 2.4943V 2.1560V 2.8370V -5.7576nS 2.4943V 2.1560V 2.8370V -5.8586nS 2.4943V 2.1560V 2.8370V -5.9596nS 2.4943V 2.1560V 2.8370V -6.0606nS 2.4943V 2.1560V 2.8370V -6.1616nS 2.4943V 2.1560V 2.8370V -6.2626nS 2.4943V 2.1560V 2.8370V -6.3636nS 2.4943V 2.1560V 2.8370V -6.4646nS 2.4943V 2.1560V 2.8370V -6.5657nS 2.4943V 2.1560V 2.8370V -6.6667nS 2.4943V 2.1560V 2.8370V -6.7677nS 2.4943V 2.1560V 2.8370V -6.8687nS 2.4943V 2.1560V 2.8370V -6.9697nS 2.4943V 2.1560V 2.8370V -7.0707nS 2.4943V 2.1560V 2.8370V -7.1717nS 2.4943V 2.1560V 2.8370V -7.2727nS 2.4943V 2.1560V 2.8370V -7.3737nS 2.4943V 2.1560V 2.8370V -7.4747nS 2.4943V 2.1560V 2.8370V -7.5758nS 2.4943V 2.1560V 2.8370V -7.6768nS 2.4943V 2.1560V 2.8370V -7.7778nS 2.4943V 2.1560V 2.8370V -7.8788nS 2.4943V 2.1560V 2.8370V -7.9798nS 2.4943V 2.1560V 2.8370V -8.0808nS 2.4943V 2.1560V 2.8370V -8.1818nS 2.4943V 2.1560V 2.8370V -8.2828nS 2.4943V 2.1560V 2.8370V -8.3838nS 2.4943V 2.1560V 2.8370V -8.4848nS 2.4943V 2.1560V 2.8370V -8.5859nS 2.4943V 2.1560V 2.8370V -8.6869nS 2.4943V 2.1560V 2.8370V -8.7879nS 2.4943V 2.1560V 2.8370V -8.8889nS 2.4943V 2.1560V 2.8370V -8.9899nS 2.4943V 2.1560V 2.8370V -9.0909nS 2.4943V 2.1560V 2.8370V -9.1919nS 2.4943V 2.1560V 2.8370V -9.2929nS 2.4943V 2.1560V 2.8370V -9.3939nS 2.4943V 2.1560V 2.8370V -9.4949nS 2.4943V 2.1560V 2.8370V -9.5960nS 2.4943V 2.1560V 2.8370V -9.6970nS 2.4943V 2.1560V 2.8370V -9.7980nS 2.4943V 2.1560V 2.8370V -9.8990nS 2.4943V 2.1560V 2.8370V -10.0000nS 2.4943V 2.1560V 2.8369V -| -[Falling Waveform] -R_fixture= 50.0000 -V_fixture= 0.0 -V_fixture_min= 0.0 -V_fixture_max= 0.0 -|time V(typ) V(min) V(max) -| -0.0S 2.4943V 2.1560V 2.8370V -0.1010nS 2.4943V 2.1560V 2.8370V -0.2020nS 2.4943V 2.1560V 2.8370V -0.3030nS 2.4943V 2.1560V 2.8370V -0.4040nS 2.4943V 2.1560V 2.8378V -0.5051nS 2.4943V 2.1560V 2.8500V -0.6061nS 2.4952V 2.1560V 1.9447V -0.7071nS 2.4905V 2.1560V 0.3637V -0.8081nS 2.4067V 2.1560V 67.8100mV -0.9091nS 1.4125V 2.1561V 29.4150mV -1.0101nS 0.4767V 2.1575V 14.9410mV -1.1111nS 0.1262V 2.1538V 7.5466mV -1.2121nS 43.6680mV 2.1382V 3.8422mV -1.3131nS 26.1960mV 1.7150V 1.8945mV -1.4141nS 16.2920mV 1.0257V 0.9804mV -1.5152nS 10.0550mV 0.5310V 0.5148mV -1.6162nS 6.1813mV 0.2066V 0.2988mV -1.7172nS 3.9618mV 85.0700mV 0.1781mV -1.8182nS 2.4789mV 45.0760mV 0.1309mV -1.9192nS 1.5559mV 28.7760mV 93.0170uV -2.0202nS 0.9974mV 19.8010mV 83.3720uV -2.1212nS 0.6445mV 14.0690mV 58.3290uV -2.2222nS 0.4351mV 10.1110mV 63.2910uV -2.3232nS 0.2957mV 7.2280mV 53.7290uV -2.4242nS 0.2210mV 5.1895mV 54.2190uV -2.5253nS 0.1601mV 3.7800mV 40.3540uV -2.6263nS 0.1279mV 2.7268mV 47.2160uV -2.7273nS 0.1002mV 1.9853mV 36.9860uV -2.8283nS 88.8660uV 1.4440mV 40.0480uV -2.9293nS 72.7920uV 1.0670mV 26.3870uV -3.0303nS 69.1040uV 0.7846mV 34.6390uV -3.1313nS 57.4210uV 0.5846mV 26.3910uV -3.2323nS 56.9730uV 0.4404mV 29.4630uV -3.3333nS 47.8400uV 0.3494mV 17.8610uV -3.4343nS 48.1880uV 0.2584mV 25.6730uV -3.5354nS 40.2540uV 0.2118mV 18.4590uV -3.6364nS 41.5730uV 0.1702mV 21.8800uV -3.7374nS 34.4050uV 0.1443mV 11.4790uV -3.8384nS 35.9660uV 0.1162mV 17.0260uV -3.9394nS 29.3730uV 0.1105mV 5.6280uV -4.0404nS 31.4140uV 89.4040uV 15.1470uV -4.1414nS 25.3750uV 81.0200uV 11.2580uV -4.2424nS 27.4070uV 65.5230uV 14.1370uV -4.3434nS 21.6970uV 73.0300uV 6.2960uV -4.4444nS 23.9220uV 61.3290uV 11.4660uV -4.5455nS 18.5100uV 55.7850uV 2.5000uV -4.6465nS 21.0070uV 43.3670uV 8.5284uV -4.7475nS 15.9410uV 53.7310uV -0.8463uV -4.8485nS 18.4620uV 44.3590uV 8.1933uV -4.9495nS 13.5820uV 42.1040uV 5.3730uV -5.0505nS 13.8755uV 37.5100uV 5.0024uV -5.1515nS 14.2440uV 35.8510uV 6.5401uV -5.2525nS 9.9306uV 32.2800uV -0.5688uV -5.3535nS 12.5350uV 22.2570uV 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0.9661V 0.6180V -9.1919nS 0.7517V 0.9661V 0.6180V -9.2929nS 0.7516V 0.9661V 0.6180V -9.3939nS 0.7517V 0.9661V 0.6180V -9.4949nS 0.7516V 0.9661V 0.6180V -9.5960nS 0.7516V 0.9661V 0.6180V -9.6970nS 0.7516V 0.9661V 0.6180V -9.7980nS 0.7516V 0.9661V 0.6180V -9.8990nS 0.7516V 0.9661V 0.6180V -10.0000nS 0.7517V 0.9661V 0.6180V -| -| End [Model] lvt330s160aaaaaaaaou -|************************************************************************ -| End [Component] -[End] diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep deleted file mode 100644 index e5894f8..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep +++ /dev/null @@ -1,22 +0,0 @@ ----------------------------------------------------------------------- -Report for cell RAM2GS.TECH -Register bits: 119 of 877 (13.569%) -I/O cells: 63 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 10 100.0 - EFB 1 100.0 - FD1P3AX 30 100.0 - FD1P3AY 4 100.0 - FD1P3IX 3 100.0 - FD1S3AX 64 100.0 - FD1S3IX 14 100.0 - FD1S3JX 4 100.0 - GSR 1 100.0 - IB 25 100.0 - INV 3 100.0 - LUT4 236 100.0 - OB 30 100.0 - PFUMX 16 100.0 - TOTAL 449 diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn deleted file mode 100644 index 86c3161..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn +++ /dev/null @@ -1,86 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Tue Aug 17 06:21:07 2021 - - -Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf - -Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp deleted file mode 100644 index aa483f5..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp +++ /dev/null @@ -1,402 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2GS' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr - RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use - rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX - O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/ - LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -Target Vendor: LATTICE -Target Device: LCMXO2-640HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2 -Mapped on: 10/09/21 01:19:14 - -Design Summary --------------- - - Number of registers: 119 out of 877 (14%) - PFU registers: 119 out of 640 (19%) - PIO registers: 0 out of 237 (0%) - Number of SLICEs: 131 out of 320 (41%) - SLICEs as Logic/ROM: 131 out of 320 (41%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 10 out of 320 (3%) - Number of LUT4s: 255 out of 640 (40%) - Number used as logic LUTs: 235 - Number used as distributed RAM: 0 - Number used as ripple logic: 20 - Number used as shift registers: 0 - Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 5 - Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK ) - Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Number of Clock Enables: 14 - Net RCLK_c_enable_27: 8 loads, 8 LSLICEs - Net RCLK_c_enable_20: 4 loads, 4 LSLICEs - - Page 1 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -Design Summary (cont) ---------------------- - Net RCLK_c_enable_29: 2 loads, 2 LSLICEs - Net RCLK_c_enable_25: 2 loads, 2 LSLICEs - Net InitReady: 1 loads, 1 LSLICEs - Net RCLK_c_enable_24: 2 loads, 2 LSLICEs - Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs - Net RCLK_c_enable_26: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs - Net Ready_N_280: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_28: 1 loads, 1 LSLICEs - Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs - Number of LSRs: 8 - Net RASr2: 1 loads, 1 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Net wb_rst: 1 loads, 0 LSLICEs - Net nRWE_N_210: 1 loads, 1 LSLICEs - Net C1Submitted_N_232: 2 loads, 2 LSLICEs - Net wb_adr_7__N_92: 2 loads, 2 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net InitReady: 36 loads - Net FS_10: 32 loads - Net FS_11: 32 loads - Net FS_9: 26 loads - Net FS_7: 25 loads - Net FS_8: 23 loads - Net FS_5: 21 loads - Net FS_6: 21 loads - Net FS_12: 20 loads - Net Ready: 18 loads - - - - - Number of warnings: 0 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - - No errors or warnings present. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RCLK | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nFWE | INPUT | LVTTL33 | | - - Page 2 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| nCRAS | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nCCAS | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[3] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| CROW[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| CROW[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[0] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[1] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[2] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[3] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[4] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[5] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[6] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[7] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[8] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| MAin[9] | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| PHI2 | INPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RDQML | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RDQMH | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRCAS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRRAS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRWE | OUTPUT | LVTTL33 | | - - Page 3 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| RCKE | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| nRCS | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[2] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[3] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[4] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[5] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[6] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[7] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[8] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[9] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[10] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RA[11] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RBA[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RBA[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVTTL33 | | - - Page 4 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -IO (PIO) Attributes (cont) --------------------------- -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVTTL33 | | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block i2 undriven or does not drive anything - clipped. -Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_151 was merged into signal PHI2_c -Signal nRWE_N_209 was merged into signal nRWE_N_210 -Signal RCLK_c_enable_22 was merged into signal InitReady -Signal n2557 was merged into signal nRowColSel_N_34 -Signal n4935 was merged into signal Ready -Signal n4933 was merged into signal nRowColSel_N_35 -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped. -Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped. -Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped. -Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped. -Block i4008 was optimized away. -Block nRWE_I_53_1_lut was optimized away. -Block InitReady_I_0_586_1_lut_rep_73 was optimized away. -Block i1683_1_lut was optimized away. -Block i1044_1_lut_rep_86 was optimized away. -Block i1684_1_lut_rep_84 was optimized away. -Block i1 was optimized away. - - - -Embedded Functional Block Connection Summary --------------------------------------------- - - Desired WISHBONE clock frequency: 50.0 MHz - Clock source: wb_clk - Reset source: wb_rst - Functions mode: - I2C #1 (Primary) Function: DISABLED - I2C #2 (Secondary) Function: DISABLED - SPI Function: DISABLED - Timer/Counter Function: DISABLED - Timer/Counter Mode: NO_WB - UFM Connection: DISABLED - PLL0 Connection: DISABLED - PLL1 Connection: DISABLED - I2C Function Summary: - -------------------- - - Page 5 - - - - -Design: RAM2GS Date: 10/09/21 01:19:14 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - None - SPI Function Summary: - -------------------- - None - Timer/Counter Function Summary: - ------------------------------ - None - UFM Function Summary: - -------------------- - UFM Utilization: General Purpose Flash Memory - Available General - Purpose Flash Memory: 191 Pages (191*128 Bits) - - EBR Blocks with Unique - Initialization Data: 0 - - WID EBR Instance - --- ------------ - - -ASIC Components ---------------- - -Instance Name: ufmefb - Type: EFB - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 37 MB - - - - - - - - - - - - - - - - - - - - - - - - - - Page 6 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. 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- - -

BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 17 06:21:07 2021
-
-
-Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                         2.08**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                      JTAG_PORT  |                       ENABLE**  |
-+---------------------------------+---------------------------------+
-|                       SDM_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                       I2C_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  CONFIGURATION  |                          CFG**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                        MY_ASSP  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|               ONE_TIME_PROGRAM  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                 ENABLE_TRANSFR  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  SHAREDEBRINIT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 1.95.
- 
-Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
- 
-===========
-UFM Summary.
-===========
-UFM Size:        191 Pages (128*191 Bits).
-UFM Utilization: General Purpose Flash Memory.
- 
-Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     0 Page.
- 
-Total CPU Time: 1 secs 
-Total REAL Time: 2 secs 
-Peak Memory Usage: 245 MB
-
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html deleted file mode 100644 index 2e5e5a5..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html +++ /dev/null @@ -1,198 +0,0 @@ - -I/O Timing Report - - -
I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Sat Oct 09 01:19:25 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F    -0.195      M       1.729     4
-CROW[1] nCRAS F    -0.218      M       1.801     4
-Din[0]  PHI2  F     6.339      4       1.186     4
-Din[0]  nCCAS F     1.641      4       0.107     M
-Din[1]  PHI2  F     6.084      4       1.570     4
-Din[1]  nCCAS F     0.198      4       1.314     4
-Din[2]  PHI2  F     3.778      4       1.771     4
-Din[2]  nCCAS F     0.075      4       1.431     4
-Din[3]  PHI2  F     4.331      4       1.705     4
-Din[3]  nCCAS F    -0.116      M       1.722     4
-Din[4]  PHI2  F     6.176      4       1.711     4
-Din[4]  nCCAS F     1.065      4       0.575     4
-Din[5]  PHI2  F     4.684      4       1.261     4
-Din[5]  nCCAS F    -0.081      M       1.625     4
-Din[6]  PHI2  F     5.243      4       0.356     4
-Din[6]  nCCAS F     1.414      4       0.309     4
-Din[7]  PHI2  F     6.602      4       1.175     4
-Din[7]  nCCAS F    -0.286      M       2.137     4
-MAin[0] PHI2  F     5.034      4       0.629     4
-MAin[0] nCRAS F     1.094      4       0.380     4
-MAin[1] PHI2  F     6.081      4       1.157     4
-MAin[1] nCRAS F     0.544      4       0.877     4
-MAin[2] PHI2  F     9.979      4      -0.319     M
-MAin[2] nCRAS F    -0.050      M       1.401     4
-MAin[3] PHI2  F     9.162      4      -0.219     M
-MAin[3] nCRAS F     1.032      4       0.440     4
-MAin[4] PHI2  F    11.678      4      -0.770     M
-MAin[4] nCRAS F    -0.150      M       1.620     4
-MAin[5] PHI2  F     8.668      4      -0.081     M
-MAin[5] nCRAS F    -0.050      M       1.401     4
-MAin[6] PHI2  F     8.516      4      -0.025     M
-MAin[6] nCRAS F     1.003      4       0.478     4
-MAin[7] PHI2  F     9.320      4      -0.061     M
-MAin[7] nCRAS F     1.001      4       0.478     4
-MAin[8] nCRAS F    -0.146      M       1.657     4
-MAin[9] nCRAS F    -0.360      M       2.140     4
-PHI2    RCLK  R     3.079      4      -0.602     M
-nCCAS   RCLK  R     3.574      4      -0.705     M
-nCCAS   nCRAS F     3.232      4      -0.351     M
-nCRAS   RCLK  R     2.757      4      -0.470     M
-nFWE    PHI2  F     5.913      4       0.723     4
-nFWE    nCRAS F     0.547      4       0.890     4
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    10.062         4        3.164          M
-RA[0]  RCLK  R    10.645         4        3.471          M
-RA[0]  nCRAS F    11.744         4        3.770          M
-RA[10] RCLK  R     9.485         4        3.236          M
-RA[11] PHI2  R    11.513         4        3.824          M
-RA[1]  RCLK  R    10.921         4        3.549          M
-RA[1]  nCRAS F    12.664         4        4.036          M
-RA[2]  RCLK  R    10.923         4        3.527          M
-RA[2]  nCRAS F    12.463         4        3.984          M
-RA[3]  RCLK  R    11.178         4        3.615          M
-RA[3]  nCRAS F    12.304         4        3.917          M
-RA[4]  RCLK  R    11.365         4        3.630          M
-RA[4]  nCRAS F    13.243         4        4.179          M
-RA[5]  RCLK  R    11.365         4        3.630          M
-RA[5]  nCRAS F    12.940         4        4.098          M
-RA[6]  RCLK  R    11.099         4        3.573          M
-RA[6]  nCRAS F    12.162         4        3.870          M
-RA[7]  RCLK  R    10.948         4        3.552          M
-RA[7]  nCRAS F    12.282         4        3.936          M
-RA[8]  RCLK  R    11.114         4        3.608          M
-RA[8]  nCRAS F    12.909         4        4.116          M
-RA[9]  RCLK  R    11.005         4        3.561          M
-RA[9]  nCRAS F    12.959         4        4.081          M
-RBA[0] nCRAS F    11.842         4        3.911          M
-RBA[1] nCRAS F    11.343         4        3.771          M
-RCKE   RCLK  R     9.884         4        3.362          M
-RDQMH  RCLK  R    10.941         4        3.559          M
-RDQML  RCLK  R    10.641         4        3.470          M
-RD[0]  nCCAS F    12.628         4        4.413          M
-RD[1]  nCCAS F    12.231         4        4.302          M
-RD[2]  nCCAS F    12.231         4        4.302          M
-RD[3]  nCCAS F    11.928         4        4.221          M
-RD[4]  nCCAS F    12.427         4        4.361          M
-RD[5]  nCCAS F    12.697         4        4.400          M
-RD[6]  nCCAS F    12.427         4        4.361          M
-RD[7]  nCCAS F    12.427         4        4.361          M
-nRCAS  RCLK  R     9.674         4        3.300          M
-nRCS   RCLK  R     9.674         4        3.300          M
-nRRAS  RCLK  R     9.797         4        3.322          M
-nRWE   RCLK  R     9.275         4        3.194          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: M
-
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- - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj deleted file mode 100644 index 7540ad6..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj +++ /dev/null @@ -1,41 +0,0 @@ --a "MachXO2" --d LCMXO2-640HC --t TQFP100 --s 4 --frequency 200 --optimization_goal Balanced --bram_utilization 100 --ramstyle Auto --romstyle auto --dsp_utilization 100 --use_dsp 1 --use_carry_chain 1 --carry_chain_length 0 --force_gsr Auto --resource_sharing 1 --propagate_constants 1 --remove_duplicate_regs 1 --mux_style Auto --max_fanout 1000 --fsm_encoding_style Auto --twr_paths 3 --fix_gated_clocks 1 --loop_limit 1950 - - - --use_io_insertion 1 --resolve_mixed_drivers 0 --use_io_reg auto - - --lpf 1 --p "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC" --ver "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v" --top RAM2GS - - --p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC" - --ngd "RAM2GS_LCMXO2_640HC_impl1.ngd" - diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam deleted file mode 100644 index 1db8fb1..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam +++ /dev/null @@ -1,94 +0,0 @@ -[ START MERGED ] -n4935 Ready -n4933 nRowColSel_N_35 -n2557 nRowColSel_N_34 -nRWE_N_209 nRWE_N_210 -PHI2_N_151 PHI2_c -RCLK_c_enable_22 InitReady -[ END MERGED ] -[ START CLIPPED ] -GND_net -VCC_net -FS_972_add_4_1/S0 -FS_972_add_4_1/CI -FS_972_add_4_19/S1 -FS_972_add_4_19/CO -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RCLK" SITE "63" ; -LOCATE COMP "nFWE" SITE "15" ; -LOCATE COMP "nCRAS" SITE "17" ; -LOCATE COMP "nCCAS" SITE "9" ; -LOCATE COMP "Din[0]" SITE "3" ; -LOCATE COMP "Din[1]" SITE "96" ; -LOCATE COMP "Din[2]" SITE "88" ; -LOCATE COMP "Din[3]" SITE "97" ; -LOCATE COMP "Din[4]" SITE "99" ; -LOCATE COMP "Din[5]" SITE "98" ; -LOCATE COMP "Din[6]" SITE "2" ; -LOCATE COMP "Din[7]" SITE "1" ; -LOCATE COMP "CROW[0]" SITE "10" ; -LOCATE COMP "CROW[1]" SITE "16" ; -LOCATE COMP "MAin[0]" SITE "14" ; -LOCATE COMP "MAin[1]" SITE "12" ; -LOCATE COMP "MAin[2]" SITE "13" ; -LOCATE COMP "MAin[3]" SITE "21" ; -LOCATE COMP "MAin[4]" SITE "20" ; -LOCATE COMP "MAin[5]" SITE "19" ; -LOCATE COMP "MAin[6]" SITE "24" ; -LOCATE COMP "MAin[7]" SITE "18" ; -LOCATE COMP "MAin[8]" SITE "25" ; -LOCATE COMP "MAin[9]" SITE "32" ; -LOCATE COMP "PHI2" SITE "8" ; -LOCATE COMP "RDQML" SITE "48" ; -LOCATE COMP "RDQMH" SITE "51" ; -LOCATE COMP "nRCAS" SITE "52" ; -LOCATE COMP "nRRAS" SITE "54" ; -LOCATE COMP "nRWE" SITE "49" ; -LOCATE COMP "RCKE" SITE "53" ; -LOCATE COMP "nRCS" SITE "57" ; -LOCATE COMP "RA[0]" SITE "66" ; -LOCATE COMP "RA[1]" SITE "67" ; -LOCATE COMP "RA[2]" SITE "69" ; -LOCATE COMP "RA[3]" SITE "71" ; -LOCATE COMP "RA[4]" SITE "74" ; -LOCATE COMP "RA[5]" SITE "70" ; -LOCATE COMP "RA[6]" SITE "68" ; -LOCATE COMP "RA[7]" SITE "75" ; -LOCATE COMP "RA[8]" SITE "65" ; -LOCATE COMP "RA[9]" SITE "62" ; -LOCATE COMP "RA[10]" SITE "64" ; -LOCATE COMP "RA[11]" SITE "59" ; -LOCATE COMP "RBA[0]" SITE "58" ; -LOCATE COMP "RBA[1]" SITE "60" ; -LOCATE COMP "LED" SITE "34" ; -LOCATE COMP "Dout[0]" SITE "76" ; -LOCATE COMP "Dout[1]" SITE "86" ; -LOCATE COMP "Dout[2]" SITE "87" ; -LOCATE COMP "Dout[3]" SITE "85" ; -LOCATE COMP "Dout[4]" SITE "83" ; -LOCATE COMP "Dout[5]" SITE "84" ; -LOCATE COMP "Dout[6]" SITE "78" ; -LOCATE COMP "Dout[7]" SITE "82" ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[7]" SITE "43" ; -PERIOD NET "PHI2_c" 350.000000 ns ; -USE PRIMARY NET "RCLK_c" ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -USE PRIMARY NET "PHI2_c" ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -USE PRIMARY NET "nCRAS_c" ; -PERIOD NET "RCLK_c" 16.000000 ns ; -USE PRIMARY NET "nCCAS_c" ; -SCHEMATIC END ; -[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr deleted file mode 100644 index 1264102..0000000 --- a/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr +++ /dev/null @@ -1,10 +0,0 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zs7?8xHYK4pwLf$>sx5;ou8pB}4QkW%B-Hl6tR%HIG$5)i11+wNv2`tKQ`SapV0~G( z0a0xkY;kQ2uIo@6`lcGuAOf*zZD>GLn}s*G&px7(@6pxVTn`>^#tit`d5z@O#d1w=KAtN=5 z(GdvT6{^a#w3B;#6IzN|G_R84mR2gA>wq61nP zI-sO%2Z9|VR{CyqMJJ%xG14_IY!4mdy8@C{2$HT|fy9b%A2=Il8QyC20T%lT5yg+5 zWr%`IfxYw;IGpbr1rACwEQ#IjZ78liM}-Y2YLoc z(WNcGz+ET*uo<1#!CgtCNF;38kGA@x9neY)k+8RZ42o}7iDugvP4&nLb+Y??tW{iV zSB`P*?(?V4wmW&U_BdhUuytFu4eEt3^g71pf`HX8L7J#t89NmwUT03^T$gCR8KTGz!YC9p!)VB3{W*Hbw +
  • Session Log (20:59 16-Aug)
      • diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm similarity index 55% rename from CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm rename to CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm index 7408ad9..741590b 100644 --- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_srr.htm +++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_srr.htm @@ -1,11 +1,11 @@ 
      -
+
 #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
 #install: C:\lscc\diamond\3.12\synpbase
 #OS: Windows 8 6.2
 #Hostname: ZANEPC
 
-# Tue Aug 15 22:34:17 2023
+# Wed Aug 16 20:59:29 2023
 
 #Implementation: impl1
 
@@ -25,7 +25,7 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 ###########################################################[
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -43,38 +43,57 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
-@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 
-
-@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 
-
+@N: :  | Running in 64-bit mode 
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
+@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
-Options changed - recompiling
+
+Compiler output is up to date.  No re-compile necessary
+
 Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
+@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : machxo2.v(1124) | Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : machxo2.v(1800) | Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : REFB.v(8) | Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 92MB)
+@N:CG364 : RAM2GS-LCMXO2.v(1) | Synthesizing module RAM2GS in library work.
 Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
+Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
 Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
+Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
 
 For a summary of runtime and memory usage per design unit, please see file:
 ==========================================================
 Linked File:  layer0.rt.csv
 
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 ###########################################################[
@@ -94,22 +113,23 @@ Hostname: ZANEPC
 Implementation : impl1
 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
 
-@N: :  | Running in 64-bit mode 
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
+@N: :  | Running in 64-bit mode 
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
+Linker output is up to date. No re-linking necessary
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 For a summary of runtime and memory usage for all design units, please see file:
 ==========================================================
-Linked File:  impl1_comp.rt.csv
+Linked File:  LCMXO2_640HC_impl1_comp.rt.csv
 
 @END
 
@@ -118,53 +138,30 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Tue Aug 15 22:34:18 2023
+# Wed Aug 16 20:59:29 2023
 
 ###########################################################]
 
 
      -
-###########################################################[
+
 
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-@N:NF107 : ram2gs-spi.v(1) | Selected library: work cell: RAM2GS view verilog as top level
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 22:34:19 2023
-
-###########################################################]
+@A: :  | multi_srs_gen output is up to date. No run necessary. 
+To force a re-synthesis, select [Resynthesize All] in menu [Run].
+Click link to view previous log file.
+Multi-srs Generator Report
+Linked File:  LCMXO2_640HC_impl1_multi_srs_gen.srr
 
 
      -
+
 Premap Report
 
 
 
      -
-# Tue Aug 15 22:34:20 2023
+
+# Wed Aug 16 20:59:30 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -186,14 +183,14 @@ Implementation : impl1
 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
 
 Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+Linked File:  LCMXO2_640HC_impl1_scck.rpt
+See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_scck.rpt"
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
 
 Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
@@ -201,84 +198,83 @@ Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s
 Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB)
 
 
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)
 
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
+@N:FX493 :  | Applying initial value "0" on instance InitReady. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance Ready. 
+@N:FX493 :  | Applying initial value "0" on instance RCKE. 
+@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
+@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRCS. 
+@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
+@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
+@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
+@N:FX493 :  | Applying initial value "0" on instance CMDUFMWrite. 
+@N:FX493 :  | Applying initial value "0" on instance CmdUFMData. 
+@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
+@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
+@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
+@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
+@N:FX493 :  | Applying initial value "1" on instance nRWE. 
 
 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 172MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
+@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
 
 Clock Summary
 ******************
 
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       RCLK       62.5 MHz      16.000        declared     default_clkgroup     65   
+                                                                                        
+0 -       PHI2       2.9 MHz       350.000       declared     default_clkgroup     18   
+                                                                                        
+0 -       nCRAS      2.9 MHz       350.000       declared     default_clkgroup     14   
+                                                                                        
+0 -       nCCAS      2.9 MHz       350.000       declared     default_clkgroup     8    
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
 
 
 
 Clock Load Summary
 ***********************
 
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
+           Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin             Seq Example     Seq Example       Comb Example      
+-----------------------------------------------------------------------------------------
+RCLK       65        RCLK(port)      CASr2.C         -                 -                 
+                                                                                         
+PHI2       18        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
+                                                                                         
+nCRAS      14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
+                                                                                         
+nCCAS      8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
+                                                                                         
+System     0         -               -               -                 -                 
+=========================================================================================
 
 ICG Latch Removal Summary:
 Number of ICG latches removed: 0
@@ -292,52 +288,52 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
+4 non-gated/non-generated clock tree(s) driving 105 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
+ClockId_0_0       RCLK                port                   65         nRWE           
+ClockId_0_1       PHI2                port                   18         RA11           
+ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
+ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
 =======================================================================================
 
 
 ##### END OF CLOCK OPTIMIZATION REPORT ######
 
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
+@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 175MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 22:34:21 2023
+# Wed Aug 16 20:59:32 2023
 
 ###########################################################]
 
 
      -
+
 Map & Optimize Report
 
 
 
      -
-# Tue Aug 15 22:34:22 2023
+
+# Wed Aug 16 20:59:32 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -356,11 +352,11 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
 
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+@N:MF916 :  | Option synthesis_strategy=base is enabled.  
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
 
 Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
 
@@ -377,103 +373,98 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
 
 Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
 
-@N:MT204 :  | Auto Constrain mode is disabled because the following clocks are already defined: 
-
-            RCLK
-            PHI2
-            nCRAS
-            nCCAS
-
 
 Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
 
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
+@N:MO231 : ram2gs-lcmxo2.v(161) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
+@N:MO231 : ram2gs-lcmxo2.v(148) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
+@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
+@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
+@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
+@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
 
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 175MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 176MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+   1		0h:00m:01s		    -2.34ns		 199 /       105
+   2		0h:00m:01s		    -2.34ns		 208 /       105
+   3		0h:00m:01s		    -2.34ns		 208 /       105
+@N:FX271 : ram2gs-lcmxo2.v(302) | Replicating instance CmdSubmitted (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(161) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
+@N:FX271 : ram2gs-lcmxo2.v(119) | Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
 Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
+Added 4 Registers via timing driven replication
+Added 1 LUTs via timing driven replication
 
-   4		0h:00m:01s		    -2.04ns		 140 /        90
+   4		0h:00m:01s		    -1.83ns		 210 /       109
 
 
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
+   5		0h:00m:01s		    -1.83ns		 211 /       109
+   6		0h:00m:01s		    -1.83ns		 212 /       109
+   7		0h:00m:01s		    -1.83ns		 212 /       109
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 177MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 186MB)
 
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_m.srm
+Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB)
 
 Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi 
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 193MB)
 
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
+@W:MT246 : refb.v(78) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N:MT615 :  | Found clock RCLK with period 16.00ns  
+@N:MT615 :  | Found clock PHI2 with period 350.00ns  
+@N:MT615 :  | Found clock nCRAS with period 350.00ns  
+@N:MT615 :  | Found clock nCCAS with period 350.00ns  
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 22:34:24 2023
+# Timing report written on Wed Aug 16 20:59:35 2023
 #
 
 
@@ -483,9 +474,9 @@ Wire load mode:         top
 Paths requested:        5
 Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
                        
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
 
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
+@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
 
 
 
@@ -493,41 +484,44 @@ Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
 *******************
 
 
-Worst slack in design: -2.389
+Worst slack in design: -1.832
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
+PHI2               2.9 MHz       1.0 MHz       350.000       991.270       -1.832     declared     default_clkgroup
+RCLK               62.5 MHz      22.1 MHz      16.000        45.315        -0.784     declared     default_clkgroup
 nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
+nCRAS              2.9 MHz       1.0 MHz       350.000       953.610       -1.725     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            15.472     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
 
 
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
+@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
+@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
 
 
 
 Clock Relationships
 *******************
 
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
+Clocks            |    rise  to  rise    |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
+---------------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack    |  constraint  slack    |  constraint  slack  
+---------------------------------------------------------------------------------------------------------------
+System    RCLK    |  16.000      15.472  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      System  |  16.000      14.892  |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      RCLK    |  16.000      8.605   |  No paths    -        |  No paths    -        |  No paths    -      
+RCLK      PHI2    |  2.000       0.216   |  No paths    -        |  1.000       -0.636   |  No paths    -      
+RCLK      nCRAS   |  No paths    -       |  No paths    -        |  1.000       -0.784   |  No paths    -      
+PHI2      RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.832 
+PHI2      PHI2    |  No paths    -       |  350.000     346.115  |  175.000     168.921  |  175.000     173.428
+nCRAS     RCLK    |  No paths    -       |  No paths    -        |  No paths    -        |  1.000       -1.725 
+===============================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
@@ -549,46 +543,46 @@ No IO constraint found
 Starting Points with Worst Slack
 ********************************
 
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
+                      Starting                                                 Arrival            
+Instance              Reference     Type         Pin     Net                   Time        Slack  
+                      Clock                                                                       
+--------------------------------------------------------------------------------------------------
+CMDUFMWrite           PHI2          FD1P3AX      Q       CMDUFMWrite           1.044       -1.832 
+CmdSubmitted_fast     PHI2          FD1S3AX      Q       CmdSubmitted_fast     1.044       -1.832 
+CmdSubmitted          PHI2          FD1S3AX      Q       CmdSubmitted          1.148       -1.708 
+CmdLEDEN              PHI2          FD1P3AX      Q       CmdLEDEN              1.044       -0.572 
+Cmdn8MEGEN            PHI2          FD1P3AX      Q       Cmdn8MEGEN            1.044       -0.572 
+CmdUFMData            PHI2          FD1P3AX      Q       CmdUFMData            0.972       -0.500 
+Bank_0io[0]           PHI2          IFS1P3DX     Q       Bank[0]               0.972       168.921
+Bank_0io[1]           PHI2          IFS1P3DX     Q       Bank[1]               0.972       168.921
+Bank_0io[2]           PHI2          IFS1P3DX     Q       Bank[2]               0.972       168.921
+Bank_0io[3]           PHI2          IFS1P3DX     Q       Bank[3]               0.972       168.921
+==================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
+               Starting                                             Required           
+Instance       Reference     Type        Pin     Net                Time         Slack 
+               Clock                                                                   
+---------------------------------------------------------------------------------------
+wb_adr[0]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[1]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[2]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[3]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[4]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[5]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[6]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_adr[7]      PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_cyc_stb     PHI2          FD1P3IX     SP      un1_wb_clk32_i     0.528        -1.832
+wb_dati[0]     PHI2          FD1P3AX     SP      un1_wb_clk32_i     0.528        -1.832
+=======================================================================================
 
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -598,122 +592,110 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 2: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.917
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CmdSubmitted_fast / Q
+    Ending point:                            wb_adr[0] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CmdSubmitted_fast        FD1S3AX      Q        Out     1.044     1.044 r     -         
+CmdSubmitted_fast        Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     B        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 r     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[0]                FD1P3AX      SP       In      0.000     2.361 r     -         
+=======================================================================================
 
 
 Path information for path number 3: 
       Requested Period:                      1.000
-    - Setup time:                            -0.462
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
+    = Required time:                         0.528
 
-    - Propagation time:                      3.214
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[7] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[7]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 4: 
       Requested Period:                      1.000
-    - Setup time:                            -0.089
+    - Setup time:                            0.472
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
+    = Required time:                         0.528
 
-    - Propagation time:                      2.605
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.517
+    = Slack (critical) :                     -1.832
 
-    Number of logic level(s):                2
-    Starting point:                          CmdUFMCS / Q
-    Ending point:                            nUFMCS / D
+    Number of logic level(s):                1
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[6] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdUFMCS             FD1P3AX      Q        Out     0.972     0.972 r     -         
-CmdUFMCS             Net          -        -       -         -           1         
-nUFMCS_s_0_m4_yy     ORCALUT4     A        In      0.000     0.972 r     -         
-nUFMCS_s_0_m4_yy     ORCALUT4     Z        Out     1.017     1.989 r     -         
-nUFMCS_s_0_m4_yy     Net          -        -       -         -           1         
-nUFMCS_s_0_N_5_i     ORCALUT4     C        In      0.000     1.989 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.605 f     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.605 f     -         
-===================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[6]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 Path information for path number 5: 
@@ -722,26 +704,26 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         0.528
 
-    - Propagation time:                      1.765
+    - Propagation time:                      2.361
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.236
+    = Slack (critical) :                     -1.832
 
     Number of logic level(s):                1
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            LEDEN / SP
+    Starting point:                          CMDUFMWrite / Q
+    Ending point:                            wb_adr[5] / SP
     The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-CmdSubmitted       FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted       Net          -        -       -         -           4         
-un1_FS_13_i_0      ORCALUT4     A        In      0.000     1.148 r     -         
-un1_FS_13_i_0      ORCALUT4     Z        Out     0.617     1.765 r     -         
-N_28               Net          -        -       -         -           1         
-LEDEN              FD1P3AX      SP       In      0.000     1.765 r     -         
-=================================================================================
+Instance / Net                        Pin      Pin               Arrival     No. of    
+Name                     Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------
+CMDUFMWrite              FD1P3AX      Q        Out     1.044     1.044 r     -         
+CMDUFMWrite              Net          -        -       -         -           2         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     A        In      0.000     1.044 r     -         
+CMDUFMWrite_RNIHQ1E1     ORCALUT4     Z        Out     1.317     2.361 f     -         
+un1_wb_clk32_i           Net          -        -       -         -           18        
+wb_adr[5]                FD1P3AX      SP       In      0.000     2.361 f     -         
+=======================================================================================
 
 
 
@@ -762,13 +744,13 @@ Instance       Reference     Type        Pin     Net            Time        Slac
 Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
 LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
 n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
+FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.605 
+FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       8.605 
+FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.108       8.605 
+FS[6]          RCLK          FD1S3AX     Q       FS[6]          1.268       8.872 
+FS[5]          RCLK          FD1S3AX     Q       FS[5]          1.228       8.912 
+FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.302       9.679 
+FS[10]         RCLK          FD1S3AX     Q       FS[10]         1.299       9.682 
 ==================================================================================
 
 
@@ -794,7 +776,7 @@ RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -949,13 +931,15 @@ RowA[6]            FD1S3AX      D        In      0.000     1.873 r     -
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
+              Starting                                        Arrival           
+Instance      Reference     Type        Pin     Net           Time        Slack 
+              Clock                                                             
+--------------------------------------------------------------------------------
+CBR_fast      nCRAS         FD1S3AX     Q       CBR_fast      1.108       -1.725
+CBR           nCRAS         FD1S3AX     Q       CBR           1.148       -1.693
+FWEr          nCRAS         FD1S3AX     Q       FWEr          1.108       -1.653
+FWEr_fast     nCRAS         FD1S3AX     Q       FWEr_fast     0.972       -1.589
+================================================================================
 
 
 Ending Points with Worst Slack
@@ -965,17 +949,17 @@ FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
 Instance       Reference     Type         Pin     Net                Time         Slack 
                Clock                                                                    
 ----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
+nRCAS_0io      nCRAS         OFS1P3BX     D       N_186_i            1.089        -1.725
+nRWE_0io       nCRAS         OFS1P3BX     D       N_44_i             1.089        -1.725
+nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.693
+RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.653
+nRCS_0io       nCRAS         OFS1P3BX     D       N_32_i             1.089        -1.653
 ========================================================================================
 
 
 
 Worst Path Information
-View Worst Path in Analyst
+View Worst Path in Analyst
 ***********************
 
 
@@ -985,12 +969,12 @@ Path information for path number 1:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -998,15 +982,15 @@ Path information for path number 1:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
+nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.197 r     -         
+nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.813 f     -         
+N_186_i                   Net          -        -       -         -           1         
+nRCAS_0io                 OFS1P3BX     D        In      0.000     2.813 f     -         
 ========================================================================================
 
 
@@ -1016,12 +1000,12 @@ Path information for path number 2:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.909
+    - Propagation time:                      2.813
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
+    = Slack (non-critical) :                 -1.725
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
+    Starting point:                          CBR_fast / Q
     Ending point:                            nRWE_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
@@ -1029,15 +1013,15 @@ Path information for path number 2:
 Instance / Net                         Pin      Pin               Arrival     No. of    
 Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
 ----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
+CBR_fast                  FD1S3AX      Q        Out     1.108     1.108 r     -         
+CBR_fast                  Net          -        -       -         -           3         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.108 r     -         
+nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.197 r     -         
 nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
+nRWE_0io_RNO              ORCALUT4     C        In      0.000     2.197 r     -         
+nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.813 r     -         
+N_44_i                    Net          -        -       -         -           1         
+nRWE_0io                  OFS1P3BX     D        In      0.000     2.813 r     -         
 ========================================================================================
 
 
@@ -1047,29 +1031,29 @@ Path information for path number 3:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
+    Starting point:                          CBR / Q
     Ending point:                            nRCAS_0io / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
     The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
 
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+CBR                 FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                 Net          -        -       -         -           4         
+nRCAS_0io_RNO_0     ORCALUT4     A        In      0.000     1.148 r     -         
+nRCAS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+nRCAS_0io_RNO_0     Net          -        -       -         -           1         
+nRCAS_0io_RNO       ORCALUT4     C        In      0.000     2.165 f     -         
+nRCAS_0io_RNO       ORCALUT4     Z        Out     0.617     2.781 r     -         
+N_186_i             Net          -        -       -         -           1         
+nRCAS_0io           OFS1P3BX     D        In      0.000     2.781 r     -         
+==================================================================================
 
 
 Path information for path number 4: 
@@ -1078,28 +1062,28 @@ Path information for path number 4:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.853
+    - Propagation time:                      2.781
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
+    = Slack (non-critical) :                 -1.693
 
     Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          CBR / Q
+    Ending point:                            nRowColSel / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                       Pin      Pin               Arrival     No. of    
 Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
 --------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCS_0io_RNO            ORCALUT4     B        In      0.000     2.237 r     -         
-nRCS_0io_RNO            ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_27_i                  Net          -        -       -         -           1         
-nRCS_0io                OFS1P3BX     D        In      0.000     2.853 f     -         
+CBR                     FD1S3AX      Q        Out     1.148     1.148 r     -         
+CBR                     Net          -        -       -         -           4         
+nRowColSel_0_0_a3_0     ORCALUT4     B        In      0.000     1.148 r     -         
+nRowColSel_0_0_a3_0     ORCALUT4     Z        Out     1.017     2.165 f     -         
+N_97                    Net          -        -       -         -           1         
+nRowColSel_0_0          ORCALUT4     B        In      0.000     2.165 f     -         
+nRowColSel_0_0          ORCALUT4     Z        Out     0.617     2.781 f     -         
+nRowColSel_0_0          Net          -        -       -         -           1         
+nRowColSel              FD1S3IX      D        In      0.000     2.781 f     -         
 ======================================================================================
 
 
@@ -1109,76 +1093,144 @@ Path information for path number 5:
     + Clock delay at ending point:           0.000 (ideal)
     = Required time:                         1.089
 
-    - Propagation time:                      2.837
+    - Propagation time:                      2.741
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.749
+    = Slack (non-critical) :                 -1.653
 
     Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCS_0io / D
+    Starting point:                          FWEr / Q
+    Ending point:                            RCKEEN / D
     The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
 
 Instance / Net                  Pin      Pin               Arrival     No. of    
 Name               Type         Name     Dir     Delay     Time        Fan Out(s)
 ---------------------------------------------------------------------------------
-CBR                FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                Net          -        -       -         -           7         
-nRCS_0io_RNO_0     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCS_0io_RNO_0     ORCALUT4     Z        Out     1.017     2.221 f     -         
-N_27_i_sn          Net          -        -       -         -           1         
-nRCS_0io_RNO       ORCALUT4     C        In      0.000     2.221 f     -         
-nRCS_0io_RNO       ORCALUT4     Z        Out     0.617     2.837 r     -         
-N_27_i             Net          -        -       -         -           1         
-nRCS_0io           OFS1P3BX     D        In      0.000     2.837 r     -         
+FWEr               FD1S3AX      Q        Out     1.108     1.108 r     -         
+FWEr               Net          -        -       -         -           3         
+RCKEEN_8_u_1_0     ORCALUT4     C        In      0.000     1.108 r     -         
+RCKEEN_8_u_1_0     ORCALUT4     Z        Out     1.017     2.125 r     -         
+RCKEEN_8_u_1_0     Net          -        -       -         -           1         
+RCKEEN_8_u         ORCALUT4     C        In      0.000     2.125 r     -         
+RCKEEN_8_u         ORCALUT4     Z        Out     0.617     2.741 r     -         
+RCKEEN_8           Net          -        -       -         -           1         
+RCKEEN             FD1S3AX      D        In      0.000     2.741 r     -         
 =================================================================================
 
 
 
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       15.472
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       15.472
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+             Starting                                             Required           
+Instance     Reference     Type        Pin     Net                Time         Slack 
+             Clock                                                                   
+-------------------------------------------------------------------------------------
+LEDEN        System        FD1P3AX     D       LEDEN_6_i_m2       16.089       15.472
+n8MEGEN      System        FD1P3AX     D       n8MEGEN_6_i_m2     16.089       15.472
+=====================================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      16.000
+    - Setup time:                            -0.089
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         16.089
+
+    - Propagation time:                      0.617
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 15.472
+
+    Number of logic level(s):                1
+    Starting point:                          ufmefb.EFBInst_0 / WBDATO0
+    Ending point:                            n8MEGEN / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
+
+Instance / Net                    Pin         Pin               Arrival     No. of    
+Name                 Type         Name        Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     EFB          WBDATO0     Out     0.000     0.000 r     -         
+wb_dato[0]           Net          -           -       -         -           1         
+n8MEGEN_6_i_m2       ORCALUT4     C           In      0.000     0.000 r     -         
+n8MEGEN_6_i_m2       ORCALUT4     Z           Out     0.617     0.617 r     -         
+n8MEGEN_6_i_m2       Net          -           -       -         -           1         
+n8MEGEN              FD1P3AX      D           In      0.000     0.617 r     -         
+======================================================================================
+
+
+
 ##### END OF TIMING REPORT #####]
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 193MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 193MB)
 
 ---------------------------------------
-Resource Usage Report
+Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 90 of 640 (14%)
+Register bits: 109 of 640 (17%)
 PIC Latch:       0
-I/O cells:       67
+I/O cells:       63
 
 
 Details:
 BB:             8
 CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
+EFB:            1
+FD1P3AX:        27
+FD1P3IX:        3
+FD1S3AX:        51
 FD1S3IX:        3
 GSR:            1
-IB:             26
+IB:             25
 IFS1P3DX:       9
-INV:            7
-OB:             33
+INV:            8
+OB:             30
 OFS1P3BX:       4
-OFS1P3DX:       12
+OFS1P3DX:       11
 OFS1P3JX:       1
-ORCALUT4:       135
+ORCALUT4:       206
 PFUMX:          1
 PUR:            1
-VHI:            1
-VLO:            1
+VHI:            2
+VLO:            2
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 193MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 22:34:24 2023
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Aug 16 20:59:35 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
new file mode 100644
index 0000000..d3b0487
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/LCMXO2_640HC_impl1_toc.htm
@@ -0,0 +1,60 @@
+  
+  
+    
+      
+   
+
+  
+   
+    
+
+   
+
+  
+ 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg
deleted file mode 100644
index 3b8cd49..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1.plg
+++ /dev/null
@@ -1,23 +0,0 @@
-@P:  Worst Slack : -2.389
-@P:  PHI2 - Estimated Frequency : 0.8 MHz
-@P:  PHI2 - Requested Frequency : 2.9 MHz
-@P:  PHI2 - Estimated Period : 1186.150
-@P:  PHI2 - Requested Period : 350.000
-@P:  PHI2 - Slack : -2.389
-@P:  RCLK - Estimated Frequency : 18.4 MHz
-@P:  RCLK - Requested Frequency : 62.5 MHz
-@P:  RCLK - Estimated Period : 54.224
-@P:  RCLK - Requested Period : 16.000
-@P:  RCLK - Slack : -0.784
-@P:  nCCAS - Estimated Frequency : NA
-@P:  nCCAS - Requested Frequency : 2.9 MHz
-@P:  nCCAS - Estimated Period : NA
-@P:  nCCAS - Requested Period : 350.000
-@P:  nCCAS - Slack : NA
-@P:  nCRAS - Estimated Frequency : 1.0 MHz
-@P:  nCRAS - Requested Frequency : 2.9 MHz
-@P:  nCRAS - Estimated Period : 987.210
-@P:  nCRAS - Requested Period : 350.000
-@P:  nCRAS - Slack : -1.821
-@P:  Total Area : 142.0
-@P:  CPU Time : 0h:00m:02s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm
deleted file mode 100644
index cf508f4..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_srr.htm
+++ /dev/null
@@ -1,983 +0,0 @@
-
      -
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEPC
-
-# Tue Aug 15 23:12:41 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
-Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
-Selecting top level module RAM2GS
-@N:CG364 : RAM2GS-SPI.v(1) | Synthesizing module RAM2GS in library work.
-Running optimization stage 1 on RAM2GS .......
-Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
-Running optimization stage 2 on RAM2GS .......
-Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
-
-For a summary of runtime and memory usage per design unit, please see file:
-==========================================================
-Linked File:  layer0.rt.csv
-
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-Linked File:  RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:41 2023
-
-###########################################################]
-
-
      
-
      -
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N: :  | Running in 64-bit mode 
-File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Aug 15 23:12:42 2023
-
-###########################################################]
-
-
      
-
      -
-# Tue Aug 15 23:12:42 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
-
-Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-Linked File:  RAM2GS_LCMXO2_640HC_impl1_scck.rpt
-See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-@N:FX493 :  | Applying initial value "0" on instance InitReady. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance Ready. 
-@N:FX493 :  | Applying initial value "0" on instance RCKE. 
-@N:FX493 :  | Applying initial value "1" on instance nRCAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdLEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance Cmdn8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRCS. 
-@N:FX493 :  | Applying initial value "0" on instance LEDEN. 
-@N:FX493 :  | Applying initial value "0" on instance n8MEGEN. 
-@N:FX493 :  | Applying initial value "1" on instance nRRAS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance CmdUFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance C1Submitted. 
-@N:FX493 :  | Applying initial value "0" on instance CmdSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance ADSubmitted. 
-@N:FX493 :  | Applying initial value "0" on instance XOR8MEG. 
-@N:FX493 :  | Applying initial value "1" on instance nUFMCS. 
-@N:FX493 :  | Applying initial value "0" on instance UFMSDI. 
-@N:FX493 :  | Applying initial value "0" on instance UFMCLK. 
-@N:FX493 :  | Applying initial value "0" on instance CmdEnable. 
-@N:FX493 :  | Applying initial value "1" on instance nRWE. 
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:FX1184 :  | Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS  
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock        Clock                Clock
-Level     Clock     Frequency     Period        Type         Group                Load 
----------------------------------------------------------------------------------------
-0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
-                                                                                       
-0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
-                                                                                       
-0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
-                                                                                       
-0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
-=======================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-RCLK      48        RCLK(port)      CASr2.C         -                 -                 
-                                                                                        
-PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
-                                                                                        
-nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
-                                                                                        
-nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-ClockId_0_0       RCLK                port                   48         nRWE           
-ClockId_0_1       PHI2                port                   19         RA11           
-ClockId_0_2       nCCAS               port                   8          WRD[7:0]       
-ClockId_0_3       nCRAS               port                   14         RowA[9:0]      
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Aug 15 23:12:44 2023
-
-###########################################################]
-
-
      
-
      -
-# Tue Aug 15 23:12:44 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEPC
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
-
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
-
-@N:MO231 : ram2gs-spi.v(147) | Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
-@N:MO231 : ram2gs-spi.v(134) | Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
-@N:FX493 :  | Applying initial value "0" on instance IS[0]. 
-@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
-@N:FX493 :  | Applying initial value "0" on instance IS[1]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[2]. 
-@N:FX493 :  | Applying initial value "0" on instance IS[3]. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    -2.34ns		 128 /        89
-   2		0h:00m:01s		    -2.34ns		 140 /        89
-   3		0h:00m:01s		    -2.34ns		 140 /        89
-@N:FX271 : ram2gs-spi.v(147) | Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   4		0h:00m:01s		    -2.04ns		 140 /        90
-
-
-   5		0h:00m:01s		    -2.04ns		 141 /        90
-   6		0h:00m:01s		    -2.04ns		 141 /        90
-   7		0h:00m:01s		    -2.04ns		 141 /        90
-   8		0h:00m:01s		    -2.04ns		 141 /        90
-   9		0h:00m:01s		    -2.04ns		 141 /        90
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)
-
-Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)
-
-@N:MT615 :  | Found clock RCLK with period 16.00ns  
-@N:MT615 :  | Found clock PHI2 with period 350.00ns  
-@N:MT615 :  | Found clock nCRAS with period 350.00ns  
-@N:MT615 :  | Found clock nCCAS with period 350.00ns  
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Tue Aug 15 23:12:47 2023
-#
-
-
-Top view:               RAM2GS
-Requested Frequency:    2.9 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -2.389
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
-RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
-nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
-nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-@W:MT118 :  | Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT118 :  | Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.   
-@W:MT116 :  | Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.   
-@W:MT117 :  | Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.   
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
---------------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
---------------------------------------------------------------------------------------------------------------
-RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
-RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
-RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
-PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
-PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
-nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
-==============================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PHI2
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                 Starting                                            Arrival            
-Instance         Reference     Type         Pin     Net              Time        Slack  
-                 Clock                                                                  
-----------------------------------------------------------------------------------------
-CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
-CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
-CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
-CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
-Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
-CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
-Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
-Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
-Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
-Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                Starting                                                Required            
-Instance        Reference     Type         Pin     Net                  Time         Slack  
-                Clock                                                                       
---------------------------------------------------------------------------------------------
-UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
-nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
-UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
-LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
-n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
-LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
-n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
-UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
-ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
-C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
-============================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         0.528
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -2.389
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMCLK_0io / SP
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
-UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
-i2_i                 Net          -        -       -         -           1         
-UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.917
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.829
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            nUFMCS / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                    Pin      Pin               Arrival     No. of    
-Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
-CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted         Net          -        -       -         -           4         
-PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i              Net          -        -       -         -           3         
-nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
-nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
-nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
-nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
-===================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.462
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.462
-
-    - Propagation time:                      3.214
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.751
-
-    Number of logic level(s):                2
-    Starting point:                          CmdSubmitted / Q
-    Ending point:                            UFMSDI / D
-    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
-CmdSubmitted        Net          -        -       -         -           4         
-PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
-PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
-N_141_i             Net          -        -       -         -           3         
-UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
-UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
-UFMSDI_RNO          Net          -        -       -         -           1         
-UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
-==================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: RCLK
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-               Starting                                         Arrival           
-Instance       Reference     Type        Pin     Net            Time        Slack 
-               Clock                                                              
-----------------------------------------------------------------------------------
-Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
-LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
-n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
-FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
-FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
-FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
-FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
-FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
-FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
-InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
-==================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                          Required           
-Instance       Reference     Type         Pin     Net            Time         Slack 
-               Clock                                                                
-------------------------------------------------------------------------------------
-RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
-RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
-RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
-RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
-RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
-RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
-RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
-RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
-RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
-RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
-====================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RBA_0io[0] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
-RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
-RBAd_0[0]          Net          -        -       -         -           1         
-RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[9] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
-RowAd_0[9]         Net          -        -       -         -           1         
-RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
-=================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      1.873
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.784
-
-    Number of logic level(s):                1
-    Starting point:                          Ready_fast / Q
-    Ending point:                            RowA[8] / D
-    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
-    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
-Ready_fast         Net          -        -       -         -           14        
-RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
-RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
-RowAd_0[8]         Net          -        -       -         -           1         
-RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: nCRAS
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                   Arrival           
-Instance     Reference     Type        Pin     Net      Time        Slack 
-             Clock                                                        
---------------------------------------------------------------------------
-CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
-FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
-==========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-               Starting                                              Required           
-Instance       Reference     Type         Pin     Net                Time         Slack 
-               Clock                                                                    
-----------------------------------------------------------------------------------------
-nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
-nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
-nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
-nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
-RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
-========================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
-nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
-N_179_i                   Net          -        -       -         -           1         
-nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
-========================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.909
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.821
-
-    Number of logic level(s):                2
-    Starting point:                          CBR / Q
-    Ending point:                            nRWE_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                         Pin      Pin               Arrival     No. of    
-Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
-CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
-CBR                       Net          -        -       -         -           7         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
-nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
-nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
-nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
-nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
-N_180_i                   Net          -        -       -         -           1         
-nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
-========================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      1.000
-    - Setup time:                            -0.089
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         1.089
-
-    - Propagation time:                      2.853
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -1.765
-
-    Number of logic level(s):                2
-    Starting point:                          FWEr / Q
-    Ending point:                            nRCAS_0io / D
-    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
-    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
-
-Instance / Net                       Pin      Pin               Arrival     No. of    
-Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
-FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
-FWEr                    Net          -        -       -         -           4         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
-nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
-N_27_i_1                Net          -        -       -         -           2         
-nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
-nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
-N_179_i                 Net          -        -       -         -           1         
-nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
-======================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 90 of 640 (14%)
-PIC Latch:       0
-I/O cells:       67
-
-
-Details:
-BB:             8
-CCU2D:          10
-FD1P3AX:        11
-FD1S3AX:        49
-FD1S3AY:        1
-FD1S3IX:        3
-GSR:            1
-IB:             26
-IFS1P3DX:       9
-INV:            7
-OB:             33
-OFS1P3BX:       4
-OFS1P3DX:       12
-OFS1P3JX:       1
-ORCALUT4:       135
-PFUMX:          1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Aug 15 23:12:47 2023
-
-###########################################################]
-
-
      
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm
deleted file mode 100644
index dd30c89..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/RAM2GS_LCMXO2_640HC_impl1_toc.htm
+++ /dev/null
@@ -1,58 +0,0 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
- 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
index 67c8bf4..b95cb8d 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_compiler.log
@@ -1,10 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v  -jobname  "compiler" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-SPI.v -jobname "compiler"
+C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -top  RAM2GS  -hdllog  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr  -encrypt  -mp  4  -verification_mode 0 -rtl_xmr_naming  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC  -I D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -I C:\lscc\diamond\3.12\synpbase\lib   -v2001  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -encrypt  -pro  -dmgen  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -D_MULTIPLE_FILE_COMPILATION_UNIT_  -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v -lib work -fv2001 D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v  -jobname  "compiler" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe -osyn ..\synwork\LCMXO2_640HC_impl1_comp.srs -top RAM2GS -hdllog ..\synlog\LCMXO2_640HC_impl1_compiler.srr -encrypt -mp 4 -verification_mode 0 -rtl_xmr_naming -verilog -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I ..\..\..\LCMXO2-640HC -I ..\ -I C:\lscc\diamond\3.12\synpbase\lib -v2001 -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -encrypt -pro -dmgen ..\dm -ui -fid2 -ram -sharing on -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work -fv2001 ..\..\..\RAM2GS-LCMXO2.v -lib work -fv2001 ..\..\REFB.v -jobname "compiler"
 rc:0 success:1 runtime:1
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs|io:o|time:1692155561|size:10463|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692155561|size:4591|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:o|time:1692233918|size:21157|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_compiler.srr|io:o|time:1692233969|size:6365|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
 file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
-file:..\..\..\RAM2GS-SPI.v|io:i|time:1692155394|size:11758|exec:0|csum:1D033D06BAC573F583D1480CDDD96F81
+file:..\..\..\RAM2GS-LCMXO2.v|io:i|time:1692233914|size:28573|exec:0|csum:28E8FB7DCCB7771914C4CAAAD23A3A6B
+file:.\-fv2001|io:i|time:0|size:-1|exec:0|csum:
+file:..\..\REFB.v|io:i|time:1692233522|size:5624|exec:0|csum:AE22D4C116724FF57C15D0DA14242382
 file:C:\lscc\diamond\3.12\synpbase\bin64\c_hdl.exe|io:i|time:1628601404|size:5754368|exec:1|csum:EF00E91BAA13FCD84C7D68B353143F73
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
index 9cc96e0..77a28d0 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_fpga_mapper.log
@@ -1,12 +1,12 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\RAM2GS_LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO2_640HC_impl1.edi -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO2_640HC_impl1.plg -osyn ..\RAM2GS_LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -flow mapping  -multisrs  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr  -sn  2021.03  -jobname  "fpga_mapper" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -flow mapping -multisrs -oedif ..\LCMXO2_640HC_impl1.edi -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\LCMXO2_640HC_impl1.srm -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr -sn 2021.03 -jobname "fpga_mapper"
 rc:1 success:1 runtime:3
-file:..\RAM2GS_LCMXO2_640HC_impl1.edi|io:o|time:1692155566|size:135533|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233975|size:204145|exec:0|csum:
 file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:i|time:1692155563|size:16785|exec:0|csum:E0DA21F06B7F0F84BB4B88EF6879699C
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:i|time:1692233971|size:28839|exec:0|csum:6AF572CB579AF7B57405A148BF7BEB9E
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO2_640HC_impl1.plg|io:o|time:1692155567|size:853|exec:0|csum:
-file:..\RAM2GS_LCMXO2_640HC_impl1.srm|io:o|time:1692155566|size:30417|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692155567|size:35619|exec:0|csum:
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692233975|size:1070|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.srm|io:o|time:1692233974|size:38081|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_fpga_mapper.srr|io:o|time:1692233975|size:50128|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
index b38047b..cf97934 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_multi_srs_gen.log
@@ -1,7 +1,7 @@
-C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr
+C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe  -link  -top  RAM2GS  -multisrs  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe -link -top RAM2GS -multisrs ..\synwork\LCMXO2_640HC_impl1_comp.srs -osyn ..\synwork\LCMXO2_640HC_impl1_mult.srs -log ..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr
 rc:0 success:1 runtime:0
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs|io:i|time:1692155561|size:10463|exec:0|csum:43BAA23EACACCD6D11E31E1651718DD7
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs|io:o|time:1692155562|size:10332|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692155562|size:1163|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_comp.srs|io:i|time:1692233918|size:21157|exec:0|csum:BB526DCCC65867AFD6AA24AF2B7D8510
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:o|time:1692233919|size:13269|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_multi_srs_gen.srr|io:o|time:1692233919|size:1156|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\syn_nfilter.exe|io:i|time:1628601758|size:8899584|exec:1|csum:163057E8B8449A642661642A20A2247D
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
index 3ea9f3a..736b297 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/cmdrec_premap.log
@@ -1,14 +1,14 @@
-C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -infer_seqShift  -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\RAM2GS_LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -ta_num_paths  3  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_cck.rpt   -freq 70.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\RAM2GS_LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
-relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -infer_seqShift -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\RAM2GS_LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -ta_num_paths 3 -oedif ..\RAM2GS_LCMXO2_640HC_impl1.edi -conchk_prepass ..\RAM2GS_LCMXO2_640HC_impl1_cck.rpt -freq 70.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam RAM2GS_LCMXO2_640HC_impl1.plg -osyn ..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
+C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1   -part LCMXO2_640HC  -package TG100C  -grade -4    -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0  -top_level_module  RAM2GS  -implementation  impl1  -oedif  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.edi  -conchk_prepass  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1_cck.rpt   -freq 100.000   -tcl  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v  -devicelib  C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v  -ologparam  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\syntmp\LCMXO2_640HC_impl1.plg  -osyn  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_prem.srd  -prjdir  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\  -prjname  proj_1  -log  D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_premap.srr  -sn  2021.03  -jobname  "premap" 
+relcom:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\impl1 -part LCMXO2_640HC -package TG100C -grade -4 -maxfan 1000 -pipe -infer_seqShift -forcenogsr -fixgatedclocks 1 -fixgeneratedclocks 1 -RWCheckOnRam 1 -gcc_allow_lat_combloops 0 -gcc_disable_clock_latches 0 -gcc_convert_lats_to_regs 0 -use_rename_in_edif 1 -Write_declared_clocks_only 1 -enable_gcc_in_premap -seqshift_no_replicate 0 -summaryfile ..\synlog\report\LCMXO2_640HC_impl1_premap.xml -merge_inferred_clocks 0 -top_level_module RAM2GS -implementation impl1 -oedif ..\LCMXO2_640HC_impl1.edi -conchk_prepass ..\LCMXO2_640HC_impl1_cck.rpt -freq 100.000 -tcl ..\..\..\RAM2GS.sdc ..\synwork\LCMXO2_640HC_impl1_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\LCMXO2_640HC_impl1_prem.srd -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v -devicelib C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v -ologparam LCMXO2_640HC_impl1.plg -osyn ..\synwork\LCMXO2_640HC_impl1_prem.srd -prjdir ..\ -prjname proj_1 -log ..\synlog\LCMXO2_640HC_impl1_premap.srr -sn 2021.03 -jobname "premap"
 rc:1 success:1 runtime:2
-file:..\RAM2GS_LCMXO2_640HC_impl1.edi|io:o|time:1692155404|size:135532|exec:0|csum:
-file:..\RAM2GS_LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692155564|size:4751|exec:0|csum:
+file:..\LCMXO2_640HC_impl1.edi|io:o|time:1692233923|size:210943|exec:0|csum:
+file:..\LCMXO2_640HC_impl1_cck.rpt|io:o|time:1692233972|size:4979|exec:0|csum:
 file:..\..\..\RAM2GS.sdc|io:i|time:1692153140|size:181|exec:0|csum:86E5121E7073876CE838886B655C290C
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_mult.srs|io:i|time:1692155562|size:10332|exec:0|csum:0BE029DC3BEEF698461F9E379A2ED022
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:o|time:1692155563|size:16785|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_mult.srs|io:i|time:1692233919|size:13269|exec:0|csum:9E33176D7D9CB39EFA557E27492465CA
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v|io:i|time:1628601068|size:54295|exec:0|csum:CFBBE5B6AB5A98F0C71C4E305509B0E3
 file:C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v|io:i|time:1628601068|size:40584|exec:0|csum:62845CEC2BB6FEBE1BA059B1E18015F4
-file:RAM2GS_LCMXO2_640HC_impl1.plg|io:o|time:1692155563|size:0|exec:0|csum:
-file:..\synwork\RAM2GS_LCMXO2_640HC_impl1_prem.srd|io:o|time:1692155563|size:16785|exec:0|csum:
-file:..\synlog\RAM2GS_LCMXO2_640HC_impl1_premap.srr|io:o|time:1692155564|size:8429|exec:0|csum:
+file:LCMXO2_640HC_impl1.plg|io:o|time:1692233970|size:0|exec:0|csum:
+file:..\synwork\LCMXO2_640HC_impl1_prem.srd|io:o|time:1692233971|size:28839|exec:0|csum:
+file:..\synlog\LCMXO2_640HC_impl1_premap.srr|io:o|time:1692233972|size:8565|exec:0|csum:
 file:C:\lscc\diamond\3.12\synpbase\bin64\m_gen_lattice.exe|io:i|time:1633636068|size:42036736|exec:1|csum:184AE1D82114F8176EA5D4186DC7E4B1
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg b/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg
deleted file mode 100644
index 3b8cd49..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1.plg
+++ /dev/null
@@ -1,23 +0,0 @@
-@P:  Worst Slack : -2.389
-@P:  PHI2 - Estimated Frequency : 0.8 MHz
-@P:  PHI2 - Requested Frequency : 2.9 MHz
-@P:  PHI2 - Estimated Period : 1186.150
-@P:  PHI2 - Requested Period : 350.000
-@P:  PHI2 - Slack : -2.389
-@P:  RCLK - Estimated Frequency : 18.4 MHz
-@P:  RCLK - Requested Frequency : 62.5 MHz
-@P:  RCLK - Estimated Period : 54.224
-@P:  RCLK - Requested Period : 16.000
-@P:  RCLK - Slack : -0.784
-@P:  nCCAS - Estimated Frequency : NA
-@P:  nCCAS - Requested Frequency : 2.9 MHz
-@P:  nCCAS - Estimated Period : NA
-@P:  nCCAS - Requested Period : 350.000
-@P:  nCCAS - Slack : NA
-@P:  nCRAS - Estimated Frequency : 1.0 MHz
-@P:  nCRAS - Requested Frequency : 2.9 MHz
-@P:  nCRAS - Estimated Period : 987.210
-@P:  nCRAS - Requested Period : 350.000
-@P:  nCRAS - Slack : -1.821
-@P:  Total Area : 142.0
-@P:  CPU Time : 0h:00m:02s
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm b/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm
deleted file mode 100644
index b6ef59b..0000000
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/impl1_toc.htm
+++ /dev/null
@@ -1,55 +0,0 @@
-  
-  
-    
-      
-   
-
-  
-   
-    
-
-   
-
-  
- 
\ No newline at end of file
diff --git a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
index 5f88a13..9175808 100644
--- a/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
+++ b/CPLD/LCMXO2-640HC/impl1/syntmp/statusReport.html
@@ -12,7 +12,7 @@
    Project Name  proj_1  Device Name  impl1: Lattice MachXO2 : LCMXO2_640HC 
   Implementation Name  impl1  Top Module  RAM2GS 
  		  
-		    Pipelining  0  Retiming  0 
+		    Pipelining  1  Retiming  0 
   Resource Sharing  1  Fanout Guide  1000 
   Disable I/O Insertion  0  Disable Sequential Optimizations  0 
   Clock Conversion  1  FSM Compiler  1 
@@ -34,40 +34,38 @@
          
   
    (compiler)Complete
- 4
+ 8
 0
 0
 -
 00m:00s
 -
-8/15/2023
      11:12:41 PM
+8/16/2023
      8:59:29 PM
  
 
  
    (premap)Complete
- 27
+ 23
  1
 0
 0m:01s
 0m:01s
-174MB
-8/15/2023
      11:12:44 PM
+175MB
+8/16/2023
      8:59:32 PM
  
 
  
    (fpga_mapper)Complete
- 19
- 6
+ 22
+ 7
 0
-0m:02s
-0m:02s
-184MB
-8/15/2023
      11:12:47 PM
+0m:03s
+0m:03s
+193MB
+8/16/2023
      8:59:35 PM
  
 
-
-  Multi-srs Generator
-  Complete8/15/2023
      11:12:42 PM 		
+ 		
      
  
       
  
@@ -75,8 +73,8 @@
  
-
-
+
+
+(total_luts)
       
       
       
         
   
      Register bits 90I/O cells 67Register bits 109I/O cells 63
 
      
 
       
 Block RAMs
@@ -86,7 +84,7 @@
 
      
 
       
 ORCA LUTs
-(total_luts) 135 206
 
       
       
     

      
@@ -96,10 +94,11 @@
   
  
    Clock NameReq FreqEst FreqSlack 
- PHI22.9 MHz0.8 MHz-2.389 
- RCLK62.5 MHz18.4 MHz-0.784 
+ PHI22.9 MHz1.0 MHz-1.832 
+ RCLK62.5 MHz22.1 MHz-0.784 
  nCCAS2.9 MHzNANA 
- nCRAS2.9 MHz1.0 MHz-1.821 
+ nCRAS2.9 MHz1.0 MHz-1.725 
+ System100.0 MHzNA15.472 
  
  
 
      
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer b/CPLD/LCMXO2-640HC/impl1/synwork/.cckTransfer
index 5aa3ef009922e39ca9db2d22f849bb1bbd30284b..5be0367a8d17ca95aac755314f30f037738728a8 100644
GIT binary patch
delta 433
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delta 433
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
new file mode 100644
index 0000000..68dc0e5
--- /dev/null
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
+#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
+0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work REFB 1
+module work RAM2GS 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
similarity index 100%
rename from CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv
rename to CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.rt.csv
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_comp.srs
new file mode 100644
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new file mode 100644
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literal 0
HcmV?d00001

diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_m_srm/fileinfo.srm
new file mode 100644
index 0000000000000000000000000000000000000000..f43e3da9c269911355e253ff983bc575e5b894d0
GIT binary patch
literal 328
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literal 0
HcmV?d00001

diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
similarity index 97%
rename from CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr
rename to CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
index 4fc0177..bf5564a 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/RAM2GS_LCMXO2_640HC_impl1_mult.gcr
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.gcr
@@ -1,12 +1,12 @@
 i RCLK
 m 0 0
-u 27 48
+u 30 65
 p {p:RCLK}{t:nRWE.C}
 e ckid0_0 {t:nRWE.C} dffs
 c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
 i PHI2
 m 0 0
-u 12 19
+u 11 18
 p {p:PHI2}{t:RA11.C}
 e ckid0_1 {t:RA11.C} sdffr
 c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_mult.srs
new file mode 100644
index 0000000000000000000000000000000000000000..e9279133688462e42dc52dc7c6191e6ec2c8efc4
GIT binary patch
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm b/CPLD/LCMXO2-640HC/impl1/synwork/LCMXO2_640HC_impl1_prem_srm/1.srm
new file mode 100644
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new file mode 100644
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep
deleted file mode 100644
index 841c519..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.fdep
+++ /dev/null
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-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\hypermods.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
-#CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692152477
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.rt.csv b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.rt.csv
deleted file mode 100644
index 915b7cd..0000000
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_comp.srs
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr
deleted file mode 100644
index 4fc0177..0000000
--- a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.gcr
+++ /dev/null
@@ -1,26 +0,0 @@
-i RCLK
-m 0 0
-u 27 48
-p {p:RCLK}{t:nRWE.C}
-e ckid0_0 {t:nRWE.C} dffs
-c ckid0_0 {p:RCLK} port Unsupported/too complex instance on clock path
-i PHI2
-m 0 0
-u 12 19
-p {p:PHI2}{t:RA11.C}
-e ckid0_1 {t:RA11.C} sdffr
-c ckid0_1 {p:PHI2} port Unsupported/too complex instance on clock path
-i nCCAS
-m 0 0
-u 1 8
-p {p:nCCAS}{t:CASr_2.I[0]}{t:CASr_2.OUT[0]}{t:WRD[7:0].C}
-e ckid0_2 {t:WRD[7:0].C} dff
-c ckid0_2 {p:nCCAS} port Unsupported/too complex instance on clock path
-i nCRAS
-m 0 0
-u 4 14
-p {p:nCRAS}{t:RASr_2.I[0]}{t:RASr_2.OUT[0]}{t:RowA[9:0].C}
-e ckid0_3 {t:RowA[9:0].C} sdffpatr
-c ckid0_3 {p:nCRAS} port Unsupported/too complex instance on clock path
-l 0 0 0 0 0 0
-r 0 0 0 0 0 0 0 0
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_mult.srs
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/fileinfo.srm
deleted file mode 100644
index 77da4e045c03310eddc1ffac52ce585dff5b0d1c..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm b/CPLD/LCMXO2-640HC/impl1/synwork/impl1_prem_srm/skeleton.srm
deleted file mode 100644
index da1f86c6cf082e5a9da3de51745e74e205da07ab..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 934
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diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
index 1b93d00..1a088e6 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/incr_compile.rpt
@@ -22,7 +22,7 @@ Modules that may have changed as a result of file changes: 0
 MID:  lib.cell.view
 
 *******************************************************************
-Unmodified files: 7
+Unmodified files: 8
 FID:  path (timestamp)
 0        C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v (2021-08-10 09:11:08)
 1        C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v (2021-08-10 09:11:08)
@@ -30,9 +30,11 @@ FID:  path (timestamp)
 3        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v (2021-08-10 09:07:02)
 4        C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh (2021-08-10 09:07:02)
 5        C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v (2021-08-10 09:07:02)
-6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v (2023-08-15 23:09:54)
+7        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v (2023-08-16 20:52:02)
+6        D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v (2023-08-16 20:58:34)
 
 *******************************************************************
-Unchanged modules: 1
+Unchanged modules: 2
 MID:  lib.cell.view
 0        work.RAM2GS.verilog
+1        work.REFB.verilog
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
index 77735f2..b5d3d64 100644
--- a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
+++ b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.fdep
@@ -1,4 +1,4 @@
-#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\RAM2GS_LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001"
+#OPTIONS:"|-layerid|0|-orig_srs|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\synwork\\LCMXO2_640HC_impl1_comp.srs|-top|RAM2GS|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC|-I|D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\impl1\\|-I|C:\\lscc\\diamond\\3.12\\synpbase\\lib|-v2001|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v|-devicelib|C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-fv2001|-lib|work|-fv2001"
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\bin64\\c_ver.exe":1628601508
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\machxo2.v":1628601068
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\lucent\\pmi_def.v":1628601068
@@ -6,13 +6,18 @@
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\umr_capim.v":1628600822
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_objects.v":1628600822
 #CUR:"C:\\lscc\\diamond\\3.12\\synpbase\\lib\\vlog\\scemi_pipes.svh":1628600822
-#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-SPI.v":1692155394
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\RAM2GS-LCMXO2.v":1692233914
+#CUR:"D:\\OneDrive\\Documents\\GitHub\\RAM2GS\\CPLD\\LCMXO2-640HC\\REFB.v":1692233522
 #numinternalfiles:6
 #defaultlanguage:verilog
-0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" verilog
+0			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-LCMXO2.v" verilog
+1			"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" verilog
 #Dependency Lists(Uses List)
-0 -1
+0 1
+1 -1
 #Dependency Lists(Users Of)
 0 -1
+1 0
 #Design Unit to File Association
 module work RAM2GS 0
+module work REFB 1
diff --git a/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs b/CPLD/LCMXO2-640HC/impl1/synwork/layer0.srs
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CBMMvq

delta 43
ycmZp0XmHrTBEZJT-@w4%u(42*e_}%{TOA|2cq9Mh23bqy-~i9b`(qH%6M)8dag}jVPlP~eMFe*+C=R41+JXxLpt_TMo
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z22oMz^8BJ~kSS%UMVUGI>62gB%WyICzhmJ4#s7u>-DW|D2mCxN%*>pOY%EMbl6~_p
He>MRCA-FoI

delta 148
zcmZoTz}Rqrae}m<90LOb8xX@l=tLc3M!Ag%g}jWalP~eMFse)r=R41+Hd&qjt`Iw4
zAOrsq{tkX0ejdIvd=vNrH!CVw^Re2pu`rZR=9SZ$Tr0=U864oLSC(?ej%o7*xm-cs
tJ2tm?fu=L^zhK~hu~{(S9{=PQ_A+dY{J$9Ze*yXL`575D|MF)O0022DCw~9{

diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
deleted file mode 100644
index 1c1a02c..0000000
--- a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
+++ /dev/null
@@ -1,250 +0,0 @@
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
-3	 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
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diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file
deleted file mode 100644
index 7e27975..0000000
--- a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file
+++ /dev/null
@@ -1,250 +0,0 @@
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-LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]"
-LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]"
-LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
-LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
-LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]"
-LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
-LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
-LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
-LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
-LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
-LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]"
-LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
-LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]"
-LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
diff --git a/CPLD/LCMXO2-640HC-old/msg_file.log b/CPLD/LCMXO2-640HC/msg_file.log
similarity index 69%
rename from CPLD/LCMXO2-640HC-old/msg_file.log
rename to CPLD/LCMXO2-640HC/msg_file.log
index e93ec92..6f835a7 100644
--- a/CPLD/LCMXO2-640HC-old/msg_file.log
+++ b/CPLD/LCMXO2-640HC/msg_file.log
@@ -1,5 +1,5 @@
-SCUBA, Version Diamond (64-bit) 3.12.0.240.2
-Tue Aug 17 05:48:29 2021
+SCUBA, Version Diamond (64-bit) 3.12.1.454
+Wed Aug 16 20:52:02 2023
   
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -9,20 +9,20 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
   
 BEGIN SCUBA Module Synthesis
   
-    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
-    Circuit name     : EFB
+    Issued command   : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 
+    Circuit name     : REFB
     Module type      : efb
     Module Version   : 1.2
     Ports            : 
     Inputs       : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
     Outputs      : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
     I/O buffer       : not inserted
-    EDIF output      : EFB.edn
-    Verilog output   : EFB.v
-    Verilog template : EFB_tmpl.v
+    EDIF output      : REFB.edn
+    Verilog output   : REFB.v
+    Verilog template : REFB_tmpl.v
     Verilog purpose  : for synthesis and simulation
     Bus notation     : big endian
-    Report output    : EFB.srp
+    Report output    : REFB.srp
     Estimated Resource Usage:
   
 END   SCUBA Module Synthesis
diff --git a/CPLD/RAM2GS-AGM.v b/CPLD/RAM2GS-AGM.v
new file mode 100644
index 0000000..0dc7503
--- /dev/null
+++ b/CPLD/RAM2GS-AGM.v
@@ -0,0 +1,425 @@
+module RAM2GS(PHI2, MAin, CROW, Din, Dout,
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML,
+              nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
+
+    /* 65816 Phase 2 Clock */
+    input PHI2;
+
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
+
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
+
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
+
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
+
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
+
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+
+    /* UFM Interface */
+    reg nUFMCS = 1;
+    reg UFMCLK = 0;
+    reg UFMSDI = 0;
+    wire UFMSDO;
+    wire UFMOsc;
+    alta_ufms u_alta_ufms (
+        .i_ufm_set (1'b1), 
+        .i_osc_ena (1'b1), 
+        .i_ufm_flash_csn (nUFMCS), 
+        .i_ufm_flash_sclk (UFMCLK), 
+        .i_ufm_flash_sdi (UFMSDI), 
+        .o_ufm_flash_sdo (UFMSDO), 
+        .o_osc (UFMOsc) 
+    );
+
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMCLK = 0;
+    reg CmdUFMSDI = 0;
+    reg CmdUFMCS = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
+
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
+
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
+
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
+
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
+
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // SPI (LCMXO, iCE40, AGM) commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMCS <= Din[2];
+                CmdUFMCLK <= Din[1];
+                CmdUFMSDI <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
+
+    /* UFM Control */
+    output nUFMCSout = nUFMCS;
+    output UFMCLKout = UFMCLK;
+    output UFMSDIout = UFMSDI;
+    output UFMSDOout = UFMSDO;
+    input [3:0] In;
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            case (FS[9:5]) // Shift out read data command (0x03)
+                5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
+                5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
+                5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
+                5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
+                5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
+                5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
+                5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
+                5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
+                5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
+                5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
+                5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
+                5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
+                5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
+                5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
+                5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
+                5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
+                5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
+                5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
+                5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
+                5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
+                5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
+                5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
+                5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
+                5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
+                5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
+                5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
+                5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
+                5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
+                5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
+                5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
+                5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
+                5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            UFMSDI <= 1'b0;
+            // Latch n8MEGEN and LEDEN
+            if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
+            if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
+        end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[1];
+            UFMSDI <= 1'b0;
+        end else if (~InitReady) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            nUFMCS <= ~CmdUFMCS;
+            UFMCLK <= CmdUFMCLK;
+            UFMSDI <= CmdUFMSDI;
+        end
+    end
+endmodule
diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/RAM2GS-LCMXO2.lpf
similarity index 93%
rename from CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
rename to CPLD/RAM2GS-LCMXO2.lpf
index dbcda5a..2e973f9 100644
--- a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
+++ b/CPLD/RAM2GS-LCMXO2.lpf
@@ -24,7 +24,6 @@ LOCATE COMP "MAin[6]" SITE "24" ;
 LOCATE COMP "MAin[7]" SITE "18" ;
 LOCATE COMP "MAin[8]" SITE "25" ;
 LOCATE COMP "MAin[9]" SITE "32" ;
-LOCATE COMP "UFMSDO" SITE "27" ;
 LOCATE COMP "nFWE" SITE "15" ;
 LOCATE COMP "Dout[0]" SITE "76" ;
 LOCATE COMP "Dout[1]" SITE "86" ;
@@ -52,8 +51,6 @@ LOCATE COMP "RBA[1]" SITE "60" ;
 LOCATE COMP "RCKE" SITE "53" ;
 LOCATE COMP "RDQMH" SITE "51" ;
 LOCATE COMP "RDQML" SITE "48" ;
-LOCATE COMP "UFMCLK" SITE "28" ;
-LOCATE COMP "UFMSDI" SITE "29" ;
 LOCATE COMP "nRCAS" SITE "52" ;
 LOCATE COMP "nRCS" SITE "57" ;
 LOCATE COMP "nRRAS" SITE "54" ;
@@ -90,7 +87,6 @@ IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
-IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
 IOBUF PORT "nFWE" IO_TYPE=LVCMOS33 PULLMODE=UP ;
 IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ;
 IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 DIFFRESISTOR=OFF SLEWRATE=SLOW ;
@@ -118,13 +114,10 @@ IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RCKE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RDQMH" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RDQML" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRCAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRRAS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
@@ -133,4 +126,3 @@ IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 SLEWRATE=SLOW ;
-LOCATE COMP "nUFMCS" SITE "30" ;
diff --git a/CPLD/RAM2GS-LCMXO2.v b/CPLD/RAM2GS-LCMXO2.v
index 48ace8c..e7f3953 100644
--- a/CPLD/RAM2GS-LCMXO2.v
+++ b/CPLD/RAM2GS-LCMXO2.v
@@ -1,731 +1,735 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = ~(~nCRAS &&  LEDEN);
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg CmdLEDEN = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdUFMData = 0;
-	reg CmdUFMShift = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	reg WriteDone;
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* UFM Interface */
+    reg wb_clk;
+    reg wb_rst;
+    reg wb_cyc_stb;
+    reg wb_we;
+    reg [7:0] wb_adr;
+    reg [7:0] wb_dati;
+	wire wb_ack;
+    wire [7:0] wb_dato;
+	wire ufm_irq;
+    REFB ufmefb (
+        .wb_clk_i(wb_clk),
+        .wb_rst_i(wb_rst),
+        .wb_cyc_i(wb_cyc_stb),
+        .wb_stb_i(wb_cyc_stb),
+        .wb_we_i(wb_we),
+        .wb_adr_i(wb_adr),
+        .wb_dat_i(wb_dati),
+        .wb_dat_o(wb_dato),
+        .wb_ack_o(wb_ack),
+		.wbc_ufm_irq(ufm_irq));
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMData = 0;
+    reg CMDUFMWrite = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0) begin
-				XOR8MEG <= Din[0];
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= ~Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-			end else if (Din[7:4]==4'h3 && Din[3]) begin
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMShift <= Din[1];
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
+
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // Reserved for SPI (LCMXO, iCE40) commands
+                // Din[2] - CS
+                // Din[1] - SCK
+                // Din[0] - SDI
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // LCMXO2 commands
+                // Din[1] - Shift when low, execute when high
+                // Din[0] - Shift data
+				CMDUFMWrite <= Din[1];
 				CmdUFMData <= Din[0];
-			end
-			CmdSubmitted <= 1;
-		end else CmdSubmitted <= 0;
-	end
-	
-	reg wb_clk;
-	reg wb_rst;
-	reg wb_cyc_stb;
-	reg wb_we;
-	reg [7:0] wb_adr;
-	reg [7:0] wb_dati;
-	wire [1:0] wb_dato;
-	
-	EFB ufmefb (
-		.WBCLKI(wb_clk),
-		.WBRSTI(wb_rst),
-		.WBCYCI(wb_cyc_stb),
-		.WBSTBI(wb_cyc_stb), 
-		.WBWEI(wb_we),
-		.WBADRI7(wb_adr[7]),
-		.WBADRI6(wb_adr[6]),
-		.WBADRI5(wb_adr[5]),
-		.WBADRI4(wb_adr[4]),
-		.WBADRI3(wb_adr[3]),
-		.WBADRI2(wb_adr[2]),
-		.WBADRI1(wb_adr[1]),
-		.WBADRI0(wb_adr[0]),
-		.WBDATI7(wb_dati[7]),
-		.WBDATI6(wb_dati[6]),
-		.WBDATI5(wb_dati[5]),
-		.WBDATI4(wb_dati[4]),
-		.WBDATI3(wb_dati[3]),
-		.WBDATI2(wb_dati[2]),
-		.WBDATI1(wb_dati[1]),
-		.WBDATI0(wb_dati[0]),
-		.WBDATO1(wb_dato[1]),
-		.WBDATO0(wb_dato[0]));
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdSubmitted <= 1'b1;
+            end
+        end
+    end
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			wb_clk <= 1'b0;
-			wb_rst <= ~FS[9];
-			wb_cyc_stb <= 1'b0;
-			wb_we <= 1'b0;
-			wb_adr[7:0] <= 8'h00;
-			wb_dati[7:0] <= 8'h00;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Enable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h74;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Enable configuration interface - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h08;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Enable configuration interface - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Enable configuration interface - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Poll status register - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h3C;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Poll status register - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Poll status register - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Poll status register - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Read status register 1/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h3C;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h06: begin // Read status register 2/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Read status register 3/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Read status register 4/4
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h73;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Set UFM address - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hB4;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Set UFM address - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Set UFM address - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Set UFM address - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Set UFM address - data 1/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h40;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h06: begin // Set UFM address - data 2/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Set UFM address - data 3/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Set UFM address - data 4/4
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h01;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h04) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Read UFM page - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hCA;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Read UFM page - operand 1/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h10;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Read UFM page - operand 2/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h04: begin // Read UFM page - operand 3/3
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h01;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h05: begin // Read UFM page - data 1/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-					
-					if (FS[4:0]==5'h0C) begin
-						LEDEN <= wb_dato[1];
-						n8MEGEN <= wb_dato[0];
-					end
-				end 5'h06: begin // Read UFM page - data 2/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h07: begin // Read UFM page - data 3/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h08: begin // Read UFM page - data 4/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h09: begin // Read UFM page - data 5/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0A: begin // Read UFM page - data 6/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0B: begin // Read UFM page - data 7/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0C: begin // Read UFM page - data 8/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0D: begin // Read UFM page - data 9/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0E: begin // Read UFM page - data 10/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h0F: begin // Read UFM page - data 11/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h10: begin // Read UFM page - data 12/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h11: begin // Read UFM page - data 13/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h12: begin // Read UFM page - data 14/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h13: begin // Read UFM page - data 15/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h14: begin // Read UFM page - data 16/16
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h05) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Disable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h26;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h02: begin // Disable configuration interface - operand 1/2
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h03: begin // Disable configuration interface - operand 2/2
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h06) begin
-			wb_clk <= FS[2];
-			wb_rst <= 1'b0;
-			case (FS[9:5])
-				5'h00: begin // Open frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h80;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h01: begin // Disable configuration interface - command
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h71;
-					wb_dati[7:0] <= 8'hFF;
-					wb_cyc_stb <= ~FS[4];
-				end 5'h1F: begin // Close frame
-					wb_we <= 1'b1;
-					wb_adr[7:0] <= 8'h70;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= ~FS[4];
-				end default: begin
-					wb_we <= 1'b0;
-					wb_adr[7:0] <= 8'h00;
-					wb_dati[7:0] <= 8'h00;
-					wb_cyc_stb <= 1'b0;
-				end
-			endcase
-		end else if (~InitReady) begin
-			wb_clk <= 1'b0;
-			wb_rst <= 1'b0;
-			wb_cyc_stb <= 1'b0;
-			wb_we <= 1'b0;
-			wb_adr[7:0] <= 8'h00;
-			wb_dati[7:0] <= 8'h00;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMShift, CmdUFMData
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			if (CmdUFMShift) begin
-				wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
-				wb_dati[7:0] <= { wb_dati[6:0], wb_we };
-				wb_we <= wb_cyc_stb;
-				wb_cyc_stb <= CmdUFMData;
-				wb_clk <= 1'b0;
-			end else wb_clk <= 1'b1;
-		end
-	end
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            wb_clk <= 1'b0;
+            wb_rst <= ~FS[9];
+            wb_cyc_stb <= 1'b0;
+            wb_we <= 1'b0;
+            wb_adr[7:0] <= 8'h00;
+            wb_dati[7:0] <= 8'h00;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Enable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h74;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Enable configuration interface - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h08;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Enable configuration interface - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Enable configuration interface - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Poll status register - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h3C;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Poll status register - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Poll status register - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Poll status register - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Read status register 1/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h3C;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h06: begin // Read status register 2/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Read status register 3/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Read status register 4/4
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h73;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Set UFM address - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hB4;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Set UFM address - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Set UFM address - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Set UFM address - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Set UFM address - data 1/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h40;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h06: begin // Set UFM address - data 2/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Set UFM address - data 3/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Set UFM address - data 4/4
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h01;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h04) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Read UFM page - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hCA;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Read UFM page - operand 1/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h10;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Read UFM page - operand 2/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h04: begin // Read UFM page - operand 3/3
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h01;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h05: begin // Read UFM page - data 1/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                    
+                    if (FS[4:0]==5'h0C) begin
+                        LEDEN <= wb_dato[1];
+                        n8MEGEN <= wb_dato[0];
+                    end
+                end 5'h06: begin // Read UFM page - data 2/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h07: begin // Read UFM page - data 3/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h08: begin // Read UFM page - data 4/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h09: begin // Read UFM page - data 5/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0A: begin // Read UFM page - data 6/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0B: begin // Read UFM page - data 7/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0C: begin // Read UFM page - data 8/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0D: begin // Read UFM page - data 9/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0E: begin // Read UFM page - data 10/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h0F: begin // Read UFM page - data 11/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h10: begin // Read UFM page - data 12/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h11: begin // Read UFM page - data 13/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h12: begin // Read UFM page - data 14/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h13: begin // Read UFM page - data 15/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h14: begin // Read UFM page - data 16/16
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h05) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Disable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h26;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h02: begin // Disable configuration interface - operand 1/2
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h03: begin // Disable configuration interface - operand 2/2
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h06) begin
+            wb_clk <= FS[2];
+            wb_rst <= 1'b0;
+            case (FS[9:5])
+                5'h00: begin // Open frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h80;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h01: begin // Disable configuration interface - command
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h71;
+                    wb_dati[7:0] <= 8'hFF;
+                    wb_cyc_stb <= ~FS[4];
+                end 5'h1F: begin // Close frame
+                    wb_we <= 1'b1;
+                    wb_adr[7:0] <= 8'h70;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= ~FS[4];
+                end default: begin
+                    wb_we <= 1'b0;
+                    wb_adr[7:0] <= 8'h00;
+                    wb_dati[7:0] <= 8'h00;
+                    wb_cyc_stb <= 1'b0;
+                end
+            endcase
+        end else if (~InitReady) begin
+            wb_clk <= 1'b0;
+            wb_rst <= 1'b0;
+            wb_cyc_stb <= 1'b0;
+            wb_we <= 1'b0;
+            wb_adr[7:0] <= 8'h00;
+            wb_dati[7:0] <= 8'h00;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            if (!CMDUFMWrite) begin
+                wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
+                wb_dati[7:0] <= { wb_dati[6:0], wb_we };
+                wb_we <= wb_cyc_stb;
+                wb_cyc_stb <= CmdUFMData;
+                wb_clk <= 1'b0;
+            end else wb_clk <= 1'b1;
+        end
+    end
 endmodule
diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v
index 6e97a29..c8693fb 100644
--- a/CPLD/RAM2GS-MAX.v
+++ b/CPLD/RAM2GS-MAX.v
@@ -1,470 +1,471 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* UFM Interface */
-	reg UFMD = 0; // UFM data register bit 15
-	reg ARCLK = 0; // UFM address register clock
-	// UFM address register data input tied to 0
-	reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
-	reg DRCLK = 0; // UFM data register clock
-	reg DRDIn = 0; // UFM data register input
-	reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
-	reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
-	reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
-	reg UFMOscEN = 0; // UFM oscillator enable
-	wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
-	wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
-	wire DRDOut; // UFM data output
-	// UFM oscillator always enabled
-	wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
-	UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
-		.arclk (ARCLK),
-		.ardin (1'b0),
-		.arshft (ARShift),
-		.drclk (DRCLK),
-		.drdin (DRDIn),
-		.drshft (DRShift),
-		.erase (UFMErase),
-		.oscena (UFMOscEN),
-		.program (UFMProgram),
-		.busy (UFMBusy),
-		.drdout (DRDOut),
-		.osc (UFMOsc),
-		.rtpbusy (RTPBusy));
-	reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
-	reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* UFM State */
-	reg UFMInitDone = 0; // 1 if UFM initialization finished
-	reg UFMReqErase = 0; // 1 if UFM requires erase
+    /* UFM Interface */
+    reg UFMD = 0; // UFM data register bit 15
+    reg ARCLK = 0; // UFM address register clock
+    // UFM address register data input tied to 0
+    reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
+    reg DRCLK = 0; // UFM data register clock
+    reg DRDIn = 0; // UFM data register input
+    reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
+    reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
+    reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
+    reg UFMOscEN = 0; // UFM oscillator enable
+    wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
+    wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
+    wire DRDOut; // UFM data output
+    // UFM oscillator always enabled
+    wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
+    UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
+        .arclk (ARCLK),
+        .ardin (1'b0),
+        .arshft (ARShift),
+        .drclk (DRCLK),
+        .drdin (DRDIn),
+        .drshft (DRShift),
+        .erase (UFMErase),
+        .oscena (UFMOscEN),
+        .program (UFMProgram),
+        .busy (UFMBusy),
+        .drdout (DRDOut),
+        .osc (UFMOsc),
+        .rtpbusy (RTPBusy));
+    reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
+    reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdDRCLK = 0;
-	reg CmdDRDIn = 0;
-	reg CmdUFMErase = 0; // Set by user command. Programs UFM
-	reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* UFM State */
+    reg UFMInitDone = 0; // 1 if UFM initialization finished
+    reg UFMReqErase = 0; // 1 if UFM requires erase
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdDRCLK = 0;
+    reg CmdDRDIn = 0;
+    reg CmdUFMErase = 0; // Set by user command. Programs UFM
+    reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// MAX commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMErase <= Din[3];
-				CmdUFMPrgm <= Din[2];
-				CmdDRCLK <= Din[1];
-				CmdDRDIn <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// Reserved for SPI (LCMXO, iCE40) commands
-				// Din[2] - CS
-				// Din[1] - SCK
-				// Din[0] - SDI
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+                UFMOscEN <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+                UFMOscEN <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~Ready) begin
-			if (~UFMInitDone & FS[17:16]==2'b00) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
-				// Parallel transfer UFM data to shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // Parallel transfer to data register
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// Capture bit 15 of this UFM word in UFMD register
-				if (FS[3:0]==4'h7) UFMD <= DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// If valid setting here, set capacity setting to UFMD[14]
-				if (FS[3:0]==4'h7 && ~UFMD) n8MEGEN <= ~DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
-				if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
-				else begin // If valid setting here
-					LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
-					// If last byte in sector, mark need to erase
-					if (FS[15:8]==8'hFF) begin
-						UFMReqErase <= 1'b1; // Mark need to wrap around
-						UFMInitDone <= 1'b1; // Quit iterating
-					end
-				end
-				
-				// Increment UFM address
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b0; // Increment UFM address
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (FS[17:16]==2'b10 & UFMReqErase) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else begin
-				// Don't do anything with UFM
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // MAX commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMErase <= Din[3];
+                CmdUFMPrgm <= Din[2];
+                CmdDRCLK <= Din[1];
+                CmdDRDIn <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // Reserved for SPI (LCMXO, iCE40) commands
+                // Din[2] - CS
+                // Din[1] - SCK
+                // Din[0] - SDI
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
 
-			// Don't erase or program UFM during initialization 
-			UFMErase <= 1'b0;
-			UFMProgram <= 1'b0;
-		end else begin
-			// Can only shift UFM data register now
-			ARCLK <= 1'b0;
-			ARShift <= 1'b0;
-			DRShift <= 1'b1;
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~Ready) begin
+            if (~UFMInitDone & FS[17:16]==2'b00) begin
+                // Shift 0 into address register
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b1; // Shift 0 into address register
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
+                // Parallel transfer UFM data to shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // Parallel transfer to data register
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
+                // Shift UFM data shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b1; // Shift data register
+                // Capture bit 15 of this UFM word in UFMD register
+                if (FS[3:0]==4'h7) UFMD <= DRDOut;
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
+                // Shift UFM data shift register
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= FS[3]; // Clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b1; // Shift data register
+                // If valid setting here, set capacity setting to UFMD[14]
+                if (FS[3:0]==4'h7 && ~UFMD) n8MEGEN <= ~DRDOut;
+            end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
+                if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
+                else begin // If valid setting here
+                    LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
+                    // If last byte in sector, mark need to erase
+                    if (FS[15:8]==8'hFF) begin
+                        UFMReqErase <= 1'b1; // Mark need to wrap around
+                        UFMInitDone <= 1'b1; // Quit iterating
+                    end
+                end
+                
+                // Increment UFM address
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b0; // Increment UFM address
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else if (FS[17:16]==2'b10 & UFMReqErase) begin
+                // Shift 0 into address register
+                ARCLK <= FS[3]; // Clock address register
+                ARShift <= 1'b1; // Shift 0 into address register
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end else begin
+                // Don't do anything with UFM
+                ARCLK <= 1'b0; // Don't clock address register
+                ARShift <= 1'b0; // ARShift is don't care
+                DRCLK <= 1'b0; // Don't clock data register
+                DRDIn <= 1'b0; // DRDIn is don't care
+                DRShift <= 1'b0; // DRShift is don't care
+            end
 
-			// Set user command signals after PHI2 falls
-			if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-				LEDEN <= CmdLEDEN;
-				n8MEGEN <= Cmdn8MEGEN;
-				DRCLK <= CmdDRCLK;
-				DRDIn <= CmdDRDIn;
-			end
+            // Don't erase or program UFM during initialization 
+            UFMErase <= 1'b0;
+            UFMProgram <= 1'b0;
+        end else begin
+            // Can only shift UFM data register now
+            ARCLK <= 1'b0;
+            ARShift <= 1'b0;
+            DRShift <= 1'b1;
 
-			// UFM programming sequence
-			if (CmdUFMPrgm | CmdUFMErase) begin
-				if (~UFMBusyReg & ~RTPBusyReg) begin
-					if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
-					else if (CmdUFMPrgm) UFMProgram <= 1'b1;
-				end else if (UFMBusyReg) UFMReqErase <= 1'b0;
-			end
-		end
-	end
+            // Set user command signals after PHI2 falls
+            if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+                LEDEN <= CmdLEDEN;
+                n8MEGEN <= Cmdn8MEGEN;
+                DRCLK <= CmdDRCLK;
+                DRDIn <= CmdDRDIn;
+            end
+
+            // UFM programming sequence
+            if (CmdUFMPrgm | CmdUFMErase) begin
+                if (~UFMBusyReg & ~RTPBusyReg) begin
+                    if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
+                    else if (CmdUFMPrgm) UFMProgram <= 1'b1;
+                end else if (UFMBusyReg) UFMReqErase <= 1'b0;
+            end
+        end
+    end
 endmodule
diff --git a/CPLD/RAM2GS-SPI.v b/CPLD/RAM2GS-SPI.v
index d885e6d..1aa4a9f 100644
--- a/CPLD/RAM2GS-SPI.v
+++ b/CPLD/RAM2GS-SPI.v
@@ -1,411 +1,410 @@
 module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCS, UFMCLK, UFMSDI, UFMSDO);
+              nCCAS, nCRAS, nFWE, LED,
+              RBA, RA, RD, nRCS, RCLK, RCKE,
+              nRWE, nRRAS, nRCAS, RDQMH, RDQML,
+              nUFMCS, UFMCLK, UFMSDI, UFMSDO);
 
-	/* 65816 Phase 2 Clock */
-	input PHI2;
+    /* 65816 Phase 2 Clock */
+    input PHI2;
 
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
+    /* Async. DRAM Control Inputs */
+    input nCCAS, nCRAS;
 
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
+    /* Synchronized PHI2 and DRAM signals */
+    reg PHI2r, PHI2r2, PHI2r3;
+    reg RASr, RASr2, RASr3;
+    reg CASr, CASr2, CASr3;
+    reg FWEr;
+    reg CBR;
 
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
+    /* Activity LED */
+    reg LEDEN = 0;
+    output LED;
+    assign LED = !(!nCRAS && !CBR && LEDEN);
 
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
+    /* 65816 Data */
+    input [7:0] Din;
+    output [7:0] Dout;
+    assign Dout[7:0] = RD[7:0];
 
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
+    /* Latched 65816 Bank Address */
+    reg [7:0] Bank;
 
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+    /* Async. DRAM Address Bus */
+    input [1:0] CROW;
+    input [9:0] MAin;
+    input nFWE;
+    reg n8MEGEN = 0;
+    reg XOR8MEG = 0;
+    
+    /* SDRAM Clock */
+    input RCLK;
+    
+    /* SDRAM */
+    reg RCKEEN;
+    output reg RCKE = 0;
+    output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+    output reg [1:0] RBA;
+    reg nRowColSel;
+    reg RA11;
+    reg RA10;
+    reg [9:0] RowA;
+    output [11:0] RA;
+    assign RA[11] = RA11;
+    assign RA[10] = RA10;
+    assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+    output RDQML, RDQMH;
+    assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+    assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
+    reg [7:0] WRD;
+    inout [7:0] RD;
+    assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
 
-	/* UFM Interface */
-	output reg nUFMCS = 1;
-	output reg UFMCLK = 0;
-	output reg UFMSDI = 0;
-	input UFMSDO;
+    /* UFM Interface */
+    output reg nUFMCS = 1;
+    output reg UFMCLK = 0;
+    output reg UFMSDI = 0;
+    input UFMSDO;
 
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
+    /* UFM Command Interface */
+    reg C1Submitted = 0;
+    reg ADSubmitted = 0;
+    reg CmdEnable = 0;
+    reg CmdSubmitted = 0;
+    reg Cmdn8MEGEN = 0;
+    reg CmdLEDEN = 0;
+    reg CmdUFMCLK = 0;
+    reg CmdUFMSDI = 0;
+    reg CmdUFMCS = 0;
+    wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+    wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+    wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+    
+    /* State Counters */
+    reg InitReady = 0; // 1 if ready for init sequence
+    reg Ready = 0; // 1 if done with init sequence
+    reg [1:0] S = 0; // post-RAS State counter
+    reg [17:0] FS = 0; // Fast init state counter
+    reg [3:0] IS = 0; // Init state counter
+    
+    /* Synchronize PHI2, RAS, CAS */
+    always @(posedge RCLK) begin
+        PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+        RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+        CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+    end
+    
+    /* Latch 65816 bank when PHI2 rises */
+    always @(posedge PHI2) begin
+        if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+        else RA11 <= 1'b0; // Reserved in mode register
+        Bank[7:0] <= Din[7:0]; // Latch bank
+    end
+    
+    /* Latch bank address, row address, WE, and CAS when RAS falls */
+    always @(negedge nCRAS) begin
+        if (Ready) begin
+            RBA[1:0] <= CROW[1:0];
+            RowA[9:0] <= MAin[9:0];
+        end else begin
+            RBA[1:0] <= 2'b00;      // Reserved in mode register
+            RowA[9] <= 1'b1;        // "1" for single write mode
+            RowA[8] <= 1'b0;        // Reserved
+            RowA[7] <= 1'b0;        // "0" for not test mode
+            RowA[6:4] <= 3'b010;    // "2" for CAS latency 2
+            RowA[3] <= 1'b0;        // "0" for sequential burst (not used)
+            RowA[2:0] <= 3'b000;    // "0" for burst length 1 (no burst)
+        end
+        FWEr <= ~nFWE;
+        CBR <= ~nCCAS;
+    end
 
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
+    /* Latch write data when CAS falls */
+    always @(negedge nCCAS) begin
+        WRD[7:0] <= Din[7:0];
+    end
 
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
+    /* State counter from RAS */
+    always @(posedge RCLK) begin
+        if (~RASr2) S <= 0;
+        else if (S==2'h3) S <= 2'h3;
+        else S <= S+2'h1;
+    end
+    /* Init state counter */
+    always @(posedge RCLK) begin
+        // Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+        FS <= FS+18'h1;
+        if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+    end
 
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
+    /* SDRAM CKE */
+    always @(posedge RCLK) begin
+        // Only 1 LUT4 allowed for this function!
+        RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+    end
 
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
+    /* SDRAM command */
+    always @(posedge RCLK) begin
+        if (Ready) begin
+            if (S==0) begin
+                if (RASr2) begin
+                    if (CBR) begin
+                        // AREF
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b0;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // RA10 is don't care
+                    end else begin
+                        // ACT
+                        nRCS <= 1'b0;
+                        nRRAS <= 1'b0;
+                        nRCAS <= 1'b1;
+                        nRWE <= 1'b1;
+                        RA10 <= 1'b1; // Bank RA10 consistently "1"
+                    end
+                    // Enable clock only for reads
+                    RCKEEN <= ~CBR & ~FWEr;
+                end else if (RCKE) begin
+                    // PCall
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                    RCKEEN <= 1'b1;
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                    RCKEEN <= 1'b1;
+                end
+                nRowColSel <= 1'b0; // Select registered row addres
+            end else if (S==1) begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR; // Disable clock if refresh cycle
+            end else if (S==2) begin
+                if (~FWEr & ~CBR) begin
+                    // RD
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= 1'b1; // Select asynchronous column address
+                RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+            end else if (S==3) begin
+                if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+                    // WR
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // Auto-precharge
+                end else begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                nRowColSel <= ~(~FWEr | CASr3 | CBR);
+                RCKEEN <= ~(~FWEr | CASr2 | CBR);
+            end
+        end else if (InitReady) begin
+            if (S==0 & RASr2) begin
+                if (IS==0) begin
+                    // NOP
+                    nRCS <= 1'b1;
+                    nRRAS <= 1'b1;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end else if (IS==1) begin
+                    // PC all
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b1;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b1; // "all"
+                end else if (IS==9) begin
+                    // Load mode register
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b0;
+                    RA10 <= 1'b0; // Reserved in mode register
+                end else begin
+                    // AREF
+                    nRCS <= 1'b0;
+                    nRRAS <= 1'b0;
+                    nRCAS <= 1'b0;
+                    nRWE <= 1'b1;
+                    RA10 <= 1'b1; // RA10 is don't care
+                end
+                IS <= IS+4'h1;
+            end else begin
+                // NOP
+                nRCS <= 1'b1;
+                nRRAS <= 1'b1;
+                nRCAS <= 1'b1;
+                nRWE <= 1'b1;
+                RA10 <= 1'b1; // RA10 is don't care
+            end
+            if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b1;
+        end else begin
+            // NOP
+            nRCS <= 1'b1;
+            nRRAS <= 1'b1;
+            nRCAS <= 1'b1;
+            nRWE <= 1'b1;
+            RA10 <= 1'b1; // RA10 is don't care
+            nRowColSel <= 1'b0; // Select registered row address
+            RCKEEN <= 1'b0;
+        end
+    end
+    
+    /* Submit command when PHI2 falls */
+    always @(negedge PHI2) begin
+        // Magic number check
+        if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+            if (ADSubmitted) begin
+                CmdEnable <= 1'b1;
+            end
+            C1Submitted <= 1'b1;
+            ADSubmitted <= 1'b0;
+        end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+            if (C1Submitted) begin
+                CmdEnable <= 1'b1;
+            end
+            ADSubmitted <= 1'b1;
+            C1Submitted <= 1'b0;
+        end else if (C1WR | ADWR) begin // wrong magic number submitted
+            CmdEnable <= 1'b0;
+            C1Submitted <= 1'b0;
+            ADSubmitted <= 1'b0;
+        end else if (CMDWR) CmdEnable <= 1'b0;
 
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// Reserved for MAX commands
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// SPI (LCMXO, iCE40, AGM) commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
+        // Submit command
+        if (CMDWR & CmdEnable) begin
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
+            // if (Din[7:4]==4'h0) begin // MAX w/o LED
+            if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
+            // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
+                XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
+            end else if (Din[7:4]==4'h0) begin // Unsupported type 
+                XOR8MEG <= 0;
+            end else if (Din[7:4]==4'h1) begin
+                CmdLEDEN <= Din[1];
+                Cmdn8MEGEN <= ~Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h2) begin
+                // Reserved for MAX commands
+            end else if (Din[7:4]==4'h3 && !Din[3]) begin
+                // SPI (LCMXO, iCE40, AGM) commands
+                CmdLEDEN <= LEDEN;
+                Cmdn8MEGEN <= n8MEGEN;
+                CmdUFMCS <= Din[2];
+                CmdUFMCLK <= Din[1];
+                CmdUFMSDI <= Din[0];
+                CmdSubmitted <= 1'b1;
+            end else if (Din[7:4]==4'h3 &&  Din[3]) begin
+                // Reserved for LCMXO2 commands
+                // Din[1] - Shift when high, execute when low
+                // Din[0] - Shift data
+            end
+        end
+    end
 
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN and LEDEN
-			if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
-			if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
+    /* UFM Control */
+    always @(posedge RCLK) begin
+        if (~InitReady && FS[17:10]==8'h00) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h01) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~InitReady && FS[17:10]==8'h02) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            case (FS[9:5]) // Shift out read data command (0x03)
+                5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
+                5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
+                5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
+                5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
+                5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
+                5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
+                5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
+                5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
+                5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
+                5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
+                5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
+                5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
+                5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
+                5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
+                5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
+                5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
+                5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
+                5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
+                5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
+                5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
+                5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
+                5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
+                5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
+                5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
+                5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
+                5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
+                5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
+                5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
+                5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
+                5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
+                5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
+                5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
+            endcase
+        end else if (~InitReady && FS[17:10]==8'h03) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[4];
+            UFMSDI <= 1'b0;
+            // Latch n8MEGEN and LEDEN
+            if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
+            if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
+        end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+            nUFMCS <= 1'b0;
+            UFMCLK <= FS[1];
+            UFMSDI <= 1'b0;
+        end else if (~InitReady) begin
+            nUFMCS <= 1'b1;
+            UFMCLK <= 1'b0;
+            UFMSDI <= 1'b0;
+        end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+            // Set user command signals after PHI2 falls
+            LEDEN <= CmdLEDEN;
+            n8MEGEN <= Cmdn8MEGEN;
+            nUFMCS <= ~CmdUFMCS;
+            UFMCLK <= CmdUFMCLK;
+            UFMSDI <= CmdUFMSDI;
+        end
+    end
 endmodule
diff --git a/CPLD/RAM4GS-AGM.v b/CPLD/RAM4GS-AGM.v
deleted file mode 100644
index 19ba8e5..0000000
--- a/CPLD/RAM4GS-AGM.v
+++ /dev/null
@@ -1,426 +0,0 @@
-module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
-
-	/* 65816 Phase 2 Clock */
-	input PHI2;
-
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
-
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
-
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = !(!nCRAS && !CBR && LEDEN);
-
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
-
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
-
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD;
-	assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
-
-	/* UFM Interface */
-	reg nUFMCS = 1;
-	reg UFMCLK = 0;
-	reg UFMSDI = 0;
-	wire UFMSDO;
-	wire UFMOsc;
-	alta_ufms u_alta_ufms (
-		.i_ufm_set (1'b1), 
-		.i_osc_ena (1'b1), 
-		.i_ufm_flash_csn (nUFMCS), 
-		.i_ufm_flash_sclk (UFMCLK), 
-		.i_ufm_flash_sdi (UFMSDI), 
-		.o_ufm_flash_sdo (UFMSDO), 
-		.o_osc (UFMOsc) 
-	);
-
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdLEDEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
-
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
-
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+2'h1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+18'h1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
-
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
-
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+4'h1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
-
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED 
-			// if (Din[7:4]==4'h0) begin // MAX w/o LED
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
-			// if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
-				XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
-			end else if (Din[7:4]==4'h0) begin // Unsupported type 
-				XOR8MEG <= 0;
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// Reserved for MAX commands
-			end else if (Din[7:4]==4'h3 && !Din[3]) begin
-				// SPI (LCMXO, iCE40, AGM) commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 &&  Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end
-		end
-	end
-
-	/* UFM Control */
-	output nUFMCSout = nUFMCS;
-	output UFMCLKout = UFMCLK;
-	output UFMSDIout = UFMSDI;
-	output UFMSDOout = UFMSDO;
-	input [3:0] In;
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN and LEDEN
-			if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO;
-			if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
-endmodule