diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index 82f9818..69d8d37 100644 Binary files a/CPLD/MAXII/RAM2GS.qws and b/CPLD/MAXII/RAM2GS.qws differ diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt index d6796ed..e2d7300 100644 --- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Fri Sep 29 15:18:00 2023 +Sat Sep 30 04:44:05 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof + 5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Sep 29 15:18:00 2023 ; +; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+---------------------------------------------------------------------------+ -; Assembler Generated Files ; -+---------------------------------------------------------------------------+ -; File Name ; -+---------------------------------------------------------------------------+ -; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; -+---------------------------------------------------------------------------+ ++--------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------+ +; File Name ; ++--------------------------------------------------+ +; /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++--------------------------------------------------+ -+-----------------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; -+----------------+------------------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+------------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00171B9B ; -; Checksum ; 0x00171E13 ; -+----------------+------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------+ +; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++----------------+-----------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------+ +; JTAG usercode ; 0x00171B9B ; +; Checksum ; 0x00171E13 ; ++----------------+-----------------------------------------------------------+ +--------------------+ @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:18:00 2023 + Info: Processing started: Sat Sep 30 04:44:04 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 534 megabytes - Info: Processing ended: Fri Sep 29 15:18:00 2023 - Info: Elapsed time: 00:00:00 + Info: Peak virtual memory: 13095 megabytes + Info: Processing ended: Sat Sep 30 04:44:05 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done index e5867da..27c4db7 100644 --- a/CPLD/MAXII/output_files/RAM2GS.done +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -1 +1 @@ -Fri Sep 29 15:18:03 2023 +Sat Sep 30 04:44:09 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt index 04526bc..cebdd9c 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Fri Sep 29 15:17:59 2023 +Sat Sep 30 04:44:02 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Fri Sep 29 15:17:59 2023 ; +; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -128,7 +128,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.04 ; @@ -137,14 +137,14 @@ https://fpgasoftware.intel.com/eula. ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 1.5% ; -; Processors 3-4 ; 1.4% ; +; Processors 3-4 ; 1.2% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin. +The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin. +---------------------------------------------------------------------+ @@ -710,50 +710,50 @@ Info (332111): Found 6 clocks Info (332111): 350.000 PHI2 Info (332111): 16.000 RCLK Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 -Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 - Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 -Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "LED~0" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 - Info (186217): Destination "RASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 -Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 -Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "CBR" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 - Info (186217): Destination "RD~16" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 - Info (186217): Destination "CASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 -Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 +Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 + Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 +Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 + Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 +Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 + Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 + Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 +Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 20% of the available device resources Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.54 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 1156 megabytes - Info: Processing ended: Fri Sep 29 15:17:59 2023 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:03 + Info: Peak virtual memory: 13771 megabytes + Info: Processing ended: Sat Sep 30 04:44:02 2023 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg. +The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary index 5341ad2..455e016 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Fri Sep 29 15:17:59 2023 +Fitter Status : Successful - Sat Sep 30 04:44:02 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index 1a06689..656020a 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Fri Sep 29 15:18:02 2023 +Sat Sep 30 04:44:08 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Fri Sep 29 15:18:00 2023 ; +; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,25 +60,25 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/29/2023 15:17:44 ; +; Start date & time ; 09/30/2023 04:43:31 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 123745752457129.169601506401636 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ ++-----------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 121381084694.169606341108100 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +--------------------------------------------------------------------------------------------------------------------------+ @@ -86,24 +86,24 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 562 MB ; 00:00:30 ; -; Fitter ; 00:00:03 ; 1.0 ; 1156 MB ; 00:00:03 ; -; Assembler ; 00:00:00 ; 1.0 ; 534 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ; -; Total ; 00:00:15 ; -- ; -- ; 00:00:35 ; +; Analysis & Synthesis ; 00:00:26 ; 1.0 ; 13133 MB ; 00:00:44 ; +; Fitter ; 00:00:05 ; 1.0 ; 13771 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 13095 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:01 ; +; Total ; 00:00:34 ; -- ; -- ; 00:00:50 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -+-----------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Fitter ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Assembler ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Timing Analyzer ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -+----------------------+------------------+-----------+------------+----------------+ ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ ------------ diff --git a/CPLD/MAXII/output_files/RAM2GS.jdi b/CPLD/MAXII/output_files/RAM2GS.jdi index bb8cafe..c51e41b 100644 --- a/CPLD/MAXII/output_files/RAM2GS.jdi +++ b/CPLD/MAXII/output_files/RAM2GS.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index d637389..a61e3c4 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Fri Sep 29 15:17:55 2023 +Sat Sep 30 04:43:56 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Sep 29 15:17:55 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:56 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,7 +135,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; @@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+ -; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v ; ; -; ../RAM2GS.mif ; yes ; User Memory Initialization File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ; -+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v ; ; +; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+ +-----------------------------------------------------+ @@ -269,42 +269,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:17:44 2023 + Info: Processing started: Sat Sep 30 04:43:30 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file /users/gwolf/documents/github/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM2GS File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_unv File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 150 + Info (12023): Found entity 1: UFM_altufm_none_unv File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 150 Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 -Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 201 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 +Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 201 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 196 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings - Info: Peak virtual memory: 562 megabytes - Info: Processing ended: Fri Sep 29 15:17:55 2023 - Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:30 + Info: Peak virtual memory: 13133 megabytes + Info: Processing ended: Sat Sep 30 04:43:56 2023 + Info: Elapsed time: 00:00:26 + Info: Total CPU time (on all processors): 00:00:44 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg. +The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM2GS.map.smsg b/CPLD/MAXII/output_files/RAM2GS.map.smsg index bc53a71..af9ed7c 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.smsg +++ b/CPLD/MAXII/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 173 +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 173 diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index 62c9067..4140741 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Fri Sep 29 15:17:55 2023 +Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:56 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt index 4609677..171193f 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Fri Sep 29 15:18:02 2023 +Sat Sep 30 04:44:08 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -80,7 +80,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; @@ -88,7 +88,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 0.1% ; +----------------------------+-------------+ @@ -97,8 +97,8 @@ https://fpgasoftware.intel.com/eula. +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ -; ../RAM2GS.sdc ; OK ; Fri Sep 29 15:18:02 2023 ; -; ../RAM2GS-MAX.sdc ; OK ; Fri Sep 29 15:18:02 2023 ; +; ../RAM2GS.sdc ; OK ; Sat Sep 30 04:44:07 2023 ; +; ../RAM2GS-MAX.sdc ; OK ; Sat Sep 30 04:44:07 2023 ; +-------------------+--------+--------------------------+ @@ -601,12 +601,12 @@ No paths to report. ; 1.334 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.903 ; ; 1.640 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.861 ; ; 1.659 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ; -; 1.663 ; UFMBusyReg0 ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.884 ; +; 1.663 ; UFMBusyReg ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.884 ; ; 1.685 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.906 ; ; 1.738 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.959 ; ; 1.745 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.966 ; ; 1.783 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.004 ; -; 1.915 ; RTPBusyReg0 ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.136 ; +; 1.915 ; RTPBusyReg ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.136 ; ; 1.935 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.156 ; ; 1.950 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.171 ; ; 2.035 ; CmdUFMPrgmSync ; UFMProgStart ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.256 ; @@ -959,7 +959,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:18:01 2023 + Info: Processing started: Sat Sep 30 04:44:06 2023 Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -1003,9 +1003,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 533 megabytes - Info: Processing ended: Fri Sep 29 15:18:02 2023 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 13092 megabytes + Info: Processing ended: Sat Sep 30 04:44:08 2023 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws index 3b10519..69d8d37 100644 Binary files a/CPLD/MAXV/RAM2GS.qws and b/CPLD/MAXV/RAM2GS.qws differ diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt index aba7159..398b713 100644 --- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Fri Sep 29 15:17:55 2023 +Sat Sep 30 04:44:05 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof + 5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Sep 29 15:17:55 2023 ; +; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+--------------------------------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------------------------------+ -; File Name ; -+--------------------------------------------------------------------------+ -; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; -+--------------------------------------------------------------------------+ ++-------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------+ +; File Name ; ++-------------------------------------------------+ +; /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; ++-------------------------------------------------+ -+----------------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; -+----------------+-----------------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00172723 ; -; Checksum ; 0x00172A9B ; -+----------------+-----------------------------------------------------------------------------------+ ++---------------------------------------------------------------------------+ +; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ; ++----------------+----------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------+ +; JTAG usercode ; 0x00172723 ; +; Checksum ; 0x00172A9B ; ++----------------+----------------------------------------------------------+ +--------------------+ @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:17:55 2023 + Info: Processing started: Sat Sep 30 04:44:04 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 534 megabytes - Info: Processing ended: Fri Sep 29 15:17:55 2023 - Info: Elapsed time: 00:00:00 + Info: Peak virtual memory: 13096 megabytes + Info: Processing ended: Sat Sep 30 04:44:05 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done index 6fcbf0d..27c4db7 100644 --- a/CPLD/MAXV/output_files/RAM2GS.done +++ b/CPLD/MAXV/output_files/RAM2GS.done @@ -1 +1 @@ -Fri Sep 29 15:17:58 2023 +Sat Sep 30 04:44:09 2023 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt index f5d808a..c4f7acb 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Fri Sep 29 15:17:53 2023 +Sat Sep 30 04:44:02 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Fri Sep 29 15:17:53 2023 ; +; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -128,23 +128,23 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.03 ; +; Average used ; 1.04 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.3% ; -; Processors 3-4 ; 1.1% ; +; Processor 2 ; 1.7% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin. +The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin. +---------------------------------------------------------------------+ @@ -711,25 +711,25 @@ Info (332111): Found 6 clocks Info (332111): 350.000 PHI2 Info (332111): 16.000 RCLK Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 -Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 - Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 -Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "LED~0" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 - Info (186217): Destination "RASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 -Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 -Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 - Info (186217): Destination "CBR" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 - Info (186217): Destination "RD~16" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 - Info (186217): Destination "CASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 -Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41 +Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 + Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 +Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8 +Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22 + Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 +Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 +Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 + Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18 + Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60 + Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16 +Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -742,19 +742,19 @@ Info (170195): Router estimated average interconnect usage is 19% of the availab Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.40 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 1157 megabytes - Info: Processing ended: Fri Sep 29 15:17:54 2023 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:03 + Info: Peak virtual memory: 13772 megabytes + Info: Processing ended: Sat Sep 30 04:44:02 2023 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg. +The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg. diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary index 0e275c3..32f8976 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Fri Sep 29 15:17:53 2023 +Fitter Status : Successful - Sat Sep 30 04:44:02 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt index 61fe953..cbdab27 100644 --- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Fri Sep 29 15:17:58 2023 +Sat Sep 30 04:44:08 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Fri Sep 29 15:17:55 2023 ; +; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,25 +60,25 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/29/2023 15:17:39 ; +; Start date & time ; 09/30/2023 04:43:33 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 123745752457129.169601505901700 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+---------------------------------------+---------------------------------+---------------+-------------+------------+ ++-----------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 121381084694.169606341306136 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++---------------------------------------+------------------------------+---------------+-------------+------------+ +--------------------------------------------------------------------------------------------------------------------------+ @@ -86,24 +86,24 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 560 MB ; 00:00:28 ; -; Fitter ; 00:00:02 ; 1.0 ; 1157 MB ; 00:00:03 ; -; Assembler ; 00:00:00 ; 1.0 ; 534 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 533 MB ; 00:00:01 ; -; Total ; 00:00:15 ; -- ; -- ; 00:00:33 ; +; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13138 MB ; 00:00:41 ; +; Fitter ; 00:00:04 ; 1.0 ; 13772 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:02 ; +; Total ; 00:00:32 ; -- ; -- ; 00:00:48 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -+-----------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Fitter ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Assembler ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -; Timing Analyzer ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ; -+----------------------+------------------+-----------+------------+----------------+ ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ ------------ diff --git a/CPLD/MAXV/output_files/RAM2GS.jdi b/CPLD/MAXV/output_files/RAM2GS.jdi index c0fe1f4..23099fd 100644 --- a/CPLD/MAXV/output_files/RAM2GS.jdi +++ b/CPLD/MAXV/output_files/RAM2GS.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 7c2488d..19bfaa7 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Fri Sep 29 15:17:50 2023 +Sat Sep 30 04:43:57 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Sep 29 15:17:50 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:57 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,7 +135,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; @@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+ -; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ; -; ../RAM2GS.mif ; yes ; User Memory Initialization File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ; -+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v ; ; +; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ; ++----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+ +-----------------------------------------------------+ @@ -269,42 +269,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:17:39 2023 + Info: Processing started: Sat Sep 30 04:43:32 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file /users/gwolf/documents/github/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM2GS File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v + Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_38r File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 150 + Info (12023): Found entity 1: UFM_altufm_none_38r File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150 Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 -Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 201 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 +Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 196 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg +Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings - Info: Peak virtual memory: 560 megabytes - Info: Processing ended: Fri Sep 29 15:17:50 2023 - Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:28 + Info: Peak virtual memory: 13138 megabytes + Info: Processing ended: Sat Sep 30 04:43:57 2023 + Info: Elapsed time: 00:00:25 + Info: Total CPU time (on all processors): 00:00:41 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg. +The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXV/output_files/RAM2GS.map.smsg b/CPLD/MAXV/output_files/RAM2GS.map.smsg index 03562c6..2a02712 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.smsg +++ b/CPLD/MAXV/output_files/RAM2GS.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 173 +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 173 diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index a49e62f..abbdfbe 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Fri Sep 29 15:17:50 2023 +Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:57 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt index df87966..c3b0165 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Fri Sep 29 15:17:58 2023 +Sat Sep 30 04:44:08 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition @@ -80,14 +80,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 8 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 1 ; +; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -96,8 +97,8 @@ https://fpgasoftware.intel.com/eula. +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ -; ../RAM2GS.sdc ; OK ; Fri Sep 29 15:17:58 2023 ; -; ../RAM2GS-MAX.sdc ; OK ; Fri Sep 29 15:17:58 2023 ; +; ../RAM2GS.sdc ; OK ; Sat Sep 30 04:44:08 2023 ; +; ../RAM2GS-MAX.sdc ; OK ; Sat Sep 30 04:44:08 2023 ; +-------------------+--------+--------------------------+ @@ -601,11 +602,11 @@ No paths to report. ; 3.126 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -1.000 ; 4.946 ; 7.111 ; ; 3.230 ; nCRAS ; RASr ; nCRAS ; RCLK ; -1.000 ; 4.946 ; 7.215 ; ; 3.325 ; nCCAS ; CASr ; nCCAS ; RCLK ; -1.000 ; 4.946 ; 7.310 ; -; 3.351 ; RTPBusyReg0 ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.390 ; +; 3.351 ; RTPBusyReg ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.390 ; ; 3.374 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.413 ; ; 3.375 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.414 ; ; 3.741 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.780 ; -; 3.755 ; UFMBusyReg0 ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.794 ; +; 3.755 ; UFMBusyReg ; UFMRTPBusy ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.794 ; ; 3.768 ; UFMProgStart ; UFMProgStart ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.807 ; ; 3.800 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.839 ; ; 3.856 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.895 ; @@ -958,7 +959,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Fri Sep 29 15:17:56 2023 + Info: Processing started: Sat Sep 30 04:44:06 2023 Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -1002,9 +1003,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 533 megabytes - Info: Processing ended: Fri Sep 29 15:17:58 2023 + Info: Peak virtual memory: 13092 megabytes + Info: Processing ended: Sat Sep 30 04:44:08 2023 Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v index 258fe3c..a99c5c4 100644 --- a/CPLD/RAM2GS-MAX.v +++ b/CPLD/RAM2GS-MAX.v @@ -18,7 +18,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg CBR; /* Activity LED */ - reg LEDEN = 0; + reg LEDEN; output LED; assign LED = !(!nCRAS && !CBR && LEDEN && Ready); @@ -91,11 +91,11 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, .osc (UFMOsc), .rtpbusy (RTPBusyAsync)); // UFMBusy registered to sync with RCLK - reg UFMBusyReg0; always @(posedge RCLK) UFMBusyReg0 <= UFMBusyAsync; + reg UFMBusyReg; always @(posedge RCLK) UFMBusyReg <= UFMBusyAsync; // RTPBusy registered to sync with RCLK - reg RTPBusyReg0; always @(posedge RCLK) RTPBusyReg0 <= RTPBusyAsync; + reg RTPBusyReg; always @(posedge RCLK) RTPBusyReg <= RTPBusyAsync; // UFMRTPBusy ORs both - reg UFMRTPBusy; always @(posedge RCLK) UFMRTPBusy <= UFMBusyReg0 || RTPBusyReg0; + reg UFMRTPBusy; always @(posedge RCLK) UFMRTPBusy <= UFMBusyReg || RTPBusyReg; /* UFM State */ reg UFMInitDone = 0; // 1 if UFM initialization finished diff --git a/Documentation/GW4201DManual.pdf b/Documentation/GW4201DManual.pdf index 704e57c..d5b1321 100644 Binary files a/Documentation/GW4201DManual.pdf and b/Documentation/GW4201DManual.pdf differ