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RAM2GS
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Renamed AGM "in" signals

This commit is contained in:
Zane Kaminski 2021-04-29 19:25:30 -04:00
parent a9a06f5e5e
commit c4537afbb5
1 changed files with 2 additions and 6 deletions
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8
Hardware/src/RAM4GS-AGM.v
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@ -2,8 +2,7 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
nCCAS, nCRAS, nFWE,
RBA, RA, RD, nRCS, RCLK, RCKE,
nRWE, nRRAS, nRCAS, RDQMH, RDQML,
nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout,
nUFMCSin , UFMCLKin , UFMSDIin , UFMSDOin);
nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
/* 65816 Phase 2 Clock */
input PHI2;
@ -330,10 +329,7 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
output UFMCLKout = UFMCLK;
output UFMSDIout = UFMSDI;
output UFMSDOout = UFMSDO;
input nUFMCSin;
input UFMCLKin;
input UFMSDIin;
input UFMSDOin;
input [3:0] In;
always @(posedge RCLK) begin
if (~InitReady && FS[17:10]==8'h00) begin
nUFMCS <= 1'b1;