diff --git a/CPLD/MAXII/RAM2GS.mif b/CPLD/MAXII/RAM2GS.mif
new file mode 100644
index 0000000..3382c37
--- /dev/null
+++ b/CPLD/MAXII/RAM2GS.mif
@@ -0,0 +1,28 @@
+-- Copyright (C) 2019 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and any partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors. Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=512;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+ [000..0FD] : 0000;
+ 0FE : 5FFF;
+ [0FF..1FF] : FFFF;
+END;
diff --git a/CPLD/MAXII/RAM2GS.qsf b/CPLD/MAXII/RAM2GS.qsf
index 842c6cf..0e12cff 100644
--- a/CPLD/MAXII/RAM2GS.qsf
+++ b/CPLD/MAXII/RAM2GS.qsf
@@ -196,4 +196,5 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_global_assignment -name MIF_FILE ../RAM2GS.mif
set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
-set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
+set_global_assignment -name QIP_FILE UFM.qip
+set_location_assignment PIN_88 -to LED
\ No newline at end of file
diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws
index 5f2429b..5479d55 100644
Binary files a/CPLD/MAXII/RAM2GS.qws and b/CPLD/MAXII/RAM2GS.qws differ
diff --git a/CPLD/MAXII/UFM.v b/CPLD/MAXII/UFM.v
index 8096959..9f27eeb 100644
--- a/CPLD/MAXII/UFM.v
+++ b/CPLD/MAXII/UFM.v
@@ -34,7 +34,7 @@
//https://fpgasoftware.intel.com/eula.
-//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
+//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
@@ -44,7 +44,7 @@
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
-module UFM_altufm_none_var
+module UFM_altufm_none_unv
(
arclk,
ardin,
@@ -118,7 +118,7 @@ module UFM_altufm_none_var
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
- maxii_ufm_block1.init_file = "../RAM2GS.mif",
+ maxii_ufm_block1.init_file = "RAM2GS.mif",
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
@@ -140,11 +140,7 @@ module UFM_altufm_none_var
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
- initial/*synthesis enable_verilog_initial_construct*/
- begin
- $display("Warning: Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results.");
- end
-endmodule //UFM_altufm_none_var
+endmodule //UFM_altufm_none_unv
//VALID FILE
@@ -189,7 +185,7 @@ module UFM (
wire osc = sub_wire2;
wire rtpbusy = sub_wire3;
- UFM_altufm_none_var UFM_altufm_none_var_component (
+ UFM_altufm_none_unv UFM_altufm_none_unv_component (
.arclk (arclk),
.ardin (ardin),
.arshft (arshft),
@@ -213,7 +209,7 @@ endmodule
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
-// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS.mif"
+// Retrieval info: CONSTANT: LPM_FILE STRING "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\MAXII\RAM2GS.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb
index 0b131c1..aca770c 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb
index eaacf84..25c2cf9 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb
index 404b33c..1aff5d6 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb and b/CPLD/MAXII/db/RAM2GS.(1).cnf.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb
index 14a0d5d..67484ba 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb and b/CPLD/MAXII/db/RAM2GS.(1).cnf.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.(2).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(2).cnf.cdb
index fdc79d1..91f21a8 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(2).cnf.cdb and b/CPLD/MAXII/db/RAM2GS.(2).cnf.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb
index d26758f..e3dc552 100644
Binary files a/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb and b/CPLD/MAXII/db/RAM2GS.(2).cnf.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAXII/db/RAM2GS.asm.qmsg
index e0bef24..148265f 100644
--- a/CPLD/MAXII/db/RAM2GS.asm.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.asm.qmsg
@@ -1,7 +1,7 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880867195 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880867211 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:54:27 2023 " "Processing started: Sat Aug 12 18:54:27 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880867211 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691880867211 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691880867211 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691880867430 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691880867445 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691880867445 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4661 " "Peak virtual memory: 4661 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880867555 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:54:27 2023 " "Processing ended: Sat Aug 12 18:54:27 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880867555 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880867555 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880867555 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691880867555 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903574998 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903575014 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:54 2023 " "Processing started: Sun Aug 13 01:12:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903575014 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903575014 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903575014 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903575264 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903575279 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903575279 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:55 2023 " "Processing ended: Sun Aug 13 01:12:55 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903575389 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903575389 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAXII/db/RAM2GS.asm.rdb
index 3278723..5113c0c 100644
Binary files a/CPLD/MAXII/db/RAM2GS.asm.rdb and b/CPLD/MAXII/db/RAM2GS.asm.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb
index 6963aba..8be3571 100644
Binary files a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb differ
diff --git a/CPLD/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAXII/db/RAM2GS.cmp.cdb
index f7969fd..fd4e838 100644
Binary files a/CPLD/MAXII/db/RAM2GS.cmp.cdb and b/CPLD/MAXII/db/RAM2GS.cmp.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.cmp.hdb b/CPLD/MAXII/db/RAM2GS.cmp.hdb
index 8d39cea..731d24c 100644
Binary files a/CPLD/MAXII/db/RAM2GS.cmp.hdb and b/CPLD/MAXII/db/RAM2GS.cmp.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.cmp.idb b/CPLD/MAXII/db/RAM2GS.cmp.idb
index cb11c64..556ea78 100644
Binary files a/CPLD/MAXII/db/RAM2GS.cmp.idb and b/CPLD/MAXII/db/RAM2GS.cmp.idb differ
diff --git a/CPLD/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAXII/db/RAM2GS.cmp.rdb
index d719add..47adcb3 100644
Binary files a/CPLD/MAXII/db/RAM2GS.cmp.rdb and b/CPLD/MAXII/db/RAM2GS.cmp.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAXII/db/RAM2GS.cmp0.ddb
index fbb4d60..e321716 100644
Binary files a/CPLD/MAXII/db/RAM2GS.cmp0.ddb and b/CPLD/MAXII/db/RAM2GS.cmp0.ddb differ
diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info
index 5384081..844e3c3 100644
--- a/CPLD/MAXII/db/RAM2GS.db_info
+++ b/CPLD/MAXII/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Version_Index = 503488000
-Creation_Time = Sat Aug 12 19:09:26 2023
+Creation_Time = Sun Aug 13 01:07:41 2023
diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg
index 5e1d42d..9c62ca4 100644
--- a/CPLD/MAXII/db/RAM2GS.fit.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg
@@ -1,45 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691880865039 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691880865039 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691880865039 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880865086 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880865086 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691880865101 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691880865117 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691880865211 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691880865258 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880865258 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 331 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 333 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 332 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691880865274 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691880865289 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691880865320 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691880865320 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691880865320 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691880865320 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865336 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691880865336 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691880865414 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865524 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691880865524 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691880865820 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865820 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691880865852 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691880865961 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691880865961 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691880866086 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691880866086 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880866086 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691880866102 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880866102 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691880866133 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691880866164 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5346 " "Peak virtual memory: 5346 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:54:26 2023 " "Processing ended: Sat Aug 12 18:54:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691880866180 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903572781 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903572781 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903572781 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903572812 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903572812 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903572827 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903572843 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903572952 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903572952 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903572999 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903572999 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903572999 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903573015 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903573015 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903573031 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903573046 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903573046 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903573046 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903573046 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573077 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903573093 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903573171 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573265 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903573265 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903573588 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573588 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903573603 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903573713 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903573713 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903573873 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903573873 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573873 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903573873 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903573889 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903573904 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903573935 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5346 " "Peak virtual memory: 5346 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:53 2023 " "Processing ended: Sun Aug 13 01:12:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903573967 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903573967 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info
index d12e6b0..df04f0e 100644
--- a/CPLD/MAXII/db/RAM2GS.hier_info
+++ b/CPLD/MAXII/db/RAM2GS.hier_info
@@ -15,6 +15,7 @@ PHI2 => CmdUFMPrgm.CLK
PHI2 => CmdUFMErase.CLK
PHI2 => CmdSubmitted.CLK
PHI2 => Cmdn8MEGEN.CLK
+PHI2 => CmdLEDEN.CLK
PHI2 => XOR8MEG.CLK
PHI2 => ADSubmitted.CLK
PHI2 => C1Submitted.CLK
@@ -63,9 +64,9 @@ MAin[7] => Equal3.IN0
MAin[8] => RA.DATAA
MAin[8] => RowA.DATAB
MAin[9] => RA.DATAA
-MAin[9] => comb.DATAA
+MAin[9] => RDQMH.DATAA
MAin[9] => RowA.DATAB
-MAin[9] => comb.DATAA
+MAin[9] => RDQML.DATAA
CROW[0] => RBA.DATAB
CROW[1] => RBA.DATAB
Din[0] => CmdDRDIn.DATAB
@@ -80,45 +81,49 @@ Din[1] => WRD[1].DATAIN
Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
+Din[1] => Equal17.IN2
+Din[1] => CmdLEDEN.DATAB
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN
Din[2] => Equal14.IN6
Din[2] => Equal15.IN3
+Din[2] => Equal17.IN1
Din[3] => CmdUFMErase.DATAB
Din[3] => WRD[3].DATAIN
Din[3] => Bank[3].DATAIN
Din[3] => Equal14.IN5
Din[3] => Equal15.IN2
+Din[3] => Equal17.IN0
Din[4] => WRD[4].DATAIN
Din[4] => Bank[4].DATAIN
Din[4] => Equal14.IN4
Din[4] => Equal15.IN6
Din[4] => Equal16.IN3
-Din[4] => Equal17.IN0
-Din[4] => Equal18.IN3
+Din[4] => Equal18.IN0
+Din[4] => Equal19.IN3
Din[5] => WRD[5].DATAIN
Din[5] => Bank[5].DATAIN
Din[5] => Equal14.IN3
Din[5] => Equal15.IN1
Din[5] => Equal16.IN2
-Din[5] => Equal17.IN3
-Din[5] => Equal18.IN0
+Din[5] => Equal18.IN3
+Din[5] => Equal19.IN0
Din[6] => RA11.IN1
Din[6] => WRD[6].DATAIN
Din[6] => Bank[6].DATAIN
Din[6] => Equal14.IN1
Din[6] => Equal15.IN5
Din[6] => Equal16.IN1
-Din[6] => Equal17.IN2
Din[6] => Equal18.IN2
+Din[6] => Equal19.IN2
Din[7] => WRD[7].DATAIN
Din[7] => Bank[7].DATAIN
Din[7] => Equal14.IN0
Din[7] => Equal15.IN0
Din[7] => Equal16.IN0
-Din[7] => Equal17.IN1
Din[7] => Equal18.IN1
+Din[7] => Equal19.IN1
Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE
@@ -152,12 +157,14 @@ nCRAS => RowA[8].CLK
nCRAS => RowA[9].CLK
nCRAS => RBA[0]~reg0.CLK
nCRAS => RBA[1]~reg0.CLK
+nCRAS => LED.IN1
nCRAS => RASr.DATAIN
nFWE => comb.IN1
nFWE => CMDWR.IN1
nFWE => ADWR.IN1
nFWE => C1WR.IN1
nFWE => FWEr.DATAIN
+LED << LED.DB_MAX_OUTPUT_PORT_TYPE
RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE
@@ -184,8 +191,9 @@ nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
-RCLK => n8MEGEN.CLK
+RCLK => LEDEN.CLK
RCLK => UFMInitDone.CLK
+RCLK => n8MEGEN.CLK
RCLK => UFMD.CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
@@ -239,8 +247,8 @@ RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RDQMH << comb.DB_MAX_OUTPUT_PORT_TYPE
-RDQML << comb.DB_MAX_OUTPUT_PORT_TYPE
+RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE
+RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE
|RAM2GS|UFM:UFM_inst
@@ -253,13 +261,13 @@ drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
-busy <= UFM_altufm_none_var:UFM_altufm_none_var_component.busy
-drdout <= UFM_altufm_none_var:UFM_altufm_none_var_component.drdout
-osc <= UFM_altufm_none_var:UFM_altufm_none_var_component.osc
-rtpbusy <= UFM_altufm_none_var:UFM_altufm_none_var_component.rtpbusy
+busy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.busy
+drdout <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.drdout
+osc <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.osc
+rtpbusy <= UFM_altufm_none_unv:UFM_altufm_none_unv_component.rtpbusy
-|RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component
+|RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif
index 5c82f05..392ade2 100644
Binary files a/CPLD/MAXII/db/RAM2GS.hif and b/CPLD/MAXII/db/RAM2GS.hif differ
diff --git a/CPLD/MAXII/db/RAM2GS.lpc.html b/CPLD/MAXII/db/RAM2GS.lpc.html
index 0cdbcc5..f7c4e12 100644
--- a/CPLD/MAXII/db/RAM2GS.lpc.html
+++ b/CPLD/MAXII/db/RAM2GS.lpc.html
@@ -16,7 +16,7 @@
| Output only Bidir |
-| UFM_inst|UFM_altufm_none_var_component |
+UFM_inst|UFM_altufm_none_unv_component |
9 |
0 |
0 |
diff --git a/CPLD/MAXII/db/RAM2GS.lpc.rdb b/CPLD/MAXII/db/RAM2GS.lpc.rdb
index 6d3ed54..039dc62 100644
Binary files a/CPLD/MAXII/db/RAM2GS.lpc.rdb and b/CPLD/MAXII/db/RAM2GS.lpc.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.lpc.txt b/CPLD/MAXII/db/RAM2GS.lpc.txt
index e8e0dd8..e3e31f1 100644
--- a/CPLD/MAXII/db/RAM2GS.lpc.txt
+++ b/CPLD/MAXII/db/RAM2GS.lpc.txt
@@ -3,6 +3,6 @@
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_var_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; UFM_inst|UFM_altufm_none_unv_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 4 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD/MAXII/db/RAM2GS.map.cdb b/CPLD/MAXII/db/RAM2GS.map.cdb
index 2cb427e..b684441 100644
Binary files a/CPLD/MAXII/db/RAM2GS.map.cdb and b/CPLD/MAXII/db/RAM2GS.map.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.map.hdb b/CPLD/MAXII/db/RAM2GS.map.hdb
index 2cf92e3..7bf8462 100644
Binary files a/CPLD/MAXII/db/RAM2GS.map.hdb and b/CPLD/MAXII/db/RAM2GS.map.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.map.qmsg b/CPLD/MAXII/db/RAM2GS.map.qmsg
index a7c7c05..09dc277 100644
--- a/CPLD/MAXII/db/RAM2GS.map.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.map.qmsg
@@ -1,28 +1,27 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880854989 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880854989 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:54:14 2023 " "Processing started: Sat Aug 12 18:54:14 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880854989 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880854989 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880854989 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691880855322 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691880855322 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(52) " "Verilog HDL warning at RAM2GS-MAX.v(52): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691880863242 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880863242 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880863242 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880863273 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880863273 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_var " "Found entity 1: UFM_altufm_none_var" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880863273 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880863273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880863273 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691880863305 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(154) " "Verilog HDL assignment warning at RAM2GS-MAX.v(154): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880863305 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(159) " "Verilog HDL assignment warning at RAM2GS-MAX.v(159): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880863305 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(286) " "Verilog HDL assignment warning at RAM2GS-MAX.v(286): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880863305 "|RAM2GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880863320 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_var UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component " "Elaborating entity \"UFM_altufm_none_var\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component\"" { } { { "UFM.v" "UFM_altufm_none_var_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880863320 ""}
-{ "Warning" "WVRFX_VERI_DISPLAY_SYSTEM_CALL_WARNING" " Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. UFM.v(145) " "Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results." { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 145 0 0 } } } 0 10649 "Verilog HDL Display System Task warning at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880863320 "|RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component"}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880863586 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "243 " "Implemented 243 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691880863617 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691880863617 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691880863617 ""} { "Info" "ICUT_CUT_TM_LCELLS" "180 " "Implemented 180 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691880863617 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691880863617 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691880863617 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880863664 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880863680 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:54:23 2023 " "Processing ended: Sat Aug 12 18:54:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880863680 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880863680 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880863680 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880863680 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903562627 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903562643 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:42 2023 " "Processing started: Sun Aug 13 01:12:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903562643 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903562643 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903562643 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903562971 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903562971 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903570984 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903570984 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903570984 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903571015 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903571015 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903571015 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903571015 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571015 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903571046 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903571296 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903571343 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903571343 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903571343 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571374 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:51 2023 " "Processing ended: Sun Aug 13 01:12:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903571406 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903571406 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.map.rdb b/CPLD/MAXII/db/RAM2GS.map.rdb
index a492517..d8031a0 100644
Binary files a/CPLD/MAXII/db/RAM2GS.map.rdb and b/CPLD/MAXII/db/RAM2GS.map.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.pplq.rdb b/CPLD/MAXII/db/RAM2GS.pplq.rdb
new file mode 100644
index 0000000..9a85185
Binary files /dev/null and b/CPLD/MAXII/db/RAM2GS.pplq.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAXII/db/RAM2GS.pre_map.hdb
index 233fa08..a4242b2 100644
Binary files a/CPLD/MAXII/db/RAM2GS.pre_map.hdb and b/CPLD/MAXII/db/RAM2GS.pre_map.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAXII/db/RAM2GS.routing.rdb
index d40db85..88e339e 100644
Binary files a/CPLD/MAXII/db/RAM2GS.routing.rdb and b/CPLD/MAXII/db/RAM2GS.routing.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAXII/db/RAM2GS.rtlv.hdb
index bd0331d..1a398d0 100644
Binary files a/CPLD/MAXII/db/RAM2GS.rtlv.hdb and b/CPLD/MAXII/db/RAM2GS.rtlv.hdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb
index d94b332..1613756 100644
Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb
index 69b3ae7..e90dd16 100644
Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAXII/db/RAM2GS.sta.qmsg
index ff7cb7c..d0a14a4 100644
--- a/CPLD/MAXII/db/RAM2GS.sta.qmsg
+++ b/CPLD/MAXII/db/RAM2GS.sta.qmsg
@@ -1,25 +1,25 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880868711 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880868711 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:54:28 2023 " "Processing started: Sat Aug 12 18:54:28 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880868711 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880868711 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880868711 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691880868836 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691880868961 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691880868961 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880868992 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880868992 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691880869039 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691880869180 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691880869211 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880869211 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880869211 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691880869211 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691880869211 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691880869227 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691880869227 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.919 -92.622 PHI2 " " -8.919 -92.622 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.036 -241.671 RCLK " " -8.036 -241.671 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.777 -2.512 nCRAS " " -0.777 -2.512 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880869227 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.785 " "Worst-case hold slack is -16.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.785 -16.785 DRCLK " " -16.785 -16.785 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.266 -16.266 ARCLK " " -16.266 -16.266 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.047 -2.078 RCLK " " -1.047 -2.078 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.276 -0.276 PHI2 " " -0.276 -0.276 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.031 -0.048 nCRAS " " -0.031 -0.048 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869227 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880869227 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880869227 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880869242 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880869242 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880869242 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691880869305 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880869320 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880869320 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880869367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:54:29 2023 " "Processing ended: Sat Aug 12 18:54:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880869367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880869367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880869367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691880869367 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903576561 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903576561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:12:56 2023 " "Processing started: Sun Aug 13 01:12:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903576561 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903576561 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903576561 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903576670 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903576795 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903576795 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903576826 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903576826 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903576857 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903576998 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903577029 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577029 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903577029 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903577029 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903577045 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903577045 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903577045 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.970 -99.540 PHI2 " " -8.970 -99.540 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.571 -261.130 RCLK " " -7.571 -261.130 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.200 -7.385 nCRAS " " -1.200 -7.385 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.289 " "Worst-case hold slack is -16.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.289 -16.289 ARCLK " " -16.289 -16.289 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.153 -1.956 PHI2 " " -1.153 -1.956 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.098 0.000 nCRAS " " 0.098 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.148 0.000 RCLK " " 1.148 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903577061 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903577076 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903577092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903577092 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903577154 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903577185 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903577185 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:12:57 2023 " "Processing ended: Sun Aug 13 01:12:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903577232 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903577232 ""}
diff --git a/CPLD/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAXII/db/RAM2GS.sta.rdb
index 6bf2d72..cc4283f 100644
Binary files a/CPLD/MAXII/db/RAM2GS.sta.rdb and b/CPLD/MAXII/db/RAM2GS.sta.rdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb
index 2610e82..0559858 100644
Binary files a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb and b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb differ
diff --git a/CPLD/MAXII/db/RAM2GS.tmw_info b/CPLD/MAXII/db/RAM2GS.tmw_info
index 8d51757..610074f 100644
--- a/CPLD/MAXII/db/RAM2GS.tmw_info
+++ b/CPLD/MAXII/db/RAM2GS.tmw_info
@@ -1,3 +1,6 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
+start_full_compilation:s:00:00:15
+start_analysis_synthesis:s:00:00:09-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:03-start_full_compilation
+start_assembler:s:00:00:01-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/CPLD/MAXII/db/RAM2GS.vpr.ammdb b/CPLD/MAXII/db/RAM2GS.vpr.ammdb
index 8c19835..64c0be8 100644
Binary files a/CPLD/MAXII/db/RAM2GS.vpr.ammdb and b/CPLD/MAXII/db/RAM2GS.vpr.ammdb differ
diff --git a/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg b/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg
index 364567c..c4ddaa7 100644
--- a/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg
+++ b/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg
@@ -1,113 +1,115 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880810077 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880810093 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:29 2023 " "Processing started: Sat Aug 12 18:53:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880810093 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880810093 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880810093 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691880810414 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691880810414 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(52) " "Verilog HDL warning at RAM2GS-MAX.v(52): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691880818509 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818509 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880818540 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880818540 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_var " "Found entity 1: UFM_altufm_none_var" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818540 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818540 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(154) " "Verilog HDL assignment warning at RAM2GS-MAX.v(154): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(159) " "Verilog HDL assignment warning at RAM2GS-MAX.v(159): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(286) " "Verilog HDL assignment warning at RAM2GS-MAX.v(286): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880818587 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_var UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component " "Elaborating entity \"UFM_altufm_none_var\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component\"" { } { { "UFM.v" "UFM_altufm_none_var_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880818587 ""}
-{ "Warning" "WVRFX_VERI_DISPLAY_SYSTEM_CALL_WARNING" " Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. UFM.v(145) " "Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results." { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 145 0 0 } } } 0 10649 "Verilog HDL Display System Task warning at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818603 "|RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component"}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "243 " "Implemented 243 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_LCELLS" "180 " "Implemented 180 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691880818918 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691880818918 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818965 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:38 2023 " "Processing ended: Sat Aug 12 18:53:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818996 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691880820181 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880820196 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:39 2023 " "Processing started: Sat Aug 12 18:53:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880820196 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691880820196 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691880820196 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691880820306 ""}
-{ "Info" "0" "" "Project = RAM2GS-MAXII" { } { } 0 0 "Project = RAM2GS-MAXII" 0 0 "Fitter" 0 0 1691880820306 ""}
-{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691880820306 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691880820353 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691880820353 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691880820353 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880820384 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880820384 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691880820415 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691880820415 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691880820525 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691880820571 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880820571 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 329 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 331 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 330 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691880820587 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691880820603 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691880820618 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691880820618 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691880820618 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691880820618 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880820650 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691880820650 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691880820728 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880820837 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691880820837 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691880821181 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821181 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691880821196 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691880821306 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691880821306 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691880821446 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691880821446 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821446 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691880821462 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821462 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691880821493 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691880821525 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:41 2023 " "Processing ended: Sat Aug 12 18:53:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691880821540 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691880822540 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880822540 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:42 2023 " "Processing started: Sat Aug 12 18:53:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880822540 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691880822540 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691880822540 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691880822775 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691880822790 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691880822790 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4661 " "Peak virtual memory: 4661 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:42 2023 " "Processing ended: Sat Aug 12 18:53:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691880822900 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691880823493 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691880824025 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880824040 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:43 2023 " "Processing started: Sat Aug 12 18:53:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880824040 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824040 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824040 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691880824150 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691880824290 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691880824290 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824321 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824321 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691880824353 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691880824493 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691880824525 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824525 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824525 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691880824525 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691880824540 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691880824540 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.919 -92.622 PHI2 " " -8.919 -92.622 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.036 -241.671 RCLK " " -8.036 -241.671 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.777 -2.512 nCRAS " " -0.777 -2.512 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824540 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.785 " "Worst-case hold slack is -16.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.785 -16.785 DRCLK " " -16.785 -16.785 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.266 -16.266 ARCLK " " -16.266 -16.266 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.047 -2.078 RCLK " " -1.047 -2.078 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.276 -0.276 PHI2 " " -0.276 -0.276 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.031 -0.048 nCRAS " " -0.031 -0.048 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691880824603 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880824634 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880824634 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:44 2023 " "Processing ended: Sat Aug 12 18:53:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691880824681 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus Prime Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691880825306 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903436765 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903436781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:36 2023 " "Processing started: Sun Aug 13 01:10:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903436781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903436781 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903436781 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903437078 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903437078 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903445963 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903445963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903445963 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903446010 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903446010 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903446010 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903446010 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446010 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903446072 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903446088 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903446525 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903446525 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446572 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:46 2023 " "Processing ended: Sun Aug 13 01:10:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446588 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691903447931 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903447947 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:47 2023 " "Processing started: Sun Aug 13 01:10:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903447947 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691903447947 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691903447947 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691903448056 ""}
+{ "Info" "0" "" "Project = RAM2GS-MAXII" { } { } 0 0 "Project = RAM2GS-MAXII" 0 0 "Fitter" 0 0 1691903448056 ""}
+{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691903448056 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903448103 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903448103 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903448103 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903448150 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903448150 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903448187 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903448193 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903448318 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1691903448334 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903448365 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903448365 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903448380 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903448396 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903448443 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903448443 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903448443 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903448443 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1691903448459 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1691903448459 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 18 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1691903448459 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903448490 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903448490 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903448584 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903448724 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903448724 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903449219 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449219 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903449235 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903449344 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903449344 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903449485 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903449485 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449485 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903449500 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449500 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903449532 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903449563 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:49 2023 " "Processing ended: Sun Aug 13 01:10:49 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903449578 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691903450625 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903450625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:50 2023 " "Processing started: Sun Aug 13 01:10:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903450625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903450625 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903450625 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903450891 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903450907 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903450922 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:51 2023 " "Processing ended: Sun Aug 13 01:10:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903451020 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691903451629 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691903452426 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903452426 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:52 2023 " "Processing started: Sun Aug 13 01:10:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903452426 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903452426 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903452426 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903452582 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903452910 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903452910 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903452942 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903452942 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903452988 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903453145 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903453176 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453176 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903453176 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903453176 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903453191 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903453191 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.855 -98.476 PHI2 " " -8.855 -98.476 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.999 -266.939 RCLK " " -7.999 -266.939 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.973 -1.155 nCRAS " " -0.973 -1.155 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453223 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.789 " "Worst-case hold slack is -16.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.789 -16.789 DRCLK " " -16.789 -16.789 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.423 -16.423 ARCLK " " -16.423 -16.423 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.008 -2.101 PHI2 " " -1.008 -2.101 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.397 -1.578 nCRAS " " -0.397 -1.578 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.107 0.000 RCLK " " 1.107 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453223 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903453238 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903453238 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453254 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903453301 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903453332 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903453332 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:53 2023 " "Processing ended: Sun Aug 13 01:10:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903453379 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus Prime Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903454016 ""}
diff --git a/CPLD/MAXII/greybox_tmp/cbx_args.txt b/CPLD/MAXII/greybox_tmp/cbx_args.txt
index 1e60991..9dd62b1 100644
--- a/CPLD/MAXII/greybox_tmp/cbx_args.txt
+++ b/CPLD/MAXII/greybox_tmp/cbx_args.txt
@@ -1,6 +1,6 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX II"
-LPM_FILE=RAM2GS.mif
+LPM_FILE=D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\MAXII\RAM2GS.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
OSC_FREQUENCY=180000
diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
index 10ac0b4..dbc6b27 100644
Binary files a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ
diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt
index cc5b707..a80e1b1 100644
--- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for RAM2GS
-Sat Aug 12 18:54:27 2023
+Sun Aug 13 01:12:55 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sat Aug 12 18:54:27 2023 ;
+; Assembler Status ; Successful - Sun Aug 13 01:12:55 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
@@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+---------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------------+
-; JTAG usercode ; 0x00172B88 ;
-; Checksum ; 0x00172F80 ;
+; JTAG usercode ; 0x00172FC9 ;
+; Checksum ; 0x001732B9 ;
+----------------+---------------------------------------------------------------------------------+
@@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sat Aug 12 18:54:27 2023
+ Info: Processing started: Sun Aug 13 01:12:54 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 4661 megabytes
- Info: Processing ended: Sat Aug 12 18:54:27 2023
- Info: Elapsed time: 00:00:00
+ Info: Peak virtual memory: 4662 megabytes
+ Info: Processing ended: Sun Aug 13 01:12:55 2023
+ Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done
index a5558c6..406fd9f 100644
--- a/CPLD/MAXII/output_files/RAM2GS.done
+++ b/CPLD/MAXII/output_files/RAM2GS.done
@@ -1 +1 @@
-Sat Aug 12 18:54:30 2023
+Sun Aug 13 01:12:57 2023
diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt
index 2dce144..aef6950 100644
--- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for RAM2GS
-Sat Aug 12 18:54:26 2023
+Sun Aug 13 01:12:53 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -59,15 +59,15 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
-; Fitter Status ; Successful - Sat Aug 12 18:54:26 2023 ;
+; Fitter Status ; Successful - Sun Aug 13 01:12:53 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
-; Total logic elements ; 171 / 240 ( 71 % ) ;
-; Total pins ; 62 / 80 ( 78 % ) ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
+; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
@@ -130,13 +130,13 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
-; Average used ; 1.05 ;
+; Average used ; 1.04 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
-; Processor 2 ; 1.6% ;
-; Processors 3-4 ; 1.5% ;
+; Processor 2 ; 1.5% ;
+; Processors 3-4 ; 1.4% ;
+----------------------------+-------------+
@@ -151,31 +151,31 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
-; Total logic elements ; 171 / 240 ( 71 % ) ;
-; -- Combinational with no register ; 75 ;
-; -- Register only ; 20 ;
-; -- Combinational with a register ; 76 ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
+; -- Combinational with no register ; 76 ;
+; -- Register only ; 21 ;
+; -- Combinational with a register ; 77 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
-; -- 3 input functions ; 42 ;
-; -- 2 input functions ; 43 ;
+; -- 3 input functions ; 47 ;
+; -- 2 input functions ; 40 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 155 ;
+; -- normal mode ; 158 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 7 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 23 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
-; Total registers ; 96 / 240 ( 40 % ) ;
-; Total LABs ; 21 / 24 ( 88 % ) ;
+; Total registers ; 98 / 240 ( 41 % ) ;
+; Total LABs ; 23 / 24 ( 96 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
-; I/O pins ; 62 / 80 ( 78 % ) ;
+; I/O pins ; 63 / 80 ( 79 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; ; ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@@ -186,12 +186,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; Global signals ; 4 ;
; -- Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 22.5% / 22.5% / 22.6% ;
-; Peak interconnect usage (total/H/V) ; 22.5% / 22.5% / 22.6% ;
-; Maximum fan-out ; 54 ;
-; Highest non-global fan-out ; 40 ;
-; Total fan-out ; 643 ;
-; Average fan-out ; 2.75 ;
+; Average interconnect usage (total/H/V) ; 22.7% / 24.7% / 20.6% ;
+; Peak interconnect usage (total/H/V) ; 22.7% / 24.7% / 20.6% ;
+; Maximum fan-out ; 55 ;
+; Highest non-global fan-out ; 41 ;
+; Total fan-out ; 660 ;
+; Average fan-out ; 2.77 ;
+---------------------------------------------+-----------------------+
@@ -203,13 +203,13 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@@ -220,10 +220,10 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 15 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@@ -241,6 +241,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
+; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
@@ -252,7 +253,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
-; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ;
+; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
@@ -270,14 +271,14 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ;
-; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
-; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
+; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ;
+; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ;
+; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ;
+; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ;
+; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ;
+; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ;
+; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ;
+; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@@ -287,7 +288,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
-; 2 ; 24 / 42 ( 57 % ) ; 3.3V ; -- ;
+; 2 ; 25 / 42 ( 60 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
@@ -383,7 +384,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 72 ; 2 ; LED ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 89 ; 73 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
@@ -421,9 +422,9 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS ; 171 (171) ; 96 ; 1 ; 62 ; 0 ; 75 (75) ; 20 (20) ; 76 (76) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ;
+; |RAM2GS ; 174 (174) ; 98 ; 1 ; 63 ; 0 ; 76 (76) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
-; |UFM_altufm_none_var:UFM_altufm_none_var_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component ; UFM_altufm_none_var ; work ;
+; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -441,6 +442,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Dout[5] ; Output ; -- ;
; Dout[6] ; Output ; -- ;
; Dout[7] ; Output ; -- ;
+; LED ; Output ; -- ;
; RBA[0] ; Output ; -- ;
; RBA[1] ; Output ; -- ;
; RA[0] ; Output ; -- ;
@@ -470,6 +472,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[5] ; Bidir ; (0) ;
; RD[6] ; Bidir ; (0) ;
; RD[7] ; Bidir ; (0) ;
+; nCRAS ; Input ; (0) ;
; MAin[0] ; Input ; (0) ;
; MAin[1] ; Input ; (0) ;
; MAin[2] ; Input ; (0) ;
@@ -480,10 +483,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; MAin[7] ; Input ; (0) ;
; MAin[8] ; Input ; (0) ;
; MAin[9] ; Input ; (0) ;
-; CROW[0] ; Input ; (1) ;
-; nCRAS ; Input ; (0) ;
-; CROW[1] ; Input ; (1) ;
; RCLK ; Input ; (0) ;
+; nCCAS ; Input ; (0) ;
+; CROW[0] ; Input ; (1) ;
+; CROW[1] ; Input ; (1) ;
; PHI2 ; Input ; (0) ;
; Din[6] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
@@ -494,25 +497,25 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Din[2] ; Input ; (1) ;
; Din[3] ; Input ; (1) ;
; Din[5] ; Input ; (1) ;
-; nCCAS ; Input ; (0) ;
+---------+----------+---------------+
-+---------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~0 ; LC_X5_Y3_N4 ; 4 ; Clock enable ; no ; -- ; -- ;
-; CmdSubmitted~0 ; LC_X5_Y1_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
-; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK3 ;
-; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ;
-; Ready ; LC_X3_Y2_N5 ; 39 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; always8~5 ; LC_X5_Y2_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
-; comb~2 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
-; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
-; nCRAS ; PIN_67 ; 15 ; Clock ; yes ; Global Clock ; GCLK1 ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; CmdDRDIn~2 ; LC_X4_Y3_N9 ; 4 ; Clock enable ; no ; -- ; -- ;
+; CmdLEDEN~1 ; LC_X3_Y1_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
+; DRDIn~1 ; LC_X3_Y1_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
+; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
+; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
+; Ready ; LC_X5_Y3_N9 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; always8~7 ; LC_X5_Y2_N6 ; 3 ; Clock enable ; no ; -- ; -- ;
+; comb~0 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
+; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
+; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------+
@@ -520,10 +523,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
-; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK3 ;
-; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ;
+; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
+; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
-; nCRAS ; PIN_67 ; 15 ; Global Clock ; GCLK1 ;
+; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ;
+-------+----------+---------+----------------------+------------------+
@@ -532,62 +535,63 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
-; C4s ; 142 / 784 ( 18 % ) ;
-; Direct links ; 50 / 888 ( 6 % ) ;
+; C4s ; 138 / 784 ( 18 % ) ;
+; Direct links ; 43 / 888 ( 5 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 14 / 32 ( 44 % ) ;
-; LUT chains ; 17 / 216 ( 8 % ) ;
-; Local interconnects ; 263 / 888 ( 30 % ) ;
-; R4s ; 127 / 704 ( 18 % ) ;
+; LUT chains ; 16 / 216 ( 7 % ) ;
+; Local interconnects ; 264 / 888 ( 30 % ) ;
+; R4s ; 142 / 704 ( 20 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
-; Number of Logic Elements (Average = 8.14) ; Number of LABs (Total = 21) ;
+; Number of Logic Elements (Average = 7.57) ; Number of LABs (Total = 23) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
+; 2 ; 2 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
; 5 ; 0 ;
-; 6 ; 2 ;
+; 6 ; 1 ;
; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 14 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 13 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
-; LAB-wide Signals (Average = 1.19) ; Number of LABs (Total = 21) ;
+; LAB-wide Signals (Average = 1.22) ; Number of LABs (Total = 23) ;
+------------------------------------+------------------------------+
-; 1 Clock ; 13 ;
-; 1 Sync. clear ; 3 ;
+; 1 Clock ; 16 ;
+; 1 Clock enable ; 1 ;
+; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 1 ;
-; 2 Clocks ; 8 ;
+; 2 Clocks ; 6 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
-; Number of Signals Sourced (Average = 8.43) ; Number of LABs (Total = 21) ;
+; Number of Signals Sourced (Average = 7.83) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
+; 2 ; 2 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
; 5 ; 0 ;
-; 6 ; 2 ;
+; 6 ; 1 ;
; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 10 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 9 ;
; 11 ; 2 ;
; 12 ; 2 ;
+---------------------------------------------+------------------------------+
@@ -596,50 +600,44 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 5.43) ; Number of LABs (Total = 21) ;
+; Number of Signals Sourced Out (Average = 4.91) ; Number of LABs (Total = 23) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
-; 2 ; 2 ;
-; 3 ; 4 ;
-; 4 ; 0 ;
-; 5 ; 2 ;
-; 6 ; 3 ;
-; 7 ; 2 ;
-; 8 ; 3 ;
-; 9 ; 0 ;
-; 10 ; 3 ;
+; 2 ; 4 ;
+; 3 ; 3 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
+; 6 ; 2 ;
+; 7 ; 5 ;
+; 8 ; 2 ;
+; 9 ; 2 ;
+-------------------------------------------------+------------------------------+
-+-----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 10.19) ; Number of LABs (Total = 21) ;
-+----------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 4 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 0 ;
-; 10 ; 3 ;
-; 11 ; 0 ;
-; 12 ; 3 ;
-; 13 ; 3 ;
-; 14 ; 2 ;
-; 15 ; 1 ;
-; 16 ; 0 ;
-; 17 ; 0 ;
-; 18 ; 1 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 1 ;
-+----------------------------------------------+------------------------------+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 9.09) ; Number of LABs (Total = 23) ;
++---------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 3 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 3 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 2 ;
+; 9 ; 2 ;
+; 10 ; 0 ;
+; 11 ; 2 ;
+; 12 ; 2 ;
+; 13 ; 3 ;
+; 14 ; 2 ;
+; 15 ; 1 ;
+; 16 ; 1 ;
++---------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
@@ -661,8 +659,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
-; I/O ; RCLK ; 4.0 ;
-; I/O ; nCRAS ; 3.0 ;
+; I/O ; RCLK ; 3.1 ;
+; I/O ; nCRAS ; 2.5 ;
+-----------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
@@ -673,9 +671,9 @@ This will disable optimization of problematic paths and expose them for further
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
-; nCCAS ; CBR ; 3.041 ;
+; nCCAS ; CBR ; 2.469 ;
; PHI2 ; PHI2r ; 1.523 ;
-; nCRAS ; RASr ; 1.214 ;
+; nCRAS ; RASr ; 0.358 ;
+-----------------+----------------------+-------------------+
Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
@@ -710,16 +708,17 @@ Info (332111): Found 6 clocks
Info (332111): 1.000 PHI2
Info (332111): 1.000 RCLK
Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 34
+Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 40
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 13
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
+ Info (186217): Destination "LED~0" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
Info (186217): Destination "RASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
Info (186217): Destination "CBR" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 17
- Info (186217): Destination "comb~2" may be non-global or may not use global clock
+ Info (186217): Destination "comb~0" may be non-global or may not use global clock
Info (186217): Destination "CASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10
Info (186079): Completed Auto Global Promotion Operation
@@ -727,7 +726,7 @@ Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -735,8 +734,8 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 19% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170195): Router estimated average interconnect usage is 18% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
@@ -746,8 +745,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 5346 megabytes
- Info: Processing ended: Sat Aug 12 18:54:26 2023
- Info: Elapsed time: 00:00:02
+ Info: Processing ended: Sun Aug 13 01:12:53 2023
+ Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02
diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary
index 8e1ecb6..d0ac43e 100644
--- a/CPLD/MAXII/output_files/RAM2GS.fit.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Sat Aug 12 18:54:26 2023
+Fitter Status : Successful - Sun Aug 13 01:12:53 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
-Total logic elements : 171 / 240 ( 71 % )
-Total pins : 62 / 80 ( 78 % )
+Total logic elements : 174 / 240 ( 73 % )
+Total pins : 63 / 80 ( 79 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt
index 7aae449..d02ea55 100644
--- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt
@@ -1,5 +1,5 @@
Flow report for RAM2GS
-Sat Aug 12 18:54:29 2023
+Sun Aug 13 01:12:57 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
-; Flow Status ; Successful - Sat Aug 12 18:54:27 2023 ;
+; Flow Status ; Successful - Sun Aug 13 01:12:55 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
-; Total logic elements ; 171 / 240 ( 71 % ) ;
-; Total pins ; 62 / 80 ( 78 % ) ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
+; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 08/12/2023 18:54:15 ;
+; Start date & time ; 08/13/2023 01:12:42 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 207120313862967.169188085502776 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 207120313862967.169190356209448 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
@@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4700 MB ; 00:00:21 ;
-; Fitter ; 00:00:02 ; 1.0 ; 5346 MB ; 00:00:02 ;
-; Assembler ; 00:00:00 ; 1.0 ; 4661 MB ; 00:00:00 ;
+; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ;
+; Fitter ; 00:00:01 ; 1.0 ; 5346 MB ; 00:00:02 ;
+; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ;
-; Total ; 00:00:12 ; -- ; -- ; 00:00:24 ;
+; Total ; 00:00:12 ; -- ; -- ; 00:00:25 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt
index 796fd17..58e6867 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2GS
-Sat Aug 12 18:54:23 2023
+Sun Aug 13 01:12:51 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -46,13 +46,13 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sat Aug 12 18:54:23 2023 ;
+; Analysis & Synthesis Status ; Successful - Sun Aug 13 01:12:51 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
-; Total logic elements ; 180 ;
-; Total pins ; 62 ;
+; Total logic elements ; 183 ;
+; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
@@ -145,15 +145,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+
-; ../RAM2GS.mif ; yes ; User Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.mif ; ;
-; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
-; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v ; ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
+; ../RAM2GS.mif ; yes ; User Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ;
+; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
+; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v ; ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
+-----------------------------------------------------+
@@ -161,34 +161,34 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
-; Total logic elements ; 180 ;
-; -- Combinational with no register ; 84 ;
-; -- Register only ; 29 ;
-; -- Combinational with a register ; 67 ;
+; Total logic elements ; 183 ;
+; -- Combinational with no register ; 85 ;
+; -- Register only ; 30 ;
+; -- Combinational with a register ; 68 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
-; -- 3 input functions ; 42 ;
-; -- 2 input functions ; 43 ;
+; -- 3 input functions ; 47 ;
+; -- 2 input functions ; 40 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 164 ;
+; -- normal mode ; 167 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 9 ;
+; -- synchronous clear/load mode ; 10 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
-; Total registers ; 96 ;
+; Total registers ; 98 ;
; Total logic cells in carry chains ; 17 ;
-; I/O pins ; 62 ;
+; I/O pins ; 63 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; RCLK ;
-; Maximum fan-out ; 54 ;
-; Total fan-out ; 644 ;
-; Average fan-out ; 2.65 ;
+; Maximum fan-out ; 55 ;
+; Total fan-out ; 661 ;
+; Average fan-out ; 2.68 ;
+---------------------------------------------+-------+
@@ -197,9 +197,9 @@ https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS ; 180 (180) ; 96 ; 1 ; 62 ; 0 ; 84 (84) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
+; |RAM2GS ; 183 (183) ; 98 ; 1 ; 63 ; 0 ; 85 (85) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
-; |UFM_altufm_none_var:UFM_altufm_none_var_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component ; UFM_altufm_none_var ; work ;
+; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -218,12 +218,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 96 ;
+; Total registers ; 98 ;
; Number of registers using Synchronous Clear ; 6 ;
-; Number of registers using Synchronous Load ; 3 ;
+; Number of registers using Synchronous Load ; 4 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 8 ;
+; Number of registers using Clock Enable ; 11 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@@ -246,7 +246,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ;
+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[1] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |RAM2GS|CmdLEDEN ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@@ -269,42 +270,41 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sat Aug 12 18:54:14 2023
+ Info: Processing started: Sun Aug 13 01:12:42 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
- Info (12023): Found entity 1: UFM_altufm_none_var File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47
- Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 154
+ Info (12023): Found entity 1: UFM_altufm_none_unv File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47
+ Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 150
Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(154): truncated value with size 32 to match size of target (2) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 154
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(159): truncated value with size 32 to match size of target (18) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 159
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(286): truncated value with size 32 to match size of target (4) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 286
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 83
-Info (12128): Elaborating entity "UFM_altufm_none_var" for hierarchy "UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 205
-Warning (10649): Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 145
-Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21
-Info (21057): Implemented 243 device resources after synthesis - the final resource count might be different
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 162
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 167
+Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 294
+Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 90
+Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 201
+Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
+Info (21057): Implemented 247 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins
- Info (21059): Implemented 29 output pins
+ Info (21059): Implemented 30 output pins
Info (21060): Implemented 8 bidirectional pins
- Info (21061): Implemented 180 logic cells
+ Info (21061): Implemented 183 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings
- Info: Peak virtual memory: 4700 megabytes
- Info: Processing ended: Sat Aug 12 18:54:23 2023
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+ Info: Peak virtual memory: 4702 megabytes
+ Info: Processing ended: Sun Aug 13 01:12:51 2023
Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:21
+ Info: Total CPU time (on all processors): 00:00:22
+------------------------------------------+
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.smsg b/CPLD/MAXII/output_files/RAM2GS.map.smsg
index 65b2829..b2799f0 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.smsg
+++ b/CPLD/MAXII/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(52): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 52
+Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(59): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 59
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(177): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 177
+Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 173
diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary
index cc099da..e701717 100644
--- a/CPLD/MAXII/output_files/RAM2GS.map.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Sat Aug 12 18:54:23 2023
+Analysis & Synthesis Status : Successful - Sun Aug 13 01:12:51 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX II
-Total logic elements : 180
-Total pins : 62
+Total logic elements : 183
+Total pins : 63
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2GS.pin b/CPLD/MAXII/output_files/RAM2GS.pin
index b0122be..f7e2045 100644
--- a/CPLD/MAXII/output_files/RAM2GS.pin
+++ b/CPLD/MAXII/output_files/RAM2GS.pin
@@ -150,7 +150,7 @@ GND* : 84 : : :
GND* : 85 : : : : 2 :
GND* : 86 : : : : 2 :
GND* : 87 : : : : 2 :
-GND* : 88 : : : : 2 :
+LED : 88 : output : 3.3-V LVTTL : : 2 : Y
RD[2] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[5] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y
diff --git a/CPLD/MAXII/output_files/RAM2GS.pof b/CPLD/MAXII/output_files/RAM2GS.pof
index a55ec1e..a95b1e8 100644
Binary files a/CPLD/MAXII/output_files/RAM2GS.pof and b/CPLD/MAXII/output_files/RAM2GS.pof differ
diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt
index 3b21939..c3200be 100644
--- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt
+++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt
@@ -1,5 +1,5 @@
Timing Analyzer report for RAM2GS
-Sat Aug 12 18:54:29 2023
+Sun Aug 13 01:12:57 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -21,11 +21,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
13. Setup: 'PHI2'
14. Setup: 'RCLK'
15. Setup: 'nCRAS'
- 16. Hold: 'DRCLK'
- 17. Hold: 'ARCLK'
- 18. Hold: 'RCLK'
- 19. Hold: 'PHI2'
- 20. Hold: 'nCRAS'
+ 16. Hold: 'ARCLK'
+ 17. Hold: 'DRCLK'
+ 18. Hold: 'PHI2'
+ 19. Hold: 'nCRAS'
+ 20. Hold: 'RCLK'
21. Setup Transfers
22. Hold Transfers
23. Report TCCS
@@ -112,8 +112,8 @@ https://fpgasoftware.intel.com/eula.
+------------+-----------------+------------+------+
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
-; 53.08 MHz ; 53.08 MHz ; PHI2 ; ;
-; 125.66 MHz ; 125.66 MHz ; RCLK ; ;
+; 52.8 MHz ; 52.8 MHz ; PHI2 ; ;
+; 117.79 MHz ; 117.79 MHz ; RCLK ; ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@@ -125,9 +125,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; ARCLK ; -99.000 ; -99.000 ;
; DRCLK ; -99.000 ; -99.000 ;
-; PHI2 ; -8.919 ; -92.622 ;
-; RCLK ; -8.036 ; -241.671 ;
-; nCRAS ; -0.777 ; -2.512 ;
+; PHI2 ; -8.970 ; -99.540 ;
+; RCLK ; -7.571 ; -261.130 ;
+; nCRAS ; -1.200 ; -7.385 ;
+-------+---------+---------------+
@@ -136,11 +136,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
-; DRCLK ; -16.785 ; -16.785 ;
-; ARCLK ; -16.266 ; -16.266 ;
-; RCLK ; -1.047 ; -2.078 ;
-; PHI2 ; -0.276 ; -0.276 ;
-; nCRAS ; -0.031 ; -0.048 ;
+; ARCLK ; -16.289 ; -16.289 ;
+; DRCLK ; -16.286 ; -16.286 ;
+; PHI2 ; -1.153 ; -1.956 ;
+; nCRAS ; 0.098 ; 0.000 ;
+; RCLK ; 1.148 ; 0.000 ;
+-------+---------+---------------+
@@ -175,8 +175,8 @@ No paths to report.
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ;
-; -22.734 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.175 ; 1.559 ;
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ;
+; -22.711 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.594 ; 2.117 ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
@@ -185,226 +185,226 @@ No paths to report.
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ;
-; -22.740 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.642 ; 2.098 ;
-; -22.215 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.642 ; 1.573 ;
+; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ;
+; -22.724 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.559 ;
+; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -2.165 ; 1.549 ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++---------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2' ;
++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; -8.970 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.137 ;
+; -8.811 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.978 ;
+; -8.500 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.667 ;
+; -8.341 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.508 ;
+; -8.272 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.439 ;
+; -8.190 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.357 ;
+; -8.027 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.194 ;
+; -8.001 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ;
+; -8.001 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ;
+; -8.001 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.168 ;
+; -7.895 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ;
+; -7.895 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ;
+; -7.895 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ;
+; -7.895 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.062 ;
+; -7.875 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.042 ;
+; -7.842 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ;
+; -7.842 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ;
+; -7.842 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.009 ;
+; -7.802 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.969 ;
+; -7.800 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.967 ;
+; -7.800 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.967 ;
+; -7.762 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.929 ;
+; -7.736 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ;
+; -7.736 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ;
+; -7.736 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ;
+; -7.736 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.903 ;
+; -7.720 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.887 ;
+; -7.641 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
+; -7.641 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
+; -7.557 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.724 ;
+; -7.405 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.572 ;
+; -7.379 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.546 ;
+; -7.303 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ;
+; -7.303 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ;
+; -7.303 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.470 ;
+; -7.292 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.459 ;
+; -7.221 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ;
+; -7.221 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ;
+; -7.221 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.388 ;
+; -7.220 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.387 ;
+; -7.197 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ;
+; -7.197 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ;
+; -7.197 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ;
+; -7.197 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.364 ;
+; -7.115 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ;
+; -7.115 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ;
+; -7.115 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ;
+; -7.115 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.282 ;
+; -7.102 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.269 ;
+; -7.102 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.269 ;
+; -7.058 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ;
+; -7.058 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ;
+; -7.058 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.225 ;
+; -7.020 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.187 ;
+; -7.020 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.187 ;
+; -6.984 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ;
+; -6.952 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ;
+; -6.952 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ;
+; -6.952 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ;
+; -6.952 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.119 ;
+; -6.906 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ;
+; -6.906 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ;
+; -6.906 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ;
+; -6.857 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.024 ;
+; -6.857 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.024 ;
+; -6.800 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ;
+; -6.800 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ;
+; -6.800 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ;
+; -6.800 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.967 ;
+; -6.793 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ;
+; -6.793 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ;
+; -6.793 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.960 ;
+; -6.705 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.872 ;
+; -6.705 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.872 ;
+; -6.687 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ;
+; -6.687 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ;
+; -6.687 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ;
+; -6.687 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.854 ;
+; -6.681 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.848 ;
+; -6.599 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.766 ;
+; -6.592 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.759 ;
+; -6.592 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.759 ;
+; -6.514 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.681 ;
+; -6.436 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.603 ;
+; -6.284 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.451 ;
+; -6.171 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.338 ;
+; -6.015 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ;
+; -6.015 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ;
+; -6.015 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.182 ;
+; -5.909 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ;
+; -5.909 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ;
+; -5.909 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ;
+; -5.909 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.076 ;
+; -5.814 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.981 ;
+; -5.814 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.981 ;
+; -5.408 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ;
+; -5.408 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ;
+; -5.408 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.075 ;
+; -5.393 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.560 ;
+; -4.901 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.568 ;
++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+
+
+-----------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2' ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -8.919 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.086 ;
-; -8.919 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.086 ;
-; -8.858 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ;
-; -8.858 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ;
-; -8.858 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ;
-; -8.858 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ;
-; -8.767 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.934 ;
-; -8.767 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.934 ;
-; -8.706 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ;
-; -8.706 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ;
-; -8.706 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ;
-; -8.706 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ;
-; -8.631 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.798 ;
-; -8.631 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.798 ;
-; -8.570 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ;
-; -8.570 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ;
-; -8.570 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ;
-; -8.570 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ;
-; -8.466 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.633 ;
-; -8.466 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.633 ;
-; -8.405 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ;
-; -8.405 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ;
-; -8.405 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ;
-; -8.405 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ;
-; -8.220 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ;
-; -8.220 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ;
-; -8.159 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ;
-; -8.159 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ;
-; -8.159 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ;
-; -8.159 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ;
-; -7.978 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.145 ;
-; -7.968 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.135 ;
-; -7.925 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ;
-; -7.925 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ;
-; -7.864 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ;
-; -7.864 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ;
-; -7.864 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ;
-; -7.864 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ;
-; -7.826 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.993 ;
-; -7.816 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.983 ;
-; -7.702 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.869 ;
-; -7.702 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.869 ;
-; -7.690 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.857 ;
-; -7.680 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.847 ;
-; -7.641 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
-; -7.641 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
-; -7.641 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
-; -7.641 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ;
-; -7.525 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.692 ;
-; -7.515 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.682 ;
-; -7.413 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.580 ;
-; -7.413 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.580 ;
-; -7.352 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ;
-; -7.352 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ;
-; -7.352 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ;
-; -7.352 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ;
-; -7.279 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.446 ;
-; -7.269 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.436 ;
-; -6.984 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ;
-; -6.974 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.141 ;
-; -6.761 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.928 ;
-; -6.751 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.918 ;
-; -6.726 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.893 ;
-; -6.642 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.809 ;
-; -6.642 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.809 ;
-; -6.574 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ;
-; -6.490 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.657 ;
-; -6.490 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.657 ;
-; -6.472 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.639 ;
-; -6.462 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.629 ;
-; -6.438 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.605 ;
-; -6.354 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.521 ;
-; -6.354 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.521 ;
-; -6.273 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.440 ;
-; -6.189 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.356 ;
-; -6.189 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.356 ;
-; -6.027 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.194 ;
-; -5.943 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.110 ;
-; -5.943 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.110 ;
-; -5.732 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.899 ;
-; -5.648 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.815 ;
-; -5.648 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.815 ;
-; -5.509 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.676 ;
-; -5.425 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.592 ;
-; -5.425 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.592 ;
-; -5.220 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.387 ;
-; -5.173 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.840 ;
-; -5.173 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.840 ;
-; -5.136 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.303 ;
-; -5.136 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.303 ;
-; -5.112 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ;
-; -5.112 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ;
-; -5.112 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ;
-; -5.112 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ;
-; -3.396 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.563 ;
-; -3.353 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.020 ;
-; -3.343 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.010 ;
-; -3.184 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.851 ;
-; -3.174 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.841 ;
-; -2.980 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.647 ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK' ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -8.036 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.644 ;
-; -7.606 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.214 ;
-; -7.568 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.176 ;
-; -7.441 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.049 ;
-; -7.125 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.733 ;
-; -7.066 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.674 ;
-; -6.958 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.625 ;
-; -6.908 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.575 ;
-; -6.901 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.509 ;
-; -6.842 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.509 ;
-; -6.824 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.491 ;
-; -6.800 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.797 ;
-; -6.795 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.462 ;
-; -6.746 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.413 ;
-; -6.745 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.412 ;
-; -6.724 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.391 ;
-; -6.715 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.382 ;
-; -6.674 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.341 ;
-; -6.673 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.281 ;
-; -6.661 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.328 ;
-; -6.658 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.325 ;
-; -6.616 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.283 ;
-; -6.608 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.275 ;
-; -6.607 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.274 ;
-; -6.590 ; FS[5] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.257 ;
-; -6.585 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.193 ;
-; -6.583 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ;
-; -6.583 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ;
-; -6.568 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.235 ;
-; -6.566 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.233 ;
-; -6.561 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.228 ;
-; -6.524 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.191 ;
-; -6.511 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.178 ;
-; -6.453 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.120 ;
-; -6.446 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.113 ;
-; -6.444 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.111 ;
-; -6.427 ; FS[6] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.094 ;
-; -6.425 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.092 ;
-; -6.420 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.087 ;
-; -6.403 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.070 ;
-; -6.387 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.054 ;
-; -6.382 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.049 ;
-; -6.376 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.373 ;
-; -6.364 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.031 ;
-; -6.358 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.355 ;
-; -6.350 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.017 ;
-; -6.349 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.016 ;
-; -6.332 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.999 ;
-; -6.316 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.983 ;
-; -6.314 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.981 ;
-; -6.307 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.974 ;
-; -6.283 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.950 ;
-; -6.278 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.275 ;
-; -6.266 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.933 ;
-; -6.230 ; FS[4] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.897 ;
-; -6.219 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.886 ;
-; -6.219 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.216 ;
-; -6.186 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.853 ;
-; -6.181 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.848 ;
-; -6.169 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ;
-; -6.163 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 3.771 ;
-; -6.137 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.804 ;
-; -6.111 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.778 ;
-; -6.046 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.713 ;
-; -6.029 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.696 ;
-; -6.022 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.689 ;
-; -6.010 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.677 ;
-; -5.989 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.656 ;
-; -5.972 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.639 ;
-; -5.909 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 2.906 ;
-; -5.900 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.567 ;
-; -5.899 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.566 ;
-; -5.898 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.565 ;
-; -5.873 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.540 ;
-; -5.834 ; InitReady ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.501 ;
-; -5.834 ; InitReady ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.501 ;
-; -5.822 ; FS[8] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.489 ;
-; -5.785 ; InitReady ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.452 ;
-; -5.737 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.404 ;
-; -5.727 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.394 ;
-; -5.718 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.385 ;
-; -5.666 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ;
-; -5.663 ; S[1] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.330 ;
-; -5.663 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.330 ;
-; -5.652 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.642 ; 7.961 ;
-; -5.646 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.313 ;
-; -5.614 ; S[1] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.281 ;
-; -5.604 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.271 ;
-; -5.600 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.267 ;
-; -5.591 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.258 ;
-; -5.590 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.257 ;
-; -5.588 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.255 ;
-; -5.571 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.238 ;
-; -5.558 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.225 ;
-; -5.526 ; S[0] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.193 ;
-; -5.526 ; S[0] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.193 ;
-; -5.525 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.192 ;
-; -5.503 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.170 ;
-; -5.477 ; S[0] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.144 ;
-; -5.467 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.134 ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
+; Setup: 'RCLK' ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+; -7.571 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 5.142 ;
+; -7.490 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.157 ;
+; -7.466 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.133 ;
+; -7.389 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.056 ;
+; -7.346 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.917 ;
+; -7.336 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.003 ;
+; -7.186 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.853 ;
+; -7.161 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.828 ;
+; -7.150 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.817 ;
+; -7.143 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.810 ;
+; -7.141 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 4.011 ;
+; -7.134 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 4.004 ;
+; -7.112 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.779 ;
+; -7.097 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.764 ;
+; -7.095 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.762 ;
+; -7.093 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.760 ;
+; -7.032 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.603 ;
+; -7.025 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.596 ;
+; -6.999 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.666 ;
+; -6.979 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.849 ;
+; -6.979 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.849 ;
+; -6.953 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.620 ;
+; -6.940 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.607 ;
+; -6.934 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.601 ;
+; -6.922 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.589 ;
+; -6.871 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.538 ;
+; -6.832 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.403 ;
+; -6.819 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.486 ;
+; -6.802 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.469 ;
+; -6.795 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.366 ;
+; -6.765 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.432 ;
+; -6.754 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.421 ;
+; -6.722 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.389 ;
+; -6.702 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.369 ;
+; -6.684 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.351 ;
+; -6.632 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.299 ;
+; -6.624 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.291 ;
+; -6.601 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 4.172 ;
+; -6.590 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.460 ;
+; -6.583 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ;
+; -6.575 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.242 ;
+; -6.567 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.234 ;
+; -6.556 ; S[0] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.223 ;
+; -6.522 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.189 ;
+; -6.463 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.130 ;
+; -6.446 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.113 ;
+; -6.432 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.099 ;
+; -6.431 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.098 ;
+; -6.407 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.074 ;
+; -6.393 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.060 ;
+; -6.390 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.057 ;
+; -6.387 ; InitReady ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.054 ;
+; -6.383 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.050 ;
+; -6.358 ; S[0] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.025 ;
+; -6.354 ; S[0] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.021 ;
+; -6.335 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.002 ;
+; -6.323 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.990 ;
+; -6.318 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.985 ;
+; -6.306 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.973 ;
+; -6.293 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.864 ;
+; -6.287 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.954 ;
+; -6.287 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.157 ;
+; -6.276 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.943 ;
+; -6.269 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.840 ;
+; -6.268 ; S[1] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.935 ;
+; -6.256 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.596 ; 3.827 ;
+; -6.243 ; CmdLEDEN ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 3.113 ;
+; -6.228 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.895 ;
+; -6.189 ; InitReady ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.856 ;
+; -6.185 ; InitReady ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.852 ;
+; -6.178 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.845 ;
+; -6.155 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.822 ;
+; -6.154 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.821 ;
+; -6.127 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.794 ;
+; -6.122 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.789 ;
+; -6.107 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.774 ;
+; -6.107 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.297 ; 2.977 ;
+; -6.090 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.757 ;
+; -6.076 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.743 ;
+; -6.070 ; S[1] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.737 ;
+; -6.066 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.733 ;
+; -6.054 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.721 ;
+; -6.038 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.705 ;
+; -6.036 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.703 ;
+; -6.035 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.702 ;
+; -6.020 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.687 ;
+; -6.012 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.679 ;
+; -5.975 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.642 ;
+; -5.957 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.624 ;
+; -5.940 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.607 ;
+; -5.881 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.548 ;
+; -5.760 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.427 ;
+; -5.757 ; S[0] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.424 ;
+; -5.744 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.411 ;
+; -5.733 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.400 ;
+; -5.721 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.388 ;
+; -5.718 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.385 ;
+; -5.712 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.379 ;
+; -5.695 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.362 ;
+; -5.671 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.338 ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------+
@@ -412,150 +412,42 @@ No paths to report.
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.777 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.907 ; 6.851 ;
-; -0.446 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.172 ;
-; -0.445 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.171 ;
-; -0.434 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.160 ;
-; -0.410 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.136 ;
-; -0.277 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.907 ; 6.851 ;
-; 0.127 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.599 ;
-; 0.128 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.598 ;
-; 0.137 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.589 ;
-; 0.145 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.581 ;
-; 0.398 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.328 ;
-; 0.406 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.320 ;
-; 0.463 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.263 ;
-; 0.477 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.249 ;
+; -1.200 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.944 ; 7.311 ;
+; -0.837 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.600 ;
+; -0.837 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.600 ;
+; -0.836 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.599 ;
+; -0.829 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.592 ;
+; -0.775 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.538 ;
+; -0.711 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.474 ;
+; -0.707 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.470 ;
+; -0.700 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.944 ; 7.311 ;
+; -0.653 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 3.416 ;
+; 0.342 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.421 ;
+; 0.346 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.417 ;
+; 0.347 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.416 ;
+; 0.348 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.596 ; 2.415 ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK' ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.785 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.642 ; 1.573 ;
-; -16.260 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.642 ; 2.098 ;
-; 60.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ARCLK' ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.266 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.175 ; 1.559 ;
-; 60.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
+; -16.289 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.594 ; 2.117 ;
+; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-+----------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK' ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; -1.047 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; 0.000 ; 3.348 ; 2.898 ;
-; -1.031 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 3.348 ; 2.914 ;
-; -0.547 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; -0.500 ; 3.348 ; 2.898 ;
-; -0.531 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 3.348 ; 2.914 ;
-; 1.128 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.697 ;
-; 1.247 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.816 ;
-; 1.348 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.917 ;
-; 1.398 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.619 ;
-; 1.628 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.697 ;
-; 1.659 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ;
-; 1.660 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.881 ;
-; 1.678 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.899 ;
-; 1.687 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.908 ;
-; 1.747 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.816 ;
-; 1.848 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.917 ;
-; 1.919 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.140 ;
-; 1.962 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.183 ;
-; 1.963 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.184 ;
-; 1.972 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.193 ;
-; 1.973 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.194 ;
-; 2.044 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.265 ;
-; 2.107 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.328 ;
-; 2.116 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ;
-; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ;
-; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ;
-; 2.117 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ;
-; 2.117 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ;
-; 2.126 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ;
-; 2.143 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.364 ;
-; 2.144 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ;
-; 2.144 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ;
-; 2.145 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ;
-; 2.151 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.372 ;
-; 2.166 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.387 ;
-; 2.221 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ;
-; 2.222 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.443 ;
-; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ;
-; 2.231 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ;
-; 2.239 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ;
-; 2.239 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ;
-; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ;
-; 2.241 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ;
-; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ;
-; 2.250 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ;
-; 2.251 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.472 ;
-; 2.251 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.472 ;
-; 2.264 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.485 ;
-; 2.353 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.574 ;
-; 2.414 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.635 ;
-; 2.476 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.697 ;
-; 2.586 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.807 ;
-; 2.597 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.818 ;
-; 2.633 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.854 ;
-; 2.692 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.913 ;
-; 2.703 ; DRDIn ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.924 ;
-; 2.704 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.925 ;
-; 2.712 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.933 ;
-; 2.814 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ;
-; 2.868 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.089 ;
-; 2.902 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.123 ;
-; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ;
-; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ;
-; 2.949 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ;
-; 2.975 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.196 ;
-; 2.976 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.197 ;
-; 2.977 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.198 ;
-; 2.979 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.200 ;
-; 2.995 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.216 ;
-; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ;
-; 3.060 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ;
-; 3.062 ; Ready ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.283 ;
-; 3.085 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.306 ;
-; 3.086 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.307 ;
-; 3.087 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.308 ;
-; 3.088 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.309 ;
-; 3.167 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.388 ;
-; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ;
-; 3.171 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ;
-; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ;
-; 3.179 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ;
-; 3.179 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ;
-; 3.181 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ;
-; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ;
-; 3.197 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.418 ;
-; 3.200 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.421 ;
-; 3.212 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.433 ;
-; 3.217 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.438 ;
-; 3.243 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.464 ;
-; 3.278 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.499 ;
-; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ;
-; 3.290 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ;
-; 3.290 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ;
-; 3.290 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ;
-; 3.302 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.523 ;
-; 3.311 ; IS[2] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.532 ;
-; 3.359 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.580 ;
-; 3.362 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.583 ;
-; 3.365 ; RASr2 ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.586 ;
-; 3.401 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.622 ;
-; 3.401 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.622 ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'DRCLK' ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.549 ;
+; -16.276 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -2.165 ; 1.559 ;
+; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------+
@@ -563,129 +455,237 @@ No paths to report.
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -0.276 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.170 ; 2.615 ;
-; 0.043 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.170 ; 3.434 ;
-; 0.634 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.170 ; 4.025 ;
-; 1.675 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 1.896 ;
-; 1.927 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.148 ;
-; 2.154 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.375 ;
-; 3.426 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.647 ;
-; 3.620 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.841 ;
-; 3.630 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.851 ;
-; 3.789 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.010 ;
-; 3.799 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.020 ;
-; 3.842 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.563 ;
-; 4.018 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.739 ;
-; 4.023 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.744 ;
-; 4.307 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.028 ;
-; 4.312 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.033 ;
-; 4.530 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.251 ;
-; 4.535 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.256 ;
-; 4.825 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.546 ;
-; 4.830 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.551 ;
-; 5.071 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.792 ;
-; 5.076 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.797 ;
-; 5.236 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.957 ;
-; 5.241 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.962 ;
-; 5.324 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.045 ;
-; 5.372 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.093 ;
-; 5.377 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.098 ;
-; 5.524 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.245 ;
-; 5.529 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.250 ;
-; 5.558 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ;
-; 5.558 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ;
-; 5.558 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ;
-; 5.558 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ;
-; 5.613 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.334 ;
-; 5.619 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.840 ;
-; 5.619 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.840 ;
-; 5.666 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.387 ;
-; 5.836 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.557 ;
-; 5.955 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.676 ;
-; 6.131 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.852 ;
-; 6.178 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.899 ;
-; 6.186 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.907 ;
-; 6.377 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.098 ;
-; 6.473 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.194 ;
-; 6.475 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.196 ;
-; 6.542 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.263 ;
-; 6.678 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.399 ;
-; 6.698 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.419 ;
-; 6.719 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.440 ;
-; 6.830 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.551 ;
-; 6.884 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.605 ;
-; 6.993 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.714 ;
-; 7.020 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.741 ;
-; 7.172 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.893 ;
-; 7.239 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ;
-; 7.404 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.125 ;
-; 7.540 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.261 ;
-; 7.692 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.413 ;
-; 7.798 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ;
-; 7.798 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ;
-; 7.798 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ;
-; 7.798 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ;
-; 7.859 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.580 ;
-; 7.859 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.580 ;
-; 8.087 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ;
-; 8.087 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ;
-; 8.087 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ;
-; 8.087 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ;
-; 8.148 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.869 ;
-; 8.148 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.869 ;
-; 8.310 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ;
-; 8.310 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ;
-; 8.310 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ;
-; 8.310 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ;
-; 8.371 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.092 ;
-; 8.371 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.092 ;
-; 8.605 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ;
-; 8.605 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ;
-; 8.605 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ;
-; 8.605 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ;
-; 8.666 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ;
-; 8.666 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ;
-; 8.851 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ;
-; 8.851 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ;
-; 8.851 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ;
-; 8.851 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ;
-; 8.912 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.633 ;
-; 8.912 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.633 ;
-; 9.016 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ;
-; 9.016 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ;
-; 9.016 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ;
-; 9.016 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ;
-; 9.077 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.798 ;
-; 9.077 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.798 ;
-; 9.152 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ;
-; 9.152 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ;
-; 9.152 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ;
-; 9.152 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ;
-; 9.213 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.934 ;
-; 9.213 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.934 ;
+; -1.153 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.297 ; 1.865 ;
+; -0.554 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.297 ; 2.464 ;
+; -0.249 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.297 ; 3.269 ;
+; 0.610 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.297 ; 4.128 ;
+; 2.107 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.328 ;
+; 2.145 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.366 ;
+; 2.537 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.758 ;
+; 3.233 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.454 ;
+; 3.661 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.882 ;
+; 3.747 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.968 ;
+; 3.954 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.675 ;
+; 4.175 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.396 ;
+; 4.607 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.328 ;
+; 4.617 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.338 ;
+; 5.232 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.453 ;
+; 5.347 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ;
+; 5.347 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ;
+; 5.347 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ;
+; 5.347 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.568 ;
+; 5.385 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.106 ;
+; 5.395 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.116 ;
+; 5.498 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.219 ;
+; 5.508 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.229 ;
+; 5.650 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.371 ;
+; 5.660 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.381 ;
+; 5.813 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.534 ;
+; 5.823 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.544 ;
+; 5.839 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.560 ;
+; 5.854 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ;
+; 5.854 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ;
+; 5.854 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.075 ;
+; 5.895 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.616 ;
+; 5.905 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.626 ;
+; 6.163 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.884 ;
+; 6.355 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ;
+; 6.355 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ;
+; 6.355 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ;
+; 6.355 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.076 ;
+; 6.434 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.155 ;
+; 6.444 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.165 ;
+; 6.461 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ;
+; 6.461 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ;
+; 6.461 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.182 ;
+; 6.591 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.312 ;
+; 6.593 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.314 ;
+; 6.603 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.324 ;
+; 6.617 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.338 ;
+; 6.730 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.451 ;
+; 6.882 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.603 ;
+; 6.941 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.662 ;
+; 7.045 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.766 ;
+; 7.054 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.775 ;
+; 7.127 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.848 ;
+; 7.133 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ;
+; 7.133 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ;
+; 7.133 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ;
+; 7.133 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.854 ;
+; 7.206 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.927 ;
+; 7.239 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ;
+; 7.239 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ;
+; 7.239 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ;
+; 7.246 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ;
+; 7.246 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ;
+; 7.246 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ;
+; 7.246 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.967 ;
+; 7.352 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ;
+; 7.352 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ;
+; 7.352 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.073 ;
+; 7.369 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.090 ;
+; 7.369 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.090 ;
+; 7.398 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ;
+; 7.398 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ;
+; 7.398 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ;
+; 7.398 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.119 ;
+; 7.451 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.172 ;
+; 7.482 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.203 ;
+; 7.504 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ;
+; 7.504 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ;
+; 7.504 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.225 ;
+; 7.561 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ;
+; 7.561 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ;
+; 7.561 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ;
+; 7.561 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.282 ;
+; 7.634 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.355 ;
+; 7.643 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ;
+; 7.643 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ;
+; 7.643 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ;
+; 7.643 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.364 ;
+; 7.666 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.387 ;
+; 7.667 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ;
+; 7.667 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ;
+; 7.667 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.388 ;
+; 7.749 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ;
+; 7.749 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ;
+; 7.749 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.470 ;
+; 7.797 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.518 ;
+; 7.825 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.546 ;
+; 7.879 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.600 ;
+; 7.990 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.711 ;
+; 8.149 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.870 ;
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-+--------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS' ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.031 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.249 ;
-; -0.017 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.263 ;
-; 0.040 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.320 ;
-; 0.048 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.328 ;
-; 0.301 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.581 ;
-; 0.309 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.589 ;
-; 0.318 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.598 ;
-; 0.319 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.599 ;
-; 0.723 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.907 ; 6.851 ;
-; 0.856 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.136 ;
-; 0.880 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.160 ;
-; 0.891 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.171 ;
-; 0.892 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.172 ;
-; 1.223 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.907 ; 6.851 ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
++-------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS' ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.098 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.415 ;
+; 0.099 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.416 ;
+; 0.100 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.417 ;
+; 0.104 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 2.421 ;
+; 1.099 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.416 ;
+; 1.146 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.944 ; 7.311 ;
+; 1.153 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.470 ;
+; 1.157 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.474 ;
+; 1.221 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.538 ;
+; 1.275 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.592 ;
+; 1.282 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.599 ;
+; 1.283 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.600 ;
+; 1.283 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.596 ; 3.600 ;
+; 1.646 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.944 ; 7.311 ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK' ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 1.148 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.717 ;
+; 1.174 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.743 ;
+; 1.378 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.947 ;
+; 1.639 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.860 ;
+; 1.648 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.717 ;
+; 1.658 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.879 ;
+; 1.674 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.743 ;
+; 1.822 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.043 ;
+; 1.878 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.947 ;
+; 1.887 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.108 ;
+; 1.943 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.164 ;
+; 1.959 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.180 ;
+; 2.010 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.231 ;
+; 2.011 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.232 ;
+; 2.107 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.328 ;
+; 2.116 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ;
+; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ;
+; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ;
+; 2.125 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ;
+; 2.125 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.346 ;
+; 2.134 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.355 ;
+; 2.158 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.379 ;
+; 2.192 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.413 ;
+; 2.233 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ;
+; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ;
+; 2.240 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.461 ;
+; 2.241 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ;
+; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ;
+; 2.250 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ;
+; 2.252 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.473 ;
+; 2.259 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.480 ;
+; 2.261 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.482 ;
+; 2.261 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.482 ;
+; 2.272 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.493 ;
+; 2.275 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.496 ;
+; 2.277 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.498 ;
+; 2.284 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.505 ;
+; 2.286 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.507 ;
+; 2.288 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.509 ;
+; 2.445 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.666 ;
+; 2.471 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.692 ;
+; 2.505 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.726 ;
+; 2.529 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.750 ;
+; 2.540 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.761 ;
+; 2.554 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.775 ;
+; 2.555 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.776 ;
+; 2.560 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.781 ;
+; 2.562 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.783 ;
+; 2.575 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.796 ;
+; 2.602 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.823 ;
+; 2.612 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.833 ;
+; 2.638 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.859 ;
+; 2.641 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.862 ;
+; 2.678 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.899 ;
+; 2.696 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ;
+; 2.920 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.141 ;
+; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ;
+; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ;
+; 2.957 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.178 ;
+; 2.966 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.187 ;
+; 2.967 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ;
+; 2.990 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.211 ;
+; 3.015 ; RASr2 ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.236 ;
+; 3.040 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.261 ;
+; 3.058 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.279 ;
+; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ;
+; 3.068 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.289 ;
+; 3.074 ; PHI2r3 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.295 ;
+; 3.077 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.298 ;
+; 3.080 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.301 ;
+; 3.081 ; PHI2r3 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.302 ;
+; 3.095 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.316 ;
+; 3.095 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.316 ;
+; 3.101 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.322 ;
+; 3.107 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.328 ;
+; 3.117 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.338 ;
+; 3.158 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.379 ;
+; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ;
+; 3.172 ; RCKE~reg0 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.393 ;
+; 3.173 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.394 ;
+; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ;
+; 3.179 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ;
+; 3.180 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.401 ;
+; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ;
+; 3.186 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.407 ;
+; 3.195 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.416 ;
+; 3.211 ; Ready ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.432 ;
+; 3.276 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.497 ;
+; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ;
+; 3.283 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.504 ;
+; 3.290 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ;
+; 3.291 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.512 ;
+; 3.361 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.582 ;
+; 3.372 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.593 ;
+; 3.376 ; RASr2 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.597 ;
+; 3.402 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.623 ;
+; 3.417 ; IS[0] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.638 ;
+; 3.422 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.643 ;
+; 3.468 ; Ready ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.689 ;
+; 3.471 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.692 ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------+
@@ -699,14 +699,13 @@ No paths to report.
; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ;
; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ;
-; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ;
-; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ;
-; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ;
-; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ;
+; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ;
+; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ;
+; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ;
; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ;
; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ;
-; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ;
-; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ;
+; PHI2 ; RCLK ; 1 ; 13 ; 0 ; 0 ;
+; RCLK ; RCLK ; 618 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -722,14 +721,13 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ;
; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ;
-; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ;
-; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ;
-; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ;
-; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ;
+; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ;
+; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ;
+; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ;
; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ;
; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ;
-; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ;
-; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ;
+; PHI2 ; RCLK ; 1 ; 13 ; 0 ; 0 ;
+; RCLK ; RCLK ; 618 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -753,10 +751,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 30 ; 30 ;
-; Unconstrained Input Port Paths ; 231 ; 231 ;
-; Unconstrained Output Ports ; 37 ; 37 ;
-; Unconstrained Output Port Paths ; 75 ; 75 ;
+; Unconstrained Input Ports ; 31 ; 31 ;
+; Unconstrained Input Port Paths ; 257 ; 257 ;
+; Unconstrained Output Ports ; 38 ; 38 ;
+; Unconstrained Output Port Paths ; 78 ; 78 ;
+---------------------------------+-------+------+
@@ -808,6 +806,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
@@ -825,6 +824,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -891,6 +891,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCRAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
@@ -908,6 +909,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -946,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sat Aug 12 18:54:28 2023
+ Info: Processing started: Sun Aug 13 01:12:56 2023
Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -972,17 +974,17 @@ Info (332146): Worst-case setup slack is -99.000
Info (332119): ========= =================== =====================
Info (332119): -99.000 -99.000 ARCLK
Info (332119): -99.000 -99.000 DRCLK
- Info (332119): -8.919 -92.622 PHI2
- Info (332119): -8.036 -241.671 RCLK
- Info (332119): -0.777 -2.512 nCRAS
-Info (332146): Worst-case hold slack is -16.785
+ Info (332119): -8.970 -99.540 PHI2
+ Info (332119): -7.571 -261.130 RCLK
+ Info (332119): -1.200 -7.385 nCRAS
+Info (332146): Worst-case hold slack is -16.289
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): -16.785 -16.785 DRCLK
- Info (332119): -16.266 -16.266 ARCLK
- Info (332119): -1.047 -2.078 RCLK
- Info (332119): -0.276 -0.276 PHI2
- Info (332119): -0.031 -0.048 nCRAS
+ Info (332119): -16.289 -16.289 ARCLK
+ Info (332119): -16.286 -16.286 DRCLK
+ Info (332119): -1.153 -1.956 PHI2
+ Info (332119): 0.098 0.000 nCRAS
+ Info (332119): 1.148 0.000 RCLK
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -29.500
@@ -999,7 +1001,7 @@ Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4676 megabytes
- Info: Processing ended: Sat Aug 12 18:54:29 2023
+ Info: Processing ended: Sun Aug 13 01:12:57 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.summary b/CPLD/MAXII/output_files/RAM2GS.sta.summary
index bd02d51..1493d48 100644
--- a/CPLD/MAXII/output_files/RAM2GS.sta.summary
+++ b/CPLD/MAXII/output_files/RAM2GS.sta.summary
@@ -11,36 +11,36 @@ Slack : -99.000
TNS : -99.000
Type : Setup 'PHI2'
-Slack : -8.919
-TNS : -92.622
+Slack : -8.970
+TNS : -99.540
Type : Setup 'RCLK'
-Slack : -8.036
-TNS : -241.671
+Slack : -7.571
+TNS : -261.130
Type : Setup 'nCRAS'
-Slack : -0.777
-TNS : -2.512
-
-Type : Hold 'DRCLK'
-Slack : -16.785
-TNS : -16.785
+Slack : -1.200
+TNS : -7.385
Type : Hold 'ARCLK'
-Slack : -16.266
-TNS : -16.266
+Slack : -16.289
+TNS : -16.289
-Type : Hold 'RCLK'
-Slack : -1.047
-TNS : -2.078
+Type : Hold 'DRCLK'
+Slack : -16.286
+TNS : -16.286
Type : Hold 'PHI2'
-Slack : -0.276
-TNS : -0.276
+Slack : -1.153
+TNS : -1.956
Type : Hold 'nCRAS'
-Slack : -0.031
-TNS : -0.048
+Slack : 0.098
+TNS : 0.000
+
+Type : Hold 'RCLK'
+Slack : 1.148
+TNS : 0.000
Type : Minimum Pulse Width 'ARCLK'
Slack : -29.500
diff --git a/CPLD/MAXV/RAM2GS.mif b/CPLD/MAXV/RAM2GS.mif
new file mode 100644
index 0000000..3382c37
--- /dev/null
+++ b/CPLD/MAXV/RAM2GS.mif
@@ -0,0 +1,28 @@
+-- Copyright (C) 2019 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and any partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors. Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=512;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+ [000..0FD] : 0000;
+ 0FE : 5FFF;
+ [0FF..1FF] : FFFF;
+END;
diff --git a/CPLD/MAXV/RAM2GS.qsf b/CPLD/MAXV/RAM2GS.qsf
index eafca6c..5bcd66a 100644
--- a/CPLD/MAXV/RAM2GS.qsf
+++ b/CPLD/MAXV/RAM2GS.qsf
@@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "MAX V"
-set_global_assignment -name DEVICE 5M240ZT100C5
+set_global_assignment -name DEVICE 5M240ZT100C4
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:29 AUGUST 12, 2023"
@@ -48,17 +48,13 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
#
#
set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name QIP_FILE UFM.qip
-#set_global_assignment -name MIF_FILE "../RAM2GS.mif"
-
-
set_location_assignment PIN_12 -to RCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
@@ -196,4 +192,5 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
-set_location_assignment PIN_88 -to LED
\ No newline at end of file
+set_location_assignment PIN_88 -to LED
+set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws
new file mode 100644
index 0000000..ae9cf90
Binary files /dev/null and b/CPLD/MAXV/RAM2GS.qws differ
diff --git a/CPLD/MAXV/UFM.v b/CPLD/MAXV/UFM.v
index be7c3d0..b863c22 100644
--- a/CPLD/MAXV/UFM.v
+++ b/CPLD/MAXV/UFM.v
@@ -140,10 +140,6 @@ module UFM_altufm_none_38r
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
- initial/*synthesis enable_verilog_initial_construct*/
- begin
- $display("Warning: Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results.");
- end
endmodule //UFM_altufm_none_38r
//VALID FILE
diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb
index b818a97..aca770c 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb
index e8f81ef..72b603e 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb
index 568c09b..e16c609 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(1).cnf.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb
index 67fd6b0..67a1ae0 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(1).cnf.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb
index d31e8fb..2d7dfff 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(2).cnf.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb
index 2089a7b..0868d4b 100644
Binary files a/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(2).cnf.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAXV/db/RAM2GS.asm.qmsg
index 2b45eea..0dee2b1 100644
--- a/CPLD/MAXV/db/RAM2GS.asm.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.asm.qmsg
@@ -1,7 +1,7 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691899329552 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691899329558 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 00:02:09 2023 " "Processing started: Sun Aug 13 00:02:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691899329558 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691899329558 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691899329558 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691899329812 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691899329835 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691899329841 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691899329955 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 00:02:09 2023 " "Processing ended: Sun Aug 13 00:02:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691899329955 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691899329955 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691899329955 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691899329955 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903457578 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903457594 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:57 2023 " "Processing started: Sun Aug 13 01:10:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903457594 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903457594 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903457594 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903457797 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903457828 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903457828 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:57 2023 " "Processing ended: Sun Aug 13 01:10:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903457938 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903457938 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAXV/db/RAM2GS.asm.rdb
index 4f9d7b9..c292f72 100644
Binary files a/CPLD/MAXV/db/RAM2GS.asm.rdb and b/CPLD/MAXV/db/RAM2GS.asm.rdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb
index ae39009..93b3d50 100644
Binary files a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb differ
diff --git a/CPLD/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAXV/db/RAM2GS.cmp.cdb
index ef4cb92..a3870a7 100644
Binary files a/CPLD/MAXV/db/RAM2GS.cmp.cdb and b/CPLD/MAXV/db/RAM2GS.cmp.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.cmp.hdb b/CPLD/MAXV/db/RAM2GS.cmp.hdb
index 59bcd11..6c0a9f7 100644
Binary files a/CPLD/MAXV/db/RAM2GS.cmp.hdb and b/CPLD/MAXV/db/RAM2GS.cmp.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAXV/db/RAM2GS.cmp.idb
index 6f8dd2f..e44e69b 100644
Binary files a/CPLD/MAXV/db/RAM2GS.cmp.idb and b/CPLD/MAXV/db/RAM2GS.cmp.idb differ
diff --git a/CPLD/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAXV/db/RAM2GS.cmp.rdb
index 5e85673..6ecb70d 100644
Binary files a/CPLD/MAXV/db/RAM2GS.cmp.rdb and b/CPLD/MAXV/db/RAM2GS.cmp.rdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.cmp0.ddb b/CPLD/MAXV/db/RAM2GS.cmp0.ddb
index 4b0a19b..dc6bd54 100644
Binary files a/CPLD/MAXV/db/RAM2GS.cmp0.ddb and b/CPLD/MAXV/db/RAM2GS.cmp0.ddb differ
diff --git a/CPLD/MAXV/db/RAM2GS.db_info b/CPLD/MAXV/db/RAM2GS.db_info
index 96d0bc3..a117676 100644
--- a/CPLD/MAXV/db/RAM2GS.db_info
+++ b/CPLD/MAXV/db/RAM2GS.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Version_Index = 503488000
-Creation_Time = Sat Aug 12 19:12:38 2023
+Creation_Time = Sun Aug 13 00:27:41 2023
diff --git a/CPLD/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAXV/db/RAM2GS.fit.qmsg
index edf0cb6..fac2c7c 100644
--- a/CPLD/MAXV/db/RAM2GS.fit.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.fit.qmsg
@@ -1,45 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691899327137 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691899327137 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691899327137 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691899327184 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691899327184 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691899327215 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691899327215 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691899327324 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691899327324 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691899327371 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691899327371 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691899327387 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691899327387 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 335 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691899327387 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691899327387 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691899327402 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691899327418 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691899327434 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691899327434 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691899327434 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691899327434 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691899327465 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691899327465 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691899327559 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691899327668 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691899327668 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691899327998 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691899327998 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691899328014 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691899328139 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691899328139 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691899328389 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691899328389 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691899328389 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691899328389 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691899328404 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691899328436 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691899328467 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691899328498 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 00:02:08 2023 " "Processing ended: Sun Aug 13 00:02:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691899328498 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691899328498 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691899328498 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691899328498 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903455438 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903455438 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903455438 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903455469 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903455469 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903455500 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903455500 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903455594 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903455594 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903455641 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903455641 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903455641 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903455641 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903455656 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903455656 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903455656 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903455672 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903455703 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903455703 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903455703 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903455703 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903455719 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903455719 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903455797 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903455906 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903455906 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903456234 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456234 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903456266 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903456375 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903456375 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903456500 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903456500 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456516 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903456516 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903456531 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903456547 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903456578 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:56 2023 " "Processing ended: Sun Aug 13 01:10:56 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903456609 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903456609 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.hier_info b/CPLD/MAXV/db/RAM2GS.hier_info
index 6deabca..f655925 100644
--- a/CPLD/MAXV/db/RAM2GS.hier_info
+++ b/CPLD/MAXV/db/RAM2GS.hier_info
@@ -15,6 +15,7 @@ PHI2 => CmdUFMPrgm.CLK
PHI2 => CmdUFMErase.CLK
PHI2 => CmdSubmitted.CLK
PHI2 => Cmdn8MEGEN.CLK
+PHI2 => CmdLEDEN.CLK
PHI2 => XOR8MEG.CLK
PHI2 => ADSubmitted.CLK
PHI2 => C1Submitted.CLK
@@ -81,6 +82,7 @@ Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
Din[1] => Equal17.IN2
+Din[1] => CmdLEDEN.DATAB
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN
@@ -189,8 +191,9 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
-RCLK => n8MEGEN.CLK
+RCLK => LEDEN.CLK
RCLK => UFMInitDone.CLK
+RCLK => n8MEGEN.CLK
RCLK => UFMD.CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif
index 147978c..cf97260 100644
Binary files a/CPLD/MAXV/db/RAM2GS.hif and b/CPLD/MAXV/db/RAM2GS.hif differ
diff --git a/CPLD/MAXV/db/RAM2GS.map.cdb b/CPLD/MAXV/db/RAM2GS.map.cdb
index a2f67c1..8024be4 100644
Binary files a/CPLD/MAXV/db/RAM2GS.map.cdb and b/CPLD/MAXV/db/RAM2GS.map.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.map.hdb b/CPLD/MAXV/db/RAM2GS.map.hdb
index 15fe7ce..fc39e15 100644
Binary files a/CPLD/MAXV/db/RAM2GS.map.hdb and b/CPLD/MAXV/db/RAM2GS.map.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAXV/db/RAM2GS.map.qmsg
index 32e9fa7..10cac29 100644
--- a/CPLD/MAXV/db/RAM2GS.map.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.map.qmsg
@@ -1,29 +1,27 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691899316920 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691899316920 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 00:01:56 2023 " "Processing started: Sun Aug 13 00:01:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691899316920 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899316920 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899316920 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691899317201 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691899317201 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691899325309 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691899325309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899325309 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691899325340 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691899325340 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691899325340 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691899325340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899325340 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691899325371 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "CmdLEDEN RAM2GS-MAX.v(103) " "Verilog HDL or VHDL warning at RAM2GS-MAX.v(103): object \"CmdLEDEN\" assigned a value but never read" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 103 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1691899325371 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691899325371 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691899325371 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691899325371 "|RAM2GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691899325387 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691899325402 ""}
-{ "Warning" "WVRFX_VERI_DISPLAY_SYSTEM_CALL_WARNING" " Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. UFM.v(145) " "Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results." { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 145 0 0 } } } 0 10649 "Verilog HDL Display System Task warning at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899325402 "|RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component"}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691899325652 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "246 " "Implemented 246 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691899325699 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691899325699 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691899325699 ""} { "Info" "ICUT_CUT_TM_LCELLS" "182 " "Implemented 182 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691899325699 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691899325699 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691899325699 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899325746 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691899325762 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 00:02:05 2023 " "Processing ended: Sun Aug 13 00:02:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691899325762 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691899325762 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691899325762 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899325762 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903444032 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903444032 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:43 2023 " "Processing started: Sun Aug 13 01:10:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903444032 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903444032 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903444032 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903444516 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903444516 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903453629 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903453629 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903453660 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903453660 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453660 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903453660 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903453660 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903453691 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903453707 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903453723 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903453984 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903454031 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903454031 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903454031 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903454078 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:54 2023 " "Processing ended: Sun Aug 13 01:10:54 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903454094 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903454094 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.map.rdb b/CPLD/MAXV/db/RAM2GS.map.rdb
index b22686c..89c4807 100644
Binary files a/CPLD/MAXV/db/RAM2GS.map.rdb and b/CPLD/MAXV/db/RAM2GS.map.rdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAXV/db/RAM2GS.pre_map.hdb
index 029d4ed..5a435a8 100644
Binary files a/CPLD/MAXV/db/RAM2GS.pre_map.hdb and b/CPLD/MAXV/db/RAM2GS.pre_map.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAXV/db/RAM2GS.routing.rdb
index 4f215c5..d09de7b 100644
Binary files a/CPLD/MAXV/db/RAM2GS.routing.rdb and b/CPLD/MAXV/db/RAM2GS.routing.rdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAXV/db/RAM2GS.rtlv.hdb
index 823f7b4..9d58585 100644
Binary files a/CPLD/MAXV/db/RAM2GS.rtlv.hdb and b/CPLD/MAXV/db/RAM2GS.rtlv.hdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb
index 650e223..ad3563e 100644
Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb
index a0f7cf0..9706cf7 100644
Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAXV/db/RAM2GS.sta.qmsg
index 7f0d32a..493f545 100644
--- a/CPLD/MAXV/db/RAM2GS.sta.qmsg
+++ b/CPLD/MAXV/db/RAM2GS.sta.qmsg
@@ -1,25 +1,25 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691899331738 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691899331744 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 00:02:11 2023 " "Processing started: Sun Aug 13 00:02:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691899331744 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691899331744 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691899331744 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691899331892 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691899332075 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691899332076 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332122 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332122 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691899332158 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691899332441 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691899332483 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332484 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691899332485 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691899332485 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691899332489 ""}
-{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691899332499 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691899332501 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -20.679 -213.940 PHI2 " " -20.679 -213.940 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -20.375 -594.272 RCLK " " -20.375 -594.272 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.508 -18.066 nCRAS " " -5.508 -18.066 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332508 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332508 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -15.989 " "Worst-case hold slack is -15.989" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.989 -15.989 DRCLK " " -15.989 -15.989 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.590 -14.590 ARCLK " " -14.590 -14.590 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.710 -3.324 PHI2 " " -2.710 -3.324 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.704 -2.798 nCRAS " " -0.704 -2.798 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.603 -0.801 RCLK " " -0.603 -0.801 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332513 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332513 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691899332520 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691899332526 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691899332534 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691899332534 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691899332611 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691899332633 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691899332634 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691899332686 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 00:02:12 2023 " "Processing ended: Sun Aug 13 00:02:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691899332686 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691899332686 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691899332686 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691899332686 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903459094 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903459110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:58 2023 " "Processing started: Sun Aug 13 01:10:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903459110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459110 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459110 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903459219 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903459328 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903459328 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459360 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459360 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903459407 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903459578 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903459610 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459610 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903459610 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903459610 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903459610 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903459625 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.792 -122.191 PHI2 " " -10.792 -122.191 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.864 -306.770 RCLK " " -8.864 -306.770 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.878 -11.627 nCRAS " " -2.878 -11.627 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.715 " "Worst-case hold slack is -16.715" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.715 -16.715 DRCLK " " -16.715 -16.715 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.888 -15.888 ARCLK " " -15.888 -15.888 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.520 -0.782 PHI2 " " -0.520 -0.782 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.622 0.000 nCRAS " " 0.622 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459625 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903459625 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903459641 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903459641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903459641 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903459703 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903459719 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903459719 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:59 2023 " "Processing ended: Sun Aug 13 01:10:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903459766 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903459766 ""}
diff --git a/CPLD/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAXV/db/RAM2GS.sta.rdb
index 6dd2345..15ada92 100644
Binary files a/CPLD/MAXV/db/RAM2GS.sta.rdb and b/CPLD/MAXV/db/RAM2GS.sta.rdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb
new file mode 100644
index 0000000..ceb12fd
Binary files /dev/null and b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb differ
diff --git a/CPLD/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb
deleted file mode 100644
index 8745cf6..0000000
Binary files a/CPLD/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb and /dev/null differ
diff --git a/CPLD/MAXV/db/RAM2GS.tmw_info b/CPLD/MAXV/db/RAM2GS.tmw_info
index 5f02de9..6f8e418 100644
--- a/CPLD/MAXV/db/RAM2GS.tmw_info
+++ b/CPLD/MAXV/db/RAM2GS.tmw_info
@@ -1,6 +1,6 @@
start_full_compilation:s:00:00:17
-start_analysis_synthesis:s:00:00:10-start_full_compilation
+start_analysis_synthesis:s:00:00:11-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
-start_timing_analyzer:s:00:00:03-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/CPLD/MAXV/db/RAM2GS.vpr.ammdb b/CPLD/MAXV/db/RAM2GS.vpr.ammdb
index eddc82a..64c0be8 100644
Binary files a/CPLD/MAXV/db/RAM2GS.vpr.ammdb and b/CPLD/MAXV/db/RAM2GS.vpr.ammdb differ
diff --git a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg
index f22b7b9..aada0d4 100644
--- a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg
+++ b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg
@@ -1,15 +1,112 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691899286513 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691899286519 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 00:01:26 2023 " "Processing started: Sun Aug 13 00:01:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691899286519 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899286519 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899286519 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691899286820 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691899286820 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691899295121 ""}
-{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"end\"; \"end\" without \"begin\" RAM2GS-MAX.v(373) " "Verilog HDL syntax error at RAM2GS-MAX.v(373) near text: \"end\"; \"end\" without \"begin\" . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 373 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1691899295121 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "RAM2GS RAM2GS-MAX.v(1) " "Ignored design unit \"RAM2GS\" at RAM2GS-MAX.v(1) due to previous errors" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1691899295121 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 0 0 " "Found 0 design units, including 0 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899295121 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691899295152 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691899295152 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691899295152 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691899295152 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899295152 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899295168 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691899295184 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 13 00:01:35 2023 " "Processing ended: Sun Aug 13 00:01:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691899295184 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691899295184 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691899295184 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899295184 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus Prime Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691899295824 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903396510 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903396515 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:09:56 2023 " "Processing started: Sun Aug 13 01:09:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903396515 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903396515 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903396515 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903396906 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903396906 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903405936 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405936 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903405936 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903405967 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903405967 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405967 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903405967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903405967 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 "|RAM2GS"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903405999 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903406014 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406264 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406280 ""}
+{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903406280 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903406311 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903406311 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903406311 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903406358 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:06 2023 " "Processing ended: Sun Aug 13 01:10:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903406374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903406374 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691903407577 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903407577 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:07 2023 " "Processing started: Sun Aug 13 01:10:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903407577 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691903407577 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691903407577 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691903407686 ""}
+{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691903407686 ""}
+{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691903407686 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903407717 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903407717 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903407717 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903407764 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903407764 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903407795 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903407811 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903407906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903407906 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903407953 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903407953 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903407953 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903407969 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903407969 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903407985 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903408000 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903408000 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903408000 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903408000 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408031 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903408031 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903408110 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408219 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903408219 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903408578 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408578 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903408594 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "21 " "Router estimated average interconnect usage is 21% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903408703 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903408703 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903408860 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903408860 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408860 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903408860 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903408875 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903408891 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903408922 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:08 2023 " "Processing ended: Sun Aug 13 01:10:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903408953 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903408953 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691903409960 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903409976 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:09 2023 " "Processing started: Sun Aug 13 01:10:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903409976 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903409976 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903409976 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903410226 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903410242 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903410257 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:10 2023 " "Processing ended: Sun Aug 13 01:10:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903410351 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903410351 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691903410976 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691903411523 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903411523 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:11 2023 " "Processing started: Sun Aug 13 01:10:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903411523 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903411523 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903411523 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903411632 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903411742 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903411742 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903411789 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903411789 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903411835 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903412007 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903412039 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412039 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903412039 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903412039 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903412039 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903412054 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903412054 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.721 -118.450 PHI2 " " -10.721 -118.450 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.110 -293.269 RCLK " " -9.110 -293.269 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.660 -10.655 nCRAS " " -2.660 -10.655 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412054 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.633 " "Worst-case hold slack is -16.633" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.633 -16.633 DRCLK " " -16.633 -16.633 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.892 -15.892 ARCLK " " -15.892 -15.892 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.638 -1.005 PHI2 " " -0.638 -1.005 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 nCRAS " " 0.319 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903412070 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903412070 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903412132 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903412164 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903412164 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:12 2023 " "Processing ended: Sun Aug 13 01:10:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903412210 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903412210 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903412851 ""}
diff --git a/CPLD/MAXV/greybox_tmp/cbx_args.txt b/CPLD/MAXV/greybox_tmp/cbx_args.txt
index 1493d8a..eadc163 100644
--- a/CPLD/MAXV/greybox_tmp/cbx_args.txt
+++ b/CPLD/MAXV/greybox_tmp/cbx_args.txt
@@ -1,6 +1,6 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX V"
-LPM_FILE=RAM2GS.mif
+LPM_FILE=D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\MAXV\RAM2GS.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
OSC_FREQUENCY=180000
diff --git a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
index 7f6c597..425b2ac 100644
Binary files a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ
diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt
index 08e14e4..65d50b7 100644
--- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for RAM2GS
-Sun Aug 13 00:02:09 2023
+Sun Aug 13 01:10:57 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -38,11 +38,11 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sun Aug 13 00:02:09 2023 ;
+; Assembler Status ; Successful - Sun Aug 13 01:10:57 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Device ; 5M240ZT100C4 ;
+-----------------------+---------------------------------------+
@@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+--------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------------------------------+
-; JTAG usercode ; 0x001725A1 ;
-; Checksum ; 0x00172999 ;
+; JTAG usercode ; 0x0017386C ;
+; Checksum ; 0x00173C5C ;
+----------------+--------------------------------------------------------------------------------+
@@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sun Aug 13 00:02:09 2023
+ Info: Processing started: Sun Aug 13 01:10:57 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4662 megabytes
- Info: Processing ended: Sun Aug 13 00:02:09 2023
+ Info: Processing ended: Sun Aug 13 01:10:57 2023
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done
index be0fa75..2b520e3 100644
--- a/CPLD/MAXV/output_files/RAM2GS.done
+++ b/CPLD/MAXV/output_files/RAM2GS.done
@@ -1 +1 @@
-Sun Aug 13 00:02:13 2023
+Sun Aug 13 01:11:00 2023
diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt
index 011acfc..ebed07c 100644
--- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for RAM2GS
-Sun Aug 13 00:02:08 2023
+Sun Aug 13 01:10:56 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -59,14 +59,14 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
-; Fitter Status ; Successful - Sun Aug 13 00:02:08 2023 ;
+; Fitter Status ; Successful - Sun Aug 13 01:10:56 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Device ; 5M240ZT100C4 ;
; Timing Models ; Final ;
-; Total logic elements ; 173 / 240 ( 72 % ) ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@@ -78,7 +78,7 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device ; 5M240ZT100C5 ; ;
+; Device ; 5M240ZT100C4 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
@@ -130,13 +130,13 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
-; Average used ; 1.04 ;
+; Average used ; 1.05 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.6% ;
-; Processors 3-4 ; 1.2% ;
+; Processors 3-4 ; 1.5% ;
+----------------------------+-------------+
@@ -151,28 +151,28 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
-; Total logic elements ; 173 / 240 ( 72 % ) ;
-; -- Combinational with no register ; 77 ;
-; -- Register only ; 20 ;
-; -- Combinational with a register ; 76 ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
+; -- Combinational with no register ; 76 ;
+; -- Register only ; 21 ;
+; -- Combinational with a register ; 77 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 58 ;
-; -- 3 input functions ; 44 ;
-; -- 2 input functions ; 42 ;
+; -- 4 input functions ; 57 ;
+; -- 3 input functions ; 47 ;
+; -- 2 input functions ; 40 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 157 ;
+; -- normal mode ; 158 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 7 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 22 ;
+; -- synchronous clear/load mode ; 23 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
-; Total registers ; 96 / 240 ( 40 % ) ;
-; Total LABs ; 22 / 24 ( 92 % ) ;
+; Total registers ; 98 / 240 ( 41 % ) ;
+; Total LABs ; 21 / 24 ( 88 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
; I/O pins ; 63 / 79 ( 80 % ) ;
@@ -186,12 +186,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
; Global signals ; 4 ;
; -- Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 25.7% / 30.6% / 20.5% ;
-; Peak interconnect usage (total/H/V) ; 25.7% / 30.6% / 20.5% ;
-; Maximum fan-out ; 54 ;
-; Highest non-global fan-out ; 40 ;
-; Total fan-out ; 652 ;
-; Average fan-out ; 2.75 ;
+; Average interconnect usage (total/H/V) ; 24.0% / 26.3% / 21.7% ;
+; Peak interconnect usage (total/H/V) ; 24.0% / 26.3% / 21.7% ;
+; Maximum fan-out ; 55 ;
+; Highest non-global fan-out ; 41 ;
+; Total fan-out ; 660 ;
+; Average fan-out ; 2.77 ;
+---------------------------------------------+-----------------------+
@@ -203,7 +203,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@@ -220,8 +220,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
-; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@@ -243,7 +243,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
-; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
+; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
@@ -259,10 +259,10 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
-; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
+; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
-; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@@ -425,7 +425,7 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS ; 173 (173) ; 96 ; 1 ; 63 ; 0 ; 77 (77) ; 20 (20) ; 76 (76) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ;
+; |RAM2GS ; 174 (174) ; 98 ; 1 ; 63 ; 0 ; 76 (76) ; 21 (21) ; 77 (77) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@@ -486,10 +486,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; MAin[7] ; Input ; (0) ;
; MAin[8] ; Input ; (0) ;
; MAin[9] ; Input ; (0) ;
+; RCLK ; Input ; (0) ;
; nCCAS ; Input ; (0) ;
; CROW[0] ; Input ; (1) ;
; CROW[1] ; Input ; (1) ;
-; RCLK ; Input ; (0) ;
; PHI2 ; Input ; (0) ;
; Din[6] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
@@ -503,21 +503,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------+----------+---------------+
-+---------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1 ; LC_X6_Y2_N8 ; 4 ; Clock enable ; no ; -- ; -- ;
-; CmdSubmitted~0 ; LC_X6_Y1_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
-; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK1 ;
-; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ;
-; Ready ; LC_X3_Y3_N9 ; 39 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; always8~7 ; LC_X7_Y2_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
-; comb~0 ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
-; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
-; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+; CmdDRDIn~2 ; LC_X5_Y4_N8 ; 4 ; Clock enable ; no ; -- ; -- ;
+; CmdLEDEN~1 ; LC_X5_Y4_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
+; DRDIn~1 ; LC_X4_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
+; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ;
+; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
+; Ready ; LC_X4_Y3_N6 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; always8~7 ; LC_X5_Y4_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
+; comb~0 ; LC_X4_Y4_N8 ; 8 ; Output enable ; no ; -- ; -- ;
+; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
+; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ;
++------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------+
@@ -525,8 +526,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
-; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK1 ;
-; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ;
+; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK1 ;
+; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK3 ;
+-------+----------+---------+----------------------+------------------+
@@ -537,109 +538,112 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
-; C4s ; 125 / 784 ( 16 % ) ;
-; Direct links ; 39 / 888 ( 4 % ) ;
+; C4s ; 141 / 784 ( 18 % ) ;
+; Direct links ; 52 / 888 ( 6 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 15 / 32 ( 47 % ) ;
-; LUT chains ; 20 / 216 ( 9 % ) ;
-; Local interconnects ; 263 / 888 ( 30 % ) ;
-; R4s ; 173 / 704 ( 25 % ) ;
+; LUT chains ; 19 / 216 ( 9 % ) ;
+; Local interconnects ; 269 / 888 ( 30 % ) ;
+; R4s ; 149 / 704 ( 21 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
-; Number of Logic Elements (Average = 7.86) ; Number of LABs (Total = 22) ;
+; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 21) ;
+--------------------------------------------+------------------------------+
-; 1 ; 3 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
+; 1 ; 0 ;
+; 2 ; 3 ;
+; 3 ; 0 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 6 ;
-; 10 ; 10 ;
+; 8 ; 2 ;
+; 9 ; 2 ;
+; 10 ; 13 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
-; LAB-wide Signals (Average = 1.14) ; Number of LABs (Total = 22) ;
+; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 21) ;
+------------------------------------+------------------------------+
-; 1 Clock ; 14 ;
-; 1 Sync. clear ; 2 ;
+; 1 Clock ; 11 ;
+; 1 Clock enable ; 6 ;
+; 1 Sync. clear ; 3 ;
; 1 Sync. load ; 2 ;
-; 2 Clocks ; 7 ;
+; 2 Clocks ; 10 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
-; Number of Signals Sourced (Average = 8.14) ; Number of LABs (Total = 22) ;
+; Number of Signals Sourced (Average = 8.57) ; Number of LABs (Total = 21) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
-; 1 ; 3 ;
-; 2 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 3 ;
; 3 ; 0 ;
-; 4 ; 1 ;
+; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 5 ;
-; 10 ; 8 ;
-; 11 ; 2 ;
-; 12 ; 1 ;
+; 8 ; 2 ;
+; 9 ; 1 ;
+; 10 ; 10 ;
+; 11 ; 4 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 5.27) ; Number of LABs (Total = 22) ;
+; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 21) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
-; 1 ; 3 ;
-; 2 ; 1 ;
-; 3 ; 2 ;
-; 4 ; 3 ;
-; 5 ; 3 ;
-; 6 ; 2 ;
-; 7 ; 2 ;
-; 8 ; 4 ;
-; 9 ; 0 ;
-; 10 ; 2 ;
+; 1 ; 0 ;
+; 2 ; 5 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 2 ;
+; 6 ; 4 ;
+; 7 ; 3 ;
+; 8 ; 1 ;
+; 9 ; 3 ;
+; 10 ; 1 ;
+-------------------------------------------------+------------------------------+
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 9.77) ; Number of LABs (Total = 22) ;
-+---------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-; 2 ; 3 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 3 ;
-; 10 ; 1 ;
-; 11 ; 2 ;
-; 12 ; 0 ;
-; 13 ; 3 ;
-; 14 ; 1 ;
-; 15 ; 1 ;
-; 16 ; 4 ;
-+---------------------------------------------+------------------------------+
++-----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 10.19) ; Number of LABs (Total = 21) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 1 ;
+; 2 ; 1 ;
+; 3 ; 2 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 2 ;
+; 9 ; 1 ;
+; 10 ; 2 ;
+; 11 ; 3 ;
+; 12 ; 2 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+; 15 ; 1 ;
+; 16 ; 2 ;
+; 17 ; 1 ;
+; 18 ; 0 ;
+; 19 ; 1 ;
++----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
@@ -661,8 +665,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
-; I/O ; nCRAS ; 2.4 ;
-; I/O ; RCLK ; 1.8 ;
+; I/O ; nCRAS ; 2.2 ;
+; I/O ; RCLK ; 1.9 ;
+-----------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
@@ -673,9 +677,9 @@ This will disable optimization of problematic paths and expose them for further
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
-; nCCAS ; CBR ; 2.449 ;
-; PHI2 ; PHI2r ; 0.948 ;
-; nCRAS ; RASr ; 0.420 ;
+; nCCAS ; CBR ; 2.167 ;
+; PHI2 ; PHI2r ; 0.871 ;
+; nCRAS ; RASr ; 0.519 ;
+-----------------+----------------------+-------------------+
Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
@@ -685,19 +689,15 @@ Note: This table only shows the top 3 path(s) that have the largest delay added
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS"
+Info (119006): Selected device 5M240ZT100C4 for design "RAM2GS"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device 5M80ZT100C5 is compatible
- Info (176445): Device 5M80ZT100I5 is compatible
- Info (176445): Device 5M160ZT100C5 is compatible
- Info (176445): Device 5M160ZT100I5 is compatible
- Info (176445): Device 5M240ZT100I5 is compatible
- Info (176445): Device 5M570ZT100C5 is compatible
- Info (176445): Device 5M570ZT100I5 is compatible
+ Info (176445): Device 5M80ZT100C4 is compatible
+ Info (176445): Device 5M160ZT100C4 is compatible
+ Info (176445): Device 5M570ZT100C4 is compatible
Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
@@ -743,15 +743,15 @@ Info (170195): Router estimated average interconnect usage is 18% of the availab
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.24 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.23 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 5345 megabytes
- Info: Processing ended: Sun Aug 13 00:02:08 2023
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:03
+ Info: Processing ended: Sun Aug 13 01:10:56 2023
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:02
+----------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary
index 48fae11..1a4d304 100644
--- a/CPLD/MAXV/output_files/RAM2GS.fit.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Sun Aug 13 00:02:08 2023
+Fitter Status : Successful - Sun Aug 13 01:10:56 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX V
-Device : 5M240ZT100C5
+Device : 5M240ZT100C4
Timing Models : Final
-Total logic elements : 173 / 240 ( 72 % )
+Total logic elements : 174 / 240 ( 73 % )
Total pins : 63 / 79 ( 80 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt
index 65ccb06..fb9261e 100644
--- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt
@@ -1,5 +1,5 @@
Flow report for RAM2GS
-Sun Aug 13 00:02:12 2023
+Sun Aug 13 01:10:59 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
-; Flow Status ; Successful - Sun Aug 13 00:02:09 2023 ;
+; Flow Status ; Successful - Sun Aug 13 01:10:57 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Device ; 5M240ZT100C4 ;
; Timing Models ; Final ;
-; Total logic elements ; 173 / 240 ( 72 % ) ;
+; Total logic elements ; 174 / 240 ( 73 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 08/13/2023 00:01:57 ;
+; Start date & time ; 08/13/2023 01:10:44 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+---------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 207120313862967.169189931707604 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 207120313862967.169190344412624 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
@@ -84,11 +84,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ;
-; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:03 ;
+; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4701 MB ; 00:00:24 ;
+; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:02 ;
; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ;
-; Total ; 00:00:12 ; -- ; -- ; 00:00:26 ;
+; Total ; 00:00:13 ; -- ; -- ; 00:00:27 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2GS.jdi b/CPLD/MAXV/output_files/RAM2GS.jdi
index fff5f81..9e57cf9 100644
--- a/CPLD/MAXV/output_files/RAM2GS.jdi
+++ b/CPLD/MAXV/output_files/RAM2GS.jdi
@@ -1,8 +1,8 @@
-
+
-
+
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt
index cdb8fc4..70fb58f 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2GS
-Sun Aug 13 00:02:05 2023
+Sun Aug 13 01:10:54 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Aug 13 00:02:05 2023 ;
+; Analysis & Synthesis Status ; Successful - Sun Aug 13 01:10:54 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
-; Total logic elements ; 182 ;
+; Total logic elements ; 183 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@@ -63,7 +63,7 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5M240ZT100C5 ; ;
+; Device ; 5M240ZT100C4 ; ;
; Top-level entity name ; RAM2GS ; RAM2GS ;
; Family name ; MAX V ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
@@ -145,14 +145,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+
-; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
-; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ;
-+----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------+---------+
+; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
+; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ;
+; RAM2GS.mif ; yes ; Auto-Found Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------+---------+
+-----------------------------------------------------+
@@ -160,34 +161,34 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
-; Total logic elements ; 182 ;
-; -- Combinational with no register ; 86 ;
-; -- Register only ; 29 ;
-; -- Combinational with a register ; 67 ;
+; Total logic elements ; 183 ;
+; -- Combinational with no register ; 85 ;
+; -- Register only ; 30 ;
+; -- Combinational with a register ; 68 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 58 ;
-; -- 3 input functions ; 44 ;
-; -- 2 input functions ; 42 ;
+; -- 4 input functions ; 57 ;
+; -- 3 input functions ; 47 ;
+; -- 2 input functions ; 40 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 166 ;
+; -- normal mode ; 167 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 9 ;
+; -- synchronous clear/load mode ; 10 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
-; Total registers ; 96 ;
+; Total registers ; 98 ;
; Total logic cells in carry chains ; 17 ;
; I/O pins ; 63 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; RCLK ;
-; Maximum fan-out ; 54 ;
-; Total fan-out ; 653 ;
-; Average fan-out ; 2.65 ;
+; Maximum fan-out ; 55 ;
+; Total fan-out ; 661 ;
+; Average fan-out ; 2.68 ;
+---------------------------------------------+-------+
@@ -196,7 +197,7 @@ https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
-; |RAM2GS ; 182 (182) ; 96 ; 1 ; 63 ; 0 ; 86 (86) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
+; |RAM2GS ; 183 (183) ; 98 ; 1 ; 63 ; 0 ; 85 (85) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@@ -217,12 +218,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 96 ;
+; Total registers ; 98 ;
; Number of registers using Synchronous Clear ; 6 ;
-; Number of registers using Synchronous Load ; 3 ;
+; Number of registers using Synchronous Load ; 4 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 8 ;
+; Number of registers using Clock Enable ; 11 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@@ -245,7 +246,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ;
+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[1] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |RAM2GS|CmdLEDEN ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@@ -268,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sun Aug 13 00:01:56 2023
+ Info: Processing started: Sun Aug 13 01:10:43 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@@ -276,15 +278,13 @@ Info (12021): Found 1 design units, including 1 entities, in source file /onedri
Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_38r File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 47
- Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 154
+ Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 150
Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at RAM2GS-MAX.v(103): object "CmdLEDEN" assigned a value but never read File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 103
Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 162
Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 167
Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 294
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 90
-Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 205
-Warning (10649): Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 145
+Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 201
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
@@ -293,18 +293,18 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26
-Info (21057): Implemented 246 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 247 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins
Info (21059): Implemented 30 output pins
Info (21060): Implemented 8 bidirectional pins
- Info (21061): Implemented 182 logic cells
+ Info (21061): Implemented 183 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
- Info: Peak virtual memory: 4702 megabytes
- Info: Processing ended: Sun Aug 13 00:02:05 2023
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:22
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+ Info: Peak virtual memory: 4701 megabytes
+ Info: Processing ended: Sun Aug 13 01:10:54 2023
+ Info: Elapsed time: 00:00:11
+ Info: Total CPU time (on all processors): 00:00:24
+------------------------------------------+
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.smsg b/CPLD/MAXV/output_files/RAM2GS.map.smsg
index 00ba75e..797a1b6 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.smsg
+++ b/CPLD/MAXV/output_files/RAM2GS.map.smsg
@@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(59): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 59
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(177): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 177
+Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 173
diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary
index 628418d..fcf4424 100644
--- a/CPLD/MAXV/output_files/RAM2GS.map.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Sun Aug 13 00:02:05 2023
+Analysis & Synthesis Status : Successful - Sun Aug 13 01:10:54 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX V
-Total logic elements : 182
+Total logic elements : 183
Total pins : 63
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2GS.pin b/CPLD/MAXV/output_files/RAM2GS.pin
index 88c2384..a2196ff 100644
--- a/CPLD/MAXV/output_files/RAM2GS.pin
+++ b/CPLD/MAXV/output_files/RAM2GS.pin
@@ -59,7 +59,7 @@
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C5
+CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C4
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
diff --git a/CPLD/MAXV/output_files/RAM2GS.pof b/CPLD/MAXV/output_files/RAM2GS.pof
index bee274d..01fae2e 100644
Binary files a/CPLD/MAXV/output_files/RAM2GS.pof and b/CPLD/MAXV/output_files/RAM2GS.pof differ
diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt
index 87db55c..d256f44 100644
--- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt
+++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt
@@ -1,5 +1,5 @@
Timing Analyzer report for RAM2GS
-Sun Aug 13 00:02:12 2023
+Sun Aug 13 01:10:59 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@@ -67,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2GS ;
; Device Family ; MAX V ;
-; Device Name ; 5M240ZT100C5 ;
+; Device Name ; 5M240ZT100C4 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
@@ -105,16 +105,16 @@ https://fpgasoftware.intel.com/eula.
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-+-------------------------------------------------+
-; Fmax Summary ;
-+-----------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
-; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
-; 23.61 MHz ; 23.61 MHz ; PHI2 ; ;
-; 46.78 MHz ; 46.78 MHz ; RCLK ; ;
-+-----------+-----------------+------------+------+
++--------------------------------------------------+
+; Fmax Summary ;
++------------+-----------------+------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
+; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
+; 44.28 MHz ; 44.28 MHz ; PHI2 ; ;
+; 101.38 MHz ; 101.38 MHz ; RCLK ; ;
++------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@@ -125,9 +125,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; ARCLK ; -99.000 ; -99.000 ;
; DRCLK ; -99.000 ; -99.000 ;
-; PHI2 ; -20.679 ; -213.940 ;
-; RCLK ; -20.375 ; -594.272 ;
-; nCRAS ; -5.508 ; -18.066 ;
+; PHI2 ; -10.792 ; -122.191 ;
+; RCLK ; -8.864 ; -306.770 ;
+; nCRAS ; -2.878 ; -11.627 ;
+-------+---------+---------------+
@@ -136,11 +136,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
-; DRCLK ; -15.989 ; -15.989 ;
-; ARCLK ; -14.590 ; -14.590 ;
-; PHI2 ; -2.710 ; -3.324 ;
-; nCRAS ; -0.704 ; -2.798 ;
-; RCLK ; -0.603 ; -0.801 ;
+; DRCLK ; -16.715 ; -16.715 ;
+; ARCLK ; -15.888 ; -15.888 ;
+; PHI2 ; -0.520 ; -0.782 ;
+; nCRAS ; 0.622 ; 0.000 ;
+; RCLK ; 1.178 ; 0.000 ;
+-------+---------+---------------+
@@ -176,7 +176,7 @@ No paths to report.
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ;
-; -24.410 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.447 ; 2.963 ;
+; -23.112 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.409 ; 1.703 ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
@@ -186,225 +186,225 @@ No paths to report.
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ;
-; -24.574 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.006 ; 4.568 ;
-; -23.011 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.006 ; 3.005 ;
+; -22.902 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.586 ; 2.316 ;
+; -22.285 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.586 ; 1.699 ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-+------------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2' ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -20.679 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.858 ;
-; -20.678 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.857 ;
-; -20.482 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.661 ;
-; -20.481 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.660 ;
-; -20.138 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.317 ;
-; -20.138 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.317 ;
-; -20.050 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.229 ;
-; -20.049 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.228 ;
-; -19.991 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.170 ;
-; -19.990 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.169 ;
-; -19.941 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.120 ;
-; -19.941 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.120 ;
-; -19.848 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.027 ;
-; -19.847 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.026 ;
-; -19.509 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.688 ;
-; -19.509 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.688 ;
-; -19.450 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.629 ;
-; -19.450 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.629 ;
-; -19.383 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.562 ;
-; -19.382 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.561 ;
-; -19.307 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.486 ;
-; -19.307 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.486 ;
-; -18.842 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.021 ;
-; -18.842 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.021 ;
-; -18.641 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.820 ;
-; -18.641 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.820 ;
-; -18.444 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.623 ;
-; -18.444 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.623 ;
-; -18.012 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.191 ;
-; -18.012 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.191 ;
-; -17.953 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.132 ;
-; -17.953 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.132 ;
-; -17.810 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.989 ;
-; -17.810 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.989 ;
-; -17.712 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.891 ;
-; -17.712 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.891 ;
-; -17.712 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.891 ;
-; -17.712 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.891 ;
-; -17.515 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.694 ;
-; -17.515 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.694 ;
-; -17.515 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.694 ;
-; -17.515 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.694 ;
-; -17.345 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.524 ;
-; -17.345 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.524 ;
-; -17.229 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.408 ;
-; -17.228 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.407 ;
-; -17.083 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.262 ;
-; -17.083 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.262 ;
-; -17.083 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.262 ;
-; -17.083 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.262 ;
-; -17.028 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.207 ;
-; -17.024 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.203 ;
-; -17.024 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.203 ;
-; -17.024 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.203 ;
-; -17.024 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.203 ;
-; -16.881 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.060 ;
-; -16.881 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.060 ;
-; -16.881 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.060 ;
-; -16.881 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.060 ;
-; -16.831 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.010 ;
-; -16.688 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.867 ;
-; -16.688 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.867 ;
-; -16.597 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.776 ;
-; -16.596 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.775 ;
-; -16.416 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.595 ;
-; -16.416 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.595 ;
-; -16.416 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.595 ;
-; -16.416 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.595 ;
-; -16.399 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.578 ;
-; -16.340 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.519 ;
-; -16.197 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.376 ;
-; -16.056 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.235 ;
-; -16.056 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.235 ;
-; -15.732 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.911 ;
-; -15.262 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 15.941 ;
-; -15.262 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 15.941 ;
-; -15.191 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.370 ;
-; -15.191 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.370 ;
-; -14.559 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.738 ;
-; -14.559 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.738 ;
-; -14.262 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.441 ;
-; -14.262 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.441 ;
-; -14.262 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.441 ;
-; -14.262 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.441 ;
-; -13.630 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.809 ;
-; -13.630 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.809 ;
-; -13.630 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.809 ;
-; -13.630 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.809 ;
-; -13.578 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.757 ;
-; -12.946 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 13.125 ;
-; -12.152 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.831 ;
-; -11.778 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.457 ;
-; -11.777 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.456 ;
-; -9.102 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.781 ;
-; -9.102 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.781 ;
-; -9.102 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.781 ;
-; -9.102 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.781 ;
-; -8.265 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.944 ;
-; -8.264 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.943 ;
-; -7.149 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.328 ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------+
+; Setup: 'PHI2' ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
+; -10.792 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.032 ;
+; -10.792 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.032 ;
+; -10.774 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.014 ;
+; -10.774 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.014 ;
+; -10.757 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.997 ;
+; -10.703 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.943 ;
+; -10.700 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.940 ;
+; -10.596 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.836 ;
+; -10.596 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.836 ;
+; -10.578 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.818 ;
+; -10.578 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.818 ;
+; -10.561 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.801 ;
+; -10.507 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.747 ;
+; -10.504 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.744 ;
+; -9.847 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.087 ;
+; -9.847 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.087 ;
+; -9.829 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.069 ;
+; -9.829 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.069 ;
+; -9.812 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.052 ;
+; -9.758 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.998 ;
+; -9.755 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.995 ;
+; -9.747 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.987 ;
+; -9.747 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.987 ;
+; -9.729 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.969 ;
+; -9.729 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.969 ;
+; -9.712 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.952 ;
+; -9.658 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.898 ;
+; -9.655 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.895 ;
+; -9.547 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.787 ;
+; -9.547 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.787 ;
+; -9.529 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.769 ;
+; -9.529 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.769 ;
+; -9.512 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.752 ;
+; -9.458 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.698 ;
+; -9.455 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.695 ;
+; -9.286 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.526 ;
+; -9.286 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.526 ;
+; -9.130 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.370 ;
+; -9.130 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.370 ;
+; -9.112 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.352 ;
+; -9.112 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.352 ;
+; -9.095 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.335 ;
+; -9.090 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.330 ;
+; -9.090 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.330 ;
+; -9.041 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.281 ;
+; -9.038 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.278 ;
+; -8.798 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.038 ;
+; -8.798 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.038 ;
+; -8.780 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.020 ;
+; -8.780 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.020 ;
+; -8.763 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.003 ;
+; -8.709 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.949 ;
+; -8.706 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.946 ;
+; -8.560 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.800 ;
+; -8.560 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.800 ;
+; -8.364 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.604 ;
+; -8.364 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.604 ;
+; -8.341 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.581 ;
+; -8.341 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.581 ;
+; -8.241 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.481 ;
+; -8.241 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.481 ;
+; -8.082 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.322 ;
+; -8.082 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.322 ;
+; -8.064 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ;
+; -8.064 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ;
+; -8.064 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.304 ;
+; -8.047 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.287 ;
+; -8.041 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.281 ;
+; -8.041 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.281 ;
+; -7.993 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.233 ;
+; -7.990 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.230 ;
+; -7.868 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ;
+; -7.624 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.864 ;
+; -7.624 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.864 ;
+; -7.615 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.855 ;
+; -7.615 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.855 ;
+; -7.515 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.755 ;
+; -7.515 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.755 ;
+; -7.315 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.555 ;
+; -7.315 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.555 ;
+; -7.292 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.532 ;
+; -7.292 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.532 ;
+; -7.119 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.359 ;
+; -7.019 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.259 ;
+; -6.898 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.138 ;
+; -6.898 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.138 ;
+; -6.819 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.059 ;
+; -6.576 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.816 ;
+; -6.576 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.816 ;
+; -6.566 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.806 ;
+; -6.566 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.806 ;
+; -6.410 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.150 ;
+; -6.410 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.150 ;
+; -6.402 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.642 ;
+; -6.375 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.115 ;
+; -6.070 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.310 ;
+; -5.850 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.090 ;
+; -5.850 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.090 ;
+; -5.758 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.498 ;
+; -5.758 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.498 ;
++---------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-+------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK' ;
-+---------+--------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+--------------+-------------+--------------+-------------+--------------+------------+------------+
-; -20.375 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 21.054 ;
-; -20.318 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.997 ;
-; -20.151 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 20.830 ;
-; -18.665 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.344 ;
-; -18.647 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.326 ;
-; -18.590 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.269 ;
-; -18.423 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 19.102 ;
-; -18.294 ; Ready ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.973 ;
-; -18.244 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.923 ;
-; -18.204 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 13.664 ;
-; -18.046 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.725 ;
-; -17.740 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.419 ;
-; -17.731 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -6.601 ; 11.309 ;
-; -17.656 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.335 ;
-; -17.548 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.227 ;
-; -17.518 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.197 ;
-; -17.461 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.140 ;
-; -17.422 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.101 ;
-; -17.421 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.100 ;
-; -17.385 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.064 ;
-; -17.294 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.973 ;
-; -17.257 ; S[1] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.936 ;
-; -17.154 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.833 ;
-; -17.099 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.778 ;
-; -16.953 ; RCKE~reg0 ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.632 ;
-; -16.937 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.616 ;
-; -16.918 ; FS[8] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.597 ;
-; -16.884 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.563 ;
-; -16.781 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.460 ;
-; -16.780 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.459 ;
-; -16.727 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 12.187 ;
-; -16.683 ; S[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.362 ;
-; -16.631 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.310 ;
-; -16.584 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.263 ;
-; -16.528 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.207 ;
-; -16.498 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.177 ;
-; -16.402 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.081 ;
-; -16.401 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.080 ;
-; -16.318 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.997 ;
-; -16.220 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -6.601 ; 9.798 ;
-; -16.153 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.832 ;
-; -16.087 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.766 ;
-; -16.020 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 11.480 ;
-; -15.939 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.618 ;
-; -15.931 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.610 ;
-; -15.929 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.608 ;
-; -15.883 ; PHI2r2 ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.562 ;
-; -15.808 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.487 ;
-; -15.698 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.377 ;
-; -15.676 ; S[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.355 ;
-; -15.594 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.273 ;
-; -15.589 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.268 ;
-; -15.532 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.211 ;
-; -15.531 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.210 ;
-; -15.513 ; Ready ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.192 ;
-; -15.481 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.160 ;
-; -15.446 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.125 ;
-; -15.291 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 10.751 ;
-; -15.244 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.923 ;
-; -15.190 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.869 ;
-; -15.189 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.868 ;
-; -15.092 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.771 ;
-; -15.067 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.746 ;
-; -15.018 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.697 ;
-; -14.987 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.666 ;
-; -14.887 ; IS[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.566 ;
-; -14.859 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.538 ;
-; -14.753 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.432 ;
-; -14.747 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.426 ;
-; -14.716 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 10.176 ;
-; -14.679 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.358 ;
-; -14.561 ; IS[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.240 ;
-; -14.504 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.183 ;
-; -14.451 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -6.601 ; 8.029 ;
-; -14.429 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.108 ;
-; -14.249 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.928 ;
-; -14.218 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.897 ;
-; -14.217 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.896 ;
-; -14.216 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.895 ;
-; -14.201 ; FS[15] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.880 ;
-; -14.197 ; UFMInitDone ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.876 ;
-; -14.168 ; IS[3] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.847 ;
-; -14.112 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.791 ;
-; -14.107 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -6.601 ; 7.685 ;
-; -14.059 ; UFMD ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.738 ;
-; -14.058 ; UFMD ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.737 ;
-; -14.054 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.733 ;
-; -14.053 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.732 ;
-; -14.032 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.711 ;
-; -14.027 ; RASr2 ; RCKE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.706 ;
-; -14.024 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.703 ;
-; -13.986 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.719 ; 9.446 ;
-; -13.921 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.600 ;
-; -13.866 ; FS[3] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.545 ;
-; -13.850 ; IS[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.529 ;
-; -13.839 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.518 ;
-; -13.830 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.509 ;
-; -13.733 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.412 ;
-; -13.668 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.347 ;
-; -13.625 ; FS[9] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.304 ;
-+---------+--------------+-------------+--------------+-------------+--------------+------------+------------+
++-----------------------------------------------------------------------------------------------------------+
+; Setup: 'RCLK' ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+; -8.864 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.604 ;
+; -8.716 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.456 ;
+; -8.605 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 6.619 ;
+; -8.582 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.322 ;
+; -8.538 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.278 ;
+; -8.430 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.627 ;
+; -8.372 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.112 ;
+; -8.349 ; S[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.089 ;
+; -8.314 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.511 ;
+; -8.271 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.011 ;
+; -8.258 ; FS[5] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.998 ;
+; -8.237 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.977 ;
+; -8.197 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.937 ;
+; -8.093 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.833 ;
+; -8.090 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.830 ;
+; -8.068 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.808 ;
+; -8.018 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.758 ;
+; -8.014 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.754 ;
+; -7.992 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.732 ;
+; -7.965 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 5.162 ;
+; -7.955 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.695 ;
+; -7.910 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.924 ;
+; -7.893 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.633 ;
+; -7.890 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.630 ;
+; -7.885 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.899 ;
+; -7.877 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.891 ;
+; -7.844 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.584 ;
+; -7.826 ; FS[6] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.566 ;
+; -7.799 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.539 ;
+; -7.785 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.799 ;
+; -7.752 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.492 ;
+; -7.746 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.486 ;
+; -7.734 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.474 ;
+; -7.710 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.450 ;
+; -7.697 ; FS[9] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.437 ;
+; -7.688 ; UFMD ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.428 ;
+; -7.663 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.403 ;
+; -7.584 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.781 ;
+; -7.555 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.295 ;
+; -7.549 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.289 ;
+; -7.542 ; UFMInitDone ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.282 ;
+; -7.503 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.243 ;
+; -7.494 ; FS[9] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.234 ;
+; -7.452 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.192 ;
+; -7.390 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.130 ;
+; -7.386 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.126 ;
+; -7.381 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.121 ;
+; -7.377 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.574 ;
+; -7.354 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.094 ;
+; -7.308 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.048 ;
+; -7.285 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.025 ;
+; -7.279 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.019 ;
+; -7.260 ; S[1] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.000 ;
+; -7.234 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.974 ;
+; -7.224 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.964 ;
+; -7.185 ; UFMD ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.925 ;
+; -7.182 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.196 ;
+; -7.165 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.905 ;
+; -7.163 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.903 ;
+; -7.162 ; S[1] ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ;
+; -7.157 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.171 ;
+; -7.151 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.891 ;
+; -7.146 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.886 ;
+; -7.138 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.878 ;
+; -7.099 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.043 ; 4.296 ;
+; -7.082 ; S[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.822 ;
+; -7.061 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.801 ;
+; -7.057 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.071 ;
+; -7.050 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.790 ;
+; -7.047 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.787 ;
+; -7.041 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.781 ;
+; -7.029 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 5.043 ;
+; -7.000 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.740 ;
+; -6.997 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.737 ;
+; -6.954 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.694 ;
+; -6.935 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.675 ;
+; -6.918 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.658 ;
+; -6.915 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.655 ;
+; -6.914 ; FS[15] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.654 ;
+; -6.911 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.651 ;
+; -6.888 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.628 ;
+; -6.880 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.620 ;
+; -6.844 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.584 ;
+; -6.817 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.557 ;
+; -6.808 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.548 ;
+; -6.741 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.481 ;
+; -6.684 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.424 ;
+; -6.670 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.410 ;
+; -6.669 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.409 ;
+; -6.616 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.356 ;
+; -6.597 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.337 ;
+; -6.579 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.319 ;
+; -6.554 ; S[0] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.294 ;
+; -6.552 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.226 ; 4.566 ;
+; -6.545 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.285 ;
+; -6.539 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ;
+; -6.539 ; Ready ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.279 ;
+; -6.525 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.265 ;
+; -6.506 ; Ready ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.246 ;
+; -6.495 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.235 ;
++--------+--------------+-------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------+
@@ -412,20 +412,20 @@ No paths to report.
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -5.508 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 9.665 ; 15.352 ;
-; -5.008 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 9.665 ; 15.352 ;
-; -3.107 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 8.005 ;
-; -2.132 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 7.030 ;
-; -2.131 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 7.029 ;
-; -2.059 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 6.957 ;
-; -1.485 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 6.383 ;
-; -1.453 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 6.351 ;
-; -0.098 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 4.996 ;
-; -0.093 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 4.991 ;
-; 1.337 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 3.561 ;
-; 1.338 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 3.560 ;
-; 1.339 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 3.559 ;
-; 1.344 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 4.719 ; 3.554 ;
+; -2.878 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.942 ; 9.060 ;
+; -2.378 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.942 ; 9.060 ;
+; -1.724 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 4.190 ;
+; -1.614 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 4.080 ;
+; -0.911 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.377 ;
+; -0.906 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.372 ;
+; -0.905 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.371 ;
+; -0.897 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.363 ;
+; -0.896 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.362 ;
+; -0.896 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 3.362 ;
+; 0.035 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.431 ;
+; 0.037 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.429 ;
+; 0.041 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.425 ;
+; 0.044 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.226 ; 2.422 ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
@@ -434,8 +434,8 @@ No paths to report.
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -15.989 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.006 ; 3.005 ;
-; -14.426 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.006 ; 4.568 ;
+; -16.715 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.586 ; 1.699 ;
+; -16.098 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.586 ; 2.316 ;
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
@@ -445,7 +445,7 @@ No paths to report.
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -14.590 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.447 ; 2.963 ;
+; -15.888 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.409 ; 1.703 ;
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
@@ -455,237 +455,237 @@ No paths to report.
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -2.710 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 6.601 ; 3.430 ;
-; -0.614 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.601 ; 6.026 ;
-; 1.718 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.601 ; 8.358 ;
-; 3.394 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.433 ;
-; 3.740 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.779 ;
-; 5.431 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.470 ;
-; 7.789 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.328 ;
-; 8.904 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.943 ;
-; 8.905 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.944 ;
-; 9.742 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.781 ;
-; 9.742 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.781 ;
-; 9.742 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.781 ;
-; 9.742 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.781 ;
-; 11.356 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.895 ;
-; 11.361 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.900 ;
-; 11.988 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.527 ;
-; 11.993 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.532 ;
-; 12.417 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.456 ;
-; 12.418 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.457 ;
-; 12.792 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.831 ;
-; 13.036 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.575 ;
-; 13.586 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.125 ;
-; 13.668 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.207 ;
-; 14.142 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.681 ;
-; 14.147 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.686 ;
-; 14.218 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.757 ;
-; 14.270 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.809 ;
-; 14.270 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.809 ;
-; 14.270 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.809 ;
-; 14.270 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.809 ;
-; 14.607 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.146 ;
-; 14.612 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.151 ;
-; 14.750 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.289 ;
-; 14.755 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.294 ;
-; 14.809 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.348 ;
-; 14.814 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.353 ;
-; 14.902 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.441 ;
-; 14.902 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.441 ;
-; 14.902 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.441 ;
-; 14.902 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.441 ;
-; 14.996 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.535 ;
-; 15.241 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.780 ;
-; 15.246 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.785 ;
-; 15.438 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.977 ;
-; 15.443 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.982 ;
-; 15.628 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.167 ;
-; 15.822 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.361 ;
-; 15.902 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 15.941 ;
-; 15.902 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 15.941 ;
-; 16.287 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.826 ;
-; 16.372 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.911 ;
-; 16.430 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.969 ;
-; 16.489 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.028 ;
-; 16.696 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.235 ;
-; 16.696 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.235 ;
-; 16.837 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.376 ;
-; 16.921 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.460 ;
-; 16.980 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.519 ;
-; 17.039 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.578 ;
-; 17.056 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.595 ;
-; 17.056 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.595 ;
-; 17.056 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.595 ;
-; 17.056 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.595 ;
-; 17.118 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.657 ;
-; 17.328 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.867 ;
-; 17.328 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.867 ;
-; 17.471 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.010 ;
-; 17.521 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.060 ;
-; 17.521 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.060 ;
-; 17.521 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.060 ;
-; 17.521 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.060 ;
-; 17.664 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.203 ;
-; 17.664 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.203 ;
-; 17.664 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.203 ;
-; 17.664 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.203 ;
-; 17.668 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.207 ;
-; 17.723 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.262 ;
-; 17.723 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.262 ;
-; 17.723 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.262 ;
-; 17.723 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.262 ;
-; 17.782 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.321 ;
-; 18.155 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.694 ;
-; 18.155 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.694 ;
-; 18.155 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.694 ;
-; 18.155 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.694 ;
-; 18.247 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.786 ;
-; 18.352 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.891 ;
-; 18.352 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.891 ;
-; 18.352 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.891 ;
-; 18.352 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.891 ;
-; 18.390 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.929 ;
-; 18.449 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.988 ;
-; 18.881 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.420 ;
-; 19.078 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.617 ;
-; 19.482 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.021 ;
-; 19.482 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.021 ;
-; 19.947 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.486 ;
-; 19.947 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.486 ;
-; 20.090 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.629 ;
-; 20.090 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.629 ;
+; -0.520 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.043 ; 2.097 ;
+; -0.262 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.043 ; 2.355 ;
+; 0.491 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.043 ; 3.608 ;
+; 0.692 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.043 ; 3.809 ;
+; 2.016 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.090 ;
+; 2.425 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.499 ;
+; 3.402 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.476 ;
+; 3.809 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.383 ;
+; 4.217 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.291 ;
+; 4.220 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.294 ;
+; 4.348 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.422 ;
+; 4.834 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.908 ;
+; 4.837 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.911 ;
+; 4.936 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.010 ;
+; 4.936 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.010 ;
+; 5.491 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.065 ;
+; 5.501 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.075 ;
+; 6.020 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.594 ;
+; 6.207 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.781 ;
+; 6.217 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.791 ;
+; 6.424 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.498 ;
+; 6.424 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.498 ;
+; 6.539 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.113 ;
+; 6.549 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.123 ;
+; 6.595 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.169 ;
+; 6.736 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.310 ;
+; 6.956 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.530 ;
+; 6.966 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.540 ;
+; 7.041 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.115 ;
+; 7.068 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.642 ;
+; 7.076 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.150 ;
+; 7.076 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.150 ;
+; 7.156 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.730 ;
+; 7.166 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.740 ;
+; 7.242 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.816 ;
+; 7.242 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.816 ;
+; 7.256 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.830 ;
+; 7.266 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.840 ;
+; 7.311 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.885 ;
+; 7.485 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.059 ;
+; 7.643 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.217 ;
+; 7.685 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.259 ;
+; 7.785 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.359 ;
+; 7.958 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.532 ;
+; 7.958 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.532 ;
+; 8.005 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.579 ;
+; 8.015 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.589 ;
+; 8.060 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.634 ;
+; 8.201 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.775 ;
+; 8.211 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.785 ;
+; 8.260 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.834 ;
+; 8.290 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.864 ;
+; 8.290 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.864 ;
+; 8.360 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.934 ;
+; 8.534 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.108 ;
+; 8.580 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.154 ;
+; 8.707 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.281 ;
+; 8.707 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.281 ;
+; 8.713 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.287 ;
+; 8.730 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ;
+; 8.730 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ;
+; 8.730 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.304 ;
+; 8.748 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.322 ;
+; 8.748 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.322 ;
+; 8.907 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.481 ;
+; 8.907 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.481 ;
+; 9.007 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.581 ;
+; 9.007 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.581 ;
+; 9.109 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.683 ;
+; 9.296 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.870 ;
+; 9.305 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.879 ;
+; 9.429 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.003 ;
+; 9.446 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.020 ;
+; 9.446 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.020 ;
+; 9.464 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.038 ;
+; 9.464 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.038 ;
+; 9.628 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.202 ;
+; 9.756 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.330 ;
+; 9.756 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.330 ;
+; 9.761 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.335 ;
+; 9.778 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.352 ;
+; 9.778 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.352 ;
+; 9.796 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.370 ;
+; 9.796 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.370 ;
+; 9.952 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.526 ;
+; 9.952 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.526 ;
+; 10.045 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.619 ;
+; 10.178 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.752 ;
+; 10.195 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.769 ;
+; 10.195 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.769 ;
+; 10.213 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.787 ;
+; 10.213 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.787 ;
+; 10.245 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.819 ;
+; 10.345 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.919 ;
+; 10.378 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.952 ;
+; 10.395 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.969 ;
+; 10.395 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.969 ;
+; 10.413 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.987 ;
+; 10.413 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.987 ;
+; 10.478 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.052 ;
+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-+--------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS' ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.704 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 3.554 ;
-; -0.699 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 3.559 ;
-; -0.698 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 3.560 ;
-; -0.697 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 3.561 ;
-; 0.733 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 4.991 ;
-; 0.738 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 4.996 ;
-; 2.093 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 6.351 ;
-; 2.125 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 6.383 ;
-; 2.699 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 6.957 ;
-; 2.771 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 7.029 ;
-; 2.772 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 7.030 ;
-; 3.747 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.719 ; 8.005 ;
-; 5.648 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 9.665 ; 15.352 ;
-; 6.148 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 9.665 ; 15.352 ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
++-------------------------------------------------------------------------------------------------------+
+; Hold: 'nCRAS' ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.622 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.422 ;
+; 0.625 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.425 ;
+; 0.629 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.429 ;
+; 0.631 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 2.431 ;
+; 1.562 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.362 ;
+; 1.562 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.362 ;
+; 1.563 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.363 ;
+; 1.571 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.371 ;
+; 1.572 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.372 ;
+; 1.577 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 3.377 ;
+; 2.280 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 4.080 ;
+; 2.390 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.226 ; 4.190 ;
+; 3.044 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.942 ; 9.060 ;
+; 3.544 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.942 ; 9.060 ;
++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-+----------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK' ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.603 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 4.946 ; 4.876 ;
-; -0.198 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; 0.000 ; 4.946 ; 5.281 ;
-; -0.103 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 4.946 ; 4.876 ;
-; 0.302 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; -0.500 ; 4.946 ; 5.281 ;
-; 2.127 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 4.946 ; 7.112 ;
-; 2.206 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 4.946 ; 7.191 ;
-; 2.412 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 4.946 ; 7.397 ;
-; 2.627 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 4.946 ; 7.112 ;
-; 2.706 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 4.946 ; 7.191 ;
-; 2.912 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 4.946 ; 7.397 ;
-; 3.105 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.144 ;
-; 3.266 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.305 ;
-; 3.376 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.415 ;
-; 3.388 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.427 ;
-; 3.473 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.512 ;
-; 3.476 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.515 ;
-; 3.767 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.806 ;
-; 4.015 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.054 ;
-; 4.065 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.104 ;
-; 4.092 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.131 ;
-; 4.571 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.610 ;
-; 4.617 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.656 ;
-; 4.841 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.880 ;
-; 4.845 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.884 ;
-; 4.849 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.888 ;
-; 5.228 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.267 ;
-; 5.229 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.268 ;
-; 5.242 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.281 ;
-; 5.243 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.282 ;
-; 5.243 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.282 ;
-; 5.253 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.292 ;
-; 5.256 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.295 ;
-; 5.261 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.300 ;
-; 5.262 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.301 ;
-; 5.266 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.305 ;
-; 5.270 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.309 ;
-; 5.416 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.455 ;
-; 5.443 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.482 ;
-; 5.452 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.491 ;
-; 5.452 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.491 ;
-; 5.460 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.499 ;
-; 5.463 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.502 ;
-; 5.465 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.504 ;
-; 5.466 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.505 ;
-; 5.466 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.505 ;
-; 5.466 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.505 ;
-; 5.474 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.513 ;
-; 5.475 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.514 ;
-; 5.488 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.527 ;
-; 5.491 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.530 ;
-; 5.520 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.559 ;
-; 5.524 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.563 ;
-; 5.671 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.710 ;
-; 5.676 ; DRDIn ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.715 ;
-; 5.804 ; InitReady ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.843 ;
-; 5.889 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.928 ;
-; 5.963 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.002 ;
-; 5.964 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.003 ;
-; 5.977 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.016 ;
-; 5.978 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.017 ;
-; 5.988 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.027 ;
-; 5.997 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.036 ;
-; 6.107 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.146 ;
-; 6.121 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.160 ;
-; 6.122 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.161 ;
-; 6.132 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.171 ;
-; 6.141 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.180 ;
-; 6.251 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.290 ;
-; 6.269 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.308 ;
-; 6.276 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.315 ;
-; 6.356 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.395 ;
-; 6.395 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.434 ;
-; 6.442 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.481 ;
-; 6.445 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.484 ;
-; 6.449 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.488 ;
-; 6.454 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.493 ;
-; 6.454 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.493 ;
-; 6.462 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.501 ;
-; 6.465 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.504 ;
-; 6.476 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.515 ;
-; 6.477 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.516 ;
-; 6.493 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.532 ;
-; 6.510 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.549 ;
-; 6.598 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.637 ;
-; 6.598 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.637 ;
-; 6.620 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.659 ;
-; 6.621 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.660 ;
-; 6.669 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.708 ;
-; 6.742 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.781 ;
-; 6.757 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.796 ;
-; 6.757 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.796 ;
-; 6.757 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.796 ;
-; 6.757 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.796 ;
-; 6.764 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.803 ;
-; 6.765 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.804 ;
-; 6.777 ; FS[0] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ;
-; 6.777 ; FS[0] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ;
-; 6.777 ; FS[0] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ;
-; 6.777 ; FS[0] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ;
-; 6.777 ; FS[0] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ;
-+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
++---------------------------------------------------------------------------------------------------------+
+; Hold: 'RCLK' ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 1.178 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.716 ; 4.968 ;
+; 1.189 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.716 ; 4.979 ;
+; 1.227 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.716 ; 5.017 ;
+; 1.678 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.716 ; 4.968 ;
+; 1.689 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.716 ; 4.979 ;
+; 1.727 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.716 ; 5.017 ;
+; 2.010 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.084 ;
+; 2.073 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.147 ;
+; 2.079 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.153 ;
+; 2.276 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.350 ;
+; 2.278 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.352 ;
+; 2.292 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ;
+; 2.512 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.586 ;
+; 2.607 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.681 ;
+; 2.732 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.806 ;
+; 2.766 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.840 ;
+; 2.798 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.872 ;
+; 2.803 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ;
+; 2.812 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.886 ;
+; 2.813 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ;
+; 2.823 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.897 ;
+; 2.837 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.911 ;
+; 2.842 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.916 ;
+; 2.843 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ;
+; 2.845 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.919 ;
+; 2.846 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.920 ;
+; 2.892 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.966 ;
+; 2.948 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.022 ;
+; 2.949 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ;
+; 2.949 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ;
+; 2.957 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.031 ;
+; 2.957 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.031 ;
+; 2.958 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ;
+; 2.959 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.033 ;
+; 2.961 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ;
+; 2.961 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ;
+; 2.967 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ;
+; 2.967 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ;
+; 3.029 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.103 ;
+; 3.049 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.123 ;
+; 3.191 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.265 ;
+; 3.247 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.321 ;
+; 3.266 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.340 ;
+; 3.299 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.373 ;
+; 3.382 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.456 ;
+; 3.391 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.465 ;
+; 3.393 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.467 ;
+; 3.427 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.501 ;
+; 3.487 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.561 ;
+; 3.487 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.561 ;
+; 3.533 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.607 ;
+; 3.534 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.608 ;
+; 3.544 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.618 ;
+; 3.558 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.632 ;
+; 3.563 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.637 ;
+; 3.566 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.640 ;
+; 3.646 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.720 ;
+; 3.657 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.731 ;
+; 3.671 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.745 ;
+; 3.676 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.750 ;
+; 3.679 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.753 ;
+; 3.694 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.768 ;
+; 3.731 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.805 ;
+; 3.759 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.833 ;
+; 3.782 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.856 ;
+; 3.789 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.863 ;
+; 3.797 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.871 ;
+; 3.812 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.886 ;
+; 3.813 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.887 ;
+; 3.814 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.888 ;
+; 3.822 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.896 ;
+; 3.823 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.897 ;
+; 3.824 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.898 ;
+; 3.826 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.900 ;
+; 3.839 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.913 ;
+; 3.872 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.946 ;
+; 3.875 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.949 ;
+; 3.882 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.956 ;
+; 3.911 ; Ready ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.985 ;
+; 3.926 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.000 ;
+; 3.935 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.009 ;
+; 3.936 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.010 ;
+; 3.953 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.027 ;
+; 3.956 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.030 ;
+; 3.978 ; IS[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.052 ;
+; 3.986 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.060 ;
+; 4.039 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.113 ;
+; 4.048 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.122 ;
+; 4.049 ; RCKE~reg0 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.123 ;
+; 4.149 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.223 ;
+; 4.174 ; FS[0] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ;
+; 4.174 ; FS[0] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ;
+; 4.174 ; FS[0] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ;
+; 4.174 ; FS[0] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ;
+; 4.174 ; FS[0] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.248 ;
+; 4.182 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ;
+; 4.182 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ;
+; 4.182 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ;
+; 4.182 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.256 ;
+; 4.190 ; InitReady ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.264 ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------+
@@ -699,14 +699,13 @@ No paths to report.
; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ;
; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ;
-; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ;
-; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ;
-; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ;
-; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ;
+; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ;
+; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ;
+; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ;
; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ;
; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ;
-; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ;
-; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ;
+; PHI2 ; RCLK ; 1 ; 13 ; 0 ; 0 ;
+; RCLK ; RCLK ; 618 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -722,14 +721,13 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ;
; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ;
-; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ;
-; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ;
-; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ;
-; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ;
+; PHI2 ; PHI2 ; 0 ; 1 ; 160 ; 15 ;
+; RCLK ; PHI2 ; 2 ; 0 ; 2 ; 0 ;
+; DRCLK ; RCLK ; 3 ; 0 ; 0 ; 0 ;
; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ;
; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ;
-; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ;
-; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ;
+; PHI2 ; RCLK ; 1 ; 13 ; 0 ; 0 ;
+; RCLK ; RCLK ; 618 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -754,9 +752,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 31 ; 31 ;
-; Unconstrained Input Port Paths ; 241 ; 241 ;
+; Unconstrained Input Port Paths ; 257 ; 257 ;
; Unconstrained Output Ports ; 38 ; 38 ;
-; Unconstrained Output Port Paths ; 77 ; 77 ;
+; Unconstrained Output Port Paths ; 78 ; 78 ;
+---------------------------------+-------+------+
@@ -950,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
- Info: Processing started: Sun Aug 13 00:02:11 2023
+ Info: Processing started: Sun Aug 13 01:10:58 2023
Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -976,17 +974,17 @@ Info (332146): Worst-case setup slack is -99.000
Info (332119): ========= =================== =====================
Info (332119): -99.000 -99.000 ARCLK
Info (332119): -99.000 -99.000 DRCLK
- Info (332119): -20.679 -213.940 PHI2
- Info (332119): -20.375 -594.272 RCLK
- Info (332119): -5.508 -18.066 nCRAS
-Info (332146): Worst-case hold slack is -15.989
+ Info (332119): -10.792 -122.191 PHI2
+ Info (332119): -8.864 -306.770 RCLK
+ Info (332119): -2.878 -11.627 nCRAS
+Info (332146): Worst-case hold slack is -16.715
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): -15.989 -15.989 DRCLK
- Info (332119): -14.590 -14.590 ARCLK
- Info (332119): -2.710 -3.324 PHI2
- Info (332119): -0.704 -2.798 nCRAS
- Info (332119): -0.603 -0.801 RCLK
+ Info (332119): -16.715 -16.715 DRCLK
+ Info (332119): -15.888 -15.888 ARCLK
+ Info (332119): -0.520 -0.782 PHI2
+ Info (332119): 0.622 0.000 nCRAS
+ Info (332119): 1.178 0.000 RCLK
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -29.500
@@ -1003,7 +1001,7 @@ Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4676 megabytes
- Info: Processing ended: Sun Aug 13 00:02:12 2023
+ Info: Processing ended: Sun Aug 13 01:10:59 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.summary b/CPLD/MAXV/output_files/RAM2GS.sta.summary
index 0102c16..26bc439 100644
--- a/CPLD/MAXV/output_files/RAM2GS.sta.summary
+++ b/CPLD/MAXV/output_files/RAM2GS.sta.summary
@@ -11,36 +11,36 @@ Slack : -99.000
TNS : -99.000
Type : Setup 'PHI2'
-Slack : -20.679
-TNS : -213.940
+Slack : -10.792
+TNS : -122.191
Type : Setup 'RCLK'
-Slack : -20.375
-TNS : -594.272
+Slack : -8.864
+TNS : -306.770
Type : Setup 'nCRAS'
-Slack : -5.508
-TNS : -18.066
+Slack : -2.878
+TNS : -11.627
Type : Hold 'DRCLK'
-Slack : -15.989
-TNS : -15.989
+Slack : -16.715
+TNS : -16.715
Type : Hold 'ARCLK'
-Slack : -14.590
-TNS : -14.590
+Slack : -15.888
+TNS : -15.888
Type : Hold 'PHI2'
-Slack : -2.710
-TNS : -3.324
+Slack : -0.520
+TNS : -0.782
Type : Hold 'nCRAS'
-Slack : -0.704
-TNS : -2.798
+Slack : 0.622
+TNS : 0.000
Type : Hold 'RCLK'
-Slack : -0.603
-TNS : -0.801
+Slack : 1.178
+TNS : 0.000
Type : Minimum Pulse Width 'ARCLK'
Slack : -29.500
diff --git a/CPLD/MAXV/output_files/greybox_tmp/cbx_args.txt b/CPLD/MAXV/output_files/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..1493d8a
--- /dev/null
+++ b/CPLD/MAXV/output_files/greybox_tmp/cbx_args.txt
@@ -0,0 +1,25 @@
+ERASE_TIME=500000000
+INTENDED_DEVICE_FAMILY="MAX V"
+LPM_FILE=RAM2GS.mif
+LPM_HINT=UNUSED
+LPM_TYPE=altufm_none
+OSC_FREQUENCY=180000
+PORT_ARCLKENA=PORT_UNUSED
+PORT_DRCLKENA=PORT_UNUSED
+PROGRAM_TIME=1600000
+WIDTH_UFM_ADDRESS=9
+DEVICE_FAMILY="MAX V"
+CBX_AUTO_BLACKBOX=ALL
+arclk
+ardin
+arshft
+busy
+drclk
+drdin
+drdout
+drshft
+erase
+osc
+oscena
+program
+rtpbusy
diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v
index 1477a0b..c97b46a 100644
--- a/CPLD/RAM2GS-MAX.v
+++ b/CPLD/RAM2GS-MAX.v
@@ -19,7 +19,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
/* Activity LED */
reg LEDEN = 0;
output LED;
- assign LED = !(!nCRAS && !CBR && !LEDEN);
+ assign LED = !(!nCRAS && !CBR && LEDEN);
/* 65816 Data */
input [7:0] Din;
@@ -398,17 +398,25 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
// Capture bit 15 of this UFM word in UFMD register
if (FS[3:0]==4'h7) UFMD <= DRDOut;
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
- // Check saved capacity entry
+ // Shift UFM data shift register
+ ARCLK <= 1'b0; // Don't clock address register
+ ARShift <= 1'b0; // ARShift is don't care
+ DRCLK <= FS[3]; // Clock data register
+ DRDIn <= 1'b0; // DRDIn is don't care
+ DRShift <= 1'b1; // Shift data register
+ // If valid setting here, set capacity setting to UFMD[14]
+ if (FS[3:0]==4'h7 && ~UFMD) n8MEGEN <= ~DRDOut;
+ end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
else begin // If valid setting here
- n8MEGEN <= ~DRDOut; // Set capacity setting
+ LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
// If last byte in sector, mark need to erase
if (FS[15:8]==8'hFF) begin
UFMReqErase <= 1'b1; // Mark need to wrap around
UFMInitDone <= 1'b1; // Quit iterating
end
end
- end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
+
// Increment UFM address
ARCLK <= FS[3]; // Clock address register
ARShift <= 1'b0; // Increment UFM address
@@ -442,6 +450,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
// Set user command signals after PHI2 falls
if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+ LEDEN <= CmdLEDEN;
n8MEGEN <= Cmdn8MEGEN;
DRCLK <= CmdDRCLK;
DRDIn <= CmdDRDIn;
diff --git a/CPLD/RAM2GS.mif b/CPLD/RAM2GS.mif
deleted file mode 100644
index 65c8441..0000000
--- a/CPLD/RAM2GS.mif
+++ /dev/null
@@ -1,27 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and its AMPP partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, Altera MegaCore Function License
--- Agreement, or other applicable license agreement, including,
--- without limitation, that your use is for the sole purpose of
--- programming logic devices manufactured by Altera and sold by
--- Altera or its authorized distributors. Please refer to the
--- applicable agreement for further details.
-
--- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=16;
-DEPTH=512;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
- [000..0FD] : 0000;
- 0FE : 7FFF;
- [0FF..1FF] : FFFF;
-END;
diff --git a/CPLD/RAM2GS.qsf b/CPLD/RAM2GS.qsf
deleted file mode 100644
index ad6ce4f..0000000
--- a/CPLD/RAM2GS.qsf
+++ /dev/null
@@ -1,216 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 21:16:34 March 08, 2020
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# RAM4GS_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE EPM240T100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name SDC_FILE constraints.sdc
-set_global_assignment -name VERILOG_FILE RAM4GS.v
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-set_global_assignment -name SMART_RECOMPILE OFF
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
-set_global_assignment -name SAFE_STATE_MACHINE ON
-
-
-
-set_global_assignment -name MIF_FILE RAM4GS.mif
-set_global_assignment -name QIP_FILE UFM.qip
-
-
-
-set_location_assignment PIN_12 -to RCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
-
-set_location_assignment PIN_52 -to PHI2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
-
-set_location_assignment PIN_67 -to nCRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
-
-set_location_assignment PIN_53 -to nCCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
-
-set_location_assignment PIN_48 -to nFWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
-
-set_location_assignment PIN_49 -to MAin[0]
-set_location_assignment PIN_51 -to MAin[1]
-set_location_assignment PIN_50 -to MAin[2]
-set_location_assignment PIN_71 -to MAin[3]
-set_location_assignment PIN_70 -to MAin[4]
-set_location_assignment PIN_69 -to MAin[5]
-set_location_assignment PIN_72 -to MAin[6]
-set_location_assignment PIN_68 -to MAin[7]
-set_location_assignment PIN_73 -to MAin[8]
-set_location_assignment PIN_74 -to MAin[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
-
-set_location_assignment PIN_54 -to CROW[0]
-set_location_assignment PIN_55 -to CROW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
-
-set_location_assignment PIN_35 -to Din[2]
-set_location_assignment PIN_36 -to Din[1]
-set_location_assignment PIN_37 -to Din[3]
-set_location_assignment PIN_38 -to Din[5]
-set_location_assignment PIN_39 -to Din[4]
-set_location_assignment PIN_40 -to Din[7]
-set_location_assignment PIN_41 -to Din[6]
-set_location_assignment PIN_42 -to Din[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
-
-set_location_assignment PIN_33 -to Dout[0]
-set_location_assignment PIN_57 -to Dout[1]
-set_location_assignment PIN_56 -to Dout[2]
-set_location_assignment PIN_47 -to Dout[3]
-set_location_assignment PIN_44 -to Dout[4]
-set_location_assignment PIN_28 -to Dout[5]
-set_location_assignment PIN_34 -to Dout[6]
-set_location_assignment PIN_43 -to Dout[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
-
-set_location_assignment PIN_8 -to RCKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
-
-set_location_assignment PIN_3 -to nRCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
-
-set_location_assignment PIN_100 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-
-set_location_assignment PIN_6 -to nRRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
-
-set_location_assignment PIN_4 -to nRCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
-
-set_location_assignment PIN_5 -to RBA[0]
-set_location_assignment PIN_14 -to RBA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
-
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-
-set_location_assignment PIN_2 -to RDQMH
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
-
-set_location_assignment PIN_98 -to RDQML
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
-
-set_location_assignment PIN_96 -to RD[0]
-set_location_assignment PIN_90 -to RD[1]
-set_location_assignment PIN_89 -to RD[2]
-set_location_assignment PIN_99 -to RD[3]
-set_location_assignment PIN_92 -to RD[4]
-set_location_assignment PIN_91 -to RD[5]
-set_location_assignment PIN_95 -to RD[6]
-set_location_assignment PIN_97 -to RD[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
-
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD