Create folders for all board layouts

Hardware/AGM/cpld-src/RAM4GS.v

@@ -0,0 +1,406 @@
+module RAM4GS(PHI2, MAin, CROW, Din, Dout,
+			  nCCAS, nCRAS, nFWE,
+			  RBA, RA, RD, nRCS, RCLK, RCKE,
+			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
+			  nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout,
+			  nUFMCSin , UFMCLKin , UFMSDIin , UFMSDOin);
+
+	/* 65816 Phase 2 Clock */
+	input PHI2;
+
+	/* Async. DRAM Control Inputs */
+	input nCCAS, nCRAS;
+
+	/* Synchronized PHI2 and DRAM signals */
+	reg PHI2r, PHI2r2, PHI2r3;
+	reg RASr, RASr2, RASr3;
+	reg CASr, CASr2, CASr3;
+	reg FWEr;
+	reg CBR;
+
+	/* 65816 Data */
+	input [7:0] Din;
+	output [7:0] Dout = RD[7:0];
+
+	/* Latched 65816 Bank Address */
+	reg [7:0] Bank;
+
+	/* Async. DRAM Address Bus */
+	input [1:0] CROW;
+	input [9:0] MAin;
+	input nFWE;
+	reg n8MEGEN = 0;
+	reg XOR8MEG = 0;
+	
+	/* SDRAM Clock */
+	input RCLK;
+	
+	/* SDRAM */
+	reg RCKEEN;
+	output reg RCKE = 0;
+	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
+	output reg [1:0] RBA;
+	reg nRowColSel;
+	reg RA11;
+	reg RA10;
+	reg [9:0] RowA;
+	output [11:0] RA;
+	assign RA[11] = RA11;
+	assign RA[10] = RA10;
+	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
+	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
+	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
+	reg [7:0] WRD;
+	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
+
+	/* UFM Interface */
+	reg nUFMCS = 1;
+	reg UFMCLK = 0;
+	reg UFMSDI = 0;
+	wire UFMSDO;
+	wire UFMOsc;
+	alta_ufms u_alta_ufms (
+		.i_ufm_set (1'b1), 
+		.i_osc_ena (1'b1), 
+		.i_ufm_flash_csn (nUFMCS), 
+		.i_ufm_flash_sclk (UFMCLK), 
+		.i_ufm_flash_sdi (UFMSDI), 
+		.o_ufm_flash_sdo (UFMSDO), 
+		.o_osc (UFMOsc) 
+	);
+
+	/* UFM Command Interface */
+	reg C1Submitted = 0;
+	reg ADSubmitted = 0;
+	reg CmdEnable = 0;
+	reg CmdSubmitted = 0;
+	reg Cmdn8MEGEN = 0;
+	reg CmdUFMCLK = 0;
+	reg CmdUFMSDI = 0;
+	reg CmdUFMCS = 0;
+	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
+	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
+	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
+	
+	/* State Counters */
+	reg InitReady = 0; // 1 if ready for init sequence
+	reg Ready = 0; // 1 if done with init sequence
+	reg [1:0] S = 0; // post-RAS State counter
+	reg [17:0] FS = 0; // Fast init state counter
+	reg [3:0] IS = 0; // Init state counter
+	reg WriteDone;
+	
+	/* Synchronize PHI2, RAS, CAS */
+	always @(posedge RCLK) begin
+		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
+		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
+		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
+	end
+	
+	/* Latch 65816 bank when PHI2 rises */
+	always @(posedge PHI2) begin
+		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
+		else RA11 <= 1'b0; // Reserved in mode register
+		Bank[7:0] <= Din[7:0]; // Latch bank
+	end
+	
+	/* Latch bank address, row address, WE, and CAS when RAS falls */
+	always @(negedge nCRAS) begin
+		if (Ready) begin
+			RBA[1:0] <= CROW[1:0];
+			RowA[9:0] <= MAin[9:0];
+		end else begin
+			RBA[1:0] <= 2'b00;		// Reserved in mode register
+			RowA[9] <= 1'b1;		// "1" for single write mode
+			RowA[8] <= 1'b0;		// Reserved
+			RowA[7] <= 1'b0;		// "0" for not test mode
+			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
+			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
+			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
+		end
+		FWEr <= ~nFWE;
+		CBR <= ~nCCAS;
+	end
+
+	/* Latch write data when CAS falls */
+	always @(negedge nCCAS) begin
+		WRD[7:0] <= Din[7:0];
+	end
+
+	/* State counter from RAS */
+	always @(posedge RCLK) begin
+		if (~RASr2) S <= 0;
+		else if (S==2'h3) S <= 2'h3;
+		else S <= S+1;
+	end
+	/* Init state counter */
+	always @(posedge RCLK) begin
+		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
+		FS <= FS+1;
+		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
+	end
+
+	/* SDRAM CKE */
+	always @(posedge RCLK) begin
+		// Only 1 LUT4 allowed for this function!
+		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
+	end
+
+	/* SDRAM command */
+	always @(posedge RCLK) begin
+		if (Ready) begin
+			if (S==0) begin
+				if (RASr2) begin
+					if (CBR) begin
+						// AREF
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b0;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // RA10 is don't care
+					end else begin
+						// ACT
+						nRCS <= 1'b0;
+						nRRAS <= 1'b0;
+						nRCAS <= 1'b1;
+						nRWE <= 1'b1;
+						RA10 <= 1'b1; // Bank RA10 consistently "1"
+					end
+					// Enable clock only for reads
+					RCKEEN <= ~CBR & ~FWEr;
+				end else if (RCKE) begin
+					// PCall
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+					RCKEEN <= 1'b1;
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+					RCKEEN <= 1'b1;
+				end
+				nRowColSel <= 1'b0; // Select registered row addres
+			end else if (S==1) begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR; // Disable clock if refresh cycle
+			end else if (S==2) begin
+				if (~FWEr & ~CBR) begin
+					// RD
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= 1'b1; // Select asynchronous column address
+				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
+			end else if (S==3) begin
+				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
+					// WR
+					nRCS <= 1'b0;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // Auto-precharge
+				end else begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				nRowColSel <= ~(~FWEr | CASr3 | CBR);
+				RCKEEN <= ~(~FWEr | CASr2 | CBR);
+			end
+		end else if (InitReady) begin
+			if (S==0 & RASr2) begin
+				if (IS==0) begin
+					// NOP
+					nRCS <= 1'b1;
+					nRRAS <= 1'b1;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end else if (IS==1) begin
+					// PC all
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b1;
+					nRWE <= 1'b0;
+					RA10 <= 1'b1; // "all"
+				end else if (IS==9) begin
+					// Load mode register
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b0;
+					RA10 <= 1'b0; // Reserved in mode register
+				end else begin
+					// AREF
+					nRCS <= 1'b0;
+					nRRAS <= 1'b0;
+					nRCAS <= 1'b0;
+					nRWE <= 1'b1;
+					RA10 <= 1'b1; // RA10 is don't care
+				end
+				IS <= IS+1;
+			end else begin
+				// NOP
+				nRCS <= 1'b1;
+				nRRAS <= 1'b1;
+				nRCAS <= 1'b1;
+				nRWE <= 1'b1;
+				RA10 <= 1'b1; // RA10 is don't care
+			end
+			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b1;
+		end else begin
+			// NOP
+			nRCS <= 1'b1;
+			nRRAS <= 1'b1;
+			nRCAS <= 1'b1;
+			nRWE <= 1'b1;
+			RA10 <= 1'b1; // RA10 is don't care
+			nRowColSel <= 1'b0; // Select registered row address
+			RCKEEN <= 1'b0;
+		end
+	end
+	
+	/* Submit command when PHI2 falls */
+	always @(negedge PHI2) begin
+		// Magic number check
+		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
+			if (ADSubmitted) begin
+				CmdEnable <= 1'b1;
+			end
+			C1Submitted <= 1'b1;
+			ADSubmitted <= 1'b0;
+		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
+			if (C1Submitted) begin
+				CmdEnable <= 1'b1;
+			end
+			ADSubmitted <= 1'b1;
+			C1Submitted <= 1'b0;
+		end else if (C1WR | ADWR) begin // wrong magic number submitted
+			CmdEnable <= 1'b0;
+			C1Submitted <= 1'b0;
+			ADSubmitted <= 1'b0;
+		end else if (CMDWR) CmdEnable <= 1'b0;
+
+		// Submit command
+		if (CMDWR & CmdEnable) begin
+			if (Din[7:4]==4'h0) begin
+				XOR8MEG <= Din[0];
+			end else if (Din[7:4]==4'h1) begin
+				Cmdn8MEGEN <= ~Din[0];
+				CmdSubmitted <= 1'b1;
+			end else if (Din[7:4]==4'h3) begin
+				Cmdn8MEGEN <= n8MEGEN;
+				CmdUFMCS <= Din[2];
+				CmdUFMCLK <= Din[1];
+				CmdUFMSDI <= Din[0];
+				CmdSubmitted <= 1'b1;
+			end
+		end
+	end
+
+	/* UFM Control */
+	output nUFMCSout = nUFMCS;
+	output UFMCLKout = UFMCLK;
+	output UFMSDIout = UFMSDI;
+	output UFMSDOout = UFMSDO;
+	input nUFMCSin;
+	input UFMCLKin;
+	input UFMSDIin;
+	input UFMSDOin;
+	always @(posedge RCLK) begin
+		if (~InitReady && FS[17:10]==8'h00) begin
+			nUFMCS <= 1'b1;
+			UFMCLK <= 1'b0;
+			UFMSDI <= 1'b0;
+		end else if (~InitReady && FS[17:10]==8'h01) begin
+			nUFMCS <= 1'b0;
+			UFMCLK <= 1'b0;
+			UFMSDI <= 1'b0;
+		end else if (~InitReady && FS[17:10]==8'h02) begin
+			nUFMCS <= 1'b0;
+			UFMCLK <= FS[4];
+			case (FS[9:5]) // Shift out read data command (0x03)
+				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
+				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
+				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
+				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
+				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
+				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
+				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
+				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
+				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
+				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
+				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
+				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
+				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
+				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
+				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
+				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
+				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
+				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
+				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
+				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
+				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
+				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
+				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
+				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
+				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
+				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
+				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
+				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
+				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
+				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
+				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
+				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
+			endcase
+		end else if (~InitReady && FS[17:10]==8'h03) begin
+			nUFMCS <= 1'b0;
+			UFMCLK <= 1'b0;
+			UFMSDI <= 1'b0;
+			// Latch n8MEGEN
+			if (FS[9:4]==6'h00 && FS[3:0]==4'hF) n8MEGEN <= ~UFMSDO;
+		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
+			nUFMCS <= 1'b0;
+			UFMCLK <= FS[1];
+			UFMSDI <= 1'b0;
+		end else if (~InitReady) begin
+			nUFMCS <= 1'b1;
+			UFMCLK <= 1'b0;
+			UFMSDI <= 1'b0;
+		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
+			// Set user command signals after PHI2 falls
+			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
+			n8MEGEN <= Cmdn8MEGEN;
+			nUFMCS <= ~CmdUFMCS;
+			UFMCLK <= CmdUFMCLK;
+			UFMSDI <= CmdUFMSDI;
+		end
+	end
+endmodule

Hardware/MAX/cpld/RAM4GS.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 21:16:34  March 08, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "21:16:34  March 08, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "RAM4GS"

Hardware/MAX/cpld/RAM4GS.qsf

@@ -0,0 +1,213 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 21:16:34  March 08, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		RAM4GS_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34  MARCH 08, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name SDC_FILE constraints.sdc
+set_global_assignment -name VERILOG_FILE RAM4GS.v
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name SMART_RECOMPILE OFF
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
+set_global_assignment -name SAFE_STATE_MACHINE ON
+
+
+
+set_location_assignment PIN_12 -to RCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
+
+set_location_assignment PIN_52 -to PHI2
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
+
+set_location_assignment PIN_67 -to nCRAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
+
+set_location_assignment PIN_53 -to nCCAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
+
+set_location_assignment PIN_48 -to nFWE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
+
+set_location_assignment PIN_49 -to MAin[0]
+set_location_assignment PIN_51 -to MAin[1]
+set_location_assignment PIN_50 -to MAin[2]
+set_location_assignment PIN_71 -to MAin[3]
+set_location_assignment PIN_70 -to MAin[4]
+set_location_assignment PIN_69 -to MAin[5]
+set_location_assignment PIN_72 -to MAin[6]
+set_location_assignment PIN_68 -to MAin[7]
+set_location_assignment PIN_73 -to MAin[8]
+set_location_assignment PIN_74 -to MAin[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
+
+set_location_assignment PIN_54 -to CROW[0]
+set_location_assignment PIN_55 -to CROW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
+
+set_location_assignment PIN_35 -to Din[2]
+set_location_assignment PIN_36 -to Din[1]
+set_location_assignment PIN_37 -to Din[3]
+set_location_assignment PIN_38 -to Din[5]
+set_location_assignment PIN_39 -to Din[4]
+set_location_assignment PIN_40 -to Din[7]
+set_location_assignment PIN_41 -to Din[6]
+set_location_assignment PIN_42 -to Din[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
+
+set_location_assignment PIN_33 -to Dout[0]
+set_location_assignment PIN_57 -to Dout[1]
+set_location_assignment PIN_56 -to Dout[2]
+set_location_assignment PIN_47 -to Dout[3]
+set_location_assignment PIN_44 -to Dout[4]
+set_location_assignment PIN_28 -to Dout[5]
+set_location_assignment PIN_34 -to Dout[6]
+set_location_assignment PIN_43 -to Dout[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
+
+set_location_assignment PIN_8 -to RCKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
+
+set_location_assignment PIN_3 -to nRCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
+
+set_location_assignment PIN_100 -to nRWE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
+
+set_location_assignment PIN_6 -to nRRAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
+
+set_location_assignment PIN_4 -to nRCAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
+
+set_location_assignment PIN_5 -to RBA[0]
+set_location_assignment PIN_14 -to RBA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
+
+set_location_assignment PIN_18 -to RA[0]
+set_location_assignment PIN_20 -to RA[1]
+set_location_assignment PIN_30 -to RA[2]
+set_location_assignment PIN_27 -to RA[3]
+set_location_assignment PIN_26 -to RA[4]
+set_location_assignment PIN_29 -to RA[5]
+set_location_assignment PIN_21 -to RA[6]
+set_location_assignment PIN_19 -to RA[7]
+set_location_assignment PIN_17 -to RA[8]
+set_location_assignment PIN_15 -to RA[9]
+set_location_assignment PIN_16 -to RA[10]
+set_location_assignment PIN_7 -to RA[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
+
+set_location_assignment PIN_2 -to RDQMH
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
+
+set_location_assignment PIN_98 -to RDQML
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
+
+set_location_assignment PIN_96 -to RD[0]
+set_location_assignment PIN_90 -to RD[1]
+set_location_assignment PIN_89 -to RD[2]
+set_location_assignment PIN_99 -to RD[3]
+set_location_assignment PIN_92 -to RD[4]
+set_location_assignment PIN_91 -to RD[5]
+set_location_assignment PIN_95 -to RD[6]
+set_location_assignment PIN_97 -to RD[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
+
+set_global_assignment -name MIF_FILE RAM4GS.mif
+set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
+set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
+set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
+set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
+set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
+set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
+set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
+set_global_assignment -name QIP_FILE UFM.qip

Hardware/MAX/cpld/db/RAM4GS.asm.qmsg

@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}

Hardware/MAX/cpld/db/RAM4GS.cmp.logdb

@@ -0,0 +1 @@
+v1