From ff249330379f2d65f5e9a1e08b8636720c0a18ca Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sat, 12 Aug 2023 23:53:25 -0400 Subject: [PATCH] so far so good --- CPLD-old/MAX/RAM2GS-MAX.v | 10 +- CPLD/MAXII/RAM2GS.qsf | 146 ++- CPLD/MAXII/RAM2GS.qws | Bin 1217 -> 635 bytes CPLD/MAXII/UFM.qip | 4 + CPLD/MAXII/UFM.v | 257 +++++ CPLD/MAXII/db/.cmp.kpt | Bin 0 -> 204 bytes CPLD/MAXII/db/RAM2GS.(0).cnf.cdb | Bin 0 -> 20054 bytes CPLD/MAXII/db/RAM2GS.(0).cnf.hdb | Bin 0 -> 3613 bytes CPLD/MAXII/db/RAM2GS.(1).cnf.cdb | Bin 0 -> 1388 bytes CPLD/MAXII/db/RAM2GS.(1).cnf.hdb | Bin 0 -> 924 bytes CPLD/MAXII/db/RAM2GS.(2).cnf.cdb | Bin 0 -> 1601 bytes CPLD/MAXII/db/RAM2GS.(2).cnf.hdb | Bin 0 -> 1385 bytes CPLD/MAXII/db/RAM2GS.asm.qmsg | 7 + CPLD/MAXII/db/RAM2GS.asm.rdb | Bin 0 -> 808 bytes CPLD/MAXII/db/RAM2GS.asm_labs.ddb | Bin 0 -> 2641 bytes CPLD/MAXII/db/RAM2GS.cmp.cdb | Bin 0 -> 42776 bytes CPLD/MAXII/db/RAM2GS.cmp.hdb | Bin 0 -> 18436 bytes CPLD/MAXII/db/RAM2GS.cmp.idb | Bin 0 -> 2717 bytes CPLD/MAXII/db/RAM2GS.cmp.logdb | 1 + CPLD/MAXII/db/RAM2GS.cmp.rdb | Bin 3657 -> 14228 bytes CPLD/MAXII/db/RAM2GS.cmp0.ddb | Bin 0 -> 75185 bytes CPLD/MAXII/db/RAM2GS.db_info | 2 +- CPLD/MAXII/db/RAM2GS.fit.qmsg | 45 + CPLD/MAXII/db/RAM2GS.hier_info | 277 +++++ CPLD/MAXII/db/RAM2GS.hif | Bin 178 -> 598 bytes CPLD/MAXII/db/RAM2GS.lpc.html | 50 + CPLD/MAXII/db/RAM2GS.lpc.rdb | Bin 0 -> 495 bytes CPLD/MAXII/db/RAM2GS.lpc.txt | 8 + CPLD/MAXII/db/RAM2GS.map.cdb | Bin 0 -> 17424 bytes CPLD/MAXII/db/RAM2GS.map.hdb | Bin 8969 -> 17470 bytes CPLD/MAXII/db/RAM2GS.map.logdb | 1 + CPLD/MAXII/db/RAM2GS.map.qmsg | 37 +- CPLD/MAXII/db/RAM2GS.map.rdb | Bin 1049 -> 1261 bytes CPLD/MAXII/db/RAM2GS.pre_map.hdb | Bin 8902 -> 16509 bytes .../db/RAM2GS.root_partition.map.reg_db.cdb | Bin 0 -> 219 bytes CPLD/MAXII/db/RAM2GS.routing.rdb | Bin 0 -> 1539 bytes CPLD/MAXII/db/RAM2GS.rtlv.hdb | Bin 0 -> 16259 bytes CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb | Bin 0 -> 18369 bytes CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb | Bin 0 -> 840 bytes CPLD/MAXII/db/RAM2GS.sld_design_entry_dsc.sci | Bin 0 -> 223 bytes CPLD/MAXII/db/RAM2GS.smart_action.txt | 2 +- CPLD/MAXII/db/RAM2GS.sta.qmsg | 25 + CPLD/MAXII/db/RAM2GS.sta.rdb | Bin 0 -> 13012 bytes CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb | Bin 0 -> 45189 bytes CPLD/MAXII/db/RAM2GS.tmw_info | 3 + CPLD/MAXII/db/RAM2GS.vpr.ammdb | Bin 0 -> 630 bytes CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg | 113 ++ CPLD/MAXII/greybox_tmp/cbx_args.txt | 25 + CPLD/MAXII/incremental_db/README | 11 + .../compiled_partitions/RAM2GS.db_info | 3 + .../RAM2GS.root_partition.map.kpt | Bin 0 -> 2590 bytes CPLD/MAXII/output_files/RAM2GS.asm.rpt | 92 ++ CPLD/MAXII/output_files/RAM2GS.cdf | 13 + CPLD/MAXII/output_files/RAM2GS.done | 1 + CPLD/MAXII/output_files/RAM2GS.fit.rpt | 759 +++++++++++++ CPLD/MAXII/output_files/RAM2GS.fit.smsg | 4 + CPLD/MAXII/output_files/RAM2GS.fit.summary | 11 + CPLD/MAXII/output_files/RAM2GS.flow.rpt | 25 +- CPLD/MAXII/output_files/RAM2GS.jdi | 8 + CPLD/MAXII/output_files/RAM2GS.map.rpt | 183 ++- CPLD/MAXII/output_files/RAM2GS.map.smsg | 3 + CPLD/MAXII/output_files/RAM2GS.map.summary | 6 +- CPLD/MAXII/output_files/RAM2GS.pin | 165 +++ CPLD/MAXII/output_files/RAM2GS.pof | Bin 0 -> 7861 bytes CPLD/MAXII/output_files/RAM2GS.sld | 1 + CPLD/MAXII/output_files/RAM2GS.sta.rpt | 1006 ++++++++++++++++ CPLD/MAXII/output_files/RAM2GS.sta.summary | 69 ++ CPLD/MAXV/RAM2GS.qsf | 152 ++- CPLD/MAXV/RAM2GS.qws | Bin 619 -> 0 bytes CPLD/MAXV/UFM.qip | 4 + CPLD/MAXV/UFM.v | 257 +++++ CPLD/MAXV/db/.cmp.kpt | Bin 0 -> 204 bytes CPLD/MAXV/db/RAM2GS.(0).cnf.cdb | Bin 0 -> 20082 bytes CPLD/MAXV/db/RAM2GS.(0).cnf.hdb | Bin 0 -> 3762 bytes CPLD/MAXV/db/RAM2GS.(1).cnf.cdb | Bin 0 -> 1388 bytes CPLD/MAXV/db/RAM2GS.(1).cnf.hdb | Bin 0 -> 902 bytes CPLD/MAXV/db/RAM2GS.(2).cnf.cdb | Bin 0 -> 1589 bytes CPLD/MAXV/db/RAM2GS.(2).cnf.hdb | Bin 0 -> 1384 bytes CPLD/MAXV/db/RAM2GS.asm.qmsg | 7 + CPLD/MAXV/db/RAM2GS.asm.rdb | Bin 0 -> 809 bytes CPLD/MAXV/db/RAM2GS.asm_labs.ddb | Bin 0 -> 2721 bytes CPLD/MAXV/db/RAM2GS.cmp.cdb | Bin 0 -> 42997 bytes CPLD/MAXV/db/RAM2GS.cmp.hdb | Bin 0 -> 18368 bytes CPLD/MAXV/db/RAM2GS.cmp.idb | Bin 0 -> 2725 bytes CPLD/MAXV/db/RAM2GS.cmp.logdb | 1 + CPLD/MAXV/db/RAM2GS.cmp.rdb | Bin 3615 -> 14168 bytes CPLD/MAXV/db/RAM2GS.cmp0.ddb | Bin 0 -> 79103 bytes CPLD/MAXV/db/RAM2GS.db_info | 2 +- CPLD/MAXV/db/RAM2GS.fit.qmsg | 45 + CPLD/MAXV/db/RAM2GS.hier_info | 279 +++++ CPLD/MAXV/db/RAM2GS.hif | Bin 177 -> 573 bytes CPLD/MAXV/db/RAM2GS.lpc.html | 50 + CPLD/MAXV/db/RAM2GS.lpc.rdb | Bin 0 -> 496 bytes CPLD/MAXV/db/RAM2GS.lpc.txt | 8 + CPLD/MAXV/db/RAM2GS.map.cdb | Bin 0 -> 17594 bytes CPLD/MAXV/db/RAM2GS.map.hdb | Bin 8903 -> 17438 bytes CPLD/MAXV/db/RAM2GS.map.logdb | 1 + CPLD/MAXV/db/RAM2GS.map.qmsg | 38 +- CPLD/MAXV/db/RAM2GS.map.rdb | Bin 1049 -> 1263 bytes CPLD/MAXV/db/RAM2GS.pplq.rdb | Bin 0 -> 297 bytes CPLD/MAXV/db/RAM2GS.pre_map.hdb | Bin 8837 -> 16238 bytes .../db/RAM2GS.root_partition.map.reg_db.cdb | Bin 0 -> 219 bytes CPLD/MAXV/db/RAM2GS.routing.rdb | Bin 0 -> 1544 bytes CPLD/MAXV/db/RAM2GS.rtlv.hdb | Bin 0 -> 16184 bytes CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb | Bin 0 -> 18324 bytes CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb | Bin 0 -> 839 bytes CPLD/MAXV/db/RAM2GS.sld_design_entry_dsc.sci | Bin 0 -> 223 bytes CPLD/MAXV/db/RAM2GS.smart_action.txt | 2 +- CPLD/MAXV/db/RAM2GS.sta.qmsg | 25 + CPLD/MAXV/db/RAM2GS.sta.rdb | Bin 0 -> 13512 bytes CPLD/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb | Bin 0 -> 45869 bytes CPLD/MAXV/db/RAM2GS.tmw_info | 6 + CPLD/MAXV/db/RAM2GS.vpr.ammdb | Bin 0 -> 635 bytes CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg | 114 ++ CPLD/MAXV/greybox_tmp/cbx_args.txt | 25 + CPLD/MAXV/incremental_db/README | 11 + .../compiled_partitions/RAM2GS.db_info | 3 + .../RAM2GS.root_partition.map.kpt | Bin 0 -> 2621 bytes CPLD/MAXV/output_files/RAM2GS.asm.rpt | 92 ++ CPLD/MAXV/output_files/RAM2GS.cdf | 13 + CPLD/MAXV/output_files/RAM2GS.done | 1 + CPLD/MAXV/output_files/RAM2GS.fit.rpt | 764 +++++++++++++ CPLD/MAXV/output_files/RAM2GS.fit.smsg | 4 + CPLD/MAXV/output_files/RAM2GS.fit.summary | 11 + CPLD/MAXV/output_files/RAM2GS.flow.rpt | 25 +- CPLD/MAXV/output_files/RAM2GS.jdi | 8 + CPLD/MAXV/output_files/RAM2GS.map.rpt | 183 ++- CPLD/MAXV/output_files/RAM2GS.map.smsg | 3 + CPLD/MAXV/output_files/RAM2GS.map.summary | 6 +- CPLD/MAXV/output_files/RAM2GS.pin | 165 +++ CPLD/MAXV/output_files/RAM2GS.pof | Bin 0 -> 7861 bytes CPLD/MAXV/output_files/RAM2GS.sld | 1 + CPLD/MAXV/output_files/RAM2GS.sta.rpt | 1010 +++++++++++++++++ CPLD/MAXV/output_files/RAM2GS.sta.summary | 69 ++ CPLD/RAM2GS-MAX.v | 18 +- CPLD/RAM2GS.mif | 27 + CPLD/RAM2GS.qsf | 7 +- 137 files changed, 6736 insertions(+), 74 deletions(-) create mode 100644 CPLD/MAXII/UFM.qip create mode 100644 CPLD/MAXII/UFM.v create mode 100644 CPLD/MAXII/db/.cmp.kpt create mode 100644 CPLD/MAXII/db/RAM2GS.(0).cnf.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.(0).cnf.hdb create mode 100644 CPLD/MAXII/db/RAM2GS.(1).cnf.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.(1).cnf.hdb create mode 100644 CPLD/MAXII/db/RAM2GS.(2).cnf.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.(2).cnf.hdb create mode 100644 CPLD/MAXII/db/RAM2GS.asm.qmsg create mode 100644 CPLD/MAXII/db/RAM2GS.asm.rdb create mode 100644 CPLD/MAXII/db/RAM2GS.asm_labs.ddb create mode 100644 CPLD/MAXII/db/RAM2GS.cmp.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.cmp.hdb create mode 100644 CPLD/MAXII/db/RAM2GS.cmp.idb create mode 100644 CPLD/MAXII/db/RAM2GS.cmp.logdb create mode 100644 CPLD/MAXII/db/RAM2GS.cmp0.ddb create mode 100644 CPLD/MAXII/db/RAM2GS.fit.qmsg create mode 100644 CPLD/MAXII/db/RAM2GS.hier_info create mode 100644 CPLD/MAXII/db/RAM2GS.lpc.html create mode 100644 CPLD/MAXII/db/RAM2GS.lpc.rdb create mode 100644 CPLD/MAXII/db/RAM2GS.lpc.txt create mode 100644 CPLD/MAXII/db/RAM2GS.map.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.map.logdb create mode 100644 CPLD/MAXII/db/RAM2GS.root_partition.map.reg_db.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.routing.rdb create mode 100644 CPLD/MAXII/db/RAM2GS.rtlv.hdb create mode 100644 CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb create mode 100644 CPLD/MAXII/db/RAM2GS.sld_design_entry_dsc.sci create mode 100644 CPLD/MAXII/db/RAM2GS.sta.qmsg create mode 100644 CPLD/MAXII/db/RAM2GS.sta.rdb create mode 100644 CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb create mode 100644 CPLD/MAXII/db/RAM2GS.tmw_info create mode 100644 CPLD/MAXII/db/RAM2GS.vpr.ammdb create mode 100644 CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg create mode 100644 CPLD/MAXII/greybox_tmp/cbx_args.txt create mode 100644 CPLD/MAXII/incremental_db/README create mode 100644 CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info create mode 100644 CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt create mode 100644 CPLD/MAXII/output_files/RAM2GS.asm.rpt create mode 100644 CPLD/MAXII/output_files/RAM2GS.cdf create mode 100644 CPLD/MAXII/output_files/RAM2GS.done create mode 100644 CPLD/MAXII/output_files/RAM2GS.fit.rpt create mode 100644 CPLD/MAXII/output_files/RAM2GS.fit.smsg create mode 100644 CPLD/MAXII/output_files/RAM2GS.fit.summary create mode 100644 CPLD/MAXII/output_files/RAM2GS.jdi create mode 100644 CPLD/MAXII/output_files/RAM2GS.map.smsg create mode 100644 CPLD/MAXII/output_files/RAM2GS.pin create mode 100644 CPLD/MAXII/output_files/RAM2GS.pof create mode 100644 CPLD/MAXII/output_files/RAM2GS.sld create mode 100644 CPLD/MAXII/output_files/RAM2GS.sta.rpt create mode 100644 CPLD/MAXII/output_files/RAM2GS.sta.summary delete mode 100644 CPLD/MAXV/RAM2GS.qws create mode 100644 CPLD/MAXV/UFM.qip create mode 100644 CPLD/MAXV/UFM.v create mode 100644 CPLD/MAXV/db/.cmp.kpt create mode 100644 CPLD/MAXV/db/RAM2GS.(0).cnf.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.(0).cnf.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.(1).cnf.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.(1).cnf.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.(2).cnf.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.(2).cnf.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.asm.qmsg create mode 100644 CPLD/MAXV/db/RAM2GS.asm.rdb create mode 100644 CPLD/MAXV/db/RAM2GS.asm_labs.ddb create mode 100644 CPLD/MAXV/db/RAM2GS.cmp.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.cmp.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.cmp.idb create mode 100644 CPLD/MAXV/db/RAM2GS.cmp.logdb create mode 100644 CPLD/MAXV/db/RAM2GS.cmp0.ddb create mode 100644 CPLD/MAXV/db/RAM2GS.fit.qmsg create mode 100644 CPLD/MAXV/db/RAM2GS.hier_info create mode 100644 CPLD/MAXV/db/RAM2GS.lpc.html create mode 100644 CPLD/MAXV/db/RAM2GS.lpc.rdb create mode 100644 CPLD/MAXV/db/RAM2GS.lpc.txt create mode 100644 CPLD/MAXV/db/RAM2GS.map.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.map.logdb create mode 100644 CPLD/MAXV/db/RAM2GS.pplq.rdb create mode 100644 CPLD/MAXV/db/RAM2GS.root_partition.map.reg_db.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.routing.rdb create mode 100644 CPLD/MAXV/db/RAM2GS.rtlv.hdb create mode 100644 CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb create mode 100644 CPLD/MAXV/db/RAM2GS.sld_design_entry_dsc.sci create mode 100644 CPLD/MAXV/db/RAM2GS.sta.qmsg create mode 100644 CPLD/MAXV/db/RAM2GS.sta.rdb create mode 100644 CPLD/MAXV/db/RAM2GS.sta_cmp.5_slow.tdb create mode 100644 CPLD/MAXV/db/RAM2GS.tmw_info create mode 100644 CPLD/MAXV/db/RAM2GS.vpr.ammdb create mode 100644 CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg create mode 100644 CPLD/MAXV/greybox_tmp/cbx_args.txt create mode 100644 CPLD/MAXV/incremental_db/README create mode 100644 CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info create mode 100644 CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt create mode 100644 CPLD/MAXV/output_files/RAM2GS.asm.rpt create mode 100644 CPLD/MAXV/output_files/RAM2GS.cdf create mode 100644 CPLD/MAXV/output_files/RAM2GS.done create mode 100644 CPLD/MAXV/output_files/RAM2GS.fit.rpt create mode 100644 CPLD/MAXV/output_files/RAM2GS.fit.smsg create mode 100644 CPLD/MAXV/output_files/RAM2GS.fit.summary create mode 100644 CPLD/MAXV/output_files/RAM2GS.jdi create mode 100644 CPLD/MAXV/output_files/RAM2GS.map.smsg create mode 100644 CPLD/MAXV/output_files/RAM2GS.pin create mode 100644 CPLD/MAXV/output_files/RAM2GS.pof create mode 100644 CPLD/MAXV/output_files/RAM2GS.sld create mode 100644 CPLD/MAXV/output_files/RAM2GS.sta.rpt create mode 100644 CPLD/MAXV/output_files/RAM2GS.sta.summary create mode 100644 CPLD/RAM2GS.mif diff --git a/CPLD-old/MAX/RAM2GS-MAX.v b/CPLD-old/MAX/RAM2GS-MAX.v index ede70ee..ebb32f0 100644 --- a/CPLD-old/MAX/RAM2GS-MAX.v +++ b/CPLD-old/MAX/RAM2GS-MAX.v @@ -6,11 +6,6 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, /* 65816 Phase 2 Clock */ input PHI2; - /* Activity LED */ - reg LEDEN = 0; - output LED; - assign LED = ~(~nCRAS && LEDEN); - /* Async. DRAM Control Inputs */ input nCCAS, nCRAS; @@ -21,6 +16,11 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, reg FWEr; reg CBR; + /* Activity LED */ + reg LEDEN = 0; + output LED; + assign LED = ~(~nCRAS && LEDEN); + /* 65816 Data */ input [7:0] Din; output [7:0] Dout; diff --git a/CPLD/MAXII/RAM2GS.qsf b/CPLD/MAXII/RAM2GS.qsf index 2c99f8d..842c6cf 100644 --- a/CPLD/MAXII/RAM2GS.qsf +++ b/CPLD/MAXII/RAM2GS.qsf @@ -51,5 +51,149 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" + + +#set_global_assignment -name MIF_FILE "../RAM2GS.mif" + + + +set_location_assignment PIN_12 -to RCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK + +set_location_assignment PIN_52 -to PHI2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2 + +set_location_assignment PIN_67 -to nCRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS + +set_location_assignment PIN_53 -to nCCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS + +set_location_assignment PIN_48 -to nFWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE + +set_location_assignment PIN_49 -to MAin[0] +set_location_assignment PIN_51 -to MAin[1] +set_location_assignment PIN_50 -to MAin[2] +set_location_assignment PIN_71 -to MAin[3] +set_location_assignment PIN_70 -to MAin[4] +set_location_assignment PIN_69 -to MAin[5] +set_location_assignment PIN_72 -to MAin[6] +set_location_assignment PIN_68 -to MAin[7] +set_location_assignment PIN_73 -to MAin[8] +set_location_assignment PIN_74 -to MAin[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin + +set_location_assignment PIN_54 -to CROW[0] +set_location_assignment PIN_55 -to CROW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW + +set_location_assignment PIN_35 -to Din[2] +set_location_assignment PIN_36 -to Din[1] +set_location_assignment PIN_37 -to Din[3] +set_location_assignment PIN_38 -to Din[5] +set_location_assignment PIN_39 -to Din[4] +set_location_assignment PIN_40 -to Din[7] +set_location_assignment PIN_41 -to Din[6] +set_location_assignment PIN_42 -to Din[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din + +set_location_assignment PIN_33 -to Dout[0] +set_location_assignment PIN_57 -to Dout[1] +set_location_assignment PIN_56 -to Dout[2] +set_location_assignment PIN_47 -to Dout[3] +set_location_assignment PIN_44 -to Dout[4] +set_location_assignment PIN_28 -to Dout[5] +set_location_assignment PIN_34 -to Dout[6] +set_location_assignment PIN_43 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout + +set_location_assignment PIN_8 -to RCKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE + +set_location_assignment PIN_3 -to nRCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS + +set_location_assignment PIN_100 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE + +set_location_assignment PIN_6 -to nRRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS + +set_location_assignment PIN_4 -to nRCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS + +set_location_assignment PIN_5 -to RBA[0] +set_location_assignment PIN_14 -to RBA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA + +set_location_assignment PIN_2 -to RDQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH + +set_location_assignment PIN_98 -to RDQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML + +set_location_assignment PIN_96 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_89 -to RD[2] +set_location_assignment PIN_99 -to RD[3] +set_location_assignment PIN_92 -to RD[4] +set_location_assignment PIN_91 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_97 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD + +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD + +set_global_assignment -name MIF_FILE ../RAM2GS.mif set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" \ No newline at end of file +set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index f294354fadb00ddc97bc94165b561376a092044e..5f2429ba3bdb4ca7c5b1df7fe8d20bab4b47472a 100644 GIT binary patch delta 258 zcmb7;O%4H35QM)s%)-(QL~P&uAlO>jjD??wmB}zOi9|v&tR~_L?&1V);vOOtH}E=D z-CbS%()Zf4di5_JdrllV{5U3O%Z`i!pD9Dev>7qOV?(Mb7$Kr$KuAJY^NfzzO6kkh zQxz&w!O9V^7OW7+6-dbyiFR_biPBjg{&|Mc5hm8&Tj2F2s5HQ7-s)y)T23V40d6UM PC4H`5X17qkP_6d?n?olV literal 1217 zcmds$O)o=H5Qg9DBeAry60s0zB(2-3uLV&FHf*r4qwT$DN?Ub(BqH|yjDO${*w~4c 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zXRJxT?LTO>OL~cHw(H6gS(WubLB6sY9EOgn17}1vjJYn~zbm8~cwdeGGJ8hgB}dhb zUpbNS!>rObUrJTL`Ms)V=NYlW^UEJZsvj=&ir`B1{^%xa?yr?x430?hw z;+?g~=L$HVJX8>?l6EKhx=aux?*783%6G}l)V|>#PZ^5*y-mX_c3qo5qOBCml05$rE0VzM3@mkv`cY#% zPS0-;dDzYCJS}jM-3`OMZkBRi=7kHwyBe&Q-3{VS zvbmbDOrey@{=WNuO;dqvX5E#2mCx9uigTuPgsV7f?<@rSJo&AeM}gAO$stC0isFG2 z7C%4SFOFPwc7J^_5s_^b+LBO*$Q$!`;5%yX25^*^7}tCI^5^AKxtTO zzBtC*wWS_$DwA{x?0le%3MOXOV)>hr4HZT79q)uiG9sRW_iFI9r|_g0Vz{Q8(xJ1ksExsCFN$g37}K|zTW=_ D#t-|Z literal 0 HcmV?d00001 diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info index 088acb0..5384081 100644 --- a/CPLD/MAXII/db/RAM2GS.db_info +++ b/CPLD/MAXII/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sat Aug 12 18:39:09 2023 +Creation_Time = Sat Aug 12 19:09:26 2023 diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg new file mode 100644 index 0000000..5e1d42d --- /dev/null +++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691880865039 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691880865039 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691880865039 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880865086 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880865086 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691880865101 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691880865117 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880865211 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691880865211 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691880865258 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691880865258 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691880865258 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691880865258 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880865258 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691880865258 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880865258 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880865258 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880865258 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 331 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 333 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880865274 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 332 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691880865274 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691880865289 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691880865320 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691880865320 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691880865320 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691880865320 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865336 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691880865336 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691880865414 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865524 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691880865524 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691880865820 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880865820 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691880865852 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691880865961 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691880865961 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691880866086 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691880866086 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880866086 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691880866102 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880866102 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691880866133 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691880866164 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5346 " "Peak virtual memory: 5346 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:54:26 2023 " "Processing ended: Sat Aug 12 18:54:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880866180 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691880866180 ""} diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info new file mode 100644 index 0000000..d12e6b0 --- /dev/null +++ b/CPLD/MAXII/db/RAM2GS.hier_info @@ -0,0 +1,277 @@ +|RAM2GS +PHI2 => Bank[0].CLK +PHI2 => Bank[1].CLK +PHI2 => Bank[2].CLK +PHI2 => Bank[3].CLK +PHI2 => Bank[4].CLK +PHI2 => Bank[5].CLK +PHI2 => Bank[6].CLK +PHI2 => Bank[7].CLK +PHI2 => RA11.CLK +PHI2 => PHI2r.DATAIN +PHI2 => CmdDRDIn.CLK +PHI2 => CmdDRCLK.CLK +PHI2 => CmdUFMPrgm.CLK +PHI2 => CmdUFMErase.CLK +PHI2 => CmdSubmitted.CLK +PHI2 => Cmdn8MEGEN.CLK +PHI2 => XOR8MEG.CLK +PHI2 => ADSubmitted.CLK +PHI2 => C1Submitted.CLK +PHI2 => UFMOscEN.CLK +PHI2 => CmdEnable.CLK +MAin[0] => RA.DATAA +MAin[0] => RowA.DATAB +MAin[0] => Equal0.IN7 +MAin[0] => Equal1.IN7 +MAin[0] => Equal3.IN6 +MAin[1] => RA.DATAA +MAin[1] => RowA.DATAB +MAin[1] => Equal0.IN6 +MAin[1] => Equal1.IN6 +MAin[1] => Equal3.IN7 +MAin[2] => RA.DATAA +MAin[2] => RowA.DATAB +MAin[2] => Equal0.IN5 +MAin[2] => Equal1.IN5 +MAin[2] => Equal3.IN5 +MAin[3] => RA.DATAA +MAin[3] => RowA.DATAB +MAin[3] => Equal0.IN4 +MAin[3] => Equal1.IN4 +MAin[3] => Equal3.IN4 +MAin[4] => RA.DATAA +MAin[4] => RowA.DATAB +MAin[4] => Equal0.IN3 +MAin[4] => Equal1.IN3 +MAin[4] => Equal3.IN3 +MAin[5] => RA.DATAA +MAin[5] => RowA.DATAB +MAin[5] => Equal0.IN2 +MAin[5] => Equal1.IN2 +MAin[5] => Equal3.IN2 +MAin[6] => RA.DATAA +MAin[6] => RowA.DATAB +MAin[6] => Equal0.IN1 +MAin[6] => Equal1.IN1 +MAin[6] => Equal3.IN1 +MAin[7] => RA.DATAA +MAin[7] => RowA.DATAB +MAin[7] => Equal0.IN0 +MAin[7] => Equal1.IN0 +MAin[7] => Equal3.IN0 +MAin[8] => RA.DATAA +MAin[8] => RowA.DATAB +MAin[9] => RA.DATAA +MAin[9] => comb.DATAA +MAin[9] => RowA.DATAB +MAin[9] => comb.DATAA +CROW[0] => RBA.DATAB +CROW[1] => RBA.DATAB +Din[0] => CmdDRDIn.DATAB +Din[0] => XOR8MEG.DATAB +Din[0] => WRD[0].DATAIN +Din[0] => Bank[0].DATAIN +Din[0] => Equal14.IN2 +Din[0] => Equal15.IN4 +Din[0] => Cmdn8MEGEN.DATAB +Din[1] => CmdDRCLK.DATAB +Din[1] => WRD[1].DATAIN +Din[1] => Bank[1].DATAIN +Din[1] => Equal14.IN7 +Din[1] => Equal15.IN7 +Din[2] => CmdUFMPrgm.DATAB +Din[2] => WRD[2].DATAIN +Din[2] => Bank[2].DATAIN +Din[2] => Equal14.IN6 +Din[2] => Equal15.IN3 +Din[3] => CmdUFMErase.DATAB +Din[3] => WRD[3].DATAIN +Din[3] => Bank[3].DATAIN +Din[3] => Equal14.IN5 +Din[3] => Equal15.IN2 +Din[4] => WRD[4].DATAIN +Din[4] => Bank[4].DATAIN +Din[4] => Equal14.IN4 +Din[4] => Equal15.IN6 +Din[4] => Equal16.IN3 +Din[4] => Equal17.IN0 +Din[4] => Equal18.IN3 +Din[5] => WRD[5].DATAIN +Din[5] => Bank[5].DATAIN +Din[5] => Equal14.IN3 +Din[5] => Equal15.IN1 +Din[5] => Equal16.IN2 +Din[5] => Equal17.IN3 +Din[5] => Equal18.IN0 +Din[6] => RA11.IN1 +Din[6] => WRD[6].DATAIN +Din[6] => Bank[6].DATAIN +Din[6] => Equal14.IN1 +Din[6] => Equal15.IN5 +Din[6] => Equal16.IN1 +Din[6] => Equal17.IN2 +Din[6] => Equal18.IN2 +Din[7] => WRD[7].DATAIN +Din[7] => Bank[7].DATAIN +Din[7] => Equal14.IN0 +Din[7] => Equal15.IN0 +Din[7] => Equal16.IN0 +Din[7] => Equal17.IN1 +Din[7] => Equal18.IN1 +Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE +nCCAS => WRD[0].CLK +nCCAS => WRD[1].CLK +nCCAS => WRD[2].CLK +nCCAS => WRD[3].CLK +nCCAS => WRD[4].CLK +nCCAS => WRD[5].CLK +nCCAS => WRD[6].CLK +nCCAS => WRD[7].CLK +nCCAS => comb.IN0 +nCCAS => CBR.DATAIN +nCCAS => CASr.DATAIN +nCRAS => CBR.CLK +nCRAS => FWEr.CLK +nCRAS => RowA[0].CLK +nCRAS => RowA[1].CLK +nCRAS => RowA[2].CLK +nCRAS => RowA[3].CLK +nCRAS => RowA[4].CLK +nCRAS => RowA[5].CLK +nCRAS => RowA[6].CLK +nCRAS => RowA[7].CLK +nCRAS => RowA[8].CLK +nCRAS => RowA[9].CLK +nCRAS => RBA[0]~reg0.CLK +nCRAS => RBA[1]~reg0.CLK +nCRAS => RASr.DATAIN +nFWE => comb.IN1 +nFWE => CMDWR.IN1 +nFWE => ADWR.IN1 +nFWE => C1WR.IN1 +nFWE => FWEr.DATAIN +RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE +RD[0] <> RD[0] +RD[1] <> RD[1] +RD[2] <> RD[2] +RD[3] <> RD[3] +RD[4] <> RD[4] +RD[5] <> RD[5] +RD[6] <> RD[6] +RD[7] <> RD[7] +nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RCLK => UFMProgram.CLK +RCLK => UFMErase.CLK +RCLK => UFMReqErase.CLK +RCLK => n8MEGEN.CLK +RCLK => UFMInitDone.CLK +RCLK => UFMD.CLK +RCLK => DRShift.CLK +RCLK => DRDIn.CLK +RCLK => DRCLK.CLK +RCLK => ARShift.CLK +RCLK => ARCLK.CLK +RCLK => Ready.CLK +RCLK => IS[0].CLK +RCLK => IS[1].CLK +RCLK => IS[2].CLK +RCLK => IS[3].CLK +RCLK => nRowColSel.CLK +RCLK => RCKEEN.CLK +RCLK => RA10.CLK +RCLK => nRWE~reg0.CLK +RCLK => nRCAS~reg0.CLK +RCLK => nRRAS~reg0.CLK +RCLK => nRCS~reg0.CLK +RCLK => RCKE~reg0.CLK +RCLK => InitReady.CLK +RCLK => FS[0].CLK +RCLK => FS[1].CLK +RCLK => FS[2].CLK +RCLK => FS[3].CLK +RCLK => FS[4].CLK +RCLK => FS[5].CLK +RCLK => FS[6].CLK +RCLK => FS[7].CLK +RCLK => FS[8].CLK +RCLK => FS[9].CLK +RCLK => FS[10].CLK +RCLK => FS[11].CLK +RCLK => FS[12].CLK +RCLK => FS[13].CLK +RCLK => FS[14].CLK +RCLK => FS[15].CLK +RCLK => FS[16].CLK +RCLK => FS[17].CLK +RCLK => S[0].CLK +RCLK => S[1].CLK +RCLK => CASr3.CLK +RCLK => CASr2.CLK +RCLK => CASr.CLK +RCLK => RASr3.CLK +RCLK => RASr2.CLK +RCLK => RASr.CLK +RCLK => PHI2r3.CLK +RCLK => PHI2r2.CLK +RCLK => PHI2r.CLK +RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH << comb.DB_MAX_OUTPUT_PORT_TYPE +RDQML << comb.DB_MAX_OUTPUT_PORT_TYPE + + +|RAM2GS|UFM:UFM_inst +arclk => arclk.IN1 +ardin => ardin.IN1 +arshft => arshft.IN1 +drclk => drclk.IN1 +drdin => drdin.IN1 +drshft => drshft.IN1 +erase => erase.IN1 +oscena => oscena.IN1 +program => program.IN1 +busy <= UFM_altufm_none_var:UFM_altufm_none_var_component.busy +drdout <= UFM_altufm_none_var:UFM_altufm_none_var_component.drdout +osc <= UFM_altufm_none_var:UFM_altufm_none_var_component.osc +rtpbusy <= UFM_altufm_none_var:UFM_altufm_none_var_component.rtpbusy + + +|RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component +arclk => maxii_ufm_block1.ARCLK +ardin => maxii_ufm_block1.ARDIN +arshft => maxii_ufm_block1.ARSHFT +busy <= maxii_ufm_block1.BUSY +drclk => maxii_ufm_block1.DRCLK +drdin => maxii_ufm_block1.DRDIN +drdout <= maxii_ufm_block1.DRDOUT +drshft => maxii_ufm_block1.DRSHFT +erase => maxii_ufm_block1.ERASE +osc <= maxii_ufm_block1.OSC +oscena => maxii_ufm_block1.OSCENA +program => maxii_ufm_block1.PROGRAM +rtpbusy <= maxii_ufm_block1.BGPBUSY + + diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif index 8668e73d9428d7debb0dcec9611b0ba13fd4cab1..5c82f053b87f75c491d743be86fa2eda7e7a57c2 100644 GIT binary patch literal 598 zcmV-c0;&D14*>uG0001Zob8ldZ<{a_hVL!yKUnI`c9GO}aRR-|GLkYS&_R-03yeuD z@zEI*tt$KPGbC#(1?@xHt~P;X^PXe-ob%XxYGS3E8r~~e2(S~XmQ@L{Gsa^C-#0Q( z;be*+a;^!vCI~w)`UqE23+Sd&8(%wAit(TZyB{2|(v(7e;Gl zJa%`d9)ZyaM%u(;7Ee^H9^rkg4>cT(I*VJTgZgR4?(W0tY?k8nluN@E6s4B>5rnff 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
UFM_inst|UFM_altufm_none_var_component9000400000000
UFM_inst9404444400000
diff --git a/CPLD/MAXII/db/RAM2GS.lpc.rdb b/CPLD/MAXII/db/RAM2GS.lpc.rdb new file mode 100644 index 0000000000000000000000000000000000000000..6d3ed54371614835799c58fc76c739916eee269c GIT binary patch literal 495 zcmWe(U|?9w%?KnJ7_x!T1W1Ra78Pga=P4Lk>KW=8C^(g7=AdB-9^PX$XlQD?WtYe~_n>XWIe(2Y0D?sv;7Zh-IgV@daV|7;Yr^} z&*Oi#t>bao`rT~1oZL6(wGUdO4#qunx1CfLqqC(WMtRb$H7$7pQoQqxyXV%pIJmA* z+uS2N`_0@Mv$D;W2Iky04t4VEVh?kBuN~O!%PFm$GrOS6@3iN>*<5Suy#?RYKiIaa zPX8r01H=FS6^u!V2`LN<|6G!P#p7^*<;WcenJ14#-oJnH^p(t^BLa+5?w|XZE;oTm zGgYAFRJ(=M&mB&ohQ=NYu9v^p@8((}QPLQ}(c!qvA!O&T9lv({YTaO$VlqNcUOt!O59I~M#sB{RsV>IQ literal 0 HcmV?d00001 diff --git a/CPLD/MAXII/db/RAM2GS.lpc.txt b/CPLD/MAXII/db/RAM2GS.lpc.txt new file mode 100644 index 0000000..e8e0dd8 --- /dev/null +++ b/CPLD/MAXII/db/RAM2GS.lpc.txt @@ -0,0 +1,8 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; 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1691880810093 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:29 2023 " "Processing started: Sat Aug 12 18:53:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880810093 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880810093 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880810093 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691880810414 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691880810414 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(52) " "Verilog HDL warning at RAM2GS-MAX.v(52): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691880818509 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818509 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880818540 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691880818540 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_var " "Found entity 1: UFM_altufm_none_var" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818540 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880818540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818540 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(154) " "Verilog HDL assignment warning at RAM2GS-MAX.v(154): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(159) " "Verilog HDL assignment warning at RAM2GS-MAX.v(159): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(286) " "Verilog HDL assignment warning at RAM2GS-MAX.v(286): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691880818572 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880818587 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_var UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component " "Elaborating entity \"UFM_altufm_none_var\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_var:UFM_altufm_none_var_component\"" { } { { "UFM.v" "UFM_altufm_none_var_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691880818587 ""} +{ "Warning" "WVRFX_VERI_DISPLAY_SYSTEM_CALL_WARNING" " Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. UFM.v(145) " "Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results." { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 145 0 0 } } } 0 10649 "Verilog HDL Display System Task warning at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818603 "|RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component"} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691880818887 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "243 " "Implemented 243 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_LCELLS" "180 " "Implemented 180 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691880818918 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691880818918 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691880818918 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818965 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:38 2023 " "Processing ended: Sat Aug 12 18:53:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880818996 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880818996 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691880820181 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880820196 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:39 2023 " "Processing started: Sat Aug 12 18:53:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880820196 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691880820196 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691880820196 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691880820306 ""} +{ "Info" "0" "" "Project = RAM2GS-MAXII" { } { } 0 0 "Project = RAM2GS-MAXII" 0 0 "Fitter" 0 0 1691880820306 ""} +{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691880820306 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691880820353 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691880820353 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691880820353 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880820384 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691880820384 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691880820415 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691880820415 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691880820525 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691880820525 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691880820571 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691880820571 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691880820571 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691880820571 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691880820571 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691880820571 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880820571 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691880820571 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880820571 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 329 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 331 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691880820587 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 330 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691880820587 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691880820603 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691880820618 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691880820618 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691880820618 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691880820618 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880820650 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691880820650 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691880820728 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880820837 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691880820837 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691880821181 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821181 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691880821196 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691880821306 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691880821306 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691880821446 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691880821446 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821446 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691880821462 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691880821462 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691880821493 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691880821525 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:41 2023 " "Processing ended: Sat Aug 12 18:53:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880821540 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691880821540 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691880822540 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880822540 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:42 2023 " "Processing started: Sat Aug 12 18:53:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880822540 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691880822540 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691880822540 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691880822775 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691880822790 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691880822790 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4661 " "Peak virtual memory: 4661 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:42 2023 " "Processing ended: Sat Aug 12 18:53:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880822900 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691880822900 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691880823493 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691880824025 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880824040 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:53:43 2023 " "Processing started: Sat Aug 12 18:53:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880824040 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824040 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824040 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691880824150 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691880824290 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691880824290 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824321 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824321 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691880824353 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691880824493 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691880824525 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824525 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691880824525 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691880824525 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691880824525 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691880824540 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691880824540 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.919 -92.622 PHI2 " " -8.919 -92.622 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.036 -241.671 RCLK " " -8.036 -241.671 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.777 -2.512 nCRAS " " -0.777 -2.512 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824540 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824540 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.785 " "Worst-case hold slack is -16.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.785 -16.785 DRCLK " " -16.785 -16.785 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.266 -16.266 ARCLK " " -16.266 -16.266 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.047 -2.078 RCLK " " -1.047 -2.078 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.276 -0.276 PHI2 " " -0.276 -0.276 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.031 -0.048 nCRAS " " -0.031 -0.048 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691880824556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691880824556 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691880824603 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880824634 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691880824634 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 18:53:44 2023 " "Processing ended: Sat Aug 12 18:53:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880824681 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691880824681 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus Prime Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691880825306 ""} diff --git a/CPLD/MAXII/greybox_tmp/cbx_args.txt b/CPLD/MAXII/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..1e60991 --- /dev/null +++ b/CPLD/MAXII/greybox_tmp/cbx_args.txt @@ -0,0 +1,25 @@ +ERASE_TIME=500000000 +INTENDED_DEVICE_FAMILY="MAX II" +LPM_FILE=RAM2GS.mif +LPM_HINT=UNUSED +LPM_TYPE=altufm_none +OSC_FREQUENCY=180000 +PORT_ARCLKENA=PORT_UNUSED +PORT_DRCLKENA=PORT_UNUSED +PROGRAM_TIME=1600000 +WIDTH_UFM_ADDRESS=9 +DEVICE_FAMILY="MAX II" +CBX_AUTO_BLACKBOX=ALL +arclk +ardin +arshft +busy +drclk +drdin +drdout +drshft +erase +osc +oscena +program +rtpbusy diff --git a/CPLD/MAXII/incremental_db/README b/CPLD/MAXII/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/CPLD/MAXII/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info new file mode 100644 index 0000000..55ce4ec --- /dev/null +++ b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +Version_Index = 503488000 +Creation_Time = Sat Aug 12 18:47:27 2023 diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt new file mode 100644 index 0000000000000000000000000000000000000000..10ac0b4df58dce8fd377b4e25a30a0a15346821f GIT binary patch literal 2590 zcmV+(3gPvv4*>uG0001Zob6p}Z`(!|{oY?e=zAkxJxCF70{E4#w@sT$Xj33q7;?m< zLM+Lp=(GVA``b%OuBF&2&zx)RTn%==#d=%~@65TcbI2ThyeTgySJ8Yt%b&M~$FDly zjGoQLH-H9cOM*obyo0fTWKAD!)XIn46ilU>B`RB`<#dKaSFPC{4m7i~_ z)fD;ryvXP8@>cZgG%u=mZl1T=t1oPSC7MpE)wS-w^kKRz^WyGf)d%ZKdodrLj*i-^ zf3CmYzW@GCdmUi!Vm>X0`FQe~G1>)2hl}5j-zNWJO!k1uUw#-4UY&o#nC!c(vP-Qp z0VZFL-u5YjDK;paBL~3Z$$0+ptxzU2|n7&Swy&5T{gEjg0M3@mY6b# zaPww(M#4rAZt4Tn;Y=djT#VkvoJ9nipI*LtT`WEn;~8ZZfv4IZp$sDI%!hBzDT4?( zRWv{5!Z|`teT2CE?jY!#4Nt%Oma+(eb8<|Epbmo0F}+9!jgrFi4QT-T|3 zBliXYsLJQuDtib$t5tIQ(?jT~6B`G}9>UMr@a$qvS#*L9dEp2;ReT%fztLHv=a7wf z2Ot!!cAnfO1fzQAxi+nbV03yir0gLGRY>Pn*mvoGD1$Ee;Z9~B;io#8_4wdyF{e&u zAEBu7CU=DT2tzAe4mg`m;{z^Z^bve2OwQ{u2UpGXVIx#8m5cFx1fdJIJnlPyNVpT4 zI3*%-#DjoTFO$o_2?Ekfwwg&0gsOvdJ|ACQQ@~6hj853>mf$*$JC_M;hR#%tOX8A+ z$Zf~tgdx}cCvcv?2agnCs5(k2kERYl;zDxjkdV$OgRq`sC*vuC(CdF(bg0Chx=j^c z7ayqMS&DE}pLY(LsZ$!_l1AzAG5L?C$ z97;Lv5Di=g+Ty31Sr!DJGkzvFfHOIk6&WD(XvUEPgr8HE4$5FNbowndch3-b zR#BL8Wrna*$4jmo$Pjo|tK>Y1(6eg#$w_$zJE3ZOxS}I-n8r0m;H^JbO#AA!FJHR* zfwCCSmurT8i+%rhOJU{xqL}5A$7UX19zwE;bMxa*k?-IktjA!5>sA&p5b{Y<{d*nd!awL3=V5DH-W0%rv)k~bo{hH9fg9R7AT@%8ESzN3OYQyh$l#nTA+M_C#eOh zCloBTK=}ksQwtPOD0pgt@(G@(7AT*ng=hb%-XrCP2uL*lD^NzEV88_mDU=krKskkm z0~aW$P>|pPH5EJyE>KfJ(%=FW6*LbnSW>~JB`B!inQ(z(3MCaTP*73NR(Rw?O$AM{ z3)EC7ICg=;3I)k7P+Os6*#$~06g0a)kp<1Oi;KR3B-#ZkEEG(;K#2uUwF{J3&|JGf zd4-B>7pSnH>m8`DP;%n}brw81E>LHofhbg3)VELZ;nYQLq4cZ+-9^S!D7j!+a)Fu) zdXz0tZb9?p0_7GuqFkWpf@jJFiY^pXxwr@}NUmI<~alwYW3uuy_Q)A0f|7;7CM zk0z+Z;CXq0N(`Qu7pTPGnR$U)3=K6eP>iv@)sEjPCrt)fok3X!V*PiRbSU_6+~27K zxTpNbwRm7H2H3&;fBCWdAOCo>^8o;Vy?^(Ka$M%obUw-dc;1S)-dw%Cy28zD?50@! z@wxS)TIVDp6yPipGy)@!v+`FGJ>|D7-5M|9u30 zXzan4AH-h2o1fW7-i;RGpkb2Qdn##aClAL{iFQNx=c#^Er*Sx*5_?aHHvD_8d$hT9 zk7p{33Q@hGdn^&di0F;2pr@`Q3{Q3JbDxBf`=n`F?3+N z4D_YiW$v*?4N>^qk+L68C4mg`> z$FegFPo?$+dJ;y{r&i#?vlB**ZhxfWFuJ~;ed_CmQBEcHo>Je2>G@3AbA62u@H-q&W%iy@%OX5`${u~{ zhc$REJnaX0>Kj%)H^}xSdgEg<564qo`zgA*_Vw&3dk#x2An{yJ*?USI06d>5`))>^ zR6JJ+_MTF+L!NV=J>j5kJw1EMK29}01odz{rGALx{ya4ZWaMc-$W!xZp3js$`qb=@ z=X%QiOsQ{h@*L6ar!MLnoIF>a_Ok@_!-+l5Jnbt_b(8LyY`3ox;xOtd^VFAx5v2y^ zjuQ1_iadMDevYT!EYH=Hedbd?eCPkq<$kir&>kmg7&0gI6Jqw~DRtxHx$Cf(&Z%#( z@tmdXc{%lf#&evqucg(p7|&gYeVkI?4e`H`&mX>W_kV)cjwmlDS1-Q$69vlS9G(>r A1ONa4 literal 0 HcmV?d00001 diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt new file mode 100644 index 0000000..cc5b707 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for RAM2GS +Sat Aug 12 18:54:27 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Aug 12 18:54:27 2023 ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------+ +; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Assembler Device Options: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ; ++----------------+---------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------------------------------+ +; JTAG usercode ; 0x00172B88 ; +; Checksum ; 0x00172F80 ; ++----------------+---------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Sat Aug 12 18:54:27 2023 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4661 megabytes + Info: Processing ended: Sat Aug 12 18:54:27 2023 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/CPLD/MAXII/output_files/RAM2GS.cdf b/CPLD/MAXII/output_files/RAM2GS.cdf new file mode 100644 index 0000000..700406a --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.cdf @@ -0,0 +1,13 @@ +/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EPM240T100) Path("D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/") File("RAM2GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done new file mode 100644 index 0000000..a5558c6 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -0,0 +1 @@ +Sat Aug 12 18:54:30 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt new file mode 100644 index 0000000..2dce144 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -0,0 +1,759 @@ +Fitter report for RAM2GS +Sat Aug 12 18:54:26 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. I/O Bank Usage + 11. All Package Pins + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Delay Chain Summary + 15. Control Signals + 16. Global & Other Fast Signals + 17. Routing Usage Summary + 18. LAB Logic Elements + 19. LAB-wide Signals + 20. LAB Signals Sourced + 21. LAB Signals Sourced Out + 22. LAB Distinct Inputs + 23. Fitter Device Options + 24. Estimated Delay Added for Hold Timing Summary + 25. Estimated Delay Added for Hold Timing Details + 26. Fitter Messages + 27. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Aug 12 18:54:26 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2GS ; +; Top-level Entity Name ; RAM2GS ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 171 / 240 ( 71 % ) ; +; Total pins ; 62 / 80 ( 78 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EPM240T100C5 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.05 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 1.6% ; +; Processors 3-4 ; 1.5% ; ++----------------------------+-------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 171 / 240 ( 71 % ) ; +; -- Combinational with no register ; 75 ; +; -- Register only ; 20 ; +; -- Combinational with a register ; 76 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 42 ; +; -- 2 input functions ; 43 ; +; -- 1 input functions ; 8 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 155 ; +; -- arithmetic mode ; 16 ; +; -- qfbk mode ; 7 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 23 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 96 / 240 ( 40 % ) ; +; Total LABs ; 21 / 24 ( 88 % ) ; +; Logic elements in carry chains ; 17 ; +; Virtual pins ; 0 ; +; I/O pins ; 62 / 80 ( 78 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; ; ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +; ; ; +; -- Total Fixed Point DSP Blocks ; 0 ; +; -- Total Floating Point DSP Blocks ; 0 ; +; ; ; +; Global signals ; 4 ; +; -- Global clocks ; 4 / 4 ( 100 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 22.5% / 22.5% / 22.6% ; +; Peak interconnect usage (total/H/V) ; 22.5% / 22.5% / 22.6% ; +; Maximum fan-out ; 54 ; +; Highest non-global fan-out ; 40 ; +; Total fan-out ; 643 ; +; Average fan-out ; 2.75 ; ++---------------------------------------------+-----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ +; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 15 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Dout[0] ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[1] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; +; 2 ; 24 / 42 ( 57 % ) ; 3.3V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 2 ; 0 ; 1 ; RDQMH ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 3 ; 1 ; 1 ; nRCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 4 ; 2 ; 1 ; nRCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 5 ; 3 ; 1 ; RBA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 6 ; 4 ; 1 ; nRRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 8 ; 6 ; 1 ; RCKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 7 ; 1 ; RCLK ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 14 ; 8 ; 1 ; RBA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 28 ; 22 ; 1 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 25 ; 1 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 34 ; 26 ; 1 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 35 ; 27 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 36 ; 28 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 37 ; 29 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 38 ; 30 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 39 ; 31 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 40 ; 32 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 41 ; 33 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 42 ; 34 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 43 ; 35 ; 1 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 44 ; 36 ; 1 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 37 ; 1 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 48 ; 38 ; 1 ; nFWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 49 ; 39 ; 1 ; MAin[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 50 ; 40 ; 1 ; MAin[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 51 ; 41 ; 1 ; MAin[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 52 ; 42 ; 2 ; PHI2 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 53 ; 43 ; 2 ; nCCAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 54 ; 44 ; 2 ; CROW[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 55 ; 45 ; 2 ; CROW[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 56 ; 46 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 57 ; 47 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 58 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 62 ; 50 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 67 ; 53 ; 2 ; nCRAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 68 ; 54 ; 2 ; MAin[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 69 ; 55 ; 2 ; MAin[5] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 70 ; 56 ; 2 ; MAin[4] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 71 ; 57 ; 2 ; MAin[3] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 72 ; 58 ; 2 ; MAin[6] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 73 ; 59 ; 2 ; MAin[8] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 74 ; 60 ; 2 ; MAin[9] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 75 ; 61 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 63 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 68 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 73 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 92 ; 76 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 96 ; 78 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 97 ; 79 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 98 ; 80 ; 2 ; RDQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 99 ; 81 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 100 ; 82 ; 2 ; nRWE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------+-------+------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------+-------+------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; 2.5 V ; 10 pF ; Not Available ; +; 1.8 V ; 10 pF ; Not Available ; +; 1.5 V ; 10 pF ; Not Available ; +; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; +; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; ++----------------------------+-------+------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; |RAM2GS ; 171 (171) ; 96 ; 1 ; 62 ; 0 ; 75 (75) ; 20 (20) ; 76 (76) ; 17 (17) ; 7 (7) ; |RAM2GS ; RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; +; |UFM_altufm_none_var:UFM_altufm_none_var_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component ; UFM_altufm_none_var ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+ +; Name ; Pin Type ; Pad to Core 0 ; ++---------+----------+---------------+ +; Dout[0] ; Output ; -- ; +; Dout[1] ; Output ; -- ; +; Dout[2] ; Output ; -- ; +; Dout[3] ; Output ; -- ; +; Dout[4] ; Output ; -- ; +; Dout[5] ; Output ; -- ; +; Dout[6] ; Output ; -- ; +; Dout[7] ; Output ; -- ; +; RBA[0] ; Output ; -- ; +; RBA[1] ; Output ; -- ; +; RA[0] ; Output ; -- ; +; RA[1] ; Output ; -- ; +; RA[2] ; Output ; -- ; +; RA[3] ; Output ; -- ; +; RA[4] ; Output ; -- ; +; RA[5] ; Output ; -- ; +; RA[6] ; Output ; -- ; +; RA[7] ; Output ; -- ; +; RA[8] ; Output ; -- ; +; RA[9] ; Output ; -- ; +; RA[10] ; Output ; -- ; +; RA[11] ; Output ; -- ; +; nRCS ; Output ; -- ; +; RCKE ; Output ; -- ; +; nRWE ; Output ; -- ; +; nRRAS ; Output ; -- ; +; nRCAS ; Output ; -- ; +; RDQMH ; Output ; -- ; +; RDQML ; Output ; -- ; +; RD[0] ; Bidir ; (0) ; +; RD[1] ; Bidir ; (0) ; +; RD[2] ; Bidir ; (0) ; +; RD[3] ; Bidir ; (0) ; +; RD[4] ; Bidir ; (0) ; +; RD[5] ; Bidir ; (0) ; +; RD[6] ; Bidir ; (0) ; +; RD[7] ; Bidir ; (0) ; +; MAin[0] ; Input ; (0) ; +; MAin[1] ; Input ; (0) ; +; MAin[2] ; Input ; (0) ; +; MAin[3] ; Input ; (0) ; +; MAin[4] ; Input ; (0) ; +; MAin[5] ; Input ; (0) ; +; MAin[6] ; Input ; (0) ; +; MAin[7] ; Input ; (0) ; +; MAin[8] ; Input ; (0) ; +; MAin[9] ; Input ; (0) ; +; CROW[0] ; Input ; (1) ; +; nCRAS ; Input ; (0) ; +; CROW[1] ; Input ; (1) ; +; RCLK ; Input ; (0) ; +; PHI2 ; Input ; (0) ; +; Din[6] ; Input ; (1) ; +; nFWE ; Input ; (1) ; +; Din[0] ; Input ; (1) ; +; Din[7] ; Input ; (1) ; +; Din[1] ; Input ; (1) ; +; Din[4] ; Input ; (1) ; +; Din[2] ; Input ; (1) ; +; Din[3] ; Input ; (1) ; +; Din[5] ; Input ; (1) ; +; nCCAS ; Input ; (0) ; ++---------+----------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ +; CmdDRDIn~0 ; LC_X5_Y3_N4 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdSubmitted~0 ; LC_X5_Y1_N0 ; 2 ; Clock enable ; no ; -- ; -- ; +; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK3 ; +; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ; +; Ready ; LC_X3_Y2_N5 ; 39 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~5 ; LC_X5_Y2_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~2 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ; +; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; +; nCRAS ; PIN_67 ; 15 ; Clock ; yes ; Global Clock ; GCLK1 ; ++----------------+-------------+---------+-------------------------+--------+----------------------+------------------+ + + ++----------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++-------+----------+---------+----------------------+------------------+ +; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK3 ; +; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ; +; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ; +; nCRAS ; PIN_67 ; 15 ; Global Clock ; GCLK1 ; ++-------+----------+---------+----------------------+------------------+ + + ++--------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+--------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+--------------------+ +; C4s ; 142 / 784 ( 18 % ) ; +; Direct links ; 50 / 888 ( 6 % ) ; +; Global clocks ; 4 / 4 ( 100 % ) ; +; LAB clocks ; 14 / 32 ( 44 % ) ; +; LUT chains ; 17 / 216 ( 8 % ) ; +; Local interconnects ; 263 / 888 ( 30 % ) ; +; R4s ; 127 / 704 ( 18 % ) ; ++-----------------------+--------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 8.14) ; Number of LABs (Total = 21) ; ++--------------------------------------------+------------------------------+ +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 2 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 14 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.19) ; Number of LABs (Total = 21) ; ++------------------------------------+------------------------------+ +; 1 Clock ; 13 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 1 ; +; 2 Clocks ; 8 ; ++------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 8.43) ; Number of LABs (Total = 21) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 2 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 10 ; +; 11 ; 2 ; +; 12 ; 2 ; ++---------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 5.43) ; Number of LABs (Total = 21) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 2 ; +; 3 ; 4 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 3 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 0 ; +; 10 ; 3 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 10.19) ; Number of LABs (Total = 21) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 4 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 2 ; +; 9 ; 0 ; +; 10 ; 3 ; +; 11 ; 0 ; +; 12 ; 3 ; +; 13 ; 3 ; +; 14 ; 2 ; +; 15 ; 1 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Reserve all unused pins ; As output driving ground ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; I/O ; RCLK ; 4.0 ; +; I/O ; nCRAS ; 3.0 ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-----------------+----------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +; nCCAS ; CBR ; 3.041 ; +; PHI2 ; PHI2r ; 1.523 ; +; nCRAS ; RASr ; 1.214 ; ++-----------------+----------------------+-------------------+ +Note: This table only shows the top 3 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EPM240T100C5 for design "RAM2GS" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EPM240T100I5 is compatible + Info (176445): Device EPM240T100A5 is compatible + Info (176445): Device EPM570T100C5 is compatible + Info (176445): Device EPM570T100I5 is compatible + Info (176445): Device EPM570T100A5 is compatible +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements + Info (332127): Assuming a default timing requirement +Info (332111): Found 6 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 1.000 ARCLK + Info (332111): 1.000 DRCLK + Info (332111): 1.000 nCCAS + Info (332111): 1.000 nCRAS + Info (332111): 1.000 PHI2 + Info (332111): 1.000 RCLK +Info (186079): Completed User Assigned Global Signals Promotion Operation +Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 34 +Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7 + Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 13 +Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 7 +Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10 + Info (186217): Destination "RASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14 +Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10 +Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10 + Info (186217): Destination "CBR" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 17 + Info (186217): Destination "comb~2" may be non-global or may not use global clock + Info (186217): Destination "CASr" may be non-global or may not use global clock File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15 +Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 10 +Info (186079): Completed Auto Global Promotion Operation +Info (176234): Starting register packing +Info (186468): Started processing fast register assignments +Info (186469): Finished processing fast register assignments +Info (176235): Finished register packing +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 19% of the available device resources + Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.23 seconds. +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 5346 megabytes + Info: Processing ended: Sat Aug 12 18:54:26 2023 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg. + + diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.smsg b/CPLD/MAXII/output_files/RAM2GS.fit.smsg new file mode 100644 index 0000000..6df10d8 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.fit.smsg @@ -0,0 +1,4 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176244): Moving registers into LUTs to improve timing and density +Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary new file mode 100644 index 0000000..8e1ecb6 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -0,0 +1,11 @@ +Fitter Status : Successful - Sat Aug 12 18:54:26 2023 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition +Revision Name : RAM2GS +Top-level Entity Name : RAM2GS +Family : MAX II +Device : EPM240T100C5 +Timing Models : Final +Total logic elements : 171 / 240 ( 71 % ) +Total pins : 62 / 80 ( 78 % ) +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index 5d98ed3..7aae449 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sat Aug 12 18:40:53 2023 +Sat Aug 12 18:54:29 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,13 +41,17 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Flow Failed - Sat Aug 12 18:40:53 2023 ; +; Flow Status ; Successful - Sat Aug 12 18:54:27 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; +; Total logic elements ; 171 / 240 ( 71 % ) ; +; Total pins ; 62 / 80 ( 78 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------+---------------------------------------------+ @@ -56,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/12/2023 18:40:40 ; +; Start date & time ; 08/12/2023 18:54:15 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -67,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169188004013584 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169188085502776 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; @@ -81,8 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4688 MB ; 00:00:29 ; -; Total ; 00:00:13 ; -- ; -- ; 00:00:29 ; +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4700 MB ; 00:00:21 ; +; Fitter ; 00:00:02 ; 1.0 ; 5346 MB ; 00:00:02 ; +; Assembler ; 00:00:00 ; 1.0 ; 4661 MB ; 00:00:00 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; +; Total ; 00:00:12 ; -- ; -- ; 00:00:24 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -92,6 +99,9 @@ https://fpgasoftware.intel.com/eula. ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+------------------+------------+------------+----------------+ ; Analysis & Synthesis ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ; +----------------------+------------------+------------+------------+----------------+ @@ -99,6 +109,9 @@ https://fpgasoftware.intel.com/eula. ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS +quartus_sta RAM2GS-MAXII -c RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.jdi b/CPLD/MAXII/output_files/RAM2GS.jdi new file mode 100644 index 0000000..4294046 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index c920a8a..796fd17 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sat Aug 12 18:40:53 2023 +Sat Aug 12 18:54:23 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -10,7 +10,16 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation - 5. Analysis & Synthesis Messages + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Port Connectivity Checks: "UFM:UFM_inst" + 13. Analysis & Synthesis Messages + 14. Analysis & Synthesis Suppressed Messages @@ -37,11 +46,15 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Failed - Sat Aug 12 18:40:53 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Aug 12 18:54:23 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; +; Total logic elements ; 180 ; +; Total pins ; 62 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+---------------------------------------------+ @@ -132,23 +145,171 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+ +; ../RAM2GS.mif ; yes ; User Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.mif ; ; +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Total logic elements ; 180 ; +; -- Combinational with no register ; 84 ; +; -- Register only ; 29 ; +; -- Combinational with a register ; 67 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 42 ; +; -- 2 input functions ; 43 ; +; -- 1 input functions ; 8 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 164 ; +; -- arithmetic mode ; 16 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 9 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 96 ; +; Total logic cells in carry chains ; 17 ; +; I/O pins ; 62 ; +; UFM blocks ; 1 ; +; Maximum fan-out node ; RCLK ; +; Maximum fan-out ; 54 ; +; Total fan-out ; 644 ; +; Average fan-out ; 2.65 ; ++---------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; |RAM2GS ; 180 (180) ; 96 ; 1 ; 62 ; 0 ; 84 (84) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; +; |UFM_altufm_none_var:UFM_altufm_none_var_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component ; UFM_altufm_none_var ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ +; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2GS|UFM:UFM_inst ; UFM.v ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 96 ; +; Number of registers using Synchronous Clear ; 6 ; +; Number of registers using Synchronous Load ; 3 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 8 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; nRCS~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; nRRAS~reg0 ; 1 ; +; nRCAS~reg0 ; 1 ; +; Total number of inverted registers = 4 ; ; ++----------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "UFM:UFM_inst" ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; ardin ; Input ; Info ; Stuck at GND ; +; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ + + +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sat Aug 12 18:40:40 2023 + Info: Processing started: Sat Aug 12 18:54:14 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM4GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 -Error (12007): Top-level design entity "RAM2GS" is undefined -Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning - Error: Peak virtual memory: 4688 megabytes - Error: Processing ended: Sat Aug 12 18:40:53 2023 - Error: Elapsed time: 00:00:13 - Error: Total CPU time (on all processors): 00:00:29 + Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 2 design units, including 2 entities, in source file ufm.v + Info (12023): Found entity 1: UFM_altufm_none_var File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 154 +Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(154): truncated value with size 32 to match size of target (2) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 154 +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(159): truncated value with size 32 to match size of target (18) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 159 +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(286): truncated value with size 32 to match size of target (4) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 286 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 83 +Info (12128): Elaborating entity "UFM_altufm_none_var" for hierarchy "UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 205 +Warning (10649): Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 145 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 21 +Info (21057): Implemented 243 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 25 input pins + Info (21059): Implemented 29 output pins + Info (21060): Implemented 8 bidirectional pins + Info (21061): Implemented 180 logic cells + Info (21070): Implemented 1 User Flash Memory blocks +Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings + Info: Peak virtual memory: 4700 megabytes + Info: Processing ended: Sat Aug 12 18:54:23 2023 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:21 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM2GS.map.smsg b/CPLD/MAXII/output_files/RAM2GS.map.smsg new file mode 100644 index 0000000..65b2829 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.map.smsg @@ -0,0 +1,3 @@ +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(52): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 52 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(177): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 177 diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index 3ce6ac0..cc099da 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,5 +1,9 @@ -Analysis & Synthesis Status : Failed - Sat Aug 12 18:40:53 2023 +Analysis & Synthesis Status : Successful - Sat Aug 12 18:54:23 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX II +Total logic elements : 180 +Total pins : 62 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2GS.pin b/CPLD/MAXII/output_files/RAM2GS.pin new file mode 100644 index 0000000..b0122be --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.pin @@ -0,0 +1,165 @@ + -- Copyright (C) 2019 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +CHIP "RAM2GS" ASSIGNED TO AN: EPM240T100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND* : 1 : : : : 2 : +RDQMH : 2 : output : 3.3-V LVCMOS : : 1 : Y +nRCS : 3 : output : 3.3-V LVCMOS : : 1 : Y +nRCAS : 4 : output : 3.3-V LVCMOS : : 1 : Y +RBA[0] : 5 : output : 3.3-V LVCMOS : : 1 : Y +nRRAS : 6 : output : 3.3-V LVCMOS : : 1 : Y +RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y +RCKE : 8 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 9 : power : : 3.3V : 1 : +GNDIO : 10 : gnd : : : : +GNDINT : 11 : gnd : : : : +RCLK : 12 : input : 3.3-V LVCMOS : : 1 : Y +VCCINT : 13 : power : : 2.5V/3.3V : : +RBA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y +RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y +RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y +RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y +RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y +RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y +RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y +RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y +RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y +Dout[5] : 28 : output : 3.3-V LVCMOS : : 1 : Y +RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y +RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 31 : power : : 3.3V : 1 : +GNDIO : 32 : gnd : : : : +Dout[0] : 33 : output : 3.3-V LVCMOS : : 1 : Y +Dout[6] : 34 : output : 3.3-V LVCMOS : : 1 : Y +Din[2] : 35 : input : 3.3-V LVCMOS : : 1 : Y +Din[1] : 36 : input : 3.3-V LVCMOS : : 1 : Y +Din[3] : 37 : input : 3.3-V LVCMOS : : 1 : Y +Din[5] : 38 : input : 3.3-V LVCMOS : : 1 : Y +Din[4] : 39 : input : 3.3-V LVCMOS : : 1 : Y +Din[7] : 40 : input : 3.3-V LVCMOS : : 1 : Y +Din[6] : 41 : input : 3.3-V LVCMOS : : 1 : Y +Din[0] : 42 : input : 3.3-V LVCMOS : : 1 : Y +Dout[7] : 43 : output : 3.3-V LVCMOS : : 1 : Y +Dout[4] : 44 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 45 : power : : 3.3V : 1 : +GNDIO : 46 : gnd : : : : +Dout[3] : 47 : output : 3.3-V LVCMOS : : 1 : Y +nFWE : 48 : input : 3.3-V LVCMOS : : 1 : Y +MAin[0] : 49 : input : 3.3-V LVCMOS : : 1 : Y +MAin[2] : 50 : input : 3.3-V LVCMOS : : 1 : Y +MAin[1] : 51 : input : 3.3-V LVCMOS : : 1 : Y +PHI2 : 52 : input : 3.3-V LVCMOS : : 2 : Y +nCCAS : 53 : input : 3.3-V LVCMOS : : 2 : Y +CROW[0] : 54 : input : 3.3-V LVCMOS : : 2 : Y +CROW[1] : 55 : input : 3.3-V LVCMOS : : 2 : Y +Dout[2] : 56 : output : 3.3-V LVCMOS : : 2 : Y +Dout[1] : 57 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 58 : : : : 2 : +VCCIO2 : 59 : power : : 3.3V : 2 : +GNDIO : 60 : gnd : : : : +GND* : 61 : : : : 2 : +GND* : 62 : : : : 2 : +VCCINT : 63 : power : : 2.5V/3.3V : : +GND* : 64 : : : : 2 : +GNDINT : 65 : gnd : : : : +GND* : 66 : : : : 2 : +nCRAS : 67 : input : 3.3-V LVCMOS : : 2 : Y +MAin[7] : 68 : input : 3.3-V LVCMOS : : 2 : Y +MAin[5] : 69 : input : 3.3-V LVCMOS : : 2 : Y +MAin[4] : 70 : input : 3.3-V LVCMOS : : 2 : Y +MAin[3] : 71 : input : 3.3-V LVCMOS : : 2 : Y +MAin[6] : 72 : input : 3.3-V LVCMOS : : 2 : Y +MAin[8] : 73 : input : 3.3-V LVCMOS : : 2 : Y +MAin[9] : 74 : input : 3.3-V LVCMOS : : 2 : Y +GND* : 75 : : : : 2 : +GND* : 76 : : : : 2 : +GND* : 77 : : : : 2 : +GND* : 78 : : : : 2 : +GNDIO : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +GND* : 84 : : : : 2 : +GND* : 85 : : : : 2 : +GND* : 86 : : : : 2 : +GND* : 87 : : : : 2 : +GND* : 88 : : : : 2 : +RD[2] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[5] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[4] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y +GNDIO : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[0] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[7] : 97 : bidir : 3.3-V LVCMOS : : 2 : Y +RDQML : 98 : output : 3.3-V LVCMOS : : 2 : Y +RD[3] : 99 : bidir : 3.3-V LVCMOS : : 2 : Y +nRWE : 100 : output : 3.3-V LVCMOS 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z7{^#`yfgJN=-2WL`B08mo1eNp^o$YA=Wp{?F6>V=W1lKQSUV98<^lhI7q(lg|EumV z+{QI~5npbL3<2zc-uUYvTKU{&&^Jhlx!}2xz;rGRlz_I$Ee`J4tg#0yrUhB`* z`&oZ@g3aY8=4SkAy{ql=9N}9!tWV6h?(%4r^x8c4tKxS`h5D!4FU^HN7d_rT^Y;PV zCA0W*$$yw$i|^z0>ht^m%Ev9S>;HD diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt new file mode 100644 index 0000000..3b21939 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt @@ -0,0 +1,1006 @@ +Timing Analyzer report for RAM2GS +Sat Aug 12 18:54:29 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Fmax Summary + 6. Setup Summary + 7. Hold Summary + 8. Recovery Summary + 9. Removal Summary + 10. Minimum Pulse Width Summary + 11. Setup: 'ARCLK' + 12. Setup: 'DRCLK' + 13. Setup: 'PHI2' + 14. Setup: 'RCLK' + 15. Setup: 'nCRAS' + 16. Hold: 'DRCLK' + 17. Hold: 'ARCLK' + 18. Hold: 'RCLK' + 19. Hold: 'PHI2' + 20. Hold: 'nCRAS' + 21. Setup Transfers + 22. Hold Transfers + 23. Report TCCS + 24. Report RSKM + 25. Unconstrained Paths Summary + 26. Clock Status Summary + 27. Unconstrained Input Ports + 28. Unconstrained Output Ports + 29. Unconstrained Input Ports + 30. Unconstrained Output Ports + 31. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2GS ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; +; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; +; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; +; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; +; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++--------------------------------------------------+ +; Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 53.08 MHz ; 53.08 MHz ; PHI2 ; ; +; 125.66 MHz ; 125.66 MHz ; RCLK ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -99.000 ; -99.000 ; +; DRCLK ; -99.000 ; -99.000 ; +; PHI2 ; -8.919 ; -92.622 ; +; RCLK ; -8.036 ; -241.671 ; +; nCRAS ; -0.777 ; -2.512 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; DRCLK ; -16.785 ; -16.785 ; +; ARCLK ; -16.266 ; -16.266 ; +; RCLK ; -1.047 ; -2.078 ; +; PHI2 ; -0.276 ; -0.276 ; +; nCRAS ; -0.031 ; -0.048 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -29.500 ; -59.000 ; +; DRCLK ; -29.500 ; -59.000 ; +; PHI2 ; -2.289 ; -2.289 ; +; RCLK ; -2.289 ; -2.289 ; +; nCCAS ; -2.289 ; -2.289 ; +; nCRAS ; -2.289 ; -2.289 ; ++-------+---------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.734 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.175 ; 1.559 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.740 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.642 ; 2.098 ; +; -22.215 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.642 ; 1.573 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Setup: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -8.919 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.086 ; +; -8.919 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.086 ; +; -8.858 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ; +; -8.858 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ; +; -8.858 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ; +; -8.858 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.025 ; +; -8.767 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.934 ; +; -8.767 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.934 ; +; -8.706 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ; +; -8.706 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ; +; -8.706 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ; +; -8.706 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.873 ; +; -8.631 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.798 ; +; -8.631 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.798 ; +; -8.570 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ; +; -8.570 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ; +; -8.570 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ; +; -8.570 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.737 ; +; -8.466 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.633 ; +; -8.466 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.633 ; +; -8.405 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ; +; -8.405 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ; +; -8.405 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ; +; -8.405 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.572 ; +; -8.220 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ; +; -8.220 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ; +; -8.159 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ; +; -8.159 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ; +; -8.159 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ; +; -8.159 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.326 ; +; -7.978 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.145 ; +; -7.968 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.135 ; +; -7.925 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ; +; -7.925 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.092 ; +; -7.864 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ; +; -7.864 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ; +; -7.864 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ; +; -7.864 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.031 ; +; -7.826 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.993 ; +; -7.816 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.983 ; +; -7.702 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.869 ; +; -7.702 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.869 ; +; -7.690 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.857 ; +; -7.680 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.847 ; +; -7.641 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; +; -7.641 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; +; -7.641 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; +; -7.641 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.808 ; +; -7.525 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.692 ; +; -7.515 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.682 ; +; -7.413 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.580 ; +; -7.413 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.580 ; +; -7.352 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ; +; -7.352 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ; +; -7.352 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ; +; -7.352 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.519 ; +; -7.279 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.446 ; +; -7.269 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.436 ; +; -6.984 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ; +; -6.974 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.141 ; +; -6.761 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.928 ; +; -6.751 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.918 ; +; -6.726 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.893 ; +; -6.642 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.809 ; +; -6.642 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.809 ; +; -6.574 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.741 ; +; -6.490 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.657 ; +; -6.490 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.657 ; +; -6.472 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.639 ; +; -6.462 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.629 ; +; -6.438 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.605 ; +; -6.354 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.521 ; +; -6.354 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.521 ; +; -6.273 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.440 ; +; -6.189 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.356 ; +; -6.189 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.356 ; +; -6.027 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.194 ; +; -5.943 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.110 ; +; -5.943 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.110 ; +; -5.732 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.899 ; +; -5.648 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.815 ; +; -5.648 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.815 ; +; -5.509 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.676 ; +; -5.425 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.592 ; +; -5.425 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.592 ; +; -5.220 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.387 ; +; -5.173 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.840 ; +; -5.173 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.840 ; +; -5.136 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.303 ; +; -5.136 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.303 ; +; -5.112 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ; +; -5.112 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ; +; -5.112 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ; +; -5.112 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.779 ; +; -3.396 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 3.563 ; +; -3.353 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.020 ; +; -3.343 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 4.010 ; +; -3.184 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.851 ; +; -3.174 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.841 ; +; -2.980 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 3.647 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -8.036 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.644 ; +; -7.606 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.214 ; +; -7.568 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.176 ; +; -7.441 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 5.049 ; +; -7.125 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.733 ; +; -7.066 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.674 ; +; -6.958 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.625 ; +; -6.908 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.575 ; +; -6.901 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.509 ; +; -6.842 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.509 ; +; -6.824 ; FS[7] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.491 ; +; -6.800 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.797 ; +; -6.795 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.462 ; +; -6.746 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.413 ; +; -6.745 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.412 ; +; -6.724 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.391 ; +; -6.715 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.382 ; +; -6.674 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.341 ; +; -6.673 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.281 ; +; -6.661 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.328 ; +; -6.658 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.325 ; +; -6.616 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.283 ; +; -6.608 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.275 ; +; -6.607 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.274 ; +; -6.590 ; FS[5] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.257 ; +; -6.585 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 4.193 ; +; -6.583 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ; +; -6.583 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.250 ; +; -6.568 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.235 ; +; -6.566 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.233 ; +; -6.561 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.228 ; +; -6.524 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.191 ; +; -6.511 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.178 ; +; -6.453 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.120 ; +; -6.446 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.113 ; +; -6.444 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.111 ; +; -6.427 ; FS[6] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.094 ; +; -6.425 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.092 ; +; -6.420 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.087 ; +; -6.403 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.070 ; +; -6.387 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.054 ; +; -6.382 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.049 ; +; -6.376 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.373 ; +; -6.364 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.031 ; +; -6.358 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.355 ; +; -6.350 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.017 ; +; -6.349 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.016 ; +; -6.332 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.999 ; +; -6.316 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.983 ; +; -6.314 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.981 ; +; -6.307 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.974 ; +; -6.283 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.950 ; +; -6.278 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.275 ; +; -6.266 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.933 ; +; -6.230 ; FS[4] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.897 ; +; -6.219 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.886 ; +; -6.219 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 3.216 ; +; -6.186 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.853 ; +; -6.181 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.848 ; +; -6.169 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ; +; -6.163 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.559 ; 3.771 ; +; -6.137 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.804 ; +; -6.111 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.778 ; +; -6.046 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.713 ; +; -6.029 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.696 ; +; -6.022 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.689 ; +; -6.010 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.677 ; +; -5.989 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.656 ; +; -5.972 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.639 ; +; -5.909 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.170 ; 2.906 ; +; -5.900 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.567 ; +; -5.899 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.566 ; +; -5.898 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.565 ; +; -5.873 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.540 ; +; -5.834 ; InitReady ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.501 ; +; -5.834 ; InitReady ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.501 ; +; -5.822 ; FS[8] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.489 ; +; -5.785 ; InitReady ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.452 ; +; -5.737 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.404 ; +; -5.727 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.394 ; +; -5.718 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.385 ; +; -5.666 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.333 ; +; -5.663 ; S[1] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.330 ; +; -5.663 ; S[1] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.330 ; +; -5.652 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.642 ; 7.961 ; +; -5.646 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.313 ; +; -5.614 ; S[1] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.281 ; +; -5.604 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.271 ; +; -5.600 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.267 ; +; -5.591 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.258 ; +; -5.590 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.257 ; +; -5.588 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.255 ; +; -5.571 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.238 ; +; -5.558 ; FS[14] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.225 ; +; -5.526 ; S[0] ; IS[0] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.193 ; +; -5.526 ; S[0] ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.193 ; +; -5.525 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.192 ; +; -5.503 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.170 ; +; -5.477 ; S[0] ; IS[1] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.144 ; +; -5.467 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.134 ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Setup: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.777 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.907 ; 6.851 ; +; -0.446 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.172 ; +; -0.445 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.171 ; +; -0.434 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.160 ; +; -0.410 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 3.136 ; +; -0.277 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.907 ; 6.851 ; +; 0.127 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.599 ; +; 0.128 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.598 ; +; 0.137 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.589 ; +; 0.145 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.581 ; +; 0.398 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.328 ; +; 0.406 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.320 ; +; 0.463 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.263 ; +; 0.477 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.559 ; 2.249 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.785 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.642 ; 1.573 ; +; -16.260 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.642 ; 2.098 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.266 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.175 ; 1.559 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_var:UFM_altufm_none_var_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Hold: 'RCLK' ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; -1.047 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; 0.000 ; 3.348 ; 2.898 ; +; -1.031 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 3.348 ; 2.914 ; +; -0.547 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; -0.500 ; 3.348 ; 2.898 ; +; -0.531 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 3.348 ; 2.914 ; +; 1.128 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.697 ; +; 1.247 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.816 ; +; 1.348 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.917 ; +; 1.398 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.619 ; +; 1.628 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.697 ; +; 1.659 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ; +; 1.660 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.881 ; +; 1.678 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.899 ; +; 1.687 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.908 ; +; 1.747 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.816 ; +; 1.848 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.917 ; +; 1.919 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.140 ; +; 1.962 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.183 ; +; 1.963 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.184 ; +; 1.972 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.193 ; +; 1.973 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.194 ; +; 2.044 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.265 ; +; 2.107 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.328 ; +; 2.116 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; +; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.126 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; +; 2.143 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.364 ; +; 2.144 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ; +; 2.144 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ; +; 2.145 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ; +; 2.151 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.372 ; +; 2.166 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.387 ; +; 2.221 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; +; 2.222 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.443 ; +; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; +; 2.239 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.241 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; +; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; +; 2.250 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.472 ; +; 2.251 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.472 ; +; 2.264 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.485 ; +; 2.353 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.574 ; +; 2.414 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.635 ; +; 2.476 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.697 ; +; 2.586 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.807 ; +; 2.597 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.818 ; +; 2.633 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.854 ; +; 2.692 ; ARShift ; ARShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.913 ; +; 2.703 ; DRDIn ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.924 ; +; 2.704 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.925 ; +; 2.712 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.933 ; +; 2.814 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ; +; 2.868 ; RASr2 ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.089 ; +; 2.902 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.123 ; +; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ; +; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; +; 2.975 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.196 ; +; 2.976 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.197 ; +; 2.977 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.198 ; +; 2.979 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.200 ; +; 2.995 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.216 ; +; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ; +; 3.060 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; +; 3.062 ; Ready ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.283 ; +; 3.085 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.306 ; +; 3.086 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.307 ; +; 3.087 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.308 ; +; 3.088 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.309 ; +; 3.167 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.388 ; +; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; +; 3.171 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; +; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.181 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ; +; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ; +; 3.197 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.418 ; +; 3.200 ; S[1] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.421 ; +; 3.212 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.433 ; +; 3.217 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.438 ; +; 3.243 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.464 ; +; 3.278 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.499 ; +; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; +; 3.290 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; +; 3.290 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; +; 3.290 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.511 ; +; 3.302 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.523 ; +; 3.311 ; IS[2] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.532 ; +; 3.359 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.580 ; +; 3.362 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.583 ; +; 3.365 ; RASr2 ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.586 ; +; 3.401 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.622 ; +; 3.401 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.622 ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -0.276 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.170 ; 2.615 ; +; 0.043 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.170 ; 3.434 ; +; 0.634 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.170 ; 4.025 ; +; 1.675 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 1.896 ; +; 1.927 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.148 ; +; 2.154 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.375 ; +; 3.426 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.647 ; +; 3.620 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.841 ; +; 3.630 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.851 ; +; 3.789 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.010 ; +; 3.799 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.020 ; +; 3.842 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.563 ; +; 4.018 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.739 ; +; 4.023 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.744 ; +; 4.307 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.028 ; +; 4.312 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.033 ; +; 4.530 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.251 ; +; 4.535 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.256 ; +; 4.825 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.546 ; +; 4.830 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.551 ; +; 5.071 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.792 ; +; 5.076 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.797 ; +; 5.236 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.957 ; +; 5.241 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.962 ; +; 5.324 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.045 ; +; 5.372 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.093 ; +; 5.377 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.098 ; +; 5.524 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.245 ; +; 5.529 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.250 ; +; 5.558 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ; +; 5.558 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ; +; 5.558 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ; +; 5.558 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.779 ; +; 5.613 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.334 ; +; 5.619 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.840 ; +; 5.619 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.840 ; +; 5.666 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.387 ; +; 5.836 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.557 ; +; 5.955 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.676 ; +; 6.131 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.852 ; +; 6.178 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.899 ; +; 6.186 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.907 ; +; 6.377 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.098 ; +; 6.473 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.194 ; +; 6.475 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.196 ; +; 6.542 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.263 ; +; 6.678 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.399 ; +; 6.698 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.419 ; +; 6.719 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.440 ; +; 6.830 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.551 ; +; 6.884 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.605 ; +; 6.993 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.714 ; +; 7.020 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.741 ; +; 7.172 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.893 ; +; 7.239 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.960 ; +; 7.404 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.125 ; +; 7.540 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.261 ; +; 7.692 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.413 ; +; 7.798 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ; +; 7.798 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ; +; 7.798 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ; +; 7.798 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.519 ; +; 7.859 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.580 ; +; 7.859 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.580 ; +; 8.087 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ; +; 8.087 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ; +; 8.087 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ; +; 8.087 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.808 ; +; 8.148 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.869 ; +; 8.148 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.869 ; +; 8.310 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ; +; 8.310 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ; +; 8.310 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ; +; 8.310 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.031 ; +; 8.371 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.092 ; +; 8.371 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.092 ; +; 8.605 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ; +; 8.605 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ; +; 8.605 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ; +; 8.605 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.326 ; +; 8.666 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ; +; 8.666 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ; +; 8.851 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ; +; 8.851 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ; +; 8.851 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ; +; 8.851 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.572 ; +; 8.912 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.633 ; +; 8.912 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.633 ; +; 9.016 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ; +; 9.016 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ; +; 9.016 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ; +; 9.016 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.737 ; +; 9.077 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.798 ; +; 9.077 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.798 ; +; 9.152 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ; +; 9.152 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ; +; 9.152 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ; +; 9.152 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.873 ; +; 9.213 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.934 ; +; 9.213 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.934 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.031 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.249 ; +; -0.017 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.263 ; +; 0.040 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.320 ; +; 0.048 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.328 ; +; 0.301 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.581 ; +; 0.309 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.589 ; +; 0.318 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.598 ; +; 0.319 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 2.599 ; +; 0.723 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.907 ; 6.851 ; +; 0.856 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.136 ; +; 0.880 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.160 ; +; 0.891 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.171 ; +; 0.892 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.559 ; 3.172 ; +; 1.223 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.907 ; 6.851 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 30 ; 30 ; +; Unconstrained Input Port Paths ; 231 ; 231 ; +; Unconstrained Output Ports ; 37 ; 37 ; +; Unconstrained Output Port Paths ; 75 ; 75 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; ARCLK ; ARCLK ; Base ; Constrained ; +; DRCLK ; DRCLK ; Base ; Constrained ; +; PHI2 ; PHI2 ; Base ; Constrained ; +; RCLK ; RCLK ; Base ; Constrained ; +; nCCAS ; nCCAS ; Base ; Constrained ; +; nCRAS ; nCRAS ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; CROW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CROW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; CROW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CROW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Sat Aug 12 18:54:28 2023 +Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name nCCAS nCCAS + Info (332105): create_clock -period 1.000 -name nCRAS nCRAS + Info (332105): create_clock -period 1.000 -name RCLK RCLK + Info (332105): create_clock -period 1.000 -name PHI2 PHI2 + Info (332105): create_clock -period 1.000 -name DRCLK DRCLK + Info (332105): create_clock -period 1.000 -name ARCLK ARCLK +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -99.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -99.000 -99.000 ARCLK + Info (332119): -99.000 -99.000 DRCLK + Info (332119): -8.919 -92.622 PHI2 + Info (332119): -8.036 -241.671 RCLK + Info (332119): -0.777 -2.512 nCRAS +Info (332146): Worst-case hold slack is -16.785 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -16.785 -16.785 DRCLK + Info (332119): -16.266 -16.266 ARCLK + Info (332119): -1.047 -2.078 RCLK + Info (332119): -0.276 -0.276 PHI2 + Info (332119): -0.031 -0.048 nCRAS +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -29.500 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -29.500 -59.000 ARCLK + Info (332119): -29.500 -59.000 DRCLK + Info (332119): -2.289 -2.289 PHI2 + Info (332119): -2.289 -2.289 RCLK + Info (332119): -2.289 -2.289 nCCAS + Info (332119): -2.289 -2.289 nCRAS +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 4676 megabytes + Info: Processing ended: Sat Aug 12 18:54:29 2023 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.summary b/CPLD/MAXII/output_files/RAM2GS.sta.summary new file mode 100644 index 0000000..bd02d51 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2GS.sta.summary @@ -0,0 +1,69 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Setup 'ARCLK' +Slack : -99.000 +TNS : -99.000 + +Type : Setup 'DRCLK' +Slack : -99.000 +TNS : -99.000 + +Type : Setup 'PHI2' +Slack : -8.919 +TNS : -92.622 + +Type : Setup 'RCLK' +Slack : -8.036 +TNS : -241.671 + +Type : Setup 'nCRAS' +Slack : -0.777 +TNS : -2.512 + +Type : Hold 'DRCLK' +Slack : -16.785 +TNS : -16.785 + +Type : Hold 'ARCLK' +Slack : -16.266 +TNS : -16.266 + +Type : Hold 'RCLK' +Slack : -1.047 +TNS : -2.078 + +Type : Hold 'PHI2' +Slack : -0.276 +TNS : -0.276 + +Type : Hold 'nCRAS' +Slack : -0.031 +TNS : -0.048 + +Type : Minimum Pulse Width 'ARCLK' +Slack : -29.500 +TNS : -59.000 + +Type : Minimum Pulse Width 'DRCLK' +Slack : -29.500 +TNS : -59.000 + +Type : Minimum Pulse Width 'PHI2' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'RCLK' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'nCCAS' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'nCRAS' +Slack : -2.289 +TNS : -2.289 + +------------------------------------------------------------ diff --git a/CPLD/MAXV/RAM2GS.qsf b/CPLD/MAXV/RAM2GS.qsf index 4802195..eafca6c 100644 --- a/CPLD/MAXV/RAM2GS.qsf +++ b/CPLD/MAXV/RAM2GS.qsf @@ -44,10 +44,156 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:29 AUGUST 12, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +# +# set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" \ No newline at end of file +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" + + +set_global_assignment -name QIP_FILE UFM.qip +#set_global_assignment -name MIF_FILE "../RAM2GS.mif" + + + +set_location_assignment PIN_12 -to RCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK + +set_location_assignment PIN_52 -to PHI2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2 + +set_location_assignment PIN_67 -to nCRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS + +set_location_assignment PIN_53 -to nCCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS + +set_location_assignment PIN_48 -to nFWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE + +set_location_assignment PIN_49 -to MAin[0] +set_location_assignment PIN_51 -to MAin[1] +set_location_assignment PIN_50 -to MAin[2] +set_location_assignment PIN_71 -to MAin[3] +set_location_assignment PIN_70 -to MAin[4] +set_location_assignment PIN_69 -to MAin[5] +set_location_assignment PIN_72 -to MAin[6] +set_location_assignment PIN_68 -to MAin[7] +set_location_assignment PIN_73 -to MAin[8] +set_location_assignment PIN_74 -to MAin[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin + +set_location_assignment PIN_54 -to CROW[0] +set_location_assignment PIN_55 -to CROW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW + +set_location_assignment PIN_35 -to Din[2] +set_location_assignment PIN_36 -to Din[1] +set_location_assignment PIN_37 -to Din[3] +set_location_assignment PIN_38 -to Din[5] +set_location_assignment PIN_39 -to Din[4] +set_location_assignment PIN_40 -to Din[7] +set_location_assignment PIN_41 -to Din[6] +set_location_assignment PIN_42 -to Din[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din + +set_location_assignment PIN_33 -to Dout[0] +set_location_assignment PIN_57 -to Dout[1] +set_location_assignment PIN_56 -to Dout[2] +set_location_assignment PIN_47 -to Dout[3] +set_location_assignment PIN_44 -to Dout[4] +set_location_assignment PIN_28 -to Dout[5] +set_location_assignment PIN_34 -to Dout[6] +set_location_assignment PIN_43 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout + +set_location_assignment PIN_8 -to RCKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE + +set_location_assignment PIN_3 -to nRCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS + +set_location_assignment PIN_100 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE + +set_location_assignment PIN_6 -to nRRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS + +set_location_assignment PIN_4 -to nRCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS + +set_location_assignment PIN_5 -to RBA[0] +set_location_assignment PIN_14 -to RBA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA + +set_location_assignment PIN_2 -to RDQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH + +set_location_assignment PIN_98 -to RDQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML + +set_location_assignment PIN_96 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_89 -to RD[2] +set_location_assignment PIN_99 -to RD[3] +set_location_assignment PIN_92 -to RD[4] +set_location_assignment PIN_91 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_97 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD + +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS +set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD + +set_location_assignment PIN_88 -to LED \ No newline at end of file diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws deleted file mode 100644 index c6dfa4a514e35eeb19aeb10f756214b9525b71c9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 619 zcmbV}!AiqW5JhjA3NHNs7cNAC5NT@#5d?AJ%9Xg+nxr;FO{@_Y;y3vrZru7U*6NvQ zy0R4XJ?7oHlbJX7O^zbX*Sc;r(1U7S=t-rZU%-DY}%mXdg(<+r-RP%_a>2WNo&1U53J18#>k_XnpQr=U~Z%u24U= zRJ+y%o6lO)38fhlEG1E~D9MDGMLJWC*3o}D`8>E}(?wOwrIPncYDmabZ1cvldE@Qh duh|Jc-rwf`%GyXPhfH}i^S$kqAx+^yOF#b!XixwE diff --git a/CPLD/MAXV/UFM.qip b/CPLD/MAXV/UFM.qip new file mode 100644 index 0000000..b7d0346 --- /dev/null +++ b/CPLD/MAXV/UFM.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE Intel FPGA IP" +set_global_assignment -name IP_TOOL_VERSION "19.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"] diff --git a/CPLD/MAXV/UFM.v b/CPLD/MAXV/UFM.v new file mode 100644 index 0000000..be7c3d0 --- /dev/null +++ b/CPLD/MAXV/UFM.v @@ -0,0 +1,257 @@ +// megafunction wizard: %ALTUFM_NONE Intel FPGA IP% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTUFM_NONE + +// ============================================================ +// File Name: UFM.v +// Megafunction Name(s): +// ALTUFM_NONE +// +// Simulation Library Files(s): +// maxv +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 19.1.0 Build 670 09/22/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + +//synthesis_resources = maxv_ufm 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module UFM_altufm_none_38r + ( + arclk, + ardin, + arshft, + busy, + drclk, + drdin, + drdout, + drshft, + erase, + osc, + oscena, + program, + rtpbusy) ; + input arclk; + input ardin; + input arshft; + output busy; + input drclk; + input drdin; + output drdout; + input drshft; + input erase; + output osc; + input oscena; + input program; + output rtpbusy; + + wire wire_maxii_ufm_block1_bgpbusy; + wire wire_maxii_ufm_block1_busy; + wire wire_maxii_ufm_block1_drdout; + wire wire_maxii_ufm_block1_osc; + wire ufm_arclk; + wire ufm_ardin; + wire ufm_arshft; + wire ufm_bgpbusy; + wire ufm_busy; + wire ufm_drclk; + wire ufm_drdin; + wire ufm_drdout; + wire ufm_drshft; + wire ufm_erase; + wire ufm_osc; + wire ufm_oscena; + wire ufm_program; + + maxv_ufm maxii_ufm_block1 + ( + .arclk(ufm_arclk), + .ardin(ufm_ardin), + .arshft(ufm_arshft), + .bgpbusy(wire_maxii_ufm_block1_bgpbusy), + .busy(wire_maxii_ufm_block1_busy), + .drclk(ufm_drclk), + .drdin(ufm_drdin), + .drdout(wire_maxii_ufm_block1_drdout), + .drshft(ufm_drshft), + .erase(ufm_erase), + .osc(wire_maxii_ufm_block1_osc), + .oscena(ufm_oscena), + .program(ufm_program) + // synopsys translate_off + , + .ctrl_bgpbusy(1'b0), + .devclrn(1'b1), + .devpor(1'b1), + .sbdin(1'b0), + .sbdout() + // synopsys translate_on + ); + defparam + maxii_ufm_block1.address_width = 9, + maxii_ufm_block1.erase_time = 500000000, + maxii_ufm_block1.init_file = "RAM2GS.mif", + maxii_ufm_block1.osc_sim_setting = 180000, + maxii_ufm_block1.program_time = 1600000, + maxii_ufm_block1.lpm_type = "maxv_ufm"; + assign + busy = ufm_busy, + drdout = ufm_drdout, + osc = ufm_osc, + rtpbusy = ufm_bgpbusy, + ufm_arclk = arclk, + ufm_ardin = ardin, + ufm_arshft = arshft, + ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy, + ufm_busy = wire_maxii_ufm_block1_busy, + ufm_drclk = drclk, + ufm_drdin = drdin, + ufm_drdout = wire_maxii_ufm_block1_drdout, + ufm_drshft = drshft, + ufm_erase = erase, + ufm_osc = wire_maxii_ufm_block1_osc, + ufm_oscena = oscena, + ufm_program = program; + initial/*synthesis enable_verilog_initial_construct*/ + begin + $display("Warning: Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results."); + end +endmodule //UFM_altufm_none_38r +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module UFM ( + arclk, + ardin, + arshft, + drclk, + drdin, + drshft, + erase, + oscena, + program, + busy, + drdout, + osc, + rtpbusy); + + input arclk; + input ardin; + input arshft; + input drclk; + input drdin; + input drshft; + input erase; + input oscena; + input program; + output busy; + output drdout; + output osc; + output rtpbusy; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire sub_wire3; + wire busy = sub_wire0; + wire drdout = sub_wire1; + wire osc = sub_wire2; + wire rtpbusy = sub_wire3; + + UFM_altufm_none_38r UFM_altufm_none_38r_component ( + .arclk (arclk), + .ardin (ardin), + .arshft (arshft), + .drclk (drclk), + .drdin (drdin), + .drshft (drshft), + .erase (erase), + .oscena (oscena), + .program (program), + .busy (sub_wire0), + .drdout (sub_wire1), + .osc (sub_wire2), + .rtpbusy (sub_wire3)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V" +// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS.mif" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" +// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" +// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000" +// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9" +// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk" +// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0 +// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin" +// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0 +// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft" +// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0 +// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk" +// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0 +// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin" +// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0 +// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout" +// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0 +// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft" +// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0 +// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase" +// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0 +// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc" +// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0 +// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena" +// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0 +// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program" +// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0 +// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy" +// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE 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19:12:38 2023 diff --git a/CPLD/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAXV/db/RAM2GS.fit.qmsg new file mode 100644 index 0000000..a980d35 --- /dev/null +++ b/CPLD/MAXV/db/RAM2GS.fit.qmsg @@ -0,0 +1,45 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691898466325 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691898466325 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691898466325 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691898466372 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691898466372 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691898466388 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691898466404 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898466497 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691898466497 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691898466544 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691898466544 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691898466544 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691898466544 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898466544 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691898466544 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691898466544 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691898466544 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691898466544 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 333 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 335 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898466560 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 334 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691898466560 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691898466575 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691898466591 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691898466591 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691898466591 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691898466591 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898466622 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691898466622 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691898466700 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898466803 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691898466803 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691898467115 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898467115 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691898467131 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691898467240 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691898467240 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691898467475 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691898467475 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898467475 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.21 " "Total time spent on timing analysis during the Fitter is 0.21 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691898467475 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898467490 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691898467506 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691898467537 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691898467569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 23:47:47 2023 " "Processing ended: Sat Aug 12 23:47:47 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691898467569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691898467569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691898467569 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691898467569 ""} diff --git a/CPLD/MAXV/db/RAM2GS.hier_info b/CPLD/MAXV/db/RAM2GS.hier_info new file mode 100644 index 0000000..05f5d6b --- /dev/null +++ b/CPLD/MAXV/db/RAM2GS.hier_info @@ -0,0 +1,279 @@ +|RAM2GS +PHI2 => Bank[0].CLK +PHI2 => Bank[1].CLK +PHI2 => Bank[2].CLK +PHI2 => Bank[3].CLK +PHI2 => Bank[4].CLK +PHI2 => Bank[5].CLK +PHI2 => Bank[6].CLK +PHI2 => Bank[7].CLK +PHI2 => RA11.CLK +PHI2 => PHI2r.DATAIN +PHI2 => CmdDRDIn.CLK +PHI2 => CmdDRCLK.CLK +PHI2 => CmdUFMPrgm.CLK +PHI2 => CmdUFMErase.CLK +PHI2 => CmdSubmitted.CLK +PHI2 => Cmdn8MEGEN.CLK +PHI2 => XOR8MEG.CLK +PHI2 => ADSubmitted.CLK +PHI2 => C1Submitted.CLK +PHI2 => UFMOscEN.CLK +PHI2 => CmdEnable.CLK +MAin[0] => RA.DATAA +MAin[0] => RowA.DATAB +MAin[0] => Equal0.IN7 +MAin[0] => Equal1.IN7 +MAin[0] => Equal3.IN6 +MAin[1] => RA.DATAA +MAin[1] => RowA.DATAB +MAin[1] => Equal0.IN6 +MAin[1] => Equal1.IN6 +MAin[1] => Equal3.IN7 +MAin[2] => RA.DATAA +MAin[2] => RowA.DATAB +MAin[2] => Equal0.IN5 +MAin[2] => Equal1.IN5 +MAin[2] => Equal3.IN5 +MAin[3] => RA.DATAA +MAin[3] => RowA.DATAB +MAin[3] => Equal0.IN4 +MAin[3] => Equal1.IN4 +MAin[3] => Equal3.IN4 +MAin[4] => RA.DATAA +MAin[4] => RowA.DATAB +MAin[4] => Equal0.IN3 +MAin[4] => Equal1.IN3 +MAin[4] => Equal3.IN3 +MAin[5] => RA.DATAA +MAin[5] => RowA.DATAB +MAin[5] => Equal0.IN2 +MAin[5] => Equal1.IN2 +MAin[5] => Equal3.IN2 +MAin[6] => RA.DATAA +MAin[6] => RowA.DATAB +MAin[6] => Equal0.IN1 +MAin[6] => Equal1.IN1 +MAin[6] => Equal3.IN1 +MAin[7] => RA.DATAA +MAin[7] => RowA.DATAB +MAin[7] => Equal0.IN0 +MAin[7] => Equal1.IN0 +MAin[7] => Equal3.IN0 +MAin[8] => RA.DATAA +MAin[8] => RowA.DATAB +MAin[9] => RA.DATAA +MAin[9] => RDQMH.DATAA +MAin[9] => RowA.DATAB +MAin[9] => RDQML.DATAA +CROW[0] => RBA.DATAB +CROW[1] => RBA.DATAB +Din[0] => CmdDRDIn.DATAB +Din[0] => XOR8MEG.DATAB +Din[0] => WRD[0].DATAIN +Din[0] => Bank[0].DATAIN +Din[0] => Equal14.IN2 +Din[0] => Equal15.IN4 +Din[0] => Cmdn8MEGEN.DATAB +Din[1] => CmdDRCLK.DATAB +Din[1] => WRD[1].DATAIN +Din[1] => Bank[1].DATAIN +Din[1] => Equal14.IN7 +Din[1] => Equal15.IN7 +Din[2] => CmdUFMPrgm.DATAB +Din[2] => WRD[2].DATAIN +Din[2] => Bank[2].DATAIN +Din[2] => Equal14.IN6 +Din[2] => Equal15.IN3 +Din[3] => CmdUFMErase.DATAB +Din[3] => WRD[3].DATAIN +Din[3] => Bank[3].DATAIN +Din[3] => Equal14.IN5 +Din[3] => Equal15.IN2 +Din[4] => WRD[4].DATAIN +Din[4] => Bank[4].DATAIN +Din[4] => Equal14.IN4 +Din[4] => Equal15.IN6 +Din[4] => Equal16.IN3 +Din[4] => Equal17.IN0 +Din[4] => Equal18.IN3 +Din[5] => WRD[5].DATAIN +Din[5] => Bank[5].DATAIN +Din[5] => Equal14.IN3 +Din[5] => Equal15.IN1 +Din[5] => Equal16.IN2 +Din[5] => Equal17.IN3 +Din[5] => Equal18.IN0 +Din[6] => RA11.IN1 +Din[6] => WRD[6].DATAIN +Din[6] => Bank[6].DATAIN +Din[6] => Equal14.IN1 +Din[6] => Equal15.IN5 +Din[6] => Equal16.IN1 +Din[6] => Equal17.IN2 +Din[6] => Equal18.IN2 +Din[7] => WRD[7].DATAIN +Din[7] => Bank[7].DATAIN +Din[7] => Equal14.IN0 +Din[7] => Equal15.IN0 +Din[7] => Equal16.IN0 +Din[7] => Equal17.IN1 +Din[7] => Equal18.IN1 +Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE +nCCAS => WRD[0].CLK +nCCAS => WRD[1].CLK +nCCAS => WRD[2].CLK +nCCAS => WRD[3].CLK +nCCAS => WRD[4].CLK +nCCAS => WRD[5].CLK +nCCAS => WRD[6].CLK +nCCAS => WRD[7].CLK +nCCAS => comb.IN0 +nCCAS => CBR.DATAIN +nCCAS => CASr.DATAIN +nCRAS => CBR.CLK +nCRAS => FWEr.CLK +nCRAS => RowA[0].CLK +nCRAS => RowA[1].CLK +nCRAS => RowA[2].CLK +nCRAS => RowA[3].CLK +nCRAS => RowA[4].CLK +nCRAS => RowA[5].CLK +nCRAS => RowA[6].CLK +nCRAS => RowA[7].CLK +nCRAS => RowA[8].CLK +nCRAS => RowA[9].CLK +nCRAS => RBA[0]~reg0.CLK +nCRAS => RBA[1]~reg0.CLK +nCRAS => LED.IN1 +nCRAS => RASr.DATAIN +nFWE => comb.IN1 +nFWE => CMDWR.IN1 +nFWE => ADWR.IN1 +nFWE => C1WR.IN1 +nFWE => FWEr.DATAIN +LED << LED.DB_MAX_OUTPUT_PORT_TYPE +RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE +RD[0] <> RD[0] +RD[1] <> RD[1] +RD[2] <> RD[2] +RD[3] <> RD[3] +RD[4] <> RD[4] +RD[5] <> RD[5] +RD[6] <> RD[6] +RD[7] <> RD[7] +nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RCLK => UFMProgram.CLK +RCLK => UFMErase.CLK +RCLK => UFMReqErase.CLK +RCLK => n8MEGEN.CLK +RCLK => UFMInitDone.CLK +RCLK => UFMD.CLK +RCLK => DRShift.CLK +RCLK => DRDIn.CLK +RCLK => DRCLK.CLK +RCLK => ARShift.CLK +RCLK => ARCLK.CLK +RCLK => Ready.CLK +RCLK => IS[0].CLK +RCLK => IS[1].CLK +RCLK => IS[2].CLK +RCLK => IS[3].CLK +RCLK => nRowColSel.CLK +RCLK => RCKEEN.CLK +RCLK => RA10.CLK +RCLK => nRWE~reg0.CLK +RCLK => nRCAS~reg0.CLK +RCLK => nRRAS~reg0.CLK +RCLK => nRCS~reg0.CLK +RCLK => RCKE~reg0.CLK +RCLK => InitReady.CLK +RCLK => FS[0].CLK +RCLK => FS[1].CLK +RCLK => FS[2].CLK +RCLK => FS[3].CLK +RCLK => FS[4].CLK +RCLK => FS[5].CLK +RCLK => FS[6].CLK +RCLK => FS[7].CLK +RCLK => FS[8].CLK +RCLK => FS[9].CLK +RCLK => FS[10].CLK +RCLK => FS[11].CLK +RCLK => FS[12].CLK +RCLK => FS[13].CLK +RCLK => FS[14].CLK +RCLK => FS[15].CLK +RCLK => FS[16].CLK +RCLK => FS[17].CLK +RCLK => S[0].CLK +RCLK => S[1].CLK +RCLK => CASr3.CLK +RCLK => CASr2.CLK +RCLK => CASr.CLK +RCLK => RASr3.CLK +RCLK => RASr2.CLK +RCLK => RASr.CLK +RCLK => PHI2r3.CLK +RCLK => PHI2r2.CLK +RCLK => PHI2r.CLK +RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE +RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE + + +|RAM2GS|UFM:UFM_inst +arclk => arclk.IN1 +ardin => ardin.IN1 +arshft => arshft.IN1 +drclk => drclk.IN1 +drdin => drdin.IN1 +drshft => drshft.IN1 +erase => erase.IN1 +oscena => oscena.IN1 +program => program.IN1 +busy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.busy +drdout <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.drdout +osc <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.osc +rtpbusy <= UFM_altufm_none_38r:UFM_altufm_none_38r_component.rtpbusy + + +|RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component +arclk => maxii_ufm_block1.ARCLK +ardin => maxii_ufm_block1.ARDIN +arshft => maxii_ufm_block1.ARSHFT +busy <= maxii_ufm_block1.BUSY +drclk => maxii_ufm_block1.DRCLK +drdin => maxii_ufm_block1.DRDIN +drdout <= maxii_ufm_block1.DRDOUT +drshft => maxii_ufm_block1.DRSHFT +erase => maxii_ufm_block1.ERASE +osc <= maxii_ufm_block1.OSC +oscena => maxii_ufm_block1.OSCENA +program => maxii_ufm_block1.PROGRAM +rtpbusy <= maxii_ufm_block1.BGPBUSY + + diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif index a9f6e2ca7f61f35386628e9d9791e17ca3041c9f..9b78726a485db81e970e164f2e013459c7b4bea6 100644 GIT binary patch literal 573 zcmV-D0>b^Q4*>uG0001Zob6J}j+-zP-COEESei|{2xCaXV|Hmu5~>7JNV2sYV-ia| zQe&b$3}^6;>6y zMYkd_7{Ev>DC+LLAmReoL>@~x7&I9-k9*_YiQVGU@|x!C^^x1e9b~!W@&dNAmHH`V zA;^J&cwdK;l`)UB_xcBo=1EWF4yMI{Q(T;yso^7-Y&QW`ML2Y)!QA&YUN`lVDy5`k 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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_38r_component9000400000000
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0 0 "Design Software" 0 -1 1691898432218 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691898432223 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 23:47:12 2023 " "Processing started: Sat Aug 12 23:47:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691898432223 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898432223 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898432223 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691898432533 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691898432533 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691898440841 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691898440841 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898440841 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691898440872 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(177) " "Verilog HDL Declaration warning at UFM.v(177): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 177 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691898440872 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691898440872 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 154 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691898440872 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898440872 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691898440904 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LEDEN RAM2GS-MAX.v(20) " "Verilog HDL or VHDL warning at RAM2GS-MAX.v(20): object \"LEDEN\" assigned a value but never read" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 20 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1691898440904 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(161) " "Verilog HDL assignment warning at RAM2GS-MAX.v(161): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 161 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691898440904 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(166) " "Verilog HDL assignment warning at RAM2GS-MAX.v(166): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691898440904 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(293) " "Verilog HDL assignment warning at RAM2GS-MAX.v(293): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 293 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691898440904 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691898440919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691898440919 ""} +{ "Warning" "WVRFX_VERI_DISPLAY_SYSTEM_CALL_WARNING" " Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. UFM.v(145) " "Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results." { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 145 0 0 } } } 0 10649 "Verilog HDL Display System Task warning at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898440935 "|RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component"} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691898441185 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "245 " "Implemented 245 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691898441232 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691898441232 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691898441232 ""} { "Info" "ICUT_CUT_TM_LCELLS" "181 " "Implemented 181 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691898441232 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691898441232 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691898441232 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898441263 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691898441279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 23:47:21 2023 " "Processing ended: Sat Aug 12 23:47:21 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691898441279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691898441279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691898441279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691898441279 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691898442419 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691898442435 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 23:47:22 2023 " "Processing started: Sat Aug 12 23:47:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691898442435 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691898442435 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691898442435 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691898442529 ""} +{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691898442529 ""} +{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691898442529 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691898442591 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691898442591 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691898442591 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691898442638 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691898442638 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691898442654 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691898442669 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691898442763 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691898442763 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691898442810 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691898442810 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691898442810 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691898442810 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691898442810 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691898442810 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691898442810 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691898442810 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691898442810 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 334 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691898442825 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 335 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691898442825 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691898442841 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691898442857 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691898442857 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691898442857 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691898442857 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898442888 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691898442888 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691898442966 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898443075 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691898443075 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691898443388 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898443388 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691898443404 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691898443513 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691898443513 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691898443761 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691898443761 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898443762 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691898443772 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691898443779 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691898443796 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691898443827 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691898443858 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 23:47:23 2023 " "Processing ended: Sat Aug 12 23:47:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691898443858 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691898443858 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691898443858 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691898443858 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691898444842 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691898444842 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 23:47:24 2023 " "Processing started: Sat Aug 12 23:47:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691898444842 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691898444842 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691898444842 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691898445114 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691898445145 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691898445150 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691898445260 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 23:47:25 2023 " "Processing ended: Sat Aug 12 23:47:25 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691898445260 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691898445260 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691898445260 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691898445260 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691898445991 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691898446531 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691898446541 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 23:47:26 2023 " "Processing started: Sat Aug 12 23:47:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691898446541 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691898446541 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691898446541 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691898446650 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691898446770 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691898446770 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691898446815 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691898446815 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691898446855 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691898447085 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691898447120 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691898447120 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691898447120 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691898447120 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691898447125 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691898447135 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691898447135 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.001 -209.812 PHI2 " " -21.001 -209.812 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.876 -581.010 RCLK " " -18.876 -581.010 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.999 -22.739 nCRAS " " -4.999 -22.739 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447140 ""} } { } 0 332146 "Worst-case %1!s! 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slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691898447150 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691898447150 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691898447160 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691898447170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691898447170 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691898447245 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691898447265 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691898447265 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691898447330 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 12 23:47:27 2023 " "Processing ended: Sat Aug 12 23:47:27 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691898447330 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691898447330 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691898447330 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691898447330 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Quartus Prime Full Compilation was successful. 0 errors, 22 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691898447949 ""} diff --git a/CPLD/MAXV/greybox_tmp/cbx_args.txt b/CPLD/MAXV/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..1493d8a --- /dev/null +++ b/CPLD/MAXV/greybox_tmp/cbx_args.txt @@ -0,0 +1,25 @@ +ERASE_TIME=500000000 +INTENDED_DEVICE_FAMILY="MAX V" +LPM_FILE=RAM2GS.mif +LPM_HINT=UNUSED +LPM_TYPE=altufm_none +OSC_FREQUENCY=180000 +PORT_ARCLKENA=PORT_UNUSED +PORT_DRCLKENA=PORT_UNUSED +PROGRAM_TIME=1600000 +WIDTH_UFM_ADDRESS=9 +DEVICE_FAMILY="MAX V" +CBX_AUTO_BLACKBOX=ALL +arclk +ardin +arshft +busy +drclk +drdin +drdout +drshft +erase +osc +oscena +program +rtpbusy diff --git a/CPLD/MAXV/incremental_db/README b/CPLD/MAXV/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/CPLD/MAXV/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info new file mode 100644 index 0000000..4917539 --- /dev/null +++ b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +Version_Index = 503488000 +Creation_Time = Sat Aug 12 18:47:50 2023 diff --git a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt new file mode 100644 index 0000000000000000000000000000000000000000..09f5b3652a9252d7873c9ea69b93e105e1e00445 GIT binary patch literal 2621 zcmV-D3c~fQ4*>uG0001Zob6p*Z`(!|eebUz^u7_VB#I>91n^h7-ZtB;gxxFYO=O>~RLrZm-wv#ga$kzeV5A$|Aa)&dTbuombyP(aGoH%k|xIwkX%v>!OUx zFL%{wR>j9+RV+Rfo#@9|v8vv=d)eu3zOet5Xf~}z*LnQXr`ftJRu3PmK3HGctHtPi zeA3w$Pzi&;4;CetrW&^`z{TK;nSe)u0IH_Yb4&&E>aD$i!xp zeQK0L5c2i-eL@9HaX{gK%s|Am$>Q^Sp+e>e$kXwv&jgg%B4UqUin)C;J`g+#o$8o!UZh=?}-eEsI_YWZn3nNwjAd8+vlDj?#{V)X8k z3W%6fW%E-mog?PdONg8A9-_|0==}TdsECj_XQyNe>LKc!(u1^M4hbY8&iQ;=t@O*) zWL;2k5q(Za;~!@qODZPf&bf^5Z|1YIET&XkM4<{*F2nT@hbl;aSbw4Khe9! zz+yMz0YEI;%se?wh(`6ybH}s+qS5);h>C|OR56_!VPbOvq5|6Rhg+Em;!m|Q>-NFL zazU-k1hJ?>lUqUw;?Rbd85h&4eZcJ)38GKM$wl4f;HsGf9)#+laydRh6uM%|R z_1$wso=p~}pv)0>>U_za269B6%_un}5qma=ezH@Z!;?@oJzUX|TXf@$8F=r%8>M~o z+Se~V{6M*yEY@3veouY>Z$}a3<8n1Grq9DXzdXcbmFk`&HY;TJ9FbX}yGv}YwHtP(7sh(+|yD9|fG%hCeP60|NY&?uo4rUe=%6w0(f(}Yr* z7U-RzwP}Ig35_@{*gwIm(*hk7tUN8yL7~&91^Ory0<}OB1*=dCv{2CL*~UCUYSaSl z6TC<*&^@70sRi06Xqj4|fkL5E3$#!0LbX8qL~T6#U-ceoH$+6D^;k=sI7E#xjTr$WmG ztC9=!T+pp-fp!a8Cl_e9&z4~`YtwJ z8=m>leW8%y1$r-N9bTaKf)?V%%6h>L)9UC%HsPT8LZQVA^k2|oyg>Vfss{@#7_=NO z(1Wq{0rG5uP7Gd`7wE*`g?WKa3|^TR=*7@T^8(En+gt7Usj~89kkuKqWgyl6KuC*% z59j@ZK7dEbe^Q$Vwq}3>%Kz6Nd;IawcLyH;@Z0+jpC~6~5zQ9U;@6j*c<;^4+nX!g z^+)bj%U{2AUR7hg+l$iuEzILDceg)%cqIEi26`-e-9Ob}PP&J{`lAutor+q3U~=4a z`av*j5rA=s0PeC>3lPjgB=JtdZUKUF+;n;(ahuj)8sZvE+mr`)hy9QcOj?BC@VM#p zgkYQU;I4}m5Q52Zsi)y`Fhm6V#|^q!1bZRw#e+8O#r@-wvZp-QrZqSW@k}yk6N3E^ zS)8<~9!x?+@W_Kyvk1n=l~$hi;^U414e!Mv=E0r!vJD7^crNa>X${J8)9I<2X;YJb z7~&c{vWRV%#Ubt_N47(nMKC>*#hdr8%i5Fo5a;LFs=S}vcA~}o{QAT4c3nSe`|;b4 zxb6K$^`ZOuVsD_b`}ysAyB~k{{gb`xH^uymA?ULZC*8g4s$V*^QVy;Yv`UQg@|fpM zLfX?Qc`_kzZCH&!j9ZOq2yT%wrE@1h2dBhDb2lq$5C&4B9cFV#84G12QdBm6 zo{N7s6MvmDpJm}gIr#T8@Y7&VzWgNjI_8P@$&XFlqV~|l*okw4RAMUr+JlsKBW(_- zp{e=vXFmBOC*N3JJDUA4Xku)uI;v2#+21WvnRbV04k=?Br9DU)%`cAFr#;HKMM_qq^c!4LVH64CpM4U> zn(FyK%%~^JapBp5Lw_Jug8z=2@s5Y~AT{uxr}}}^Q~uXf8U|9{OY}Sp?)Ck5yVZ%( zu`b}Bdq%ftdyo?UZM-;)HD$ba!%=f8jI&JU|9qTP^LQ zM)%)yG2Z`fMCwne_gG=T|CwKX@NryC``@M14okf7= zx=eN4aq|sS9!8cL_|NCYdu-c-l=$zCsM`*X&u8ArC&s7Hvv$`V`+FQehnW za{oxFwF$>a`Db4q#$iTnZEui$VPy24e_2kw{W>l@Tac&1Xn3k!YYnn5j2hke)Oknj z3uEt7-%{HgQpU%twg)Ny-KjVXpGEGUd};~Xu`23c!BR^ej=Sjo3s2*d$lHUIy5rGc zo(g2^^PkbxV!vag{If3!gMI2@Hki@FP-fJ_Y!In1>M3<+wmGDX&+l&!QpP8_I@YM)qk6;Zeq + + + + + + + diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 0e26225..4a841e3 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sat Aug 12 18:40:54 2023 +Sat Aug 12 23:47:44 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -10,7 +10,16 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation - 5. Analysis & Synthesis Messages + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Port Connectivity Checks: "UFM:UFM_inst" + 13. Analysis & Synthesis Messages + 14. Analysis & Synthesis Suppressed Messages @@ -37,11 +46,15 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Failed - Sat Aug 12 18:40:54 2023 ; +; Analysis & Synthesis Status ; Successful - Sat Aug 12 23:47:44 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; +; Total logic elements ; 181 ; +; Total pins ; 63 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+---------------------------------------------+ @@ -132,23 +145,171 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+ +; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ; ++----------------------------------+-----------------+-----------------------------+-------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Total logic elements ; 181 ; +; -- Combinational with no register ; 85 ; +; -- Register only ; 29 ; +; -- Combinational with a register ; 67 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 42 ; +; -- 2 input functions ; 44 ; +; -- 1 input functions ; 8 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 165 ; +; -- arithmetic mode ; 16 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 9 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 96 ; +; Total logic cells in carry chains ; 17 ; +; I/O pins ; 63 ; +; UFM blocks ; 1 ; +; Maximum fan-out node ; RCLK ; +; Maximum fan-out ; 54 ; +; Total fan-out ; 647 ; +; Average fan-out ; 2.64 ; ++---------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +; |RAM2GS ; 181 (181) ; 96 ; 1 ; 63 ; 0 ; 85 (85) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; +; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ +; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2GS|UFM:UFM_inst ; UFM.v ; ++--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 96 ; +; Number of registers using Synchronous Clear ; 6 ; +; Number of registers using Synchronous Load ; 3 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 8 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; nRCS~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; nRRAS~reg0 ; 1 ; +; nRCAS~reg0 ; 1 ; +; Total number of inverted registers = 4 ; ; ++----------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "UFM:UFM_inst" ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; ardin ; Input ; Info ; Stuck at GND ; +; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ + + +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sat Aug 12 18:40:41 2023 + Info: Processing started: Sat Aug 12 23:47:36 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v - Info (12023): Found entity 1: RAM4GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 -Error (12007): Top-level design entity "RAM2GS" is undefined -Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning - Error: Peak virtual memory: 4687 megabytes - Error: Processing ended: Sat Aug 12 18:40:54 2023 - Error: Elapsed time: 00:00:13 - Error: Total CPU time (on all processors): 00:00:29 + Info (12023): Found entity 1: RAM2GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 +Info (12021): Found 2 design units, including 2 entities, in source file ufm.v + Info (12023): Found entity 1: UFM_altufm_none_38r File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 154 +Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy +Warning (10036): Verilog HDL or VHDL warning at RAM2GS-MAX.v(20): object "LEDEN" assigned a value but never read File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 20 +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(161): truncated value with size 32 to match size of target (2) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 161 +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(166): truncated value with size 32 to match size of target (18) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 166 +Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(293): truncated value with size 32 to match size of target (4) File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 293 +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 90 +Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 205 +Warning (10649): Verilog HDL Display System Task warning at UFM.v(145): Memory initialization file RAM2GS.mif is not found. This may result in inconsistent simulation results. File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 145 +Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 26 +Info (21057): Implemented 245 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 25 input pins + Info (21059): Implemented 30 output pins + Info (21060): Implemented 8 bidirectional pins + Info (21061): Implemented 181 logic cells + Info (21070): Implemented 1 User Flash Memory blocks +Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings + Info: Peak virtual memory: 4702 megabytes + Info: Processing ended: Sat Aug 12 23:47:45 2023 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:21 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg. diff --git a/CPLD/MAXV/output_files/RAM2GS.map.smsg b/CPLD/MAXV/output_files/RAM2GS.map.smsg new file mode 100644 index 0000000..00ba75e --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2GS.map.smsg @@ -0,0 +1,3 @@ +Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(59): extended using "x" or "z" File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 59 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(177): "program" is SystemVerilog-2005 keyword File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 177 diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index 012e6af..afed099 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,5 +1,9 @@ -Analysis & Synthesis Status : Failed - Sat Aug 12 18:40:54 2023 +Analysis & Synthesis Status : Successful - Sat Aug 12 23:47:44 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS Family : MAX V +Total logic elements : 181 +Total pins : 63 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2GS.pin b/CPLD/MAXV/output_files/RAM2GS.pin new file mode 100644 index 0000000..88c2384 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2GS.pin @@ -0,0 +1,165 @@ + -- Copyright (C) 2019 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : 1 : gnd : : : : +RDQMH : 2 : output : 3.3-V LVCMOS : : 1 : Y +nRCS : 3 : output : 3.3-V LVCMOS : : 1 : Y +nRCAS : 4 : output : 3.3-V LVCMOS : : 1 : Y +RBA[0] : 5 : output : 3.3-V LVCMOS : : 1 : Y +nRRAS : 6 : output : 3.3-V LVCMOS : : 1 : Y +RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y +RCKE : 8 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 9 : power : : 3.3V : 1 : +GND : 10 : gnd : : : : +GND : 11 : gnd : : : : +RCLK : 12 : input : 3.3-V LVCMOS : : 1 : Y +VCCINT : 13 : power : : 1.8V : : +RBA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y +RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y +RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y +RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y +RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y +RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y +RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y +RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y +RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y +Dout[5] : 28 : output : 3.3-V LVCMOS : : 1 : Y +RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y +RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 31 : power : : 3.3V : 1 : +GND : 32 : gnd : : : : +Dout[0] : 33 : output : 3.3-V LVCMOS : : 1 : Y +Dout[6] : 34 : output : 3.3-V LVCMOS : : 1 : Y +Din[2] : 35 : input : 3.3-V LVCMOS : : 1 : Y +Din[1] : 36 : input : 3.3-V LVCMOS : : 1 : Y +Din[3] : 37 : input : 3.3-V LVCMOS : : 1 : Y +Din[5] : 38 : input : 3.3-V LVCMOS : : 1 : Y +Din[4] : 39 : input : 3.3-V LVCMOS : : 1 : Y +Din[7] : 40 : input : 3.3-V LVCMOS : : 1 : Y +Din[6] : 41 : input : 3.3-V LVCMOS : : 1 : Y +Din[0] : 42 : input : 3.3-V LVCMOS : : 1 : Y +Dout[7] : 43 : output : 3.3-V LVCMOS : : 1 : Y +Dout[4] : 44 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 45 : power : : 3.3V : 1 : +GND : 46 : gnd : : : : +Dout[3] : 47 : output : 3.3-V LVCMOS : : 1 : Y +nFWE : 48 : input : 3.3-V LVCMOS : : 1 : Y +MAin[0] : 49 : input : 3.3-V LVCMOS : : 1 : Y +MAin[2] : 50 : input : 3.3-V LVCMOS : : 1 : Y +MAin[1] : 51 : input : 3.3-V LVCMOS : : 1 : Y +PHI2 : 52 : input : 3.3-V LVCMOS : : 2 : Y +nCCAS : 53 : input : 3.3-V LVCMOS : : 2 : Y +CROW[0] : 54 : input : 3.3-V LVCMOS : : 2 : Y +CROW[1] : 55 : input : 3.3-V LVCMOS : : 2 : Y +Dout[2] : 56 : output : 3.3-V LVCMOS : : 2 : Y +Dout[1] : 57 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 58 : : : : 2 : +VCCIO2 : 59 : power : : 3.3V : 2 : +GND : 60 : gnd : : : : +GND* : 61 : : : : 2 : +GND* : 62 : : : : 2 : +VCCINT : 63 : power : : 1.8V : : +GND* : 64 : : : : 2 : +GND : 65 : gnd : : : : +GND* : 66 : : : : 2 : +nCRAS : 67 : input : 3.3-V LVCMOS : : 2 : Y +MAin[7] : 68 : input : 3.3-V LVCMOS : : 2 : Y +MAin[5] : 69 : input : 3.3-V LVCMOS : : 2 : Y +MAin[4] : 70 : input : 3.3-V LVCMOS : : 2 : Y +MAin[3] : 71 : input : 3.3-V LVCMOS : : 2 : Y +MAin[6] : 72 : input : 3.3-V LVCMOS : : 2 : Y +MAin[8] : 73 : input : 3.3-V LVCMOS : : 2 : Y +MAin[9] : 74 : input : 3.3-V LVCMOS : : 2 : Y +GND* : 75 : : : : 2 : +GND* : 76 : : : : 2 : +GND* : 77 : : : : 2 : +GND* : 78 : : : : 2 : +GND : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +GND* : 84 : : : : 2 : +GND* : 85 : : : : 2 : +GND* : 86 : : : : 2 : +GND* : 87 : : : : 2 : +LED : 88 : output : 3.3-V LVTTL : : 2 : Y +RD[2] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[5] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[4] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y +GND : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[0] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[7] : 97 : bidir : 3.3-V LVCMOS : : 2 : Y +RDQML : 98 : output : 3.3-V LVCMOS : : 2 : Y +RD[3] : 99 : bidir : 3.3-V LVCMOS : : 2 : Y +nRWE : 100 : output : 3.3-V LVCMOS : : 2 : Y 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z*v4&-E%b(~?C8)tb}s1W-$xek@f^!pdGLRp5UFW7@~r2mufxxYpE z9oZuW8YSfA_6pals=*m8$~NysFKzp!J$|zN{n^gn2j(OFpUnSp{I;G?$7|#Ff8~#x j6HBh|{6(mj|00A$|McId9{AJ)|4%(|gZ*3aw;%o= diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt new file mode 100644 index 0000000..c480479 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt @@ -0,0 +1,1010 @@ +Timing Analyzer report for RAM2GS +Sat Aug 12 23:47:50 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Fmax Summary + 6. Setup Summary + 7. Hold Summary + 8. Recovery Summary + 9. Removal Summary + 10. Minimum Pulse Width Summary + 11. Setup: 'ARCLK' + 12. Setup: 'DRCLK' + 13. Setup: 'PHI2' + 14. Setup: 'RCLK' + 15. Setup: 'nCRAS' + 16. Hold: 'DRCLK' + 17. Hold: 'ARCLK' + 18. Hold: 'PHI2' + 19. Hold: 'RCLK' + 20. Hold: 'nCRAS' + 21. Setup Transfers + 22. Hold Transfers + 23. Report TCCS + 24. Report RSKM + 25. Unconstrained Paths Summary + 26. Clock Status Summary + 27. Unconstrained Input Ports + 28. Unconstrained Output Ports + 29. Unconstrained Input Ports + 30. Unconstrained Output Ports + 31. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2GS ; +; Device Family ; MAX V ; +; Device Name ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; +; nCCAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCCAS } ; +; nCRAS ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { nCRAS } ; +; PHI2 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI2 } ; +; RCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { RCLK } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 23.25 MHz ; 23.25 MHz ; PHI2 ; ; +; 52.25 MHz ; 52.25 MHz ; RCLK ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -99.000 ; -99.000 ; +; DRCLK ; -99.000 ; -99.000 ; +; PHI2 ; -21.001 ; -209.812 ; +; RCLK ; -18.876 ; -581.010 ; +; nCRAS ; -4.999 ; -22.739 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; DRCLK ; -17.852 ; -17.852 ; +; ARCLK ; -15.984 ; -15.984 ; +; PHI2 ; -0.781 ; -0.781 ; +; RCLK ; -0.589 ; -0.786 ; +; nCRAS ; -0.360 ; -1.399 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -29.500 ; -59.000 ; +; DRCLK ; -29.500 ; -59.000 ; +; PHI2 ; -2.289 ; -2.289 ; +; RCLK ; -2.289 ; -2.289 ; +; nCCAS ; -2.289 ; -2.289 ; +; nCRAS ; -2.289 ; -2.289 ; ++-------+---------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; +; -23.016 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.053 ; 2.963 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.786 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; 0.815 ; 4.601 ; +; -21.148 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; 0.815 ; 2.963 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Setup: 'PHI2' ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -21.001 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 21.180 ; +; -20.566 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.745 ; +; -20.330 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.509 ; +; -20.128 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.307 ; +; -20.112 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.291 ; +; -20.052 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.231 ; +; -20.052 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 20.231 ; +; -19.677 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.856 ; +; -19.638 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.817 ; +; -19.638 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.817 ; +; -19.617 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.796 ; +; -19.617 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.796 ; +; -19.533 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.712 ; +; -19.441 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.620 ; +; -19.381 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.560 ; +; -19.381 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.560 ; +; -19.239 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.418 ; +; -19.203 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.382 ; +; -19.203 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.382 ; +; -19.179 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.358 ; +; -19.179 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.358 ; +; -18.967 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.146 ; +; -18.967 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.146 ; +; -18.880 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 19.059 ; +; -18.765 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.944 ; +; -18.765 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.944 ; +; -18.644 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.823 ; +; -18.584 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.763 ; +; -18.584 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.763 ; +; -18.170 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.349 ; +; -18.170 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.349 ; +; -17.991 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.170 ; +; -17.931 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.110 ; +; -17.931 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 18.110 ; +; -17.517 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.696 ; +; -17.517 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 17.696 ; +; -16.677 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.856 ; +; -16.672 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.851 ; +; -16.672 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.851 ; +; -16.394 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.573 ; +; -16.237 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.416 ; +; -16.237 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.416 ; +; -16.213 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.392 ; +; -16.213 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.392 ; +; -16.036 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.215 ; +; -16.001 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.180 ; +; -16.001 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.180 ; +; -15.985 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 16.664 ; +; -15.985 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 16.664 ; +; -15.959 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 16.138 ; +; -15.799 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.978 ; +; -15.799 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.978 ; +; -15.788 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.967 ; +; -15.778 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.957 ; +; -15.778 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.957 ; +; -15.728 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.907 ; +; -15.728 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.907 ; +; -15.723 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.902 ; +; -15.571 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 16.250 ; +; -15.571 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 16.250 ; +; -15.542 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.721 ; +; -15.542 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.721 ; +; -15.521 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.700 ; +; -15.340 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.519 ; +; -15.340 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.519 ; +; -15.314 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.493 ; +; -15.314 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.493 ; +; -15.204 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.383 ; +; -15.204 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.383 ; +; -15.147 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.326 ; +; -15.087 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.266 ; +; -15.087 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.266 ; +; -14.926 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 15.105 ; +; -14.745 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.924 ; +; -14.745 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.924 ; +; -14.673 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.852 ; +; -14.673 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.852 ; +; -14.551 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.730 ; +; -14.551 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.730 ; +; -14.273 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.452 ; +; -14.092 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.271 ; +; -14.092 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 14.271 ; +; -12.605 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.284 ; +; -12.605 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.284 ; +; -12.348 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.527 ; +; -12.348 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.527 ; +; -12.327 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 13.006 ; +; -12.096 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 12.775 ; +; -12.070 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.249 ; +; -11.889 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.068 ; +; -11.889 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 12.068 ; +; -11.707 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.886 ; +; -11.707 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.886 ; +; -11.429 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.608 ; +; -11.248 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.427 ; +; -11.248 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.427 ; +; -10.525 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 11.204 ; +; -9.897 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 10.576 ; +; -8.326 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 9.005 ; +; -7.155 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.334 ; ++---------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -18.876 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -6.616 ; 12.439 ; +; -18.504 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -6.616 ; 12.067 ; +; -18.233 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 13.663 ; +; -18.139 ; S[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.818 ; +; -17.788 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.467 ; +; -17.751 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.430 ; +; -17.671 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 18.350 ; +; -17.385 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -6.616 ; 10.948 ; +; -17.274 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.953 ; +; -17.156 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -6.616 ; 10.719 ; +; -17.139 ; IS[2] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.818 ; +; -17.133 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.812 ; +; -17.039 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 12.469 ; +; -16.759 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.438 ; +; -16.467 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -6.616 ; 10.030 ; +; -16.451 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 11.881 ; +; -16.378 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 17.057 ; +; -16.363 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 11.793 ; +; -16.259 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.938 ; +; -16.221 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.900 ; +; -16.212 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.891 ; +; -16.177 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.856 ; +; -16.023 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.702 ; +; -16.020 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.699 ; +; -15.846 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.525 ; +; -15.707 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 11.137 ; +; -15.691 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.370 ; +; -15.564 ; S[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.243 ; +; -15.471 ; InitReady ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.150 ; +; -15.449 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.128 ; +; -15.375 ; S[0] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.054 ; +; -15.336 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 16.015 ; +; -15.279 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.958 ; +; -15.275 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.954 ; +; -15.258 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 10.688 ; +; -15.225 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.904 ; +; -15.199 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.878 ; +; -15.179 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.858 ; +; -15.170 ; S[1] ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.849 ; +; -15.111 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.790 ; +; -15.100 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.779 ; +; -15.077 ; IS[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.756 ; +; -14.992 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.671 ; +; -14.960 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.639 ; +; -14.900 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 10.330 ; +; -14.819 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.498 ; +; -14.800 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.479 ; +; -14.787 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.466 ; +; -14.741 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.420 ; +; -14.737 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.416 ; +; -14.688 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.367 ; +; -14.608 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 10.038 ; +; -14.608 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.287 ; +; -14.607 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.286 ; +; -14.586 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.265 ; +; -14.579 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.258 ; +; -14.535 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.214 ; +; -14.531 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.210 ; +; -14.445 ; IS[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.124 ; +; -14.445 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.124 ; +; -14.382 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.061 ; +; -14.367 ; Ready ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.046 ; +; -14.367 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.046 ; +; -14.363 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 15.042 ; +; -14.301 ; IS[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.980 ; +; -14.281 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.960 ; +; -14.244 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 9.674 ; +; -14.175 ; UFMInitDone ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.854 ; +; -14.108 ; IS[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.787 ; +; -13.950 ; FS[17] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.629 ; +; -13.913 ; S[1] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.592 ; +; -13.907 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.586 ; +; -13.850 ; UFMReqErase ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.529 ; +; -13.787 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.466 ; +; -13.783 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.462 ; +; -13.774 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.453 ; +; -13.745 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.424 ; +; -13.735 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.414 ; +; -13.682 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; -0.815 ; 13.546 ; +; -13.678 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.357 ; +; -13.638 ; InitReady ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.317 ; +; -13.545 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.224 ; +; -13.541 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.220 ; +; -13.473 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.152 ; +; -13.462 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.141 ; +; -13.454 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.133 ; +; -13.450 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.129 ; +; -13.413 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.092 ; +; -13.412 ; FS[16] ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.091 ; +; -13.373 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.052 ; +; -13.322 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 14.001 ; +; -13.310 ; FS[15] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.989 ; +; -13.289 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.968 ; +; -13.270 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.949 ; +; -13.218 ; IS[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.897 ; +; -13.153 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.832 ; +; -13.145 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -4.749 ; 8.575 ; +; -13.125 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.804 ; +; -13.097 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.776 ; +; -13.097 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 13.776 ; ++---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Setup: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -4.999 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 9.695 ; 14.873 ; +; -4.499 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 9.695 ; 14.873 ; +; -3.382 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 8.310 ; +; -2.386 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 7.314 ; +; -2.385 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 7.313 ; +; -2.384 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 7.312 ; +; -2.334 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 7.262 ; +; -2.258 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 7.186 ; +; -1.307 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 6.235 ; +; -1.304 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 6.232 ; +; 0.985 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 3.943 ; +; 0.986 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 3.942 ; +; 0.988 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 3.940 ; +; 1.000 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 4.749 ; 3.928 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -17.852 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; 0.815 ; 2.963 ; +; -16.214 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; 0.815 ; 4.601 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -15.984 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.053 ; 2.963 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'PHI2' ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ +; -0.781 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.616 ; 5.874 ; +; -0.218 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 6.616 ; 6.437 ; +; 0.330 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 6.616 ; 6.485 ; +; 3.740 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.779 ; +; 5.217 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.256 ; +; 5.474 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.513 ; +; 7.795 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.334 ; +; 8.058 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.597 ; +; 8.062 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.601 ; +; 8.699 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.238 ; +; 8.703 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.242 ; +; 8.966 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 9.005 ; +; 10.537 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 10.576 ; +; 10.902 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.441 ; +; 10.906 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 10.445 ; +; 11.165 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 11.204 ; +; 11.555 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.094 ; +; 11.559 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.098 ; +; 12.069 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.608 ; +; 12.150 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.689 ; +; 12.154 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.693 ; +; 12.347 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.886 ; +; 12.347 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.886 ; +; 12.352 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.891 ; +; 12.356 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.895 ; +; 12.399 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 11.938 ; +; 12.588 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.127 ; +; 12.592 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.131 ; +; 12.710 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.249 ; +; 12.736 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 12.775 ; +; 12.967 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.006 ; +; 12.988 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.527 ; +; 12.988 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.527 ; +; 13.023 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.562 ; +; 13.027 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.566 ; +; 13.040 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 12.579 ; +; 13.245 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.284 ; +; 13.245 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 13.284 ; +; 13.970 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 13.509 ; +; 14.611 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.150 ; +; 14.913 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.452 ; +; 15.191 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.730 ; +; 15.191 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.730 ; +; 15.243 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.782 ; +; 15.313 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.852 ; +; 15.313 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 14.852 ; +; 15.566 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.105 ; +; 15.727 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.266 ; +; 15.727 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.266 ; +; 15.844 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.383 ; +; 15.844 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.383 ; +; 15.896 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.435 ; +; 15.954 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.493 ; +; 15.954 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.493 ; +; 16.161 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.700 ; +; 16.211 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 16.250 ; +; 16.211 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 16.250 ; +; 16.363 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.902 ; +; 16.368 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.907 ; +; 16.368 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.907 ; +; 16.439 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.978 ; +; 16.439 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 15.978 ; +; 16.491 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.030 ; +; 16.599 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.138 ; +; 16.625 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 16.664 ; +; 16.625 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 16.664 ; +; 16.641 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.180 ; +; 16.641 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.180 ; +; 16.693 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.232 ; +; 16.814 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.353 ; +; 16.877 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.416 ; +; 16.877 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.416 ; +; 16.929 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.468 ; +; 17.034 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.573 ; +; 17.312 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.851 ; +; 17.312 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.851 ; +; 17.364 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 16.903 ; +; 17.467 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.006 ; +; 18.062 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.601 ; +; 18.157 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.696 ; +; 18.157 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.696 ; +; 18.264 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 17.803 ; +; 18.500 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.039 ; +; 18.571 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.110 ; +; 18.571 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.110 ; +; 18.810 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.349 ; +; 18.810 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.349 ; +; 18.935 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.474 ; +; 19.224 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.763 ; +; 19.224 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.763 ; +; 19.405 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.944 ; +; 19.405 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 18.944 ; +; 19.607 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.146 ; +; 19.607 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.146 ; +; 19.819 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.358 ; +; 19.819 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.358 ; +; 19.843 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.382 ; +; 19.843 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.382 ; +; 20.021 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.560 ; +; 20.021 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 19.560 ; ++--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Hold: 'RCLK' ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.589 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; 0.000 ; 4.946 ; 4.890 ; +; -0.197 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; 0.000 ; 4.946 ; 5.282 ; +; -0.089 ; ARCLK ; ARCLK ; ARCLK ; RCLK ; -0.500 ; 4.946 ; 4.890 ; +; 0.303 ; DRCLK ; DRCLK ; DRCLK ; RCLK ; -0.500 ; 4.946 ; 5.282 ; +; 2.125 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 4.946 ; 7.110 ; +; 2.325 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 4.946 ; 7.310 ; +; 2.625 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 4.946 ; 7.110 ; +; 2.825 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 4.946 ; 7.310 ; +; 3.374 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.413 ; +; 3.470 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.509 ; +; 3.473 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.512 ; +; 3.792 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.831 ; +; 3.852 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.891 ; +; 3.859 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.898 ; +; 4.200 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.239 ; +; 4.202 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.241 ; +; 4.390 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.429 ; +; 4.401 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.440 ; +; 4.548 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.587 ; +; 4.831 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.870 ; +; 5.217 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.256 ; +; 5.228 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.267 ; +; 5.229 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.268 ; +; 5.245 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.284 ; +; 5.252 ; DRShift ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.291 ; +; 5.255 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.294 ; +; 5.267 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.306 ; +; 5.267 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.306 ; +; 5.271 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.310 ; +; 5.309 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.348 ; +; 5.416 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.455 ; +; 5.429 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.468 ; +; 5.440 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.479 ; +; 5.440 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.479 ; +; 5.441 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.480 ; +; 5.441 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.480 ; +; 5.441 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.480 ; +; 5.442 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.481 ; +; 5.449 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.488 ; +; 5.452 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.491 ; +; 5.453 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.492 ; +; 5.456 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.495 ; +; 5.466 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.505 ; +; 5.485 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.524 ; +; 5.500 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.539 ; +; 5.515 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.554 ; +; 5.527 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.566 ; +; 5.530 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.569 ; +; 5.534 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.573 ; +; 5.814 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 4.946 ; 10.799 ; +; 5.837 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.876 ; +; 5.858 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.897 ; +; 5.952 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 5.991 ; +; 5.963 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.002 ; +; 5.964 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.003 ; +; 5.990 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.029 ; +; 6.002 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.041 ; +; 6.006 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.045 ; +; 6.096 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.135 ; +; 6.107 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.146 ; +; 6.134 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.173 ; +; 6.146 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.185 ; +; 6.150 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.189 ; +; 6.251 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.290 ; +; 6.290 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.329 ; +; 6.296 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.335 ; +; 6.314 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 4.946 ; 10.799 ; +; 6.395 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.434 ; +; 6.442 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.481 ; +; 6.442 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.481 ; +; 6.443 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.482 ; +; 6.443 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.482 ; +; 6.454 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.493 ; +; 6.455 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.494 ; +; 6.458 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.497 ; +; 6.460 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.499 ; +; 6.461 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.500 ; +; 6.503 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.542 ; +; 6.530 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.569 ; +; 6.586 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.625 ; +; 6.587 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.626 ; +; 6.598 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.637 ; +; 6.599 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.638 ; +; 6.706 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.745 ; +; 6.730 ; FS[4] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.769 ; +; 6.731 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.770 ; +; 6.742 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.781 ; +; 6.759 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.798 ; +; 6.770 ; FS[1] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.809 ; +; 6.770 ; FS[1] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.809 ; +; 6.770 ; FS[1] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.809 ; +; 6.770 ; FS[1] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.809 ; +; 6.770 ; FS[1] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.809 ; +; 6.777 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.816 ; +; 6.786 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.825 ; +; 6.786 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.825 ; +; 6.786 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.825 ; +; 6.786 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.825 ; +; 6.874 ; FS[4] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.913 ; +; 6.894 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 6.933 ; ++--------+-------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.360 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 3.928 ; +; -0.348 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 3.940 ; +; -0.346 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 3.942 ; +; -0.345 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 3.943 ; +; 1.944 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 6.232 ; +; 1.947 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 6.235 ; +; 2.898 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 7.186 ; +; 2.974 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 7.262 ; +; 3.024 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 7.312 ; +; 3.025 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 7.313 ; +; 3.026 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 7.314 ; +; 4.022 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 4.749 ; 8.310 ; +; 5.139 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 9.695 ; 14.873 ; +; 5.639 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 9.695 ; 14.873 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; RCLK ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; nCCAS ; nCRAS ; 0 ; 0 ; 1 ; 1 ; +; RCLK ; nCRAS ; 0 ; 0 ; 12 ; 0 ; +; PHI2 ; PHI2 ; 0 ; 1 ; 152 ; 14 ; +; RCLK ; PHI2 ; 2 ; 0 ; 1 ; 0 ; +; ARCLK ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; DRCLK ; RCLK ; 4 ; 2 ; 0 ; 0 ; +; nCCAS ; RCLK ; 1 ; 1 ; 0 ; 0 ; +; nCRAS ; RCLK ; 1 ; 17 ; 0 ; 0 ; +; PHI2 ; RCLK ; 1 ; 12 ; 0 ; 0 ; +; RCLK ; RCLK ; 620 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 31 ; 31 ; +; Unconstrained Input Port Paths ; 232 ; 232 ; +; Unconstrained Output Ports ; 38 ; 38 ; +; Unconstrained Output Port Paths ; 77 ; 77 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; ARCLK ; ARCLK ; Base ; Constrained ; +; DRCLK ; DRCLK ; Base ; Constrained ; +; PHI2 ; PHI2 ; Base ; Constrained ; +; RCLK ; RCLK ; Base ; Constrained ; +; nCCAS ; nCCAS ; Base ; Constrained ; +; nCRAS ; nCRAS ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; CROW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CROW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCRAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; CROW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CROW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MAin[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCCAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCRAS ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Sat Aug 12 23:47:49 2023 +Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name nCCAS nCCAS + Info (332105): create_clock -period 1.000 -name nCRAS nCRAS + Info (332105): create_clock -period 1.000 -name RCLK RCLK + Info (332105): create_clock -period 1.000 -name PHI2 PHI2 + Info (332105): create_clock -period 1.000 -name DRCLK DRCLK + Info (332105): create_clock -period 1.000 -name ARCLK ARCLK +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -99.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -99.000 -99.000 ARCLK + Info (332119): -99.000 -99.000 DRCLK + Info (332119): -21.001 -209.812 PHI2 + Info (332119): -18.876 -581.010 RCLK + Info (332119): -4.999 -22.739 nCRAS +Info (332146): Worst-case hold slack is -17.852 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -17.852 -17.852 DRCLK + Info (332119): -15.984 -15.984 ARCLK + Info (332119): -0.781 -0.781 PHI2 + Info (332119): -0.589 -0.786 RCLK + Info (332119): -0.360 -1.399 nCRAS +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -29.500 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -29.500 -59.000 ARCLK + Info (332119): -29.500 -59.000 DRCLK + Info (332119): -2.289 -2.289 PHI2 + Info (332119): -2.289 -2.289 RCLK + Info (332119): -2.289 -2.289 nCCAS + Info (332119): -2.289 -2.289 nCRAS +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 4676 megabytes + Info: Processing ended: Sat Aug 12 23:47:50 2023 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.summary b/CPLD/MAXV/output_files/RAM2GS.sta.summary new file mode 100644 index 0000000..cbf85f3 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2GS.sta.summary @@ -0,0 +1,69 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Setup 'ARCLK' +Slack : -99.000 +TNS : -99.000 + +Type : Setup 'DRCLK' +Slack : -99.000 +TNS : -99.000 + +Type : Setup 'PHI2' +Slack : -21.001 +TNS : -209.812 + +Type : Setup 'RCLK' +Slack : -18.876 +TNS : -581.010 + +Type : Setup 'nCRAS' +Slack : -4.999 +TNS : -22.739 + +Type : Hold 'DRCLK' +Slack : -17.852 +TNS : -17.852 + +Type : Hold 'ARCLK' +Slack : -15.984 +TNS : -15.984 + +Type : Hold 'PHI2' +Slack : -0.781 +TNS : -0.781 + +Type : Hold 'RCLK' +Slack : -0.589 +TNS : -0.786 + +Type : Hold 'nCRAS' +Slack : -0.360 +TNS : -1.399 + +Type : Minimum Pulse Width 'ARCLK' +Slack : -29.500 +TNS : -59.000 + +Type : Minimum Pulse Width 'DRCLK' +Slack : -29.500 +TNS : -59.000 + +Type : Minimum Pulse Width 'PHI2' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'RCLK' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'nCCAS' +Slack : -2.289 +TNS : -2.289 + +Type : Minimum Pulse Width 'nCRAS' +Slack : -2.289 +TNS : -2.289 + +------------------------------------------------------------ diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v index ac5eb43..f9d9900 100644 --- a/CPLD/RAM2GS-MAX.v +++ b/CPLD/RAM2GS-MAX.v @@ -1,5 +1,5 @@ -module RAM4GS(PHI2, MAin, CROW, Din, Dout, - nCCAS, nCRAS, nFWE, +module RAM2GS(PHI2, MAin, CROW, Din, Dout, + nCCAS, nCRAS, nFWE, LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML); @@ -16,9 +16,15 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout, reg FWEr; reg CBR; + /* Activity LED */ + reg LEDEN = 0; + output LED; + assign LED = !(!nCRAS && !CBR && LEDEN); + /* 65816 Data */ input [7:0] Din; - output [7:0] Dout = RD[7:0]; + output [7:0] Dout; + assign Dout[7:0] = RD[7:0]; /* Latched 65816 Bank Address */ reg [7:0] Bank; @@ -46,8 +52,9 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout, assign RA[11] = RA11; assign RA[10] = RA10; assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0]; - output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9]; - output RDQMH = ~nRowColSel ? 1'b1 : MAin[9]; + output RDQML, RDQMH; + assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9]; + assign RDQMH = ~nRowColSel ? 1'b1 : MAin[9]; reg [7:0] WRD; inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ; @@ -93,6 +100,7 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout, reg ADSubmitted = 0; reg CmdEnable = 0; reg CmdSubmitted = 0; + reg CmdLEDEN = 0; reg Cmdn8MEGEN = 0; reg CmdDRCLK = 0; reg CmdDRDIn = 0; diff --git a/CPLD/RAM2GS.mif b/CPLD/RAM2GS.mif new file mode 100644 index 0000000..65c8441 --- /dev/null +++ b/CPLD/RAM2GS.mif @@ -0,0 +1,27 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + [000..0FD] : 0000; + 0FE : 7FFF; + [0FF..1FF] : FFFF; +END; diff --git a/CPLD/RAM2GS.qsf b/CPLD/RAM2GS.qsf index ed8578e..ad6ce4f 100644 --- a/CPLD/RAM2GS.qsf +++ b/CPLD/RAM2GS.qsf @@ -74,6 +74,11 @@ set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name MIF_FILE RAM4GS.mif +set_global_assignment -name QIP_FILE UFM.qip + + + set_location_assignment PIN_12 -to RCLK set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK @@ -174,7 +179,6 @@ set_location_assignment PIN_95 -to RD[6] set_location_assignment PIN_97 -to RD[7] set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD -set_global_assignment -name MIF_FILE RAM4GS.mif set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE @@ -210,4 +214,3 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD set_instance_assignment -name SLOW_SLEW_RATE ON -to RD set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD -set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file

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