Map TRACE Report
Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 21:32:27 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1_map.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,3
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
PERIOD NET "PHI2_c" 350.000000 ns (0 errors) 113 items scored, 0 timing errors detected.
PERIOD NET "nCCAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "nCRAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "RCLK_c" 16.000000 ns (0 errors) 395 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 12.873ns (21.6% logic, 78.4% route), 7 logic levels.
Constraint Details:
12.873ns physical path delay SLICE_95 to SLICE_19 meets
175.000ns delay constraint less
0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
Physical Path Details:
Data path SLICE_95 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_95.CLK to SLICE_95.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 e 1.441 SLICE_95.Q1 to SLICE_67.A1 Bank_7
CTOF_DEL --- 0.371 SLICE_67.A1 to SLICE_67.F1 SLICE_67
ROUTE 1 e 1.441 SLICE_67.F1 to SLICE_82.C1 n2154
CTOF_DEL --- 0.371 SLICE_82.C1 to SLICE_82.F1 SLICE_82
ROUTE 1 e 1.441 SLICE_82.F1 to SLICE_76.B1 n26
CTOF_DEL --- 0.371 SLICE_76.B1 to SLICE_76.F1 SLICE_76
ROUTE 4 e 1.441 SLICE_76.F1 to SLICE_89.B0 n1285
CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89
ROUTE 3 e 1.441 SLICE_89.F0 to SLICE_18.D1 n2290
CTOF_DEL --- 0.371 SLICE_18.D1 to SLICE_18.F1 SLICE_18
ROUTE 3 e 1.441 SLICE_18.F1 to SLICE_90.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 SLICE_90.C0 to SLICE_90.F0 SLICE_90
ROUTE 2 e 1.441 SLICE_90.F0 to SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
12.873 (21.6% logic, 78.4% route), 7 logic levels.
Report: 26.276ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_76
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_77
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.575ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i14 (from RCLK_c +)
Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
Delay: 10.181ns (23.7% logic, 76.3% route), 6 logic levels.
Constraint Details:
10.181ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
Physical Path Details:
Data path SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from RCLK_c)
ROUTE 3 e 1.441 SLICE_7.Q0 to SLICE_78.A0 FS_14
CTOF_DEL --- 0.371 SLICE_78.A0 to SLICE_78.F0 SLICE_78
ROUTE 3 e 1.441 SLICE_78.F0 to SLICE_73.B1 n10
CTOF_DEL --- 0.371 SLICE_73.B1 to SLICE_73.F1 SLICE_73
ROUTE 4 e 0.561 SLICE_73.F1 to SLICE_73.B0 n2300
CTOF_DEL --- 0.371 SLICE_73.B0 to SLICE_73.F0 SLICE_73
ROUTE 1 e 1.441 SLICE_73.F0 to SLICE_75.C0 n11
CTOF_DEL --- 0.371 SLICE_75.C0 to SLICE_75.F0 SLICE_75
ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_33.D1 n2119
CTOF_DEL --- 0.371 SLICE_33.D1 to SLICE_33.F1 SLICE_33
ROUTE 1 e 1.441 SLICE_33.F1 to SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
--------
10.181 (23.7% logic, 76.3% route), 6 logic levels.
Report: 10.425ns is the minimum period for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_55 and
5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
12.500ns offset RCLK to RA[10] by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_55.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 e 1.441 SLICE_55.Q0 to 87.PADDO n980
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10]
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[9] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 1.441 SLICE_88.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[8] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C0 nRowColSel
CTOF_DEL --- 0.371 SLICE_95.C0 to SLICE_95.F0 SLICE_95
ROUTE 1 e 1.441 SLICE_95.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[7] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_97.C0 nRowColSel
CTOF_DEL --- 0.371 SLICE_97.C0 to SLICE_97.F0 SLICE_97
ROUTE 1 e 1.441 SLICE_97.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[6] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C0 nRowColSel
CTOF_DEL --- 0.371 SLICE_98.C0 to SLICE_98.F0 SLICE_98
ROUTE 1 e 1.441 SLICE_98.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[5] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_98.C1 to SLICE_98.F1 SLICE_98
ROUTE 1 e 1.441 SLICE_98.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.427ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 6.569ns (69.5% logic, 30.5% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
12.500ns offset RCLK to RA[4] by 3.427ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.561 SLICE_64.Q0 to SLICE_64.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_64.C1 to SLICE_64.F1 SLICE_64
ROUTE 1 e 1.441 SLICE_64.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4]
--------
6.569 (69.5% logic, 30.5% route), 3 logic levels.
Report: 9.073ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[3] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_94.C1 to SLICE_94.F1 SLICE_94
ROUTE 1 e 1.441 SLICE_94.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[2] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_95.C1 to SLICE_95.F1 SLICE_95
ROUTE 1 e 1.441 SLICE_95.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[1] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C0 nRowColSel
CTOF_DEL --- 0.371 SLICE_94.C0 to SLICE_94.F0 SLICE_94
ROUTE 1 e 1.441 SLICE_94.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
12.500ns offset RCLK to RA[0] by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.C1 nRowColSel
CTOF_DEL --- 0.371 SLICE_92.C1 to SLICE_92.F1 SLICE_92
ROUTE 1 e 1.441 SLICE_92.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0]
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_60 and
5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
12.500ns offset RCLK to nRCS by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_60.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 e 1.441 SLICE_60.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_34 and
5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
12.500ns offset RCLK to RCKE by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_34.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 e 1.441 SLICE_34.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_63 and
5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
12.500ns offset RCLK to nRWE by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_63.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 e 1.441 SLICE_63.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_61 and
5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
12.500ns offset RCLK to nRRAS by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_61.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 e 1.441 SLICE_61.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_58 and
5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
12.500ns offset RCLK to nRCAS by 4.359ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_58.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 e 1.441 SLICE_58.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS
--------
5.637 (74.4% logic, 25.6% route), 2 logic levels.
Report: 8.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
12.500ns offset RCLK to RDQMH by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.B0 nRowColSel
CTOF_DEL --- 0.371 SLICE_88.B0 to SLICE_88.F0 SLICE_88
ROUTE 1 e 1.441 SLICE_88.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.547ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
Constraint Details:
2.504ns delay RCLK to SLICE_64 and
7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
12.500ns offset RCLK to RDQML by 2.547ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
--------
2.504 (42.5% logic, 57.5% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.B0 nRowColSel
CTOF_DEL --- 0.371 SLICE_92.B0 to SLICE_92.F0 SLICE_92
ROUTE 1 e 1.441 SLICE_92.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML
--------
7.449 (61.3% logic, 38.7% route), 3 logic levels.
Report: 9.953ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.276 ns| 7
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 10.425 ns| 6
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.073 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 21:32:27 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1_map.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
PERIOD NET "PHI2_c" 350.000000 ns (0 errors) 113 items scored, 0 timing errors detected.
PERIOD NET "nCCAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "nCRAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "RCLK_c" 16.000000 ns (0 errors) 395 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.485ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_380 (from PHI2_c -)
Destination: FF Data in ADSubmitted_380 (to PHI2_c -)
Delay: 0.462ns (56.7% logic, 43.3% route), 2 logic levels.
Constraint Details:
0.462ns physical path delay SLICE_9 to SLICE_9 meets
-0.023ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 SLICE_9.CLK to SLICE_9.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_9.Q0 to SLICE_9.C0 ADSubmitted
CTOF_DEL --- 0.092 SLICE_9.C0 to SLICE_9.F0 SLICE_9
ROUTE 1 e 0.001 SLICE_9.F0 to SLICE_9.DI0 n1361 (to PHI2_c)
--------
0.462 (56.7% logic, 43.3% route), 2 logic levels.
================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i11 (from RCLK_c +)
Destination: FF Data in IS_FSM__i12 (to RCLK_c +)
Delay: 0.356ns (44.1% logic, 55.9% route), 1 logic levels.
Constraint Details:
0.356ns physical path delay SLICE_72 to SLICE_72 meets
-0.021ns M_HLD and
0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
Physical Path Details:
Data path SLICE_72 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_72.CLK to SLICE_72.Q0 SLICE_72 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_72.Q0 to SLICE_72.M1 n702 (to RCLK_c)
--------
0.356 (44.1% logic, 55.9% route), 1 logic levels.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_55 and
1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
0.000ns hold offset RCLK to RA[10] by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_55.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 e 0.515 SLICE_55.Q0 to 87.PADDO n980
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10]
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[9] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 0.515 SLICE_88.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[8] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C0 nRowColSel
CTOF_DEL --- 0.092 SLICE_95.C0 to SLICE_95.F0 SLICE_95
ROUTE 1 e 0.515 SLICE_95.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[7] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_97.C0 nRowColSel
CTOF_DEL --- 0.092 SLICE_97.C0 to SLICE_97.F0 SLICE_97
ROUTE 1 e 0.515 SLICE_97.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[6] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C0 nRowColSel
CTOF_DEL --- 0.092 SLICE_98.C0 to SLICE_98.F0 SLICE_98
ROUTE 1 e 0.515 SLICE_98.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[5] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_98.C1 to SLICE_98.F1 SLICE_98
ROUTE 1 e 0.515 SLICE_98.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.850ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 2.071ns (65.5% logic, 34.5% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
0.000ns hold offset RCLK to RA[4] by 2.850ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.199 SLICE_64.Q0 to SLICE_64.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_64.C1 to SLICE_64.F1 SLICE_64
ROUTE 1 e 0.515 SLICE_64.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4]
--------
2.071 (65.5% logic, 34.5% route), 3 logic levels.
Report: 2.850ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[3] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_94.C1 to SLICE_94.F1 SLICE_94
ROUTE 1 e 0.515 SLICE_94.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[2] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_95.C1 to SLICE_95.F1 SLICE_95
ROUTE 1 e 0.515 SLICE_95.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[1] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C0 nRowColSel
CTOF_DEL --- 0.092 SLICE_94.C0 to SLICE_94.F0 SLICE_94
ROUTE 1 e 0.515 SLICE_94.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
0.000ns hold offset RCLK to RA[0] by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.C1 nRowColSel
CTOF_DEL --- 0.092 SLICE_92.C1 to SLICE_92.F1 SLICE_92
ROUTE 1 e 0.515 SLICE_92.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0]
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_60 and
1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
0.000ns hold offset RCLK to nRCS by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_60.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 e 0.515 SLICE_60.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_34 and
1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
0.000ns hold offset RCLK to RCKE by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_34.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 e 0.515 SLICE_34.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_63 and
1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
0.000ns hold offset RCLK to nRWE by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_63.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 e 0.515 SLICE_63.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_61 and
1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
0.000ns hold offset RCLK to nRRAS by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_61.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 e 0.515 SLICE_61.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_58 and
1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
0.000ns hold offset RCLK to nRCAS by 2.559ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_58.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 e 0.515 SLICE_58.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS
--------
1.780 (71.1% logic, 28.9% route), 2 logic levels.
Report: 2.559ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
0.000ns hold offset RCLK to RDQMH by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.B0 nRowColSel
CTOF_DEL --- 0.092 SLICE_88.B0 to SLICE_88.F0 SLICE_88
ROUTE 1 e 0.515 SLICE_88.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
Constraint Details:
0.779ns delay RCLK to SLICE_64 and
2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
0.000ns hold offset RCLK to RDQML by 3.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
--------
0.779 (33.9% logic, 66.1% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.B0 nRowColSel
CTOF_DEL --- 0.092 SLICE_92.B0 to SLICE_92.F0 SLICE_92
ROUTE 1 e 0.515 SLICE_92.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML
--------
2.387 (56.8% logic, 43.2% route), 3 logic levels.
Report: 3.166ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.850 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------