PAR: Place And Route Diamond (64-bit) 3.12.1.454. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Tue Aug 15 05:22:28 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml Preference file: RAM2GS_LCMXO640C_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 -9.822 909228 0.273 0 03 Completed * : Design saved. Total (real) run time for 1-seed: 3 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" Tue Aug 15 05:22:28 2023 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf Preference file: RAM2GS_LCMXO640C_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO640C Package: TQFP100 Performance: 3 Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.17. Performance Hardware Data Status: Version 1.124. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 67/159 42% used 67/74 90% bonded SLICE 71/320 22% used Number of Signals: 262 Number of Connections: 662 Pin Constraint Summary: 67 out of 67 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: RCLK_c (driver: RCLK, clk load #: 40) PHI2_c (driver: PHI2, clk load #: 13) The following 1 signal is selected to use the secondary clock routing resources: nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) No signal is selected as Global Set/Reset. Starting Placer Phase 0. ......... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. ......... Placer score = 1223575. Finished Placer Phase 1. REAL time: 3 secs Starting Placer Phase 2. . Placer score = 1220793 Finished Placer Phase 2. REAL time: 3 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 4 (25%) General PIO: 1 out of 160 (0%) Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 PRIMARY : 2 out of 4 (50%) SECONDARY: 1 out of 4 (25%) --------------- End of Clock Report --------------- I/O Usage Summary (final): 67 out of 159 (42.1%) PIO sites used. 67 out of 74 (90.5%) bonded PIO sites used. Number of PIO comps: 67; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 18 / 18 (100%) | 3.3V | - | - | | 1 | 18 / 21 ( 85%) | 3.3V | - | - | | 2 | 13 / 14 ( 92%) | - | - | - | | 3 | 18 / 21 ( 85%) | 3.3V | - | - | +----------+----------------+------------+------------+------------+ Total placer CPU time: 2 secs Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. 0 connections routed; 662 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=nCCAS_c loads=7 clock_loads=4 Completed router resource preassignment. Real time: 3 secs Start NBR router at 05:22:31 08/15/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 05:22:31 08/15/23 Start NBR section for initial routing at 05:22:31 08/15/23 Level 1, iteration 1 0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs Level 2, iteration 1 7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs Level 3, iteration 1 9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs Level 4, iteration 1 9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 3 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 05:22:31 08/15/23 Level 4, iteration 1 5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 3 secs Level 4, iteration 2 4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 3 secs Level 4, iteration 3 4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs Level 4, iteration 4 2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs Level 4, iteration 5 2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs Level 4, iteration 6 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs Start NBR section for performance tuning (iteration 1) at 05:22:31 08/15/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs Start NBR section for re-routing at 05:22:31 08/15/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 3 secs Start NBR section for post-routing at 05:22:31 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 260 (39.27%) Estimated worst slack : -9.822ns Timing score : 909228 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=nCCAS_c loads=7 clock_loads=4 Total CPU time 2 secs Total REAL time: 3 secs Completely routed. End of route. 662 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 909228 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = -9.822 PAR_SUMMARY::Timing score> = 909.228 PAR_SUMMARY::Worst slack> = 0.273 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 2 secs Total REAL time to completion: 3 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.