--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 20:23:38 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: RAM2GS
Device,speed: LCMXO256C,M
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.540ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_375 (from PHI2_c -)
Destination: FF Data in ADSubmitted_375 (to PHI2_c -)
Delay: 0.517ns (50.7% logic, 49.3% route), 2 logic levels.
Constraint Details:
0.517ns physical path delay SLICE_9 to SLICE_9 meets
-0.023ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.540ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C3C.CLK to R6C3C.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.255 R6C3C.Q0 to R6C3C.B0 ADSubmitted
CTOF_DEL --- 0.092 R6C3C.B0 to R6C3C.F0 SLICE_9
ROUTE 1 0.000 R6C3C.F0 to R6C3C.DI0 n1355 (to PHI2_c)
--------
0.517 (50.7% logic, 49.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C3C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C3C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.089ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_373 (from PHI2_c -)
Destination: FF Data in CmdUFMCS_379 (to PHI2_c -)
FF CmdUFMCLK_380
Delay: 1.060ns (33.4% logic, 66.6% route), 3 logic levels.
Constraint Details:
1.060ns physical path delay SLICE_18 to SLICE_83 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.089ns
Physical Path Details:
Data path SLICE_18 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.174 R6C4D.Q0 to R6C3A.D1 CmdEnable
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_76
ROUTE 3 0.354 R6C3A.F1 to R4C5A.C1 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C5A.C1 to R4C5A.F1 SLICE_73
ROUTE 2 0.178 R4C5A.F1 to R5C5D.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.060 (33.4% logic, 66.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R5C5D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.165ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_373 (from PHI2_c -)
Destination: FF Data in CmdSubmitted_378 (to PHI2_c -)
Delay: 1.136ns (31.2% logic, 68.8% route), 3 logic levels.
Constraint Details:
1.136ns physical path delay SLICE_18 to SLICE_19 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.165ns
Physical Path Details:
Data path SLICE_18 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.174 R6C4D.Q0 to R6C3A.D1 CmdEnable
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_76
ROUTE 3 0.181 R6C3A.F1 to R6C3A.B0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R6C3A.B0 to R6C3A.F0 SLICE_76
ROUTE 2 0.427 R6C3A.F0 to R7C4D.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.136 (31.2% logic, 68.8% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R7C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.212ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_373 (from PHI2_c -)
Destination: FF Data in CmdUFMSDI_381 (to PHI2_c -)
Delay: 1.183ns (29.9% logic, 70.1% route), 3 logic levels.
Constraint Details:
1.183ns physical path delay SLICE_18 to SLICE_77 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.212ns
Physical Path Details:
Data path SLICE_18 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.174 R6C4D.Q0 to R6C3A.D1 CmdEnable
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_76
ROUTE 3 0.354 R6C3A.F1 to R4C5A.C1 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C5A.C1 to R4C5A.F1 SLICE_73
ROUTE 2 0.301 R4C5A.F1 to R7C5C.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.183 (29.9% logic, 70.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R7C5C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.247ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_373 (from PHI2_c -)
Destination: FF Data in XOR8MEG_376 (to PHI2_c -)
Delay: 1.218ns (29.1% logic, 70.9% route), 3 logic levels.
Constraint Details:
1.218ns physical path delay SLICE_18 to SLICE_94 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.247ns
Physical Path Details:
Data path SLICE_18 to SLICE_94:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.174 R6C4D.Q0 to R6C3A.D1 CmdEnable
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_76
ROUTE 3 0.266 R6C3A.F1 to R7C3C.A0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R7C3C.A0 to R7C3C.F0 SLICE_97
ROUTE 1 0.424 R7C3C.F0 to R8C5C.CE PHI2_N_114_enable_2 (to PHI2_c)
--------
1.218 (29.1% logic, 70.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R8C5C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.288ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_373 (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN_377 (to PHI2_c -)
Delay: 1.259ns (28.1% logic, 71.9% route), 3 logic levels.
Constraint Details:
1.259ns physical path delay SLICE_18 to SLICE_23 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.288ns
Physical Path Details:
Data path SLICE_18 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.174 R6C4D.Q0 to R6C3A.D1 CmdEnable
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_76
ROUTE 3 0.181 R6C3A.F1 to R6C3A.B0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R6C3A.B0 to R6C3A.F0 SLICE_76
ROUTE 2 0.550 R6C3A.F0 to R7C3A.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.259 (28.1% logic, 71.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R7C3A.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.392ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_374 (from PHI2_c -)
Destination: FF Data in CmdEnable_373 (to PHI2_c -)
Delay: 1.363ns (37.1% logic, 62.9% route), 4 logic levels.
Constraint Details:
1.363ns physical path delay SLICE_14 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.392ns
Physical Path Details:
Data path SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4C.CLK to R6C4C.Q0 SLICE_14 (from PHI2_c)
ROUTE 1 0.256 R6C4C.Q0 to R6C3D.A1 C1Submitted
CTOOFX_DEL --- 0.151 R6C3D.A1 to R6C3D.OFX0 i26/SLICE_70
ROUTE 1 0.269 R6C3D.OFX0 to R6C4A.B1 n13
CTOF_DEL --- 0.092 R6C4A.B1 to R6C4A.F1 SLICE_80
ROUTE 1 0.172 R6C4A.F1 to R6C4A.B0 n6
CTOF_DEL --- 0.092 R6C4A.B0 to R6C4A.F0 SLICE_80
ROUTE 1 0.161 R6C4A.F0 to R6C4D.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.363 (37.1% logic, 62.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.395ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_375 (from PHI2_c -)
Destination: FF Data in CmdEnable_373 (to PHI2_c -)
Delay: 1.366ns (37.3% logic, 62.7% route), 4 logic levels.
Constraint Details:
1.366ns physical path delay SLICE_9 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.395ns
Physical Path Details:
Data path SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C3C.CLK to R6C3C.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.255 R6C3C.Q0 to R6C3D.B0 ADSubmitted
CTOOFX_DEL --- 0.155 R6C3D.B0 to R6C3D.OFX0 i26/SLICE_70
ROUTE 1 0.269 R6C3D.OFX0 to R6C4A.B1 n13
CTOF_DEL --- 0.092 R6C4A.B1 to R6C4A.F1 SLICE_80
ROUTE 1 0.172 R6C4A.F1 to R6C4A.B0 n6
CTOF_DEL --- 0.092 R6C4A.B0 to R6C4A.F0 SLICE_80
ROUTE 1 0.161 R6C4A.F0 to R6C4D.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.366 (37.3% logic, 62.7% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C3C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4D.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 175.744ns (weighted slack = 351.488ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG_376 (from PHI2_c -)
Destination: FF Data in RA11_353 (to PHI2_c +)
Delay: 0.733ns (35.7% logic, 64.3% route), 2 logic levels.
Constraint Details:
0.733ns physical path delay SLICE_94 to SLICE_31 meets
-0.011ns DIN_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.011ns) by 175.744ns
Physical Path Details:
Data path SLICE_94 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R8C5C.CLK to R8C5C.Q0 SLICE_94 (from PHI2_c)
ROUTE 1 0.471 R8C5C.Q0 to R2C5A.C0 XOR8MEG
CTOF_DEL --- 0.092 R2C5A.C0 to R2C5A.F0 SLICE_31
ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_180 (to PHI2_c)
--------
0.733 (35.7% logic, 64.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R8C5C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R2C5A.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 176.433ns (weighted slack = 352.866ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i3 (from PHI2_c +)
Destination: FF Data in C1Submitted_374 (to PHI2_c -)
Delay: 1.404ns (24.3% logic, 75.7% route), 3 logic levels.
Constraint Details:
1.404ns physical path delay SLICE_92 to SLICE_14 meets
-0.029ns CE_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.029ns) by 176.433ns
Physical Path Details:
Data path SLICE_92 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C3B.CLK to R2C3B.Q1 SLICE_92 (from PHI2_c)
ROUTE 1 0.502 R2C3B.Q1 to R5C4B.A1 Bank_3
CTOF_DEL --- 0.092 R5C4B.A1 to R5C4B.F1 SLICE_74
ROUTE 5 0.137 R5C4B.F1 to R5C4B.C0 n1279
CTOF_DEL --- 0.092 R5C4B.C0 to R5C4B.F0 SLICE_74
ROUTE 1 0.424 R5C4B.F0 to R6C4C.CE PHI2_N_114_enable_1 (to PHI2_c)
--------
1.404 (24.3% logic, 75.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_92:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R2C3B.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200 39.PADDI to R6C4C.CLK PHI2_c
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "RCLK_c" 15.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i2 (from RCLK_c +)
Destination: FF Data in IS_FSM__i3 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_101 to SLICE_101 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_101 to SLICE_101:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4C.CLK to R5C4C.Q0 SLICE_101 (from RCLK_c)
ROUTE 1 0.161 R5C4C.Q0 to R5C4C.M1 n705 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_101:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_101:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i4 (from RCLK_c +)
Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_81 to SLICE_81 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_81 to SLICE_81:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4C.CLK to R4C4C.Q0 SLICE_81 (from RCLK_c)
ROUTE 1 0.161 R4C4C.Q0 to R4C4C.M1 n703 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_81:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_81:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i12 (from RCLK_c +)
Destination: FF Data in IS_FSM__i13 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_84 to SLICE_84 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_84 to SLICE_84:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4D.CLK to R5C4D.Q0 SLICE_84 (from RCLK_c)
ROUTE 1 0.161 R5C4D.Q0 to R5C4D.M1 n695 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i8 (from RCLK_c +)
Destination: FF Data in IS_FSM__i9 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_95 to SLICE_95 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_95 to SLICE_95:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R6C2A.CLK to R6C2A.Q0 SLICE_95 (from RCLK_c)
ROUTE 1 0.161 R6C2A.Q0 to R6C2A.M1 n699 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R6C2A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R6C2A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i11 (from RCLK_c +)
Destination: FF Data in IS_FSM__i12 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_96 to SLICE_84 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_96 to SLICE_84:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4A.CLK to R5C4A.Q1 SLICE_96 (from RCLK_c)
ROUTE 1 0.161 R5C4A.Q1 to R5C4D.M0 n696 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i10 (from RCLK_c +)
Destination: FF Data in IS_FSM__i11 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_96 to SLICE_96 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_96 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4A.CLK to R5C4A.Q0 SLICE_96 (from RCLK_c)
ROUTE 1 0.161 R5C4A.Q0 to R5C4A.M1 n697 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r_344 (from RCLK_c +)
Destination: FF Data in PHI2r2_345 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_97 to SLICE_88 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_97 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C3C.CLK to R7C3C.Q1 SLICE_97 (from RCLK_c)
ROUTE 1 0.161 R7C3C.Q1 to R7C3B.M1 PHI2r (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C3C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C3B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i14 (from RCLK_c +)
Destination: FF Data in IS_FSM__i15 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_99 to SLICE_99 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_99 to SLICE_99:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5C.CLK to R3C5C.Q0 SLICE_99 (from RCLK_c)
ROUTE 1 0.161 R3C5C.Q0 to R3C5C.M1 n693 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R3C5C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R3C5C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.345ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2_345 (from RCLK_c +)
Destination: FF Data in PHI2r3_346 (to RCLK_c +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_88 to SLICE_97 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
Data path SLICE_88 to SLICE_97:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C3B.CLK to R7C3B.Q1 SLICE_88 (from RCLK_c)
ROUTE 3 0.167 R7C3B.Q1 to R7C3C.M0 PHI2r2 (to RCLK_c)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C3B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C3C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.345ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i15 (from RCLK_c +)
Destination: FF Data in IS_FSM__i0 (to RCLK_c +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_99 to SLICE_87 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
Data path SLICE_99 to SLICE_87:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5C.CLK to R3C5C.Q1 SLICE_99 (from RCLK_c)
ROUTE 2 0.167 R3C5C.Q1 to R3C5A.M0 Ready_N_272 (to RCLK_c)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R3C5C.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_87:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R3C5A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_368 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_55 and
1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
0.000ns hold offset RCLK to RA[10] by 2.220ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C4B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 0.468 R2C4B.Q0 to 87.PADDO n974
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10]
--------
1.733 (73.0% logic, 27.0% route), 2 logic levels.
Report: 2.220ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.805ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 2.318ns (58.5% logic, 41.5% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.318ns delay SLICE_64 to RA[9] (totaling 2.805ns) meets
0.000ns hold offset RCLK to RA[9] by 2.805ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.469 R7C2B.Q0 to R3C5A.D1 nRowColSel
CTOF_DEL --- 0.092 R3C5A.D1 to R3C5A.F1 SLICE_87
ROUTE 1 0.492 R3C5A.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9]
--------
2.318 (58.5% logic, 41.5% route), 3 logic levels.
Report: 2.805ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.476ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 1.989ns (68.2% logic, 31.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.989ns delay SLICE_64 to RA[8] (totaling 2.476ns) meets
0.000ns hold offset RCLK to RA[8] by 2.476ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.435 R7C2B.Q0 to R2C2C.D0 nRowColSel
CTOF_DEL --- 0.092 R2C2C.D0 to R2C2C.F0 SLICE_98
ROUTE 1 0.197 R2C2C.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8]
--------
1.989 (68.2% logic, 31.8% route), 3 logic levels.
Report: 2.476ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.460ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 1.973ns (68.8% logic, 31.2% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.973ns delay SLICE_64 to RA[7] (totaling 2.460ns) meets
0.000ns hold offset RCLK to RA[7] by 2.460ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.222 R7C2B.Q0 to R7C2B.C1 nRowColSel
CTOF_DEL --- 0.092 R7C2B.C1 to R7C2B.F1 SLICE_64
ROUTE 1 0.394 R7C2B.F1 to 100.PADDO RA_c_7
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7]
--------
1.973 (68.8% logic, 31.2% route), 3 logic levels.
Report: 2.460ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.759ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 2.272ns (59.7% logic, 40.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.272ns delay SLICE_64 to RA[6] (totaling 2.759ns) meets
0.000ns hold offset RCLK to RA[6] by 2.759ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.435 R7C2B.Q0 to R2C2C.D1 nRowColSel
CTOF_DEL --- 0.092 R2C2C.D1 to R2C2C.F1 SLICE_98
ROUTE 1 0.480 R2C2C.F1 to 91.PADDO RA_c_6
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6]
--------
2.272 (59.7% logic, 40.3% route), 3 logic levels.
Report: 2.759ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.516ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 2.029ns (66.9% logic, 33.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.029ns delay SLICE_64 to RA[5] (totaling 2.516ns) meets
0.000ns hold offset RCLK to RA[5] by 2.516ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.278 R7C2B.Q0 to R6C2A.A1 nRowColSel
CTOF_DEL --- 0.092 R6C2A.A1 to R6C2A.F1 SLICE_95
ROUTE 1 0.394 R6C2A.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5]
--------
2.029 (66.9% logic, 33.1% route), 3 logic levels.
Report: 2.516ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.635ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 2.148ns (63.2% logic, 36.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.148ns delay SLICE_64 to RA[4] (totaling 2.635ns) meets
0.000ns hold offset RCLK to RA[4] by 2.635ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.435 R7C2B.Q0 to R2C2B.D1 nRowColSel
CTOF_DEL --- 0.092 R2C2B.D1 to R2C2B.F1 SLICE_93
ROUTE 1 0.356 R2C2B.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4]
--------
2.148 (63.2% logic, 36.8% route), 3 logic levels.
Report: 2.635ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.758ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 2.271ns (59.8% logic, 40.2% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.271ns delay SLICE_64 to RA[3] (totaling 2.758ns) meets
0.000ns hold offset RCLK to RA[3] by 2.758ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.446 R7C2B.Q0 to R2C3B.D1 nRowColSel
CTOF_DEL --- 0.092 R2C3B.D1 to R2C3B.F1 SLICE_92
ROUTE 1 0.468 R2C3B.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3]
--------
2.271 (59.8% logic, 40.2% route), 3 logic levels.
Report: 2.758ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.487ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 2.000ns (67.8% logic, 32.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.000ns delay SLICE_64 to RA[2] (totaling 2.487ns) meets
0.000ns hold offset RCLK to RA[2] by 2.487ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.446 R7C2B.Q0 to R2C3A.D0 nRowColSel
CTOF_DEL --- 0.092 R2C3A.D0 to R2C3A.F0 SLICE_90
ROUTE 1 0.197 R2C3A.F0 to 94.PADDO RA_c_2
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2]
--------
2.000 (67.8% logic, 32.1% route), 3 logic levels.
Report: 2.487ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.487ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 2.000ns (67.8% logic, 32.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.000ns delay SLICE_64 to RA[1] (totaling 2.487ns) meets
0.000ns hold offset RCLK to RA[1] by 2.487ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.446 R7C2B.Q0 to R2C3B.D0 nRowColSel
CTOF_DEL --- 0.092 R2C3B.D0 to R2C3B.F0 SLICE_92
ROUTE 1 0.197 R2C3B.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1]
--------
2.000 (67.8% logic, 32.1% route), 3 logic levels.
Report: 2.487ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.476ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 1.989ns (68.2% logic, 31.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.989ns delay SLICE_64 to RA[0] (totaling 2.476ns) meets
0.000ns hold offset RCLK to RA[0] by 2.476ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.435 R7C2B.Q0 to R2C2B.D0 nRowColSel
CTOF_DEL --- 0.092 R2C2B.D0 to R2C2B.F0 SLICE_93
ROUTE 1 0.197 R2C2B.F0 to 98.PADDO RA_c_0
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0]
--------
1.989 (68.2% logic, 31.8% route), 3 logic levels.
Report: 2.476ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_364 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_60 and
1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRCS by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C5B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.197 R2C5B.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.252ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_363 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 1.765ns (71.7% logic, 28.3% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_34 and
1.765ns delay SLICE_34 to RCKE (totaling 2.252ns) meets
0.000ns hold offset RCLK to RCKE by 2.252ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R6C5B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R6C5B.CLK to R6C5B.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 0.500 R6C5B.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE
--------
1.765 (71.7% logic, 28.3% route), 2 logic levels.
Report: 2.252ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_367 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_63 and
1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRWE by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R3C5B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 0.197 R3C5B.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.111ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_365 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 1.624ns (77.9% logic, 22.1% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_61 and
1.624ns delay SLICE_61 to nRRAS (totaling 2.111ns) meets
0.000ns hold offset RCLK to nRRAS by 2.111ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C4C.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 0.359 R2C4C.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS
--------
1.624 (77.9% logic, 22.1% route), 2 logic levels.
Report: 2.111ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_366 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_58 and
1.733ns delay SLICE_58 to nRCAS (totaling 2.220ns) meets
0.000ns hold offset RCLK to nRCAS by 2.220ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C4A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4A.CLK to R2C4A.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 0.468 R2C4A.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS
--------
1.733 (73.0% logic, 27.0% route), 2 logic levels.
Report: 2.220ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.510ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 2.023ns (67.1% logic, 32.9% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.023ns delay SLICE_64 to RDQMH (totaling 2.510ns) meets
0.000ns hold offset RCLK to RDQMH by 2.510ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.469 R7C2B.Q0 to R3C5A.D0 nRowColSel
CTOF_DEL --- 0.092 R3C5A.D0 to R3C5A.F0 SLICE_87
ROUTE 1 0.197 R3C5A.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH
--------
2.023 (67.1% logic, 32.9% route), 3 logic levels.
Report: 2.510ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.602ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_370 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 2.115ns (64.2% logic, 35.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.115ns delay SLICE_64 to RDQML (totaling 2.602ns) meets
0.000ns hold offset RCLK to RDQML by 2.602ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R7C2B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.278 R7C2B.Q0 to R6C2A.A0 nRowColSel
CTOF_DEL --- 0.092 R6C2A.A0 to R6C2A.F0 SLICE_95
ROUTE 1 0.480 R6C2A.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML
--------
2.115 (64.2% logic, 35.8% route), 3 logic levels.
Report: 2.602ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 15.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.805 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.476 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.460 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.759 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.516 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.635 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.758 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.487 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.487 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.476 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.252 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.111 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.510 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.602 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 15.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 520 paths, 6 nets, and 436 connections (70.89% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)