-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 -- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd -- Netlist created on Tue Aug 15 05:03:22 2023 -- Netlist written on Tue Aug 15 05:03:24 2023 -- Design is for device LCMXO640C -- Design is for package TQFP100 -- Design is for performance grade 3 -- entity vmuxregsre library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity vmuxregsre is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; end vmuxregsre; architecture Structure of vmuxregsre is component FL1P3DX generic (GSR: String); port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; Q: out Std_logic); end component; begin INST01: FL1P3DX generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); end Structure; -- entity vcc library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity vcc is port (PWR1: out Std_logic); ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; end vcc; architecture Structure of vcc is component VHI port (Z: out Std_logic); end component; begin INST1: VHI port map (Z=>PWR1); end Structure; -- entity gnd library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity gnd is port (PWR0: out Std_logic); ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; end gnd; architecture Structure of gnd is component VLO port (Z: out Std_logic); end component; begin INST1: VLO port map (Z=>PWR0); end Structure; -- entity ccu2B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity ccu2B is port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE; end ccu2B; architecture Structure of ccu2B is component CCU2 generic (INIT0: String; INIT1: String; INJECT1_0: String; INJECT1_1: String); port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; COUT1: out Std_logic); end component; begin inst1: CCU2 generic map (INIT0 => "0xfaaa", INIT1 => "0xfaaa", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); end Structure; -- entity SLICE_0 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_0 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_0"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; end SLICE_0; architecture Structure of SLICE_0 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_0_FS_610_add_4_8_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_0_FS_610_add_4_8_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i7: vmuxregsre port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i6: vmuxregsre port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_8: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_0_FS_610_add_4_8_S0, S1=>SLICE_0_FS_610_add_4_8_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_1 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_1 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_1"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; end SLICE_1; architecture Structure of SLICE_1 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_1_FS_610_add_4_16_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_1_FS_610_add_4_16_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i15: vmuxregsre port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i14: vmuxregsre port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_16: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_610_add_4_16_S0, S1=>SLICE_1_FS_610_add_4_16_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_2 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_2 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_2"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; end SLICE_2; architecture Structure of SLICE_2 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_2_FS_610_add_4_6_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_2_FS_610_add_4_6_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i5: vmuxregsre port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i4: vmuxregsre port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_6: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_610_add_4_6_S0, S1=>SLICE_2_FS_610_add_4_6_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_3 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_3 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_3"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; end SLICE_3; architecture Structure of SLICE_3 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_3_FS_610_add_4_14_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_3_FS_610_add_4_14_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i13: vmuxregsre port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i12: vmuxregsre port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_14: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_610_add_4_14_S0, S1=>SLICE_3_FS_610_add_4_14_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity ccu20001 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity ccu20001 is port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; end ccu20001; architecture Structure of ccu20001 is component CCU2 generic (INIT0: String; INIT1: String; INJECT1_0: String; INJECT1_1: String); port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; COUT1: out Std_logic); end component; begin inst1: CCU2 generic map (INIT0 => "0x0555", INIT1 => "0xfaaa", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); end Structure; -- entity SLICE_4 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_4 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_4"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; end SLICE_4; architecture Structure of SLICE_4 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_4_FS_610_add_4_2_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_4_FS_610_add_4_2_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20001 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i1: vmuxregsre port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i0: vmuxregsre port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_2: ccu20001 port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>SLICE_4_FS_610_add_4_2_S0, S1=>SLICE_4_FS_610_add_4_2_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_5 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_5 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_5"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; end SLICE_5; architecture Structure of SLICE_5 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_5_FS_610_add_4_12_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_5_FS_610_add_4_12_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i11: vmuxregsre port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i10: vmuxregsre port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_12: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_610_add_4_12_S0, S1=>SLICE_5_FS_610_add_4_12_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_6 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_6 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_6"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; end SLICE_6; architecture Structure of SLICE_6 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_6_FS_610_add_4_4_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_6_FS_610_add_4_4_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i3: vmuxregsre port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i2: vmuxregsre port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_4: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_610_add_4_4_S0, S1=>SLICE_6_FS_610_add_4_4_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_7 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_7 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_7"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; end SLICE_7; architecture Structure of SLICE_7 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_7_FS_610_add_4_10_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_7_FS_610_add_4_10_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i9: vmuxregsre port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i8: vmuxregsre port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_10: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_610_add_4_10_S0, S1=>SLICE_7_FS_610_add_4_10_S1, CO0=>open, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, FCO_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_dly'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_dly'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_dly'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_8 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_8 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_8"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_A1_CLK : VitalDelayType := 0 ns; tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_A0_CLK : VitalDelayType := 0 ns; tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_FCI_CLK : VitalDelayType := 0 ns; tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; end SLICE_8; architecture Structure of SLICE_8 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A1_dly : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal A0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal FCI_dly : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal VCCI: Std_logic; signal SLICE_8_FS_610_add_4_18_S1: Std_logic; signal GNDI: Std_logic; signal SLICE_8_FS_610_add_4_18_S0: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; CO1: out Std_logic); end component; begin FS_610_i17: vmuxregsre port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S1, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_610_i16: vmuxregsre port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S0, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_610_add_4_18: ccu2B port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_610_add_4_18_S0, S1=>SLICE_8_FS_610_add_4_18_S1, CO0=>open, CO1=>open); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); END BLOCK; VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_A1_CLK : x01 := '0'; VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_A0_CLK : x01 := '0'; VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_FCI_CLK : x01 := '0'; VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => A1_dly, TestSignalName => "A1", TestDelay => tisd_A1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A1_CLK_noedge_posedge, SetupLow => tsetup_A1_CLK_noedge_posedge, HoldHigh => thold_A1_CLK_noedge_posedge, HoldLow => thold_A1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A1_CLK_TimingDatash, Violation => tviol_A1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => A0_dly, TestSignalName => "A0", TestDelay => tisd_A0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_A0_CLK_noedge_posedge, SetupLow => tsetup_A0_CLK_noedge_posedge, HoldHigh => thold_A0_CLK_noedge_posedge, HoldLow => thold_A0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => A0_CLK_TimingDatash, Violation => tviol_A0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => FCI_dly, TestSignalName => "FCI", TestDelay => tisd_FCI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_FCI_CLK_noedge_posedge, SetupLow => tsetup_FCI_CLK_noedge_posedge, HoldHigh => thold_FCI_CLK_noedge_posedge, HoldLow => thold_FCI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => FCI_CLK_TimingDatash, Violation => tviol_FCI_CLK, MsgSeverity => warning); END IF; Q0_zd := Q0_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut4 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut4 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; end lut4; architecture Structure of lut4 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xDFDF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40002 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40002 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE; end lut40002; architecture Structure of lut40002 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x50DC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity vmuxregsre0003 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity vmuxregsre0003 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre0003 : ENTITY IS TRUE; end vmuxregsre0003; architecture Structure of vmuxregsre0003 is component FL1P3IY generic (GSR: String); port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; Q: out Std_logic); end component; begin INST01: FL1P3IY generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); end Structure; -- entity inverter library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity inverter is port (I: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; end inverter; architecture Structure of inverter is component INV port (A: in Std_logic; Z: out Std_logic); end component; begin INST1: INV port map (A=>I, Z=>Z); end Structure; -- entity SLICE_9 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_9 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_9"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; end SLICE_9; architecture Structure of SLICE_9 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40002 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_3_lut: lut4 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1125_4_lut: lut40002 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); ADSubmitted_407: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40004 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40004 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; end lut40004; architecture Structure of lut40004 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xEEEE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40005 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40005 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; end lut40005; architecture Structure of lut40005 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xE0F0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity vmuxregsre0006 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity vmuxregsre0006 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre0006 : ENTITY IS TRUE; end vmuxregsre0006; architecture Structure of vmuxregsre0006 is component FL1P3JY generic (GSR: String); port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; Q: out Std_logic); end component; begin INST01: FL1P3JY generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); end Structure; -- entity SLICE_14 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_14 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_14"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; end SLICE_14; architecture Structure of SLICE_14 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40005 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0006 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin i1988_2_lut: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2062_2_lut_3_lut_4_lut: lut40005 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); C1Submitted_406: vmuxregsre0006 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40007 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40007 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; end lut40007; architecture Structure of lut40007 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xDFFF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40008 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40008 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; end lut40008; architecture Structure of lut40008 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0800") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_18 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_18 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_18"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; end SLICE_18; architecture Structure of SLICE_18 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40007 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i13_4_lut: lut40007 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i3_4_lut_adj_21: lut40008 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CmdEnable_405: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40009 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40009 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; end lut40009; architecture Structure of lut40009 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0808") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40010 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40010 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; end lut40010; architecture Structure of lut40010 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFFFF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_19 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_19 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_19"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; end SLICE_19; architecture Structure of SLICE_19 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40009 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40010 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut_rep_29: lut40009 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); n2568_001_BUF1_BUF1: lut40010 port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); CmdSubmitted_411: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0 <= F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40011 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40011 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; end lut40011; architecture Structure of lut40011 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFEFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40012 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40012 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; end lut40012; architecture Structure of lut40012 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCC5C") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_23 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_23 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_23"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; end SLICE_23; architecture Structure of SLICE_23 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40011 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40012 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_3_lut_adj_2: lut40011 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); Cmdn8MEGEN_I_93_4_lut: lut40012 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); Cmdn8MEGEN_410: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40013 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40013 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; end lut40013; architecture Structure of lut40013 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x4000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_25 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_25 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_25"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; end SLICE_25; architecture Structure of SLICE_25 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40010 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40013 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i3_3_lut_4_lut_4_lut: lut40013 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); n2568_000_BUF1_BUF1: lut40010 port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); InitReady_394: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0 <= F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40014 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40014 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; end lut40014; architecture Structure of lut40014 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFDFD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_26 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_26 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_26"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; end SLICE_26; architecture Structure of SLICE_26 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40010 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2049_3_lut: lut40014 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); m1_lut: lut40010 port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); LEDEN_419: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0 <= F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40015 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40015 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; end lut40015; architecture Structure of lut40015 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xDDDD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_31 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_31 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_31"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; end SLICE_31; architecture Structure of SLICE_31 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0006 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40011 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_2_lut: lut40015 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_3_lut_adj_27: lut40011 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); RA10_400: vmuxregsre0006 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40016 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40016 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; end lut40016; architecture Structure of lut40016 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xC6C6") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_32 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_32 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_32"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; end SLICE_32; architecture Structure of SLICE_32 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40016 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Din_7_I_0_462_i6_2_lut_rep_35: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RA11_I_54_3_lut: lut40016 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); RA11_385: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40017 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40017 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; end lut40017; architecture Structure of lut40017 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xF8F8") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40018 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40018 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; end lut40018; architecture Structure of lut40018 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCACA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_34 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_34 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_34"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; end SLICE_34; architecture Structure of SLICE_34 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40017 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i78_2_lut_rep_24_3_lut: lut40017 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1259_3_lut: lut40018 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); RCKEEN_401: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40019 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40019 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; end lut40019; architecture Structure of lut40019 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xBBBB") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40020 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40020 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; end lut40020; architecture Structure of lut40020 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCFC8") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_35 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_35 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_35"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; end SLICE_35; architecture Structure of SLICE_35 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40019 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40020 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut: lut40019 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RCKE_I_0_449_4_lut: lut40020 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CASr2_383: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); RCKE_395: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_36 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_36 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_36"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; end SLICE_36; architecture Structure of SLICE_36 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40010 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i771_2_lut_rep_26_2_lut: lut40015 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); n2568_002_BUF1_BUF1: lut40010 port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); Ready_404: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0 <= F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40021 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40021 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; end lut40021; architecture Structure of lut40021 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x3A0A") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40022 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40022 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; end lut40022; architecture Structure of lut40022 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xACAC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_43 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_43 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_43"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; end SLICE_43; architecture Structure of SLICE_43 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40021 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40022 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i919_4_lut: lut40021 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i886_3_lut: lut40022 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); UFMCLK_416: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40023 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40023 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; end lut40023; architecture Structure of lut40023 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFEFF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40024 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40024 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; end lut40024; architecture Structure of lut40024 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xF202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_44 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_44 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_44"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; end SLICE_44; architecture Structure of SLICE_44 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40023 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40024 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_rep_19_4_lut: lut40023 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); n2454_bdd_3_lut_4_lut: lut40024 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); UFMSDI_417: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40025 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40025 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; end lut40025; architecture Structure of lut40025 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFEFA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40026 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40026 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; end lut40026; architecture Structure of lut40026 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0020") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_49 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_49 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_49"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; end SLICE_49; architecture Structure of SLICE_49 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40025 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40026 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2028_4_lut: lut40025 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i3_4_lut_adj_12: lut40026 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); XOR8MEG_408: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40027 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40027 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; end lut40027; architecture Structure of lut40027 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCCC5") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_56 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_56 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_56"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; end SLICE_56; architecture Structure of SLICE_56 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40027 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_3_lut_adj_4: lut4 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); n8MEGEN_I_14_4_lut: lut40027 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); n8MEGEN_418: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40028 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40028 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; end lut40028; architecture Structure of lut40028 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x7F2F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40029 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40029 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; end lut40029; architecture Structure of lut40029 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xBFBF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity vmuxregsre0030 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity vmuxregsre0030 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre0030 : ENTITY IS TRUE; end vmuxregsre0030; architecture Structure of vmuxregsre0030 is component FL1P3BX generic (GSR: String); port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; Q: out Std_logic); end component; begin INST01: FL1P3BX generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); end Structure; -- entity selmux2 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity selmux2 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; end selmux2; architecture Structure of selmux2 is component MUX21 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; begin INST1: MUX21 port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); end Structure; -- entity SLICE_58 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_58 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_58"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; end SLICE_58; architecture Structure of SLICE_58 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal SLICE_58_SLICE_58_K1_H1: Std_logic; signal GNDI: Std_logic; signal SLICE_58_i2095_GATE_H0: Std_logic; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40029 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0030 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; begin SLICE_58_K1: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>SLICE_58_SLICE_58_K1_H1); i2095_GATE: lut40029 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>SLICE_58_i2095_GATE_H0); DRIVEGND: gnd port map (PWR0=>GNDI); nRCAS_398: vmuxregsre0030 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); SLICE_58_K0K1MUX: selmux2 port map (D0=>SLICE_58_i2095_GATE_H0, D1=>SLICE_58_SLICE_58_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; OFX0_zd := OFX0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40031 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40031 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; end lut40031; architecture Structure of lut40031 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFA88") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40032 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40032 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; end lut40032; architecture Structure of lut40032 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCFDD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_60 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_60 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_60"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; end SLICE_60; architecture Structure of SLICE_60 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0030 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40031 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40032 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1234_4_lut_4_lut: lut40031 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1_4_lut_adj_17: lut40032 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); nRCS_396: vmuxregsre0030 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40033 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40033 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; end lut40033; architecture Structure of lut40033 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x7373") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40034 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40034 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; end lut40034; architecture Structure of lut40034 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFFFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_61 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_61 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_61"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; end SLICE_61; architecture Structure of SLICE_61 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal GNDI: Std_logic; signal SLICE_61_SLICE_61_K1_H1: Std_logic; signal SLICE_61_i16_GATE_H0: Std_logic; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0030 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40033 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40034 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin SLICE_61_K1: lut40033 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>SLICE_61_SLICE_61_K1_H1); DRIVEGND: gnd port map (PWR0=>GNDI); i16_GATE: lut40034 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>SLICE_61_i16_GATE_H0); nRRAS_397: vmuxregsre0030 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); SLICE_61_K0K1MUX: selmux2 port map (D0=>SLICE_61_i16_GATE_H0, D1=>SLICE_61_SLICE_61_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; OFX0_zd := OFX0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40035 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40035 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; end lut40035; architecture Structure of lut40035 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFF7F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40036 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40036 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; end lut40036; architecture Structure of lut40036 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCFC5") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_63 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_63 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_63"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; end SLICE_63; architecture Structure of SLICE_63 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0030 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40035 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40036 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut_4_lut_adj_8: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); nRWE_I_0_455_4_lut: lut40036 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); nRWE_399: vmuxregsre0030 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40037 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40037 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; end lut40037; architecture Structure of lut40037 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCFEE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_64 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_64 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_64"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; end SLICE_64; architecture Structure of SLICE_64 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40037 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i10_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1_4_lut: lut40037 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); nRowColSel_402: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40038 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40038 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; end lut40038; architecture Structure of lut40038 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x2000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_65 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_65 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_65"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; end SLICE_65; architecture Structure of SLICE_65 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40038 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Ready_bdd_4_lut: lut40038 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1_2_lut_adj_25: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); S_FSM_i4: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40039 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40039 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; end lut40039; architecture Structure of lut40039 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFFFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40040 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40040 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; end lut40040; architecture Structure of lut40040 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x4444") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_66 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_66 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_66"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; end SLICE_66; architecture Structure of SLICE_66 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40039 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40040 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut_4_lut: lut40039 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i2057_2_lut: lut40040 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); S_FSM_i3: vmuxregsre0003 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40041 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40041 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; end lut40041; architecture Structure of lut40041 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x3A3A") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_67 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_67 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_67"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; end SLICE_67; architecture Structure of SLICE_67 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40019 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40041 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1129_3_lut: lut40041 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1_2_lut_adj_23: lut40019 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); S_FSM_i2: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_68 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_68 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_68"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; end SLICE_68; architecture Structure of SLICE_68 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal M0_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40039 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2024_2_lut_rep_28: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2026_4_lut: lut40039 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CASr3_384: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); S_FSM_i1: vmuxregsre port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); M0_INVERTERIN: inverter port map (I=>M0_dly, Z=>M0_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40042 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40042 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; end lut40042; architecture Structure of lut40042 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x8000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_69 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_69 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_69"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; end SLICE_69; architecture Structure of SLICE_69 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0006 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40042 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i6_4_lut: lut40042 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i11_3_lut: lut40018 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); nUFMCS_415: vmuxregsre0006 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40043 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40043 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; end lut40043; architecture Structure of lut40043 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x1F1F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40044 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40044 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; end lut40044; architecture Structure of lut40044 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x5540") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity RCKEEN_I_0_445_SLICE_70 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RCKEEN_I_0_445_SLICE_70 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCKEEN_I_0_445_SLICE_70"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); ATTRIBUTE Vital_Level0 OF RCKEEN_I_0_445_SLICE_70 : ENTITY IS TRUE; end RCKEEN_I_0_445_SLICE_70; architecture Structure of RCKEEN_I_0_445_SLICE_70 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal GNDI: Std_logic; signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1: Std_logic; signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0: Std_logic; component gnd port (PWR0: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40043 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40044 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RCKEEN_I_0_445_SLICE_70_K1: lut40043 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1); DRIVEGND: gnd port map (PWR0=>GNDI); RCKEEN_I_0_445_GATE: lut40044 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0); RCKEEN_I_0_445_SLICE_70_K0K1MUX: selmux2 port map (D0=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0, D1=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; OFX0_zd := OFX0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40045 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40045 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; end lut40045; architecture Structure of lut40045 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0080") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40046 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40046 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; end lut40046; architecture Structure of lut40046 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0004") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity i26_SLICE_71 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity i26_SLICE_71 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "i26_SLICE_71"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); ATTRIBUTE Vital_Level0 OF i26_SLICE_71 : ENTITY IS TRUE; end i26_SLICE_71; architecture Structure of i26_SLICE_71 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal i26_SLICE_71_i26_SLICE_71_K1_H1: Std_logic; signal i26_SLICE_71_i26_GATE_H0: Std_logic; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40045 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40046 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i26_SLICE_71_K1: lut40045 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>i26_SLICE_71_i26_SLICE_71_K1_H1); i26_GATE: lut40046 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>i26_SLICE_71_i26_GATE_H0); i26_SLICE_71_K0K1MUX: selmux2 port map (D0=>i26_SLICE_71_i26_GATE_H0, D1=>i26_SLICE_71_i26_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; OFX0_zd := OFX0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 8 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40047 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40047 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; end lut40047; architecture Structure of lut40047 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x2F23") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40048 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40048 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; end lut40048; architecture Structure of lut40048 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x2F2F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity i2099_SLICE_72 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity i2099_SLICE_72 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "i2099_SLICE_72"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); ATTRIBUTE Vital_Level0 OF i2099_SLICE_72 : ENTITY IS TRUE; end i2099_SLICE_72; architecture Structure of i2099_SLICE_72 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal i2099_SLICE_72_i2099_SLICE_72_K1_H1: Std_logic; signal GNDI: Std_logic; signal i2099_SLICE_72_i2099_GATE_H0: Std_logic; component gnd port (PWR0: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40047 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40048 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2099_SLICE_72_K1: lut40047 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>i2099_SLICE_72_i2099_SLICE_72_K1_H1); i2099_GATE: lut40048 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>i2099_SLICE_72_i2099_GATE_H0); DRIVEGND: gnd port map (PWR0=>GNDI); i2099_SLICE_72_K0K1MUX: selmux2 port map (D0=>i2099_SLICE_72_i2099_GATE_H0, D1=>i2099_SLICE_72_i2099_SLICE_72_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; OFX0_zd := OFX0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40049 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40049 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; end lut40049; architecture Structure of lut40049 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x4000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40050 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40050 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; end lut40050; architecture Structure of lut40050 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0002") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity i26_adj_28_SLICE_73 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity i26_adj_28_SLICE_73 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "i26_adj_28_SLICE_73"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); ATTRIBUTE Vital_Level0 OF i26_adj_28_SLICE_73 : ENTITY IS TRUE; end i26_adj_28_SLICE_73; architecture Structure of i26_adj_28_SLICE_73 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1: Std_logic; signal i26_adj_28_SLICE_73_i26_adj_28_GATE_H0: Std_logic; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40049 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40050 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i26_adj_28_SLICE_73_K1: lut40049 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1); i26_adj_28_GATE: lut40050 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0); i26_adj_28_SLICE_73_K0K1MUX: selmux2 port map (D0=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0, D1=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; OFX0_zd := OFX0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 7 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 8 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40051 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40051 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; end lut40051; architecture Structure of lut40051 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x1F10") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40052 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40052 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; end lut40052; architecture Structure of lut40052 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0040") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_74 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_74 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_74"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; end SLICE_74; architecture Structure of SLICE_74 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40051 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40052 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i35_3_lut_4_lut: lut40051 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i3_4_lut: lut40052 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RASr3_381: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); RASr2_380: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40053 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40053 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; end lut40053; architecture Structure of lut40053 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0200") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_75 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_75 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_75"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; end SLICE_75; architecture Structure of SLICE_75 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40009 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40053 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut: lut40009 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i7_4_lut: lut40053 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40054 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40054 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; end lut40054; architecture Structure of lut40054 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x1000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40055 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40055 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; end lut40055; architecture Structure of lut40055 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xB300") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_76 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_76 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_76"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; end SLICE_76; architecture Structure of SLICE_76 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40054 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40055 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i5_3_lut_rep_15_4_lut: lut40054 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1_4_lut_4_lut: lut40055 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); IS_FSM_i9: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); IS_FSM_i8: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40056 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40056 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; end lut40056; architecture Structure of lut40056 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0004") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_77 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_77 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_77"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; end SLICE_77; architecture Structure of SLICE_77 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40011 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i3_4_lut_adj_18: lut40056 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1994_3_lut: lut40011 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); IS_FSM_i13: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i12: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40057 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40057 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; end lut40057; architecture Structure of lut40057 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0101") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_78 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_78 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_78"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; end SLICE_78; architecture Structure of SLICE_78 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40039 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40057 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i5_3_lut_rep_21_4_lut: lut40039 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i2065_2_lut_3_lut: lut40057 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowA_i7: vmuxregsre0003 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RowA_i6: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40058 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40058 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; end lut40058; architecture Structure of lut40058 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40059 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40059 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; end lut40059; architecture Structure of lut40059 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0400") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_79 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_79 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_79"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; end SLICE_79; architecture Structure of SLICE_79 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal M0_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40058 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40059 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_rep_25_3_lut: lut40058 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_4_lut: lut40059 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); PHI2r2_377: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CASr_382: vmuxregsre port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); M0_INVERTERIN: inverter port map (I=>M0_dly, Z=>M0_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40060 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40060 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; end lut40060; architecture Structure of lut40060 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xFFFD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_80 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_80 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_80"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; end SLICE_80; architecture Structure of SLICE_80 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40060 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_adj_16: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1_2_lut_3_lut_4_lut_4_lut: lut40060 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); IS_FSM_i15: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i14: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40061 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40061 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; end lut40061; architecture Structure of lut40061 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x8888") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40062 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40062 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; end lut40062; architecture Structure of lut40062 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xBFFF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_81 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_81 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_81"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; end SLICE_81; architecture Structure of SLICE_81 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40061 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40062 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1982_2_lut: lut40061 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i12_4_lut: lut40062 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CmdUFMCS_412: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); CmdUFMCLK_413: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40063 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40063 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; end lut40063; architecture Structure of lut40063 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0302") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_82 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_82 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_82"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; end SLICE_82; architecture Structure of SLICE_82 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40063 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2052_4_lut: lut40063 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1990_2_lut_rep_17: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); IS_FSM_i11: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i10: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_83 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_83 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_83"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; end SLICE_83; architecture Structure of SLICE_83 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal M0_NOTIN: Std_logic; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40026 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_4_lut: lut40008 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i4_4_lut: lut40026 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RASr_379: vmuxregsre port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); M0_INVERTERIN: inverter port map (I=>M0_dly, Z=>M0_NOTIN); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_84 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_84 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_84"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; end SLICE_84; architecture Structure of SLICE_84 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_4_lut_adj_11: lut40056 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1_2_lut_3_lut_adj_5: lut40014 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); IS_FSM_i3: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i2: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_85 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_85 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_85"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; end SLICE_85; architecture Structure of SLICE_85 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40013 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut_4_lut_adj_15: lut40013 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i2004_2_lut_rep_30: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); RBA_i2: vmuxregsre0003 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RBA_i1: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40064 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40064 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; end lut40064; architecture Structure of lut40064 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x1010") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_86 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_86 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_86"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; end SLICE_86; architecture Structure of SLICE_86 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40009 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_3_lut_adj_10: lut40009 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1_2_lut_rep_20_3_lut: lut40064 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); IS_FSM_i7: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i6: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40065 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40065 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; end lut40065; architecture Structure of lut40065 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xCAC0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_87 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_87 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_87"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; end SLICE_87; architecture Structure of SLICE_87 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40040 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40065 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_2_lut: lut40040 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i17_4_lut: lut40065 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); IS_FSM_i1: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_FSM_i0: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40066 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40066 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; end lut40066; architecture Structure of lut40066 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0062") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_88 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_88 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_88"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; end SLICE_88; architecture Structure of SLICE_88 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40009 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40066 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin n2452_bdd_2_lut_rep_18_3_lut: lut40009 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); FS_6_bdd_4_lut: lut40066 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); Bank_i1: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); Bank_i0: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_89 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_89 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_89"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; end SLICE_89; architecture Structure of SLICE_89 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_rep_16_3_lut: lut40064 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_3_lut_adj_1: lut40014 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); WRD_i1: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); WRD_i0: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_90 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_90 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_90"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; end SLICE_90; architecture Structure of SLICE_90 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0006 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40039 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2032_2_lut_3_lut_4_lut: lut40039 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i2_2_lut_rep_27: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowA_i9: vmuxregsre0006 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RowA_i8: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40067 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40067 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; end lut40067; architecture Structure of lut40067 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x8C00") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_91 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_91 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_91"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; end SLICE_91; architecture Structure of SLICE_91 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40061 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40067 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_rep_33: lut40061 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_4_lut_adj_3: lut40067 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); PHI2r_376: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); PHI2r3_378: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40068 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40068 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; end lut40068; architecture Structure of lut40068 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x2222") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40069 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40069 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; end lut40069; architecture Structure of lut40069 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x4040") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_92 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_92 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_92"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; end SLICE_92; architecture Structure of SLICE_92 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40068 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40069 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_rep_32: lut40068 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_3_lut_rep_31: lut40069 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); WRD_i7: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); WRD_i6: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40070 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40070 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; end lut40070; architecture Structure of lut40070 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x7777") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_93 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_93 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_93"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; end SLICE_93; architecture Structure of SLICE_93 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40019 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40070 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2060_2_lut: lut40070 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i1512_2_lut: lut40019 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); CmdUFMSDI_414: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_94 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_94 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_94"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; end SLICE_94; architecture Structure of SLICE_94 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40042 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1976_2_lut: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i5_4_lut: lut40042 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40071 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40071 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; end lut40071; architecture Structure of lut40071 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x0001") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_95 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_95 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_95"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; end SLICE_95; architecture Structure of SLICE_95 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0006 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40061 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40071 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_adj_22: lut40061 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2055_3_lut_4_lut: lut40071 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RowA_i5: vmuxregsre0006 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RowA_i4: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_96 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_96 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_96"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; end SLICE_96; architecture Structure of SLICE_96 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40042 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i4_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2020_4_lut: lut40042 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RowA_i3: vmuxregsre0003 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RowA_i2: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_97 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_97 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_97"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; end SLICE_97; architecture Structure of SLICE_97 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component vmuxregsre0003 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40042 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i5_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2018_4_lut: lut40042 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RowA_i1: vmuxregsre0003 port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); RowA_i0: vmuxregsre0003 port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>LSR_NOTIN, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_negedge, SetupLow => tsetup_LSR_CLK_noedge_negedge, HoldHigh => thold_LSR_CLK_noedge_negedge, HoldLow => thold_LSR_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_98 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_98 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_98"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; end SLICE_98; architecture Structure of SLICE_98 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal M1_NOTIN: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal M0_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i1_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); MAin_9_I_0_427_i9_3_lut: lut40018 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); FWEr_389: vmuxregsre port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); M1_INVERTERIN: inverter port map (I=>M1_dly, Z=>M1_NOTIN); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); CBR_390: vmuxregsre port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); M0_INVERTERIN: inverter port map (I=>M0_dly, Z=>M0_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_99 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_99 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_99"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; end SLICE_99; architecture Structure of SLICE_99 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i2_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); MAin_9_I_0_427_i8_3_lut: lut40018 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); Bank_i7: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); Bank_i6: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40072 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40072 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; end lut40072; architecture Structure of lut40072 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xF0F7") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40073 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40073 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; end lut40073; architecture Structure of lut40073 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x08FF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_100 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_100 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_100"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; end SLICE_100; architecture Structure of SLICE_100 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40072 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40073 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i2_2_lut_3_lut_4_lut: lut40072 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); i1_2_lut_4_lut_adj_7: lut40073 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); IS_FSM_i5: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); IS_FSM_i4: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_101 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_101 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_101"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; end SLICE_101; architecture Structure of SLICE_101 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i3_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); MAin_9_I_0_427_i7_3_lut: lut40018 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); Bank_i5: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); Bank_i4: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_102 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_102 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_102"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; end SLICE_102; architecture Structure of SLICE_102 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1_2_lut_adj_26: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); InitReady_bdd_3_lut: lut40014 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); Bank_i3: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); Bank_i2: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_103 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_103 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_103"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; end SLICE_103; architecture Structure of SLICE_103 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin MAin_9_I_0_427_i6_3_lut: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_3_lut_adj_14: lut40014 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); WRD_i3: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); WRD_i2: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40074 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40074 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; end lut40074; architecture Structure of lut40074 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0xF0DD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_104 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_104 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_104"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; end SLICE_104; architecture Structure of SLICE_104 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40074 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin n2414_bdd_2_lut: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); n1_bdd_4_lut: lut40074 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40075 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity lut40075 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; end lut40075; architecture Structure of lut40075 is component ROM16X1 generic (initval: String); port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; AD3: in Std_logic; DO0: out Std_logic); end component; begin INST10: ROM16X1 generic map (initval => "0x2020") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_105 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity SLICE_105 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_105"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; end SLICE_105; architecture Structure of SLICE_105 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40075 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin i1513_2_lut: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); i2_3_lut_adj_20: lut40075 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); WRD_i5: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); WRD_i4: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_negedge, SetupLow => tsetup_M1_CLK_noedge_negedge, HoldHigh => thold_M1_CLK_noedge_negedge, HoldLow => thold_M1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mjiobuf library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity mjiobuf is port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE; end mjiobuf; architecture Structure of mjiobuf is component IBPU port (I: in Std_logic; O: out Std_logic); end component; component OBZPU port (I: in Std_logic; T: in Std_logic; O: out Std_logic); end component; begin INST1: IBPU port map (I=>PADI, O=>Z); INST2: OBZPU port map (I=>I, T=>T, O=>PAD); end Structure; -- entity RD_7_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_7_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD7 : VitalDelayType := 0 ns; tpw_RD7_posedge : VitalDelayType := 0 ns; tpw_RD7_negedge : VitalDelayType := 0 ns; tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD7: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; end RD_7_B; architecture Structure of RD_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD7_ipd : std_logic := 'X'; signal RD7_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_7_713: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, PADI=>RD7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD7_ipd, RD7, tipd_RD7); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD7_zd : std_logic := 'X'; VARIABLE RD7_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD7_RD7 : x01 := '0'; VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD7_ipd, TestSignalName => "RD7", Period => tperiod_RD7, PulseWidthHigh => tpw_RD7_posedge, PulseWidthLow => tpw_RD7_negedge, PeriodData => periodcheckinfo_RD7, Violation => tviol_RD7_RD7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD7_zd := RD7_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD7_ipd'last_event, PathDelay => tpd_RD7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD7, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD7, PathCondition => TRUE)), GlitchData => RD7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_6_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_6_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD6 : VitalDelayType := 0 ns; tpw_RD6_posedge : VitalDelayType := 0 ns; tpw_RD6_negedge : VitalDelayType := 0 ns; tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD6: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; end RD_6_B; architecture Structure of RD_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD6_ipd : std_logic := 'X'; signal RD6_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_6_714: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, PADI=>RD6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD6_ipd, RD6, tipd_RD6); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD6_zd : std_logic := 'X'; VARIABLE RD6_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD6_RD6 : x01 := '0'; VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD6_ipd, TestSignalName => "RD6", Period => tperiod_RD6, PulseWidthHigh => tpw_RD6_posedge, PulseWidthLow => tpw_RD6_negedge, PeriodData => periodcheckinfo_RD6, Violation => tviol_RD6_RD6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD6_zd := RD6_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD6_ipd'last_event, PathDelay => tpd_RD6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD6, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD6, PathCondition => TRUE)), GlitchData => RD6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_5_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_5_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD5 : VitalDelayType := 0 ns; tpw_RD5_posedge : VitalDelayType := 0 ns; tpw_RD5_negedge : VitalDelayType := 0 ns; tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD5: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; end RD_5_B; architecture Structure of RD_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD5_ipd : std_logic := 'X'; signal RD5_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_5_715: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, PADI=>RD5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD5_ipd, RD5, tipd_RD5); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD5_zd : std_logic := 'X'; VARIABLE RD5_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD5_RD5 : x01 := '0'; VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD5_ipd, TestSignalName => "RD5", Period => tperiod_RD5, PulseWidthHigh => tpw_RD5_posedge, PulseWidthLow => tpw_RD5_negedge, PeriodData => periodcheckinfo_RD5, Violation => tviol_RD5_RD5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD5_zd := RD5_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD5_ipd'last_event, PathDelay => tpd_RD5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD5, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD5, PathCondition => TRUE)), GlitchData => RD5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_4_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_4_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD4 : VitalDelayType := 0 ns; tpw_RD4_posedge : VitalDelayType := 0 ns; tpw_RD4_negedge : VitalDelayType := 0 ns; tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD4: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; end RD_4_B; architecture Structure of RD_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD4_ipd : std_logic := 'X'; signal RD4_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_4_716: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, PADI=>RD4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD4_ipd, RD4, tipd_RD4); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD4_zd : std_logic := 'X'; VARIABLE RD4_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD4_RD4 : x01 := '0'; VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD4_ipd, TestSignalName => "RD4", Period => tperiod_RD4, PulseWidthHigh => tpw_RD4_posedge, PulseWidthLow => tpw_RD4_negedge, PeriodData => periodcheckinfo_RD4, Violation => tviol_RD4_RD4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD4_zd := RD4_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD4_ipd'last_event, PathDelay => tpd_RD4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD4, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD4, PathCondition => TRUE)), GlitchData => RD4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_3_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_3_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD3 : VitalDelayType := 0 ns; tpw_RD3_posedge : VitalDelayType := 0 ns; tpw_RD3_negedge : VitalDelayType := 0 ns; tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD3: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; end RD_3_B; architecture Structure of RD_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD3_ipd : std_logic := 'X'; signal RD3_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_3_717: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, PADI=>RD3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD3_ipd, RD3, tipd_RD3); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD3_zd : std_logic := 'X'; VARIABLE RD3_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD3_RD3 : x01 := '0'; VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD3_ipd, TestSignalName => "RD3", Period => tperiod_RD3, PulseWidthHigh => tpw_RD3_posedge, PulseWidthLow => tpw_RD3_negedge, PeriodData => periodcheckinfo_RD3, Violation => tviol_RD3_RD3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD3_zd := RD3_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD3_ipd'last_event, PathDelay => tpd_RD3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD3, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD3, PathCondition => TRUE)), GlitchData => RD3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_2_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_2_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD2 : VitalDelayType := 0 ns; tpw_RD2_posedge : VitalDelayType := 0 ns; tpw_RD2_negedge : VitalDelayType := 0 ns; tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD2: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; end RD_2_B; architecture Structure of RD_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD2_ipd : std_logic := 'X'; signal RD2_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_2_718: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, PADI=>RD2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD2_ipd, RD2, tipd_RD2); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD2_zd : std_logic := 'X'; VARIABLE RD2_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD2_RD2 : x01 := '0'; VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD2_ipd, TestSignalName => "RD2", Period => tperiod_RD2, PulseWidthHigh => tpw_RD2_posedge, PulseWidthLow => tpw_RD2_negedge, PeriodData => periodcheckinfo_RD2, Violation => tviol_RD2_RD2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD2_zd := RD2_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD2_ipd'last_event, PathDelay => tpd_RD2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD2, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD2, PathCondition => TRUE)), GlitchData => RD2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_1_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD1 : VitalDelayType := 0 ns; tpw_RD1_posedge : VitalDelayType := 0 ns; tpw_RD1_negedge : VitalDelayType := 0 ns; tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD1: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; end RD_1_B; architecture Structure of RD_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD1_ipd : std_logic := 'X'; signal RD1_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_1_719: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, PADI=>RD1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD1_ipd, RD1, tipd_RD1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD1_zd : std_logic := 'X'; VARIABLE RD1_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD1_RD1 : x01 := '0'; VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD1_ipd, TestSignalName => "RD1", Period => tperiod_RD1, PulseWidthHigh => tpw_RD1_posedge, PulseWidthLow => tpw_RD1_negedge, PeriodData => periodcheckinfo_RD1, Violation => tviol_RD1_RD1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD1_zd := RD1_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD1_ipd'last_event, PathDelay => tpd_RD1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD1, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD1, PathCondition => TRUE)), GlitchData => RD1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RD_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_0_B"; tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RD0 : VitalDelayType := 0 ns; tpw_RD0_posedge : VitalDelayType := 0 ns; tpw_RD0_negedge : VitalDelayType := 0 ns; tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD0: inout Std_logic); ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; end RD_0_B; architecture Structure of RD_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal PADDO_ipd : std_logic := 'X'; signal RD0_ipd : std_logic := 'X'; signal RD0_out : std_logic := 'Z'; component mjiobuf port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; PAD: out Std_logic; PADI: in Std_logic); end component; begin Dout_pad_0_720: mjiobuf port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, PADI=>RD0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); VitalWireDelay(RD0_ipd, RD0, tipd_RD0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE RD0_zd : std_logic := 'X'; VARIABLE RD0_GlitchData : VitalGlitchDataType; VARIABLE tviol_RD0_RD0 : x01 := '0'; VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RD0_ipd, TestSignalName => "RD0", Period => tperiod_RD0, PulseWidthHigh => tpw_RD0_posedge, PulseWidthLow => tpw_RD0_negedge, PeriodData => periodcheckinfo_RD0, Violation => tviol_RD0_RD0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; RD0_zd := RD0_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RD0_ipd'last_event, PathDelay => tpd_RD0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01Z ( OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD0, PathCondition => TRUE), 1 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RD0, PathCondition => TRUE)), GlitchData => RD0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mjiobuf0076 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity mjiobuf0076 is port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); ATTRIBUTE Vital_Level0 OF mjiobuf0076 : ENTITY IS TRUE; end mjiobuf0076; architecture Structure of mjiobuf0076 is component OBZPU port (I: in Std_logic; T: in Std_logic; O: out Std_logic); end component; begin INST5: OBZPU port map (I=>I, T=>T, O=>PAD); end Structure; -- entity Dout_7_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_7_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout7: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; end Dout_7_B; architecture Structure of Dout_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout7_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_7: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) VARIABLE Dout7_zd : std_logic := 'X'; VARIABLE Dout7_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout7_zd := Dout7_out; VitalPathDelay01Z ( OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout7, PathCondition => TRUE)), GlitchData => Dout7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_6_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_6_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout6: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; end Dout_6_B; architecture Structure of Dout_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout6_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_6: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) VARIABLE Dout6_zd : std_logic := 'X'; VARIABLE Dout6_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout6_zd := Dout6_out; VitalPathDelay01Z ( OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout6, PathCondition => TRUE)), GlitchData => Dout6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_5_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_5_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout5: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; end Dout_5_B; architecture Structure of Dout_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout5_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_5: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) VARIABLE Dout5_zd : std_logic := 'X'; VARIABLE Dout5_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout5_zd := Dout5_out; VitalPathDelay01Z ( OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout5, PathCondition => TRUE)), GlitchData => Dout5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_4_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_4_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout4: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; end Dout_4_B; architecture Structure of Dout_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout4_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_4: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) VARIABLE Dout4_zd : std_logic := 'X'; VARIABLE Dout4_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout4_zd := Dout4_out; VitalPathDelay01Z ( OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout4, PathCondition => TRUE)), GlitchData => Dout4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_3_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_3_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout3: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; end Dout_3_B; architecture Structure of Dout_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout3_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_3: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) VARIABLE Dout3_zd : std_logic := 'X'; VARIABLE Dout3_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout3_zd := Dout3_out; VitalPathDelay01Z ( OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout3, PathCondition => TRUE)), GlitchData => Dout3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_2_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_2_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout2: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; end Dout_2_B; architecture Structure of Dout_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout2_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_2: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) VARIABLE Dout2_zd : std_logic := 'X'; VARIABLE Dout2_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout2_zd := Dout2_out; VitalPathDelay01Z ( OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout2, PathCondition => TRUE)), GlitchData => Dout2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_1_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout1: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; end Dout_1_B; architecture Structure of Dout_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_1: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) VARIABLE Dout1_zd : std_logic := 'X'; VARIABLE Dout1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout1_zd := Dout1_out; VitalPathDelay01Z ( OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout1, PathCondition => TRUE)), GlitchData => Dout1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Dout_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_0_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; Dout0: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; end Dout_0_B; architecture Structure of Dout_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout0_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_0: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) VARIABLE Dout0_zd : std_logic := 'X'; VARIABLE Dout0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout0_zd := Dout0_out; VitalPathDelay01Z ( OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout0, PathCondition => TRUE)), GlitchData => Dout0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity LEDB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity LEDB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "LEDB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; LEDS: out Std_logic); ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; end LEDB; architecture Structure of LEDB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal LEDS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin LED_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) VARIABLE LEDS_zd : std_logic := 'X'; VARIABLE LEDS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; LEDS_zd := LEDS_out; VitalPathDelay01Z ( OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_LEDS, PathCondition => TRUE)), GlitchData => LEDS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RBA_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_1_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RBA1: out Std_logic); ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; end RBA_1_B; architecture Structure of RBA_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RBA1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RBA_pad_1: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) VARIABLE RBA1_zd : std_logic := 'X'; VARIABLE RBA1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RBA1_zd := RBA1_out; VitalPathDelay01Z ( OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RBA1, PathCondition => TRUE)), GlitchData => RBA1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RBA_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_0_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RBA0: out Std_logic); ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; end RBA_0_B; architecture Structure of RBA_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RBA0_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RBA_pad_0: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) VARIABLE RBA0_zd : std_logic := 'X'; VARIABLE RBA0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RBA0_zd := RBA0_out; VitalPathDelay01Z ( OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RBA0, PathCondition => TRUE)), GlitchData => RBA0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_11_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_11_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_11_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RA11: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; end RA_11_B; architecture Structure of RA_11_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA11_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_11: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA11_out) VARIABLE RA11_zd : std_logic := 'X'; VARIABLE RA11_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA11_zd := RA11_out; VitalPathDelay01Z ( OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA11, PathCondition => TRUE)), GlitchData => RA11_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_10_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_10_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_10_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RA10: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; end RA_10_B; architecture Structure of RA_10_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA10_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_10: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA10_out) VARIABLE RA10_zd : std_logic := 'X'; VARIABLE RA10_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA10_zd := RA10_out; VitalPathDelay01Z ( OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA10, PathCondition => TRUE)), GlitchData => RA10_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_9_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_9_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_9_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA9: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; end RA_9_B; architecture Structure of RA_9_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA9_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_9: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA9_out) VARIABLE RA9_zd : std_logic := 'X'; VARIABLE RA9_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA9_zd := RA9_out; VitalPathDelay01Z ( OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA9, PathCondition => TRUE)), GlitchData => RA9_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_8_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_8_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_8_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA8: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; end RA_8_B; architecture Structure of RA_8_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA8_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_8: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA8_out) VARIABLE RA8_zd : std_logic := 'X'; VARIABLE RA8_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA8_zd := RA8_out; VitalPathDelay01Z ( OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA8, PathCondition => TRUE)), GlitchData => RA8_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_7_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_7_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA7: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; end RA_7_B; architecture Structure of RA_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA7_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_7: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA7_out) VARIABLE RA7_zd : std_logic := 'X'; VARIABLE RA7_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA7_zd := RA7_out; VitalPathDelay01Z ( OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA7, PathCondition => TRUE)), GlitchData => RA7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_6_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_6_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA6: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; end RA_6_B; architecture Structure of RA_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA6_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_6: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA6_out) VARIABLE RA6_zd : std_logic := 'X'; VARIABLE RA6_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA6_zd := RA6_out; VitalPathDelay01Z ( OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA6, PathCondition => TRUE)), GlitchData => RA6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_5_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_5_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA5: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; end RA_5_B; architecture Structure of RA_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA5_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_5: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA5_out) VARIABLE RA5_zd : std_logic := 'X'; VARIABLE RA5_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA5_zd := RA5_out; VitalPathDelay01Z ( OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA5, PathCondition => TRUE)), GlitchData => RA5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_4_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_4_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA4: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; end RA_4_B; architecture Structure of RA_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA4_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_4: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA4_out) VARIABLE RA4_zd : std_logic := 'X'; VARIABLE RA4_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA4_zd := RA4_out; VitalPathDelay01Z ( OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA4, PathCondition => TRUE)), GlitchData => RA4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_3_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_3_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA3: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; end RA_3_B; architecture Structure of RA_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA3_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_3: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA3_out) VARIABLE RA3_zd : std_logic := 'X'; VARIABLE RA3_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA3_zd := RA3_out; VitalPathDelay01Z ( OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA3, PathCondition => TRUE)), GlitchData => RA3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_2_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_2_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA2: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; end RA_2_B; architecture Structure of RA_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA2_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_2: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA2_out) VARIABLE RA2_zd : std_logic := 'X'; VARIABLE RA2_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA2_zd := RA2_out; VitalPathDelay01Z ( OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA2, PathCondition => TRUE)), GlitchData => RA2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_1_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA1: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; end RA_1_B; architecture Structure of RA_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_1: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA1_out) VARIABLE RA1_zd : std_logic := 'X'; VARIABLE RA1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA1_zd := RA1_out; VitalPathDelay01Z ( OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA1, PathCondition => TRUE)), GlitchData => RA1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RA_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_0_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (PADDO: in Std_logic; RA0: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; end RA_0_B; architecture Structure of RA_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA0_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_0: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA0_out) VARIABLE RA0_zd : std_logic := 'X'; VARIABLE RA0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA0_zd := RA0_out; VitalPathDelay01Z ( OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA0, PathCondition => TRUE)), GlitchData => RA0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCSB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nRCSB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCSB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; nRCSS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; end nRCSB; architecture Structure of nRCSB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal nRCSS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin nRCS_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) VARIABLE nRCSS_zd : std_logic := 'X'; VARIABLE nRCSS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRCSS_zd := nRCSS_out; VitalPathDelay01Z ( OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_nRCSS, PathCondition => TRUE)), GlitchData => nRCSS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RCKEB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RCKEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCKEB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RCKES: out Std_logic); ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; end RCKEB; architecture Structure of RCKEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RCKES_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RCKE_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) VARIABLE RCKES_zd : std_logic := 'X'; VARIABLE RCKES_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RCKES_zd := RCKES_out; VitalPathDelay01Z ( OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RCKES, PathCondition => TRUE)), GlitchData => RCKES_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRWEB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nRWEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRWEB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; nRWES: out Std_logic); ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; end nRWEB; architecture Structure of nRWEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal nRWES_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin nRWE_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) VARIABLE nRWES_zd : std_logic := 'X'; VARIABLE nRWES_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRWES_zd := nRWES_out; VitalPathDelay01Z ( OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_nRWES, PathCondition => TRUE)), GlitchData => nRWES_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRRASB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nRRASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRRASB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; nRRASS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; end nRRASB; architecture Structure of nRRASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal nRRASS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin nRRAS_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) VARIABLE nRRASS_zd : std_logic := 'X'; VARIABLE nRRASS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRRASS_zd := nRRASS_out; VitalPathDelay01Z ( OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_nRRASS, PathCondition => TRUE)), GlitchData => nRRASS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCASB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nRCASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCASB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; nRCASS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; end nRCASB; architecture Structure of nRCASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal nRCASS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin nRCAS_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) VARIABLE nRCASS_zd : std_logic := 'X'; VARIABLE nRCASS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRCASS_zd := nRCASS_out; VitalPathDelay01Z ( OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_nRCASS, PathCondition => TRUE)), GlitchData => nRCASS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RDQMHB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RDQMHB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RDQMHB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RDQMHS: out Std_logic); ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; end RDQMHB; architecture Structure of RDQMHB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RDQMHS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RDQMH_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) VARIABLE RDQMHS_zd : std_logic := 'X'; VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RDQMHS_zd := RDQMHS_out; VitalPathDelay01Z ( OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RDQMHS, PathCondition => TRUE)), GlitchData => RDQMHS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RDQMLB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RDQMLB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RDQMLB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; RDQMLS: out Std_logic); ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; end RDQMLB; architecture Structure of RDQMLB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RDQMLS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RDQML_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) VARIABLE RDQMLS_zd : std_logic := 'X'; VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RDQMLS_zd := RDQMLS_out; VitalPathDelay01Z ( OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RDQMLS, PathCondition => TRUE)), GlitchData => RDQMLS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nUFMCSB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nUFMCSB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nUFMCSB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; nUFMCSS: out Std_logic); ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; end nUFMCSB; architecture Structure of nUFMCSB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal nUFMCSS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin nUFMCS_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) VARIABLE nUFMCSS_zd : std_logic := 'X'; VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nUFMCSS_zd := nUFMCSS_out; VitalPathDelay01Z ( OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_nUFMCSS, PathCondition => TRUE)), GlitchData => nUFMCSS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMCLKB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity UFMCLKB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMCLKB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; UFMCLKS: out Std_logic); ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; end UFMCLKB; architecture Structure of UFMCLKB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal UFMCLKS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin UFMCLK_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) VARIABLE UFMCLKS_zd : std_logic := 'X'; VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; UFMCLKS_zd := UFMCLKS_out; VitalPathDelay01Z ( OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_UFMCLKS, PathCondition => TRUE)), GlitchData => UFMCLKS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMSDIB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity UFMSDIB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMSDIB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) ); port (PADDO: in Std_logic; UFMSDIS: out Std_logic); ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; end UFMSDIB; architecture Structure of UFMSDIB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal UFMSDIS_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mjiobuf0076 port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin UFMSDI_pad: mjiobuf0076 port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) VARIABLE UFMSDIS_zd : std_logic := 'X'; VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; UFMSDIS_zd := UFMSDIS_out; VitalPathDelay01Z ( OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_UFMSDIS, PathCondition => TRUE)), GlitchData => UFMSDIS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mjiobuf0077 library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity mjiobuf0077 is port (Z: out Std_logic; PAD: in Std_logic); ATTRIBUTE Vital_Level0 OF mjiobuf0077 : ENTITY IS TRUE; end mjiobuf0077; architecture Structure of mjiobuf0077 is component IBPU port (I: in Std_logic; O: out Std_logic); end component; begin INST1: IBPU port map (I=>PAD, O=>Z); end Structure; -- entity PHI2B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity PHI2B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "PHI2B"; tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_PHI2S : VitalDelayType := 0 ns; tpw_PHI2S_posedge : VitalDelayType := 0 ns; tpw_PHI2S_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; PHI2S: in Std_logic); ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; end PHI2B; architecture Structure of PHI2B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PHI2S_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin PHI2_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>PHI2S_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => PHI2S_ipd, TestSignalName => "PHI2S", Period => tperiod_PHI2S, PulseWidthHigh => tpw_PHI2S_posedge, PulseWidthLow => tpw_PHI2S_negedge, PeriodData => periodcheckinfo_PHI2S, Violation => tviol_PHI2S_PHI2S, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, PathDelay => tpd_PHI2S_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_9_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_9_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_9_B"; tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin9 : VitalDelayType := 0 ns; tpw_MAin9_posedge : VitalDelayType := 0 ns; tpw_MAin9_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin9: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; end MAin_9_B; architecture Structure of MAin_9_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin9_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_9: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin9_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin9_MAin9 : x01 := '0'; VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin9_ipd, TestSignalName => "MAin9", Period => tperiod_MAin9, PulseWidthHigh => tpw_MAin9_posedge, PulseWidthLow => tpw_MAin9_negedge, PeriodData => periodcheckinfo_MAin9, Violation => tviol_MAin9_MAin9, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, PathDelay => tpd_MAin9_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_8_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_8_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_8_B"; tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin8 : VitalDelayType := 0 ns; tpw_MAin8_posedge : VitalDelayType := 0 ns; tpw_MAin8_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin8: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; end MAin_8_B; architecture Structure of MAin_8_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin8_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_8: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin8_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin8_MAin8 : x01 := '0'; VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin8_ipd, TestSignalName => "MAin8", Period => tperiod_MAin8, PulseWidthHigh => tpw_MAin8_posedge, PulseWidthLow => tpw_MAin8_negedge, PeriodData => periodcheckinfo_MAin8, Violation => tviol_MAin8_MAin8, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, PathDelay => tpd_MAin8_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_7_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_7_B"; tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin7 : VitalDelayType := 0 ns; tpw_MAin7_posedge : VitalDelayType := 0 ns; tpw_MAin7_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin7: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; end MAin_7_B; architecture Structure of MAin_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin7_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_7: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin7_MAin7 : x01 := '0'; VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin7_ipd, TestSignalName => "MAin7", Period => tperiod_MAin7, PulseWidthHigh => tpw_MAin7_posedge, PulseWidthLow => tpw_MAin7_negedge, PeriodData => periodcheckinfo_MAin7, Violation => tviol_MAin7_MAin7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, PathDelay => tpd_MAin7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_6_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_6_B"; tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin6 : VitalDelayType := 0 ns; tpw_MAin6_posedge : VitalDelayType := 0 ns; tpw_MAin6_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin6: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; end MAin_6_B; architecture Structure of MAin_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin6_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_6: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin6_MAin6 : x01 := '0'; VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin6_ipd, TestSignalName => "MAin6", Period => tperiod_MAin6, PulseWidthHigh => tpw_MAin6_posedge, PulseWidthLow => tpw_MAin6_negedge, PeriodData => periodcheckinfo_MAin6, Violation => tviol_MAin6_MAin6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, PathDelay => tpd_MAin6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_5_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_5_B"; tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin5 : VitalDelayType := 0 ns; tpw_MAin5_posedge : VitalDelayType := 0 ns; tpw_MAin5_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin5: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; end MAin_5_B; architecture Structure of MAin_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin5_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_5: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin5_MAin5 : x01 := '0'; VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin5_ipd, TestSignalName => "MAin5", Period => tperiod_MAin5, PulseWidthHigh => tpw_MAin5_posedge, PulseWidthLow => tpw_MAin5_negedge, PeriodData => periodcheckinfo_MAin5, Violation => tviol_MAin5_MAin5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, PathDelay => tpd_MAin5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_4_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_4_B"; tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin4 : VitalDelayType := 0 ns; tpw_MAin4_posedge : VitalDelayType := 0 ns; tpw_MAin4_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin4: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; end MAin_4_B; architecture Structure of MAin_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin4_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_4: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin4_MAin4 : x01 := '0'; VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin4_ipd, TestSignalName => "MAin4", Period => tperiod_MAin4, PulseWidthHigh => tpw_MAin4_posedge, PulseWidthLow => tpw_MAin4_negedge, PeriodData => periodcheckinfo_MAin4, Violation => tviol_MAin4_MAin4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, PathDelay => tpd_MAin4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_3_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_3_B"; tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin3 : VitalDelayType := 0 ns; tpw_MAin3_posedge : VitalDelayType := 0 ns; tpw_MAin3_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin3: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; end MAin_3_B; architecture Structure of MAin_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin3_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_3: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin3_MAin3 : x01 := '0'; VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin3_ipd, TestSignalName => "MAin3", Period => tperiod_MAin3, PulseWidthHigh => tpw_MAin3_posedge, PulseWidthLow => tpw_MAin3_negedge, PeriodData => periodcheckinfo_MAin3, Violation => tviol_MAin3_MAin3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, PathDelay => tpd_MAin3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_2_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_2_B"; tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin2 : VitalDelayType := 0 ns; tpw_MAin2_posedge : VitalDelayType := 0 ns; tpw_MAin2_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin2: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; end MAin_2_B; architecture Structure of MAin_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin2_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_2: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin2_MAin2 : x01 := '0'; VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin2_ipd, TestSignalName => "MAin2", Period => tperiod_MAin2, PulseWidthHigh => tpw_MAin2_posedge, PulseWidthLow => tpw_MAin2_negedge, PeriodData => periodcheckinfo_MAin2, Violation => tviol_MAin2_MAin2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, PathDelay => tpd_MAin2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_1_B"; tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin1 : VitalDelayType := 0 ns; tpw_MAin1_posedge : VitalDelayType := 0 ns; tpw_MAin1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin1: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; end MAin_1_B; architecture Structure of MAin_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin1_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_1: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin1_MAin1 : x01 := '0'; VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin1_ipd, TestSignalName => "MAin1", Period => tperiod_MAin1, PulseWidthHigh => tpw_MAin1_posedge, PulseWidthLow => tpw_MAin1_negedge, PeriodData => periodcheckinfo_MAin1, Violation => tviol_MAin1_MAin1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, PathDelay => tpd_MAin1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity MAin_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_0_B"; tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin0 : VitalDelayType := 0 ns; tpw_MAin0_posedge : VitalDelayType := 0 ns; tpw_MAin0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin0: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; end MAin_0_B; architecture Structure of MAin_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin0_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_0: mjiobuf0077 port map (Z=>PADDI_out, PAD=>MAin0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin0_MAin0 : x01 := '0'; VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin0_ipd, TestSignalName => "MAin0", Period => tperiod_MAin0, PulseWidthHigh => tpw_MAin0_posedge, PulseWidthLow => tpw_MAin0_negedge, PeriodData => periodcheckinfo_MAin0, Violation => tviol_MAin0_MAin0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, PathDelay => tpd_MAin0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity CROW_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity CROW_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "CROW_1_B"; tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_CROW1 : VitalDelayType := 0 ns; tpw_CROW1_posedge : VitalDelayType := 0 ns; tpw_CROW1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; CROW1: in Std_logic); ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; end CROW_1_B; architecture Structure of CROW_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal CROW1_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin CROW_pad_1: mjiobuf0077 port map (Z=>PADDI_out, PAD=>CROW1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_CROW1_CROW1 : x01 := '0'; VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => CROW1_ipd, TestSignalName => "CROW1", Period => tperiod_CROW1, PulseWidthHigh => tpw_CROW1_posedge, PulseWidthLow => tpw_CROW1_negedge, PeriodData => periodcheckinfo_CROW1, Violation => tviol_CROW1_CROW1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, PathDelay => tpd_CROW1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity CROW_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity CROW_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "CROW_0_B"; tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_CROW0 : VitalDelayType := 0 ns; tpw_CROW0_posedge : VitalDelayType := 0 ns; tpw_CROW0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; CROW0: in Std_logic); ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; end CROW_0_B; architecture Structure of CROW_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal CROW0_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin CROW_pad_0: mjiobuf0077 port map (Z=>PADDI_out, PAD=>CROW0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_CROW0_CROW0 : x01 := '0'; VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => CROW0_ipd, TestSignalName => "CROW0", Period => tperiod_CROW0, PulseWidthHigh => tpw_CROW0_posedge, PulseWidthLow => tpw_CROW0_negedge, PeriodData => periodcheckinfo_CROW0, Violation => tviol_CROW0_CROW0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, PathDelay => tpd_CROW0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_7_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_7_B"; tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din7 : VitalDelayType := 0 ns; tpw_Din7_posedge : VitalDelayType := 0 ns; tpw_Din7_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din7: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; end Din_7_B; architecture Structure of Din_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din7_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_7: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din7_ipd, Din7, tipd_Din7); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din7_Din7 : x01 := '0'; VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din7_ipd, TestSignalName => "Din7", Period => tperiod_Din7, PulseWidthHigh => tpw_Din7_posedge, PulseWidthLow => tpw_Din7_negedge, PeriodData => periodcheckinfo_Din7, Violation => tviol_Din7_Din7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din7_ipd'last_event, PathDelay => tpd_Din7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_6_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_6_B"; tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din6 : VitalDelayType := 0 ns; tpw_Din6_posedge : VitalDelayType := 0 ns; tpw_Din6_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din6: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; end Din_6_B; architecture Structure of Din_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din6_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_6: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din6_ipd, Din6, tipd_Din6); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din6_Din6 : x01 := '0'; VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din6_ipd, TestSignalName => "Din6", Period => tperiod_Din6, PulseWidthHigh => tpw_Din6_posedge, PulseWidthLow => tpw_Din6_negedge, PeriodData => periodcheckinfo_Din6, Violation => tviol_Din6_Din6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din6_ipd'last_event, PathDelay => tpd_Din6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_5_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_5_B"; tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din5 : VitalDelayType := 0 ns; tpw_Din5_posedge : VitalDelayType := 0 ns; tpw_Din5_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din5: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; end Din_5_B; architecture Structure of Din_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din5_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_5: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din5_ipd, Din5, tipd_Din5); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din5_Din5 : x01 := '0'; VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din5_ipd, TestSignalName => "Din5", Period => tperiod_Din5, PulseWidthHigh => tpw_Din5_posedge, PulseWidthLow => tpw_Din5_negedge, PeriodData => periodcheckinfo_Din5, Violation => tviol_Din5_Din5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din5_ipd'last_event, PathDelay => tpd_Din5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_4_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_4_B"; tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din4 : VitalDelayType := 0 ns; tpw_Din4_posedge : VitalDelayType := 0 ns; tpw_Din4_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din4: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; end Din_4_B; architecture Structure of Din_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din4_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_4: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din4_ipd, Din4, tipd_Din4); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din4_Din4 : x01 := '0'; VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din4_ipd, TestSignalName => "Din4", Period => tperiod_Din4, PulseWidthHigh => tpw_Din4_posedge, PulseWidthLow => tpw_Din4_negedge, PeriodData => periodcheckinfo_Din4, Violation => tviol_Din4_Din4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din4_ipd'last_event, PathDelay => tpd_Din4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_3_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_3_B"; tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din3 : VitalDelayType := 0 ns; tpw_Din3_posedge : VitalDelayType := 0 ns; tpw_Din3_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din3: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; end Din_3_B; architecture Structure of Din_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din3_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_3: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din3_ipd, Din3, tipd_Din3); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din3_Din3 : x01 := '0'; VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din3_ipd, TestSignalName => "Din3", Period => tperiod_Din3, PulseWidthHigh => tpw_Din3_posedge, PulseWidthLow => tpw_Din3_negedge, PeriodData => periodcheckinfo_Din3, Violation => tviol_Din3_Din3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din3_ipd'last_event, PathDelay => tpd_Din3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_2_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_2_B"; tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din2 : VitalDelayType := 0 ns; tpw_Din2_posedge : VitalDelayType := 0 ns; tpw_Din2_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din2: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; end Din_2_B; architecture Structure of Din_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din2_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_2: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din2_ipd, Din2, tipd_Din2); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din2_Din2 : x01 := '0'; VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din2_ipd, TestSignalName => "Din2", Period => tperiod_Din2, PulseWidthHigh => tpw_Din2_posedge, PulseWidthLow => tpw_Din2_negedge, PeriodData => periodcheckinfo_Din2, Violation => tviol_Din2_Din2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din2_ipd'last_event, PathDelay => tpd_Din2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_1_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_1_B"; tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din1 : VitalDelayType := 0 ns; tpw_Din1_posedge : VitalDelayType := 0 ns; tpw_Din1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din1: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; end Din_1_B; architecture Structure of Din_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din1_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_1: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din1_ipd, Din1, tipd_Din1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din1_Din1 : x01 := '0'; VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din1_ipd, TestSignalName => "Din1", Period => tperiod_Din1, PulseWidthHigh => tpw_Din1_posedge, PulseWidthLow => tpw_Din1_negedge, PeriodData => periodcheckinfo_Din1, Violation => tviol_Din1_Din1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din1_ipd'last_event, PathDelay => tpd_Din1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_0_B library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity Din_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_0_B"; tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din0 : VitalDelayType := 0 ns; tpw_Din0_posedge : VitalDelayType := 0 ns; tpw_Din0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din0: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; end Din_0_B; architecture Structure of Din_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din0_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_0: mjiobuf0077 port map (Z=>PADDI_out, PAD=>Din0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din0_ipd, Din0, tipd_Din0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din0_Din0 : x01 := '0'; VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din0_ipd, TestSignalName => "Din0", Period => tperiod_Din0, PulseWidthHigh => tpw_Din0_posedge, PulseWidthLow => tpw_Din0_negedge, PeriodData => periodcheckinfo_Din0, Violation => tviol_Din0_Din0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din0_ipd'last_event, PathDelay => tpd_Din0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nCCASB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nCCASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nCCASB"; tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nCCASS : VitalDelayType := 0 ns; tpw_nCCASS_posedge : VitalDelayType := 0 ns; tpw_nCCASS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nCCASS: in Std_logic); ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; end nCCASB; architecture Structure of nCCASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nCCASS_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nCCAS_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>nCCASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nCCASS_ipd, TestSignalName => "nCCASS", Period => tperiod_nCCASS, PulseWidthHigh => tpw_nCCASS_posedge, PulseWidthLow => tpw_nCCASS_negedge, PeriodData => periodcheckinfo_nCCASS, Violation => tviol_nCCASS_nCCASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, PathDelay => tpd_nCCASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nCRASB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nCRASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nCRASB"; tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nCRASS : VitalDelayType := 0 ns; tpw_nCRASS_posedge : VitalDelayType := 0 ns; tpw_nCRASS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nCRASS: in Std_logic); ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; end nCRASB; architecture Structure of nCRASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nCRASS_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nCRAS_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>nCRASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nCRASS_ipd, TestSignalName => "nCRASS", Period => tperiod_nCRASS, PulseWidthHigh => tpw_nCRASS_posedge, PulseWidthLow => tpw_nCRASS_negedge, PeriodData => periodcheckinfo_nCRASS, Violation => tviol_nCRASS_nCRASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, PathDelay => tpd_nCRASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nFWEB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity nFWEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nFWEB"; tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nFWES : VitalDelayType := 0 ns; tpw_nFWES_posedge : VitalDelayType := 0 ns; tpw_nFWES_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nFWES: in Std_logic); ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; end nFWEB; architecture Structure of nFWEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nFWES_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nFWE_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>nFWES_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nFWES_nFWES : x01 := '0'; VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nFWES_ipd, TestSignalName => "nFWES", Period => tperiod_nFWES, PulseWidthHigh => tpw_nFWES_posedge, PulseWidthLow => tpw_nFWES_negedge, PeriodData => periodcheckinfo_nFWES, Violation => tviol_nFWES_nFWES, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, PathDelay => tpd_nFWES_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RCLKB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RCLKB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCLKB"; tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RCLKS : VitalDelayType := 0 ns; tpw_RCLKS_posedge : VitalDelayType := 0 ns; tpw_RCLKS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; RCLKS: in Std_logic); ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; end RCLKB; architecture Structure of RCLKB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal RCLKS_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin RCLK_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>RCLKS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RCLKS_ipd, TestSignalName => "RCLKS", Period => tperiod_RCLKS, PulseWidthHigh => tpw_RCLKS_posedge, PulseWidthLow => tpw_RCLKS_negedge, PeriodData => periodcheckinfo_RCLKS, Violation => tviol_RCLKS_RCLKS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, PathDelay => tpd_RCLKS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMSDOB library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity UFMSDOB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMSDOB"; tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_UFMSDOS : VitalDelayType := 0 ns; tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; UFMSDOS: in Std_logic); ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; end UFMSDOB; architecture Structure of UFMSDOB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal UFMSDOS_ipd : std_logic := 'X'; component mjiobuf0077 port (Z: out Std_logic; PAD: in Std_logic); end component; begin UFMSDO_pad: mjiobuf0077 port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => UFMSDOS_ipd, TestSignalName => "UFMSDOS", Period => tperiod_UFMSDOS, PulseWidthHigh => tpw_UFMSDOS_posedge, PulseWidthLow => tpw_UFMSDOS_negedge, PeriodData => periodcheckinfo_UFMSDOS, Violation => tviol_UFMSDOS_UFMSDOS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, PathDelay => tpd_UFMSDOS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RAM2GS library IEEE, vital2000, MACHXO; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO.COMPONENTS.ALL; entity RAM2GS is port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); CROW: in Std_logic_vector (1 downto 0); Din: in Std_logic_vector (7 downto 0); Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; RBA: out Std_logic_vector (1 downto 0); RA: out Std_logic_vector (11 downto 0); RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; UFMSDI: out Std_logic; UFMSDO: in Std_logic); end RAM2GS; architecture Structure of RAM2GS is signal FS_7: Std_logic; signal FS_6: Std_logic; signal RCLK_c: Std_logic; signal n2010: Std_logic; signal n2011: Std_logic; signal FS_15: Std_logic; signal FS_14: Std_logic; signal n2014: Std_logic; signal n2015: Std_logic; signal FS_5: Std_logic; signal FS_4: Std_logic; signal n2009: Std_logic; signal FS_13: Std_logic; signal FS_12: Std_logic; signal n2013: Std_logic; signal FS_1: Std_logic; signal FS_0: Std_logic; signal n2008: Std_logic; signal FS_11: Std_logic; signal FS_10: Std_logic; signal n2012: Std_logic; signal FS_3: Std_logic; signal FS_2: Std_logic; signal FS_9: Std_logic; signal FS_8: Std_logic; signal FS_17: Std_logic; signal FS_16: Std_logic; signal MAin_c_1: Std_logic; signal n1326: Std_logic; signal MAin_c_0: Std_logic; signal n2263: Std_logic; signal ADSubmitted: Std_logic; signal n2242: Std_logic; signal n2459: Std_logic; signal n1413: Std_logic; signal C1Submitted_N_237: Std_logic; signal PHI2_c: Std_logic; signal Din_c_6: Std_logic; signal C1Submitted: Std_logic; signal nFWE_c: Std_logic; signal n6_adj_3: Std_logic; signal n2284: Std_logic; signal MAin_c_5: Std_logic; signal n2316: Std_logic; signal n26: Std_logic; signal MAin_c_2: Std_logic; signal n15: Std_logic; signal n2463: Std_logic; signal CmdEnable_N_248: Std_logic; signal PHI2_N_120_enable_7: Std_logic; signal CmdEnable: Std_logic; signal PHI2r2: Std_logic; signal CmdSubmitted: Std_logic; signal PHI2r3: Std_logic; signal n2568_001_BUF1: Std_logic; signal PHI2_N_120_enable_5: Std_logic; signal n2472: Std_logic; signal Din_c_5: Std_logic; signal Din_c_7: Std_logic; signal n1314: Std_logic; signal Din_c_4: Std_logic; signal n8MEGEN: Std_logic; signal Din_c_0: Std_logic; signal Cmdn8MEGEN_N_264: Std_logic; signal PHI2_N_120_enable_4: Std_logic; signal Cmdn8MEGEN: Std_logic; signal nRowColSel_N_35: Std_logic; signal RASr2: Std_logic; signal InitReady: Std_logic; signal Ready: Std_logic; signal n2568_000_BUF1: Std_logic; signal RCLK_c_enable_25: Std_logic; signal RCLK_c_enable_23: Std_logic; signal nCRAS_c: Std_logic; signal CBR: Std_logic; signal LEDEN: Std_logic; signal n2568: Std_logic; signal RCLK_c_enable_12: Std_logic; signal LED_N_84: Std_logic; signal nRowColSel_N_34: Std_logic; signal nRCAS_N_165: Std_logic; signal n2208: Std_logic; signal n2209: Std_logic; signal nRWE_N_177: Std_logic; signal RA_0S: Std_logic; signal n56: Std_logic; signal XOR8MEG: Std_logic; signal RA11_N_184: Std_logic; signal RA_c: Std_logic; signal n2478: Std_logic; signal RCKEEN_N_122: Std_logic; signal RCKEEN_N_121: Std_logic; signal RCLK_c_enable_4: Std_logic; signal RCKEEN: Std_logic; signal n2467: Std_logic; signal RCKE_c: Std_logic; signal RASr3: Std_logic; signal RASr: Std_logic; signal RCKE_N_132: Std_logic; signal CASr: Std_logic; signal nRWE_N_182: Std_logic; signal CASr2: Std_logic; signal n2568_002_BUF1: Std_logic; signal Ready_N_292: Std_logic; signal n2469: Std_logic; signal n2462: Std_logic; signal n62: Std_logic; signal n1160: Std_logic; signal CmdUFMCLK: Std_logic; signal UFMCLK_N_224: Std_logic; signal RCLK_c_enable_24: Std_logic; signal n1846: Std_logic; signal UFMCLK_c: Std_logic; signal n2470: Std_logic; signal n2272: Std_logic; signal n2471: Std_logic; signal CmdUFMSDI: Std_logic; signal n2461: Std_logic; signal UFMSDI_N_231: Std_logic; signal UFMSDI_c: Std_logic; signal Din_c_1: Std_logic; signal n2324: Std_logic; signal Din_c_2: Std_logic; signal Din_c_3: Std_logic; signal XOR8MEG_N_110: Std_logic; signal PHI2_N_120_enable_1: Std_logic; signal n2464: Std_logic; signal n1325: Std_logic; signal UFMSDO_c: Std_logic; signal n8MEGEN_N_91: Std_logic; signal RCLK_c_enable_11: Std_logic; signal n2427: Std_logic; signal n15_adj_1: Std_logic; signal nRCAS_N_161: Std_logic; signal nRCAS_c: Std_logic; signal n13: Std_logic; signal n2481: Std_logic; signal nRCS_N_136: Std_logic; signal nRCS_c: Std_logic; signal nRCS_N_139: Std_logic; signal nRowColSel_N_32: Std_logic; signal n6: Std_logic; signal nRRAS_c: Std_logic; signal n2138: Std_logic; signal nRWE_N_178: Std_logic; signal n33: Std_logic; signal nRWE_N_171: Std_logic; signal RCLK_c_enable_3: Std_logic; signal nRWE_c: Std_logic; signal nRowColSel: Std_logic; signal MAin_c_9: Std_logic; signal RowA_9: Std_logic; signal nRowColSel_N_28: Std_logic; signal n1502: Std_logic; signal n1410: Std_logic; signal RA_1_9: Std_logic; signal Ready_N_296: Std_logic; signal nRowColSel_N_33: Std_logic; signal n1503: Std_logic; signal n2414: Std_logic; signal n1093: Std_logic; signal CmdUFMCS: Std_logic; signal nUFMCS_c: Std_logic; signal n11: Std_logic; signal n1417: Std_logic; signal n2322: Std_logic; signal CASr3: Std_logic; signal n12: Std_logic; signal n2164: Std_logic; signal LEDEN_N_82: Std_logic; signal FWEr: Std_logic; signal n2476: Std_logic; signal n2475: Std_logic; signal n13_adj_2: Std_logic; signal n1: Std_logic; signal n2214: Std_logic; signal n2328: Std_logic; signal n10: Std_logic; signal n2458: Std_logic; signal n732: Std_logic; signal n733: Std_logic; signal n2290: Std_logic; signal n728: Std_logic; signal n729: Std_logic; signal n8: Std_logic; signal n727: Std_logic; signal MAin_c_7: Std_logic; signal MAin_c_6: Std_logic; signal RowA_6: Std_logic; signal RowA_7: Std_logic; signal n2468: Std_logic; signal n1280: Std_logic; signal PHI2r: Std_logic; signal nCCAS_c: Std_logic; signal n726: Std_logic; signal Bank_3: Std_logic; signal Bank_6: Std_logic; signal Bank_5: Std_logic; signal n2278: Std_logic; signal n2314: Std_logic; signal Bank_2: Std_logic; signal PHI2_N_120_enable_6: Std_logic; signal n14: Std_logic; signal n2460: Std_logic; signal n730: Std_logic; signal n2262: Std_logic; signal n2473: Std_logic; signal n738: Std_logic; signal n737: Std_logic; signal n2474: Std_logic; signal n2253: Std_logic; signal CROW_c_1: Std_logic; signal CROW_c_0: Std_logic; signal RBA_c_0: Std_logic; signal RBA_c_1: Std_logic; signal n734: Std_logic; signal n735: Std_logic; signal n7: Std_logic; signal n2451: Std_logic; signal Bank_0: Std_logic; signal Bank_1: Std_logic; signal WRD_0: Std_logic; signal WRD_1: Std_logic; signal MAin_c_8: Std_logic; signal RowA_8: Std_logic; signal WRD_6: Std_logic; signal WRD_7: Std_logic; signal RDQMH_c: Std_logic; signal RDQML_c: Std_logic; signal MAin_c_4: Std_logic; signal RowA_4: Std_logic; signal RowA_5: Std_logic; signal MAin_c_3: Std_logic; signal RowA_3: Std_logic; signal Bank_4: Std_logic; signal RowA_2: Std_logic; signal RA_1_3: Std_logic; signal Bank_7: Std_logic; signal RowA_0: Std_logic; signal RA_1_4: Std_logic; signal RowA_1: Std_logic; signal RA_1_8: Std_logic; signal RA_1_0: Std_logic; signal RA_1_7: Std_logic; signal RA_1_1: Std_logic; signal n736: Std_logic; signal RA_1_6: Std_logic; signal RA_1_2: Std_logic; signal WRD_2: Std_logic; signal RA_1_5: Std_logic; signal WRD_3: Std_logic; signal WRD_4: Std_logic; signal n984: Std_logic; signal WRD_5: Std_logic; signal Dout_c: Std_logic; signal Dout_0S: Std_logic; signal Dout_1S: Std_logic; signal Dout_2S: Std_logic; signal Dout_3S: Std_logic; signal Dout_4S: Std_logic; signal Dout_5S: Std_logic; signal Dout_6S: Std_logic; signal VCCI: Std_logic; signal GNDI_TSALL: Std_logic; component VHI port (Z: out Std_logic); end component; component VLO port (Z: out Std_logic); end component; component PUR port (PUR: in Std_logic); end component; component GSR port (GSR: in Std_logic); end component; component TSALL port (TSALL: in Std_logic); end component; component SLICE_0 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_1 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_2 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_3 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_4 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_5 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_6 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_7 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_8 port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); end component; component SLICE_9 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_14 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_18 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_19 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_23 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_25 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_26 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_31 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_32 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_34 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_35 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_36 port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_43 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_44 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_49 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_56 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_58 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); end component; component SLICE_60 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_61 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); end component; component SLICE_63 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_64 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_65 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_66 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_67 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_68 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_69 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component RCKEEN_I_0_445_SLICE_70 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); end component; component i26_SLICE_71 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); end component; component i2099_SLICE_72 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); end component; component i26_adj_28_SLICE_73 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); end component; component SLICE_74 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_75 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_76 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_77 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_78 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_79 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_80 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_81 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_82 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_83 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_84 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_85 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_86 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_87 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_88 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_89 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_90 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_91 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_92 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_93 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_94 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_95 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_96 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_97 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_98 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_99 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_100 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_101 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_102 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_103 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_104 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_105 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component RD_7_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD7: inout Std_logic); end component; component RD_6_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD6: inout Std_logic); end component; component RD_5_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD5: inout Std_logic); end component; component RD_4_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD4: inout Std_logic); end component; component RD_3_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD3: inout Std_logic); end component; component RD_2_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD2: inout Std_logic); end component; component RD_1_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD1: inout Std_logic); end component; component RD_0_B port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; RD0: inout Std_logic); end component; component Dout_7_B port (PADDO: in Std_logic; Dout7: out Std_logic); end component; component Dout_6_B port (PADDO: in Std_logic; Dout6: out Std_logic); end component; component Dout_5_B port (PADDO: in Std_logic; Dout5: out Std_logic); end component; component Dout_4_B port (PADDO: in Std_logic; Dout4: out Std_logic); end component; component Dout_3_B port (PADDO: in Std_logic; Dout3: out Std_logic); end component; component Dout_2_B port (PADDO: in Std_logic; Dout2: out Std_logic); end component; component Dout_1_B port (PADDO: in Std_logic; Dout1: out Std_logic); end component; component Dout_0_B port (PADDO: in Std_logic; Dout0: out Std_logic); end component; component LEDB port (PADDO: in Std_logic; LEDS: out Std_logic); end component; component RBA_1_B port (PADDO: in Std_logic; RBA1: out Std_logic); end component; component RBA_0_B port (PADDO: in Std_logic; RBA0: out Std_logic); end component; component RA_11_B port (PADDO: in Std_logic; RA11: out Std_logic); end component; component RA_10_B port (PADDO: in Std_logic; RA10: out Std_logic); end component; component RA_9_B port (PADDO: in Std_logic; RA9: out Std_logic); end component; component RA_8_B port (PADDO: in Std_logic; RA8: out Std_logic); end component; component RA_7_B port (PADDO: in Std_logic; RA7: out Std_logic); end component; component RA_6_B port (PADDO: in Std_logic; RA6: out Std_logic); end component; component RA_5_B port (PADDO: in Std_logic; RA5: out Std_logic); end component; component RA_4_B port (PADDO: in Std_logic; RA4: out Std_logic); end component; component RA_3_B port (PADDO: in Std_logic; RA3: out Std_logic); end component; component RA_2_B port (PADDO: in Std_logic; RA2: out Std_logic); end component; component RA_1_B port (PADDO: in Std_logic; RA1: out Std_logic); end component; component RA_0_B port (PADDO: in Std_logic; RA0: out Std_logic); end component; component nRCSB port (PADDO: in Std_logic; nRCSS: out Std_logic); end component; component RCKEB port (PADDO: in Std_logic; RCKES: out Std_logic); end component; component nRWEB port (PADDO: in Std_logic; nRWES: out Std_logic); end component; component nRRASB port (PADDO: in Std_logic; nRRASS: out Std_logic); end component; component nRCASB port (PADDO: in Std_logic; nRCASS: out Std_logic); end component; component RDQMHB port (PADDO: in Std_logic; RDQMHS: out Std_logic); end component; component RDQMLB port (PADDO: in Std_logic; RDQMLS: out Std_logic); end component; component nUFMCSB port (PADDO: in Std_logic; nUFMCSS: out Std_logic); end component; component UFMCLKB port (PADDO: in Std_logic; UFMCLKS: out Std_logic); end component; component UFMSDIB port (PADDO: in Std_logic; UFMSDIS: out Std_logic); end component; component PHI2B port (PADDI: out Std_logic; PHI2S: in Std_logic); end component; component MAin_9_B port (PADDI: out Std_logic; MAin9: in Std_logic); end component; component MAin_8_B port (PADDI: out Std_logic; MAin8: in Std_logic); end component; component MAin_7_B port (PADDI: out Std_logic; MAin7: in Std_logic); end component; component MAin_6_B port (PADDI: out Std_logic; MAin6: in Std_logic); end component; component MAin_5_B port (PADDI: out Std_logic; MAin5: in Std_logic); end component; component MAin_4_B port (PADDI: out Std_logic; MAin4: in Std_logic); end component; component MAin_3_B port (PADDI: out Std_logic; MAin3: in Std_logic); end component; component MAin_2_B port (PADDI: out Std_logic; MAin2: in Std_logic); end component; component MAin_1_B port (PADDI: out Std_logic; MAin1: in Std_logic); end component; component MAin_0_B port (PADDI: out Std_logic; MAin0: in Std_logic); end component; component CROW_1_B port (PADDI: out Std_logic; CROW1: in Std_logic); end component; component CROW_0_B port (PADDI: out Std_logic; CROW0: in Std_logic); end component; component Din_7_B port (PADDI: out Std_logic; Din7: in Std_logic); end component; component Din_6_B port (PADDI: out Std_logic; Din6: in Std_logic); end component; component Din_5_B port (PADDI: out Std_logic; Din5: in Std_logic); end component; component Din_4_B port (PADDI: out Std_logic; Din4: in Std_logic); end component; component Din_3_B port (PADDI: out Std_logic; Din3: in Std_logic); end component; component Din_2_B port (PADDI: out Std_logic; Din2: in Std_logic); end component; component Din_1_B port (PADDI: out Std_logic; Din1: in Std_logic); end component; component Din_0_B port (PADDI: out Std_logic; Din0: in Std_logic); end component; component nCCASB port (PADDI: out Std_logic; nCCASS: in Std_logic); end component; component nCRASB port (PADDI: out Std_logic; nCRASS: in Std_logic); end component; component nFWEB port (PADDI: out Std_logic; nFWES: in Std_logic); end component; component RCLKB port (PADDI: out Std_logic; RCLKS: in Std_logic); end component; component UFMSDOB port (PADDI: out Std_logic; UFMSDOS: in Std_logic); end component; begin SLICE_0I: SLICE_0 port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>n2010, Q0=>FS_6, Q1=>FS_7, FCO=>n2011); SLICE_1I: SLICE_1 port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>n2014, Q0=>FS_14, Q1=>FS_15, FCO=>n2015); SLICE_2I: SLICE_2 port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>n2009, Q0=>FS_4, Q1=>FS_5, FCO=>n2010); SLICE_3I: SLICE_3 port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>n2013, Q0=>FS_12, Q1=>FS_13, FCO=>n2014); SLICE_4I: SLICE_4 port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, FCO=>n2008); SLICE_5I: SLICE_5 port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>n2012, Q0=>FS_10, Q1=>FS_11, FCO=>n2013); SLICE_6I: SLICE_6 port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>n2008, Q0=>FS_2, Q1=>FS_3, FCO=>n2009); SLICE_7I: SLICE_7 port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>n2011, Q0=>FS_8, Q1=>FS_9, FCO=>n2012); SLICE_8I: SLICE_8 port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>n2015, Q0=>FS_16, Q1=>FS_17); SLICE_9I: SLICE_9 port map (C1=>MAin_c_1, B1=>n1326, A1=>MAin_c_0, D0=>n2263, C0=>ADSubmitted, B0=>n2242, A0=>n2459, DI0=>n1413, LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1413, Q0=>ADSubmitted, F1=>n2263); SLICE_14I: SLICE_14 port map (B1=>Din_c_6, A1=>C1Submitted, D0=>MAin_c_1, C0=>C1Submitted, B0=>n1326, A0=>nFWE_c, DI0=>n6_adj_3, LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n6_adj_3, Q0=>C1Submitted, F1=>n2284); SLICE_18I: SLICE_18 port map (D1=>MAin_c_5, C1=>n2316, B1=>n26, A1=>MAin_c_2, D0=>n15, C0=>n1326, B0=>n2463, A0=>MAin_c_1, DI0=>CmdEnable_N_248, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, F0=>CmdEnable_N_248, Q0=>CmdEnable, F1=>n1326); SLICE_19I: SLICE_19 port map (C1=>PHI2r2, B1=>CmdSubmitted, A1=>PHI2r3, DI0=>n2568_001_BUF1, CE=>PHI2_N_120_enable_5, CLK=>PHI2_c, F0=>n2568_001_BUF1, Q0=>CmdSubmitted, F1=>n2472); SLICE_23I: SLICE_23 port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, CE=>PHI2_N_120_enable_4, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, Q0=>Cmdn8MEGEN, F1=>n1314); SLICE_25I: SLICE_25 port map (D1=>nRowColSel_N_35, C1=>RASr2, B1=>InitReady, A1=>Ready, DI0=>n2568_000_BUF1, CE=>RCLK_c_enable_25, CLK=>RCLK_c, F0=>n2568_000_BUF1, Q0=>InitReady, F1=>RCLK_c_enable_23); SLICE_26I: SLICE_26 port map (C1=>nCRAS_c, B1=>CBR, A1=>LEDEN, DI0=>n2568, CE=>RCLK_c_enable_12, CLK=>RCLK_c, F0=>n2568, Q0=>LEDEN, F1=>LED_N_84); SLICE_31I: SLICE_31 port map (B1=>nRowColSel_N_34, A1=>Ready, C0=>nRCAS_N_165, B0=>Ready, A0=>n2208, DI0=>n2209, LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2209, Q0=>RA_0S, F1=>n56); SLICE_32I: SLICE_32 port map (B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n2478); SLICE_34I: SLICE_34 port map (C1=>Ready, B1=>InitReady, A1=>RASr2, C0=>Ready, B0=>RCKEEN_N_122, A0=>InitReady, DI0=>RCKEEN_N_121, CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, F1=>n2467); SLICE_35I: SLICE_35 port map (B1=>RCKE_c, A1=>RASr2, D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, M1=>CASr, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, F1=>nRWE_N_182, Q1=>CASr2); SLICE_36I: SLICE_36 port map (B1=>nRowColSel_N_35, A1=>Ready, DI0=>n2568_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, F0=>n2568_002_BUF1, Q0=>Ready, F1=>n2469); SLICE_43I: SLICE_43 port map (D1=>FS_1, C1=>n2462, B1=>n62, A1=>FS_4, C0=>InitReady, B0=>n1160, A0=>CmdUFMCLK, DI0=>UFMCLK_N_224, CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1160); SLICE_44I: SLICE_44 port map (D1=>FS_11, C1=>n2470, B1=>n2272, A1=>n2471, D0=>CmdUFMSDI, C0=>InitReady, B0=>n2462, A0=>n2461, DI0=>UFMSDI_N_231, CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2462); SLICE_49I: SLICE_49 port map (D1=>Din_c_1, C1=>n1314, B1=>LEDEN, A1=>Din_c_4, D0=>n2324, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_0, DI0=>XOR8MEG_N_110, CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>XOR8MEG_N_110, Q0=>XOR8MEG, F1=>n2324); SLICE_56I: SLICE_56 port map (C1=>FS_10, B1=>n2464, A1=>FS_11, D0=>n1325, C0=>InitReady, B0=>Cmdn8MEGEN, A0=>UFMSDO_c, DI0=>n8MEGEN_N_91, CE=>RCLK_c_enable_11, CLK=>RCLK_c, F0=>n8MEGEN_N_91, Q0=>n8MEGEN, F1=>n1325); SLICE_58I: SLICE_58 port map (D1=>n2427, C1=>RASr2, B1=>CBR, A1=>Ready, C0=>Ready, B0=>n15_adj_1, A0=>nRowColSel_N_34, DI0=>nRCAS_N_161, M0=>nRowColSel_N_35, CE=>RCLK_c_enable_4, CLK=>RCLK_c, OFX0=>nRCAS_N_161, Q0=>nRCAS_c); SLICE_60I: SLICE_60 port map (D1=>Ready, C1=>RCKE_c, B1=>InitReady, A1=>RASr2, D0=>nRowColSel_N_35, C0=>n13, B0=>n2481, A0=>n2467, DI0=>nRCS_N_136, CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, F1=>n13); SLICE_61I: SLICE_61 port map (C1=>nRCS_N_139, B1=>n13, A1=>Ready, D0=>nRowColSel_N_32, C0=>n6, B0=>nRRAS_c, A0=>n56, DI0=>n2138, M0=>nRowColSel_N_35, CLK=>RCLK_c, OFX0=>n2138, Q0=>nRRAS_c); SLICE_63I: SLICE_63 port map (D1=>nRCS_N_139, C1=>InitReady, B1=>RASr2, A1=>nRowColSel_N_35, D0=>n2208, C0=>Ready, B0=>nRWE_N_178, A0=>n33, DI0=>nRWE_N_171, CE=>RCLK_c_enable_3, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, F1=>n2208); SLICE_64I: SLICE_64 port map (C1=>nRowColSel, B1=>MAin_c_9, A1=>RowA_9, D0=>nRowColSel_N_32, C0=>nRowColSel_N_28, B0=>n1502, A0=>nRowColSel, DI0=>n1410, LSR=>n2469, CLK=>RCLK_c, F0=>n1410, Q0=>nRowColSel, F1=>RA_1_9); SLICE_65I: SLICE_65 port map (D1=>InitReady, C1=>Ready_N_296, B1=>RASr2, A1=>nRowColSel_N_32, B0=>nRowColSel_N_33, A0=>nRowColSel_N_32, DI0=>n1503, LSR=>RASr2, CLK=>RCLK_c, F0=>n1503, Q0=>nRowColSel_N_32, F1=>n2414); SLICE_66I: SLICE_66 port map (D1=>nRowColSel_N_33, C1=>nRowColSel_N_34, B1=>n2469, A1=>nRowColSel_N_32, B0=>RASr2, A0=>nRowColSel_N_32, DI0=>n1093, LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1093, Q0=>nRowColSel_N_33, F1=>RCLK_c_enable_4); SLICE_67I: SLICE_67 port map (C1=>n2472, B1=>CmdUFMCS, A1=>nUFMCS_c, B0=>CASr2, A0=>nRowColSel_N_33, M0=>n1093, LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n11, Q0=>nRowColSel_N_34, F1=>n1417); SLICE_68I: SLICE_68 port map (B1=>FS_12, A1=>FS_17, D0=>FS_3, C0=>FS_6, B0=>FS_1, A0=>FS_0, M1=>CASr2, M0=>RASr2, CLK=>RCLK_c, F0=>n2322, Q0=>nRowColSel_N_35, F1=>n2471, Q1=>CASr3); SLICE_69I: SLICE_69 port map (D1=>FS_14, C1=>FS_12, B1=>n12, A1=>FS_17, C0=>InitReady, B0=>n1417, A0=>n62, DI0=>n2164, LSR=>LEDEN_N_82, CLK=>RCLK_c, F0=>n2164, Q0=>nUFMCS_c, F1=>n62); RCKEEN_I_0_445_SLICE_70I: RCKEEN_I_0_445_SLICE_70 port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, B0=>n11, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>RCKEEN_N_122); i26_SLICE_71I: i26_SLICE_71 port map (D1=>n2284, C1=>n2476, B1=>MAin_c_1, A1=>MAin_c_0, D0=>ADSubmitted, C0=>MAin_c_0, B0=>n2475, A0=>Din_c_5, M0=>Din_c_2, OFX0=>n13_adj_2); i2099_SLICE_72I: i2099_SLICE_72 port map (D1=>nRowColSel_N_34, C1=>nRowColSel_N_35, B1=>Ready, A1=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>Ready, A0=>nRCS_N_139, M0=>n15_adj_1, OFX0=>n2481); i26_adj_28_SLICE_73I: i26_adj_28_SLICE_73 port map (D1=>MAin_c_0, C1=>Din_c_2, B1=>Din_c_3, A1=>Din_c_6, D0=>MAin_c_0, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_6, M0=>Din_c_5, OFX0=>n15); SLICE_74I: SLICE_74 port map (D1=>n1, C1=>nRowColSel_N_33, B1=>CBR, A1=>FWEr, D0=>CASr3, C0=>CASr2, B0=>FWEr, A0=>CBR, M1=>RASr2, M0=>RASr, CLK=>RCLK_c, F0=>n1, Q0=>RASr2, F1=>n15_adj_1, Q1=>RASr3); SLICE_75I: SLICE_75 port map (C1=>InitReady, B1=>FS_11, A1=>n2214, D0=>FS_11, C0=>n2272, B0=>n2328, A0=>FS_10, F0=>n2214, F1=>RCLK_c_enable_12); SLICE_76I: SLICE_76 port map (D1=>MAin_c_0, C1=>n10, B1=>n1326, A1=>nFWE_c, D0=>n2458, C0=>Din_c_4, B0=>Din_c_5, A0=>Din_c_3, M1=>n732, M0=>n733, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>PHI2_N_120_enable_4, Q0=>n732, F1=>n2458, Q1=>nRWE_N_177); SLICE_77I: SLICE_77 port map (D1=>FS_7, C1=>n2322, B1=>FS_4, A1=>n2290, C0=>FS_9, B0=>FS_5, A0=>FS_2, M1=>n728, M0=>n729, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2290, Q0=>n728, F1=>n8, Q1=>n727); SLICE_78I: SLICE_78 port map (D1=>n2471, C1=>n2272, B1=>FS_14, A1=>FS_16, C0=>InitReady, B0=>n2464, A0=>FS_11, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, F0=>n1846, Q0=>RowA_6, F1=>n2464, Q1=>RowA_7); SLICE_79I: SLICE_79 port map (C1=>Din_c_5, B1=>Din_c_3, A1=>Din_c_6, D0=>n2468, C0=>n1280, B0=>n2463, A0=>Din_c_2, M1=>PHI2r, M0=>nCCAS_c, CLK=>RCLK_c, F0=>C1Submitted_N_237, Q0=>CASr, F1=>n2468, Q1=>PHI2r2); SLICE_80I: SLICE_80 port map (B1=>nRowColSel_N_33, A1=>nRowColSel_N_34, D0=>nRowColSel_N_35, C0=>n1502, B0=>nRowColSel_N_32, A0=>Ready, M1=>n726, M0=>n727, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_3, Q0=>n726, F1=>n1502, Q1=>Ready_N_296); SLICE_81I: SLICE_81 port map (B1=>Bank_3, A1=>Bank_6, D0=>Bank_5, C0=>n2278, B0=>n2314, A0=>Bank_2, M1=>Din_c_2, M0=>Din_c_1, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>n26, Q0=>CmdUFMCLK, F1=>n2278, Q1=>CmdUFMCS); SLICE_82I: SLICE_82 port map (D1=>MAin_c_1, C1=>n14, B1=>n2460, A1=>MAin_c_0, B0=>n1326, A0=>nFWE_c, M1=>n730, M0=>nRWE_N_177, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2460, Q0=>n730, F1=>PHI2_N_120_enable_7, Q1=>n729); SLICE_83I: SLICE_83 port map (D1=>n2476, C1=>n2460, B1=>n10, A1=>MAin_c_0, D0=>MAin_c_1, C0=>CmdEnable, B0=>n2478, A0=>Din_c_4, M0=>nCRAS_c, CLK=>RCLK_c, F0=>n10, Q0=>RASr, F1=>PHI2_N_120_enable_6); SLICE_84I: SLICE_84 port map (D1=>n1314, C1=>n2262, B1=>CmdEnable, A1=>n2473, C0=>MAin_c_1, B0=>n1326, A0=>MAin_c_0, M1=>n738, M0=>nRCAS_N_165, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2262, Q0=>n738, F1=>PHI2_N_120_enable_1, Q1=>n737); SLICE_85I: SLICE_85 port map (D1=>n2474, C1=>Din_c_5, B1=>n2253, A1=>n2473, B0=>nFWE_c, A0=>Din_c_4, M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2473, Q0=>RBA_c_0, F1=>n2242, Q1=>RBA_c_1); SLICE_86I: SLICE_86 port map (C1=>Din_c_1, B1=>Din_c_0, A1=>Din_c_7, C0=>n2253, B0=>nFWE_c, A0=>Din_c_4, M1=>n734, M0=>n735, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2463, Q0=>n734, F1=>n2253, Q1=>n733); SLICE_87I: SLICE_87 port map (B1=>n2214, A1=>FS_8, D0=>n8, C0=>InitReady, B0=>n2472, A0=>n7, M1=>nRCS_N_139, M0=>Ready_N_296, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_11, Q0=>nRCS_N_139, F1=>n7, Q1=>nRCAS_N_165); SLICE_88I: SLICE_88 port map (C1=>FS_10, B1=>FS_6, A1=>n2451, D0=>FS_8, C0=>FS_5, B0=>FS_9, A0=>FS_7, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>n2451, Q0=>Bank_0, F1=>n2461, Q1=>Bank_1); SLICE_89I: SLICE_89 port map (C1=>MAin_c_1, B1=>n1326, A1=>nFWE_c, C0=>MAin_c_0, B0=>n1326, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, F0=>n1280, Q0=>WRD_0, F1=>n2459, Q1=>WRD_1); SLICE_90I: SLICE_90 port map (D1=>FS_16, C1=>FS_14, B1=>FS_12, A1=>FS_17, B0=>FS_14, A0=>FS_16, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, CLK=>nCRAS_c, F0=>n2470, Q0=>RowA_8, F1=>n2328, Q1=>RowA_9); SLICE_91I: SLICE_91 port map (B1=>Din_c_5, A1=>Din_c_3, D0=>n2458, C0=>Din_c_5, B0=>Din_c_4, A0=>Din_c_3, M1=>PHI2_c, M0=>PHI2r2, CLK=>RCLK_c, F0=>PHI2_N_120_enable_5, Q0=>PHI2r3, F1=>n2476, Q1=>PHI2r); SLICE_92I: SLICE_92 port map (B1=>Din_c_3, A1=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, A0=>Din_c_6, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>n2474, Q0=>WRD_6, F1=>n2475, Q1=>WRD_7); SLICE_93I: SLICE_93 port map (B1=>nRowColSel, A1=>MAin_c_9, B0=>nRowColSel, A0=>MAin_c_9, M0=>Din_c_0, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>RDQMH_c, Q0=>CmdUFMSDI, F1=>RDQML_c); SLICE_94I: SLICE_94 port map (B1=>FS_15, A1=>FS_13, D0=>FS_11, C0=>FS_16, B0=>FS_13, A0=>FS_15, F0=>n12, F1=>n2272); SLICE_95I: SLICE_95 port map (B1=>FS_10, A1=>n62, D0=>InitReady, C0=>FS_10, B0=>n2464, A0=>FS_11, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, CLK=>nCRAS_c, F0=>LEDEN_N_82, Q0=>RowA_4, F1=>RCLK_c_enable_25, Q1=>RowA_5); SLICE_96I: SLICE_96 port map (C1=>nRowColSel, B1=>MAin_c_3, A1=>RowA_3, D0=>Bank_1, C0=>Bank_4, B0=>MAin_c_3, A0=>MAin_c_7, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, CLK=>nCRAS_c, F0=>n2316, Q0=>RowA_2, F1=>RA_1_3, Q1=>RowA_3); SLICE_97I: SLICE_97 port map (C1=>nRowColSel, B1=>MAin_c_4, A1=>RowA_4, D0=>Bank_0, C0=>Bank_7, B0=>MAin_c_4, A0=>MAin_c_6, M1=>MAin_c_1, M0=>MAin_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2314, Q0=>RowA_0, F1=>RA_1_4, Q1=>RowA_1); SLICE_98I: SLICE_98 port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, B0=>MAin_c_8, A0=>RowA_8, M1=>nFWE_c, M0=>nCCAS_c, CLK=>nCRAS_c, F0=>RA_1_8, Q0=>CBR, F1=>RA_1_0, Q1=>FWEr); SLICE_99I: SLICE_99 port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M1=>Din_c_7, M0=>Din_c_6, CLK=>PHI2_c, F0=>RA_1_7, Q0=>Bank_6, F1=>RA_1_1, Q1=>Bank_7); SLICE_100I: SLICE_100 port map (D1=>Ready, C1=>nRowColSel_N_33, B1=>InitReady, A1=>RASr2, D0=>InitReady, C0=>PHI2r2, B0=>CmdSubmitted, A0=>PHI2r3, M1=>n736, M0=>n737, CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_24, Q0=>n736, F1=>n6, Q1=>n735); SLICE_101I: SLICE_101 port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_5, M0=>Din_c_4, CLK=>PHI2_c, F0=>RA_1_6, Q0=>Bank_4, F1=>RA_1_2, Q1=>Bank_5); SLICE_102I: SLICE_102 port map (B1=>nRWE_N_177, A1=>nRCAS_N_165, C0=>nRCAS_N_165, B0=>nRCS_N_139, A0=>InitReady, M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>n2427, Q0=>Bank_2, F1=>n33, Q1=>Bank_3); SLICE_103I: SLICE_103 port map (C1=>nRowColSel, B1=>MAin_c_5, A1=>RowA_5, C0=>CBR, B0=>CASr3, A0=>FWEr, M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>nRowColSel_N_28, Q0=>WRD_2, F1=>RA_1_5, Q1=>WRD_3); SLICE_104I: SLICE_104 port map (B1=>Ready, A1=>n2414, D0=>nRowColSel_N_35, C0=>nRWE_N_182, B0=>n1502, A0=>n1, F0=>nRWE_N_178, F1=>Ready_N_292); SLICE_105I: SLICE_105 port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>n13_adj_2, B0=>Din_c_4, A0=>n2253, M1=>Din_c_5, M0=>Din_c_4, CLK=>nCCAS_c, F0=>n14, Q0=>WRD_4, F1=>n984, Q1=>WRD_5); RD_7_I: RD_7_B port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); RD_6_I: RD_6_B port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); RD_5_I: RD_5_B port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); RD_4_I: RD_4_B port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); RD_3_I: RD_3_B port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); RD_2_I: RD_2_B port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); RD_1_I: RD_1_B port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); RD_0_I: RD_0_B port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); Dout_7_I: Dout_7_B port map (PADDO=>Dout_c, Dout7=>Dout(7)); Dout_6_I: Dout_6_B port map (PADDO=>Dout_0S, Dout6=>Dout(6)); Dout_5_I: Dout_5_B port map (PADDO=>Dout_1S, Dout5=>Dout(5)); Dout_4_I: Dout_4_B port map (PADDO=>Dout_2S, Dout4=>Dout(4)); Dout_3_I: Dout_3_B port map (PADDO=>Dout_3S, Dout3=>Dout(3)); Dout_2_I: Dout_2_B port map (PADDO=>Dout_4S, Dout2=>Dout(2)); Dout_1_I: Dout_1_B port map (PADDO=>Dout_5S, Dout1=>Dout(1)); Dout_0_I: Dout_0_B port map (PADDO=>Dout_6S, Dout0=>Dout(0)); LEDI: LEDB port map (PADDO=>LED_N_84, LEDS=>LED); RBA_1_I: RBA_1_B port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); RBA_0_I: RBA_0_B port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); RA_11_I: RA_11_B port map (PADDO=>RA_c, RA11=>RA(11)); RA_10_I: RA_10_B port map (PADDO=>RA_0S, RA10=>RA(10)); RA_9_I: RA_9_B port map (PADDO=>RA_1_9, RA9=>RA(9)); RA_8_I: RA_8_B port map (PADDO=>RA_1_8, RA8=>RA(8)); RA_7_I: RA_7_B port map (PADDO=>RA_1_7, RA7=>RA(7)); RA_6_I: RA_6_B port map (PADDO=>RA_1_6, RA6=>RA(6)); RA_5_I: RA_5_B port map (PADDO=>RA_1_5, RA5=>RA(5)); RA_4_I: RA_4_B port map (PADDO=>RA_1_4, RA4=>RA(4)); RA_3_I: RA_3_B port map (PADDO=>RA_1_3, RA3=>RA(3)); RA_2_I: RA_2_B port map (PADDO=>RA_1_2, RA2=>RA(2)); RA_1_I: RA_1_B port map (PADDO=>RA_1_1, RA1=>RA(1)); RA_0_I: RA_0_B port map (PADDO=>RA_1_0, RA0=>RA(0)); nRCSI: nRCSB port map (PADDO=>nRCS_c, nRCSS=>nRCS); RCKEI: RCKEB port map (PADDO=>RCKE_c, RCKES=>RCKE); nRWEI: nRWEB port map (PADDO=>nRWE_c, nRWES=>nRWE); nRRASI: nRRASB port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); nRCASI: nRCASB port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); RDQMHI: RDQMHB port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); RDQMLI: RDQMLB port map (PADDO=>RDQML_c, RDQMLS=>RDQML); nUFMCSI: nUFMCSB port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); UFMCLKI: UFMCLKB port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); UFMSDII: UFMSDIB port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); PHI2I: PHI2B port map (PADDI=>PHI2_c, PHI2S=>PHI2); MAin_9_I: MAin_9_B port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); MAin_8_I: MAin_8_B port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); MAin_7_I: MAin_7_B port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); MAin_6_I: MAin_6_B port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); MAin_5_I: MAin_5_B port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); MAin_4_I: MAin_4_B port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); MAin_3_I: MAin_3_B port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); MAin_2_I: MAin_2_B port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); MAin_1_I: MAin_1_B port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); MAin_0_I: MAin_0_B port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); CROW_1_I: CROW_1_B port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); CROW_0_I: CROW_0_B port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); Din_7_I: Din_7_B port map (PADDI=>Din_c_7, Din7=>Din(7)); Din_6_I: Din_6_B port map (PADDI=>Din_c_6, Din6=>Din(6)); Din_5_I: Din_5_B port map (PADDI=>Din_c_5, Din5=>Din(5)); Din_4_I: Din_4_B port map (PADDI=>Din_c_4, Din4=>Din(4)); Din_3_I: Din_3_B port map (PADDI=>Din_c_3, Din3=>Din(3)); Din_2_I: Din_2_B port map (PADDI=>Din_c_2, Din2=>Din(2)); Din_1_I: Din_1_B port map (PADDI=>Din_c_1, Din1=>Din(1)); Din_0_I: Din_0_B port map (PADDI=>Din_c_0, Din0=>Din(0)); nCCASI: nCCASB port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); nCRASI: nCRASB port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); nFWEI: nFWEB port map (PADDI=>nFWE_c, nFWES=>nFWE); RCLKI: RCLKB port map (PADDI=>RCLK_c, RCLKS=>RCLK); UFMSDOI: UFMSDOB port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); VHI_INST: VHI port map (Z=>VCCI); PUR_INST: PUR port map (PUR=>VCCI); GSR_INST: GSR port map (GSR=>VCCI); VLO_INST: VLO port map (Z=>GNDI_TSALL); TSALL_INST: TSALL port map (TSALL=>GNDI_TSALL); end Structure; library IEEE, vital2000, MACHXO; configuration Structure_CON of RAM2GS is for Structure end for; end Structure_CON;