Analysis & Synthesis report for RAM2GS Sat Nov 11 04:34:38 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. Analysis & Synthesis IP Cores Summary 9. General Register Statistics 10. Inverted Register Statistics 11. Multiplexer Restructuring Statistics (Restructuring Performed) 12. Port Connectivity Checks: "UFM:UFM_inst" 13. Analysis & Synthesis Messages 14. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2019 Intel Corporation. All rights reserved. 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Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Sat Nov 11 04:34:38 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; ; Total logic elements ; 196 ; ; Total pins ; 63 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+-------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 5M240ZT100C5 ; ; ; Top-level entity name ; RAM2GS ; RAM2GS ; ; Family name ; MAX V ; Cyclone V ; ; Maximum processors allowed for parallel compilation ; 4 ; ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; +----------------------------+-------------+ +---------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ ; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ; ; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v ; ; ; ../RAM2GS-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.mif ; ; +----------------------------------+-----------------+----------------------------------+-------------------------------------+---------+ +-----------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ ; Total logic elements ; 196 ; ; -- Combinational with no register ; 92 ; ; -- Register only ; 34 ; ; -- Combinational with a register ; 70 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 64 ; ; -- 3 input functions ; 46 ; ; -- 2 input functions ; 43 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 180 ; ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 11 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 104 ; ; Total logic cells in carry chains ; 17 ; ; I/O pins ; 63 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; RCLK ; ; Maximum fan-out ; 61 ; ; Total fan-out ; 703 ; ; Average fan-out ; 2.70 ; +---------------------------------------------+-------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ ; |RAM2GS ; 196 (196) ; 104 ; 1 ; 63 ; 0 ; 92 (92) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +---------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ ; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2GS|UFM:UFM_inst ; UFM.v ; +--------+---------------------------+---------+--------------+--------------+----------------------+-----------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 104 ; ; Number of registers using Synchronous Clear ; 7 ; ; Number of registers using Synchronous Load ; 4 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 11 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +--------------------------------------------------+ ; Inverted Register Statistics ; +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ ; nRCS~reg0 ; 1 ; ; nRWE~reg0 ; 1 ; ; nRRAS~reg0 ; 1 ; ; nRCAS~reg0 ; 1 ; ; Total number of inverted registers = 4 ; ; +----------------------------------------+---------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[1] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |RAM2GS|CmdLEDEN ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +-----------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "UFM:UFM_inst" ; +-------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-------+--------+----------+-------------------------------------------------------------------------------------+ ; ardin ; Input ; Info ; Stuck at GND ; ; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition Info: Processing started: Sat Nov 11 04:34:02 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Info (20032): Parallel compilation is enabled and will use up to 4 processors Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2gs/cpld/ram2gs-max.v Info (12023): Found entity 1: RAM2GS File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 1: UFM_altufm_none_38r File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47 Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150 Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92 Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: Y:/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201 Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27 Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different Info (21058): Implemented 25 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 8 bidirectional pins Info (21061): Implemented 196 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings Info: Peak virtual memory: 13126 megabytes Info: Processing ended: Sat Nov 11 04:34:38 2023 Info: Elapsed time: 00:00:36 Info: Total CPU time (on all processors): 00:00:41 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in Y:/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg.