# messages

id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: FX474
kind: warning
message:
User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 


id: FX1143
kind: note
message:
Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.


id: FX1056
kind: note
message:
Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


id: MT118
kind: warning
message:
Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  


id: MT117
kind: warning
message:
Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  


id: MT118
kind: warning
message:
Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  


id: MT116
kind: warning
message:
Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  


id: MT117
kind: warning
message:
Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  


